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maksyukimaksyuki
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Merge branch 'dev' into main
2 parents 2fcde70 + 45afe5b commit ab8396d

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44 files changed

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‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,9 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2._
7-
import treecorel2.common.AXI4Config
8-
9-
class AXI4Bridge extends Module with AXI4Config {
6+
class AXI4Bridge extends Module with InstConfig {
107
val io = IO(new Bundle {
118
val socEn = Input(Bool())
129
val runEn = Output(Bool())
@@ -25,10 +22,9 @@ class AXI4Bridge extends Module with AXI4Config {
2522
arbiter.io.rHdShk := io.axi.r.fire()
2623

2724
protected val wMask = arbiter.io.dxchg.wmask
28-
protected val byteSize = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
2925
protected val socARSize = arbiter.io.dxchg.rsize
3026
protected val socAWSize = MuxLookup(
31-
byteSize,
27+
PopCount(wMask),
3228
0.U,
3329
Array(
3430
8.U -> 3.U,

‎rtl/tc_l2/src/main/scala/axi4/Arbiter.scala

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,21 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2.DXCHGIO
7-
import treecorel2.common.AXI4Config
8-
96
object Arbiter {
107
// FSM var for read/write
118
val eumIDLE :: eumStandby :: eumIDLE2 :: eumAW :: eumW :: eumB :: eumAR :: eumR :: Nil = Enum(8)
129
}
1310

14-
class Arbiter extends Module with AXI4Config {
11+
class Arbiter extends Module with InstConfig {
1512
val io = IO(new Bundle {
1613
val awHdShk = Input(Bool())
1714
val wHdShk = Input(Bool())
1815
val bHdShk = Input(Bool())
1916
val arHdShk = Input(Bool())
2017
val rHdShk = Input(Bool())
21-
val axirdata = Input(UInt(64.W))
18+
val axirdata = Input(UInt(XLen.W))
2219
val dxchg = Flipped(new DXCHGIO)
2320
val state = Output(UInt(3.W))
2421
val runEn = Output(Bool())
@@ -30,13 +27,13 @@ class Arbiter extends Module with AXI4Config {
3027

3128
protected val valid = RegInit(false.B)
3229
protected val ren = RegInit(false.B)
33-
protected val raddr = RegInit(0.U(64.W))
34-
protected val rdata = RegInit(0.U(64.W))
30+
protected val raddr = RegInit(0.U(XLen.W))
31+
protected val rdata = RegInit(0.U(XLen.W))
3532
protected val rsize = RegInit(0.U(3.W))
3633
protected val wen = RegInit(false.B)
37-
protected val waddr = RegInit(0.U(64.W))
38-
protected val wdata = RegInit(0.U(64.W))
39-
protected val wmask = RegInit(0.U(8.W))
34+
protected val waddr = RegInit(0.U(XLen.W))
35+
protected val wdata = RegInit(0.U(XLen.W))
36+
protected val wmask = RegInit(0.U(MaskLen.W))
4037
protected val stateReg = RegInit(Arbiter.eumIDLE)
4138
io.state := stateReg
4239
io.dxchg.rdata := rdata

‎rtl/tc_l2/src/main/scala/axi4/Crossbar.scala

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2.common.InstConfig
7-
86
class Crossbar extends Module with InstConfig {
97
val io = IO(new Bundle {
108
val socEn = Input(Bool())
@@ -14,7 +12,7 @@ class Crossbar extends Module with InstConfig {
1412
})
1513

1614
protected val globalEn = RegInit(false.B)
17-
protected val inst = RegInit(0.U(32.W))
15+
protected val inst = RegInit(0.U(InstLen.W))
1816
protected val rdInst = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
1917

2018
io.core.globalEn := Mux(io.runEn, globalEn, false.B)
@@ -37,25 +35,25 @@ class Crossbar extends Module with InstConfig {
3735
when(io.runEn) {
3836
globalEn := false.B
3937
stateReg := eumInst
40-
inst := 0x13.U
38+
inst := NOPInst
4139
}
4240
}
4341
}
4442

4543
// because the difftest's logic addr is 0x000000
46-
protected val instSize = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
47-
protected val baseAddr = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
48-
protected val instAddr = io.core.fetch.addr - baseAddr
49-
protected val loadAddr = io.core.ld.addr - baseAddr
50-
protected val storeAddr = io.core.sd.addr - baseAddr
51-
protected val maEn = io.core.ld.en || io.core.sd.en
44+
protected val instSize = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
45+
protected val baseAddr = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
46+
protected val instAddr = io.core.fetch.addr - baseAddr
47+
protected val ldAddr = io.core.ld.addr - baseAddr
48+
protected val sdAddr = io.core.sd.addr - baseAddr
49+
protected val maEn = io.core.ld.en || io.core.sd.en
5250

5351
// prepare the data exchange io signals
5452
io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
55-
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
53+
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, ldAddr)
5654
io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
5755
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
58-
io.dxchg.waddr := storeAddr
56+
io.dxchg.waddr := sdAddr
5957
io.dxchg.wdata := io.core.sd.data
6058
io.dxchg.wmask := io.core.sd.mask
6159
}

‎rtl/tc_l2/src/main/scala/common/AXI4Config.scala

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,18 @@
1-
package treecorel2.common
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
trait AXI4Config extends InstConfig {}
6+
trait AXI4Config extends IOConfig {
7+
val AxiProtLen = 3
8+
val AxiIdLen = 4
9+
val AxiUserLen = 1
10+
val AxiSizeLen = 3 // NOTE: or 2?
11+
val AxiLen = 8
12+
val AxiStrb = 8
13+
val AxiBurstLen = 2
14+
val AxiCacheLen = 4
15+
val AxiQosLen = 4
16+
val AxiRegionLen = 4
17+
val AxiRespLen = 2
18+
}

‎rtl/tc_l2/src/main/scala/common/ConstVal.scala

Lines changed: 0 additions & 10 deletions
This file was deleted.

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala

Lines changed: 28 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,30 @@
1-
package treecorel2.common
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
trait InstConfig {
7-
val SoCEna = false
8-
val XLen = 64
9-
val InstLen = 32
10-
val RegfileNum = 32
6+
trait IOConfig {
7+
val XLen = 64
8+
val InstLen = 32
9+
val RegfileLen = 5
10+
val RegfileNum = 1 << RegfileLen
11+
val ISALen = 6
12+
// mem
13+
val MaskLen = 8
14+
val LDSize = 3
15+
// branch prediction
16+
val GHRLen = 5
17+
val PHTSize = 1 << GHRLen
18+
val BTBIdxLen = 5
19+
val BTBPcLen = XLen - BTBIdxLen
20+
val BTBTgtLen = XLen
21+
val BTBSize = 1 << BTBIdxLen
22+
}
23+
24+
trait InstConfig extends IOConfig {
25+
val SoCEna = true
26+
val CacheEna = false
27+
1128
val FlashStartAddr = "h0000000030000000".U(XLen.W)
1229
val SimStartAddr = "h0000000080000000".U(XLen.W)
1330
val DiffStartBaseAddr = "h0000000080000000".U(XLen.W)
@@ -17,8 +34,8 @@ trait InstConfig {
1734
val InstSoCRSize = 2.U
1835
val InstDiffRSize = 3.U
1936
val DiffRWSize = 3.U
20-
val CacheEna = false
2137

38+
val NOPInst = 0x13.U
2239
// inst type
2340
// nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
2441
val InstTypeLen = 3
@@ -95,14 +112,6 @@ trait InstConfig {
95112
val instFENCE_I = 59.U(InstValLen.W)
96113
val instCUST = 60.U(InstValLen.W)
97114

98-
// branch prediction
99-
val GHRLen = 5
100-
val PHTSize = 1 << GHRLen
101-
val BTBIdxLen = 5
102-
val BTBPcLen = XLen - BTBIdxLen
103-
val BTBTgtLen = XLen
104-
val BTBSize = 1 << BTBIdxLen
105-
106115
// cache
107116
val NWay = 4
108117
val NBank = 4
@@ -131,4 +140,8 @@ trait InstConfig {
131140
val medelegAddr = 0x302.U(CSRAddrLen.W)
132141
val timeCause = "h8000_0000_0000_0007".U(XLen.W)
133142
val ecallCause = "h0000_0000_0000_000b".U(XLen.W)
143+
144+
// special inst
145+
val customInst = "h0000007b".U(InstLen.W)
146+
val haltInst = "h0000006b".U(InstLen.W)
134147
}

‎rtl/tc_l2/src/main/scala/core/Processor.scala

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

66
import difftest._
7-
import treecorel2._
87

98
class Processor extends Module {
109
val io = IO(new Bundle {

‎rtl/tc_l2/src/main/scala/core/StallControl.scala

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
class StallControl extends Module with InstConfig {
7+
val io = IO(new Bundle {
8+
val globalEn = Input(Bool())
9+
val stall = Input(Bool())
10+
val st1 = Output(Bool())
11+
val st2 = Output(Bool())
12+
val st3 = Output(Bool())
13+
})
14+
15+
protected val (tickCnt, cntWrap) = Counter(io.globalEn && io.stall, 3)
16+
protected val cyc1 = io.stall && (tickCnt === 0.U)
17+
protected val cyc2 = io.stall && (tickCnt === 1.U)
18+
protected val cyc3 = io.stall && (tickCnt === 2.U)
19+
20+
io.st1 := cyc1
21+
io.st2 := cyc2
22+
io.st3 := cyc3
23+
}

‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ import chisel3._
44
import chisel3.util._
55
import difftest._
66

7-
class TreeCoreL2 extends Module {
7+
class TreeCoreL2 extends Module with InstConfig {
88
val io = IO(new Bundle {
99
val globalEn = Input(Bool())
1010
val socEn = Input(Bool())
@@ -43,31 +43,29 @@ class TreeCoreL2 extends Module {
4343
exu.io.nxtPC <> ifu.io.nxtPC
4444
exu.io.mtip <> mau.io.mtip
4545

46-
// stall
47-
protected val isStall = exu.io.stall
48-
protected val (tickCnt, cntWrap) = Counter(io.globalEn && isStall, 3)
49-
protected val cyc1 = isStall && (tickCnt === 0.U)
50-
protected val cyc2 = isStall && (tickCnt === 1.U)
51-
protected val cyc3 = isStall && (tickCnt === 2.U)
46+
// stall control
47+
protected val stallCtrl = Module(new StallControl)
48+
stallCtrl.io.globalEn := io.globalEn
49+
stallCtrl.io.stall := exu.io.stall
5250

53-
ifu.io.stall := cyc1
54-
idu.io.stall := cyc1
51+
ifu.io.stall := stallCtrl.io.st1
52+
idu.io.stall := stallCtrl.io.st1
5553
ifu.io.globalEn := io.globalEn
5654
idu.io.globalEn := io.globalEn
57-
exu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
58-
mau.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
59-
wbu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
60-
idu.io.wbdata := Mux(cyc1 || cyc2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
61-
ifu.io.nxtPC := Mux(cyc1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
55+
exu.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
56+
mau.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
57+
wbu.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
58+
idu.io.wbdata := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
59+
ifu.io.nxtPC := Mux(stallCtrl.io.st1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
6260

6361
// special judge
64-
protected val lsStall = RegEnable(cyc1, false.B, io.globalEn) || RegEnable(cyc2, false.B, io.globalEn)
65-
protected val ldDataReg = RegInit(0.U(64.W))
62+
protected val lsStall = RegEnable(stallCtrl.io.st1, false.B, io.globalEn) || RegEnable(stallCtrl.io.st2, false.B, io.globalEn)
63+
protected val ldDataReg = RegInit(0.U(XLen.W))
6664

6765
when(io.globalEn) {
68-
when(cyc1) {
66+
when(stallCtrl.io.st1) {
6967
ldDataReg := io.ld.data
70-
}.elsewhen(cyc3) {
68+
}.elsewhen(stallCtrl.io.st3) {
7169
ldDataReg := 0.U
7270
}
7371
}

‎rtl/tc_l2/src/main/scala/core/exec/ACU.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
// import chisel3._
44
// import chisel3.util._
55

6-
// import treecorel2.common.ConstVal
6+
// import treecorel2.ConstVal
77

88
// class AGU extends Module {
99
// val io = IO(new Bundle {

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