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Replace numStages with more elaborate processor structure info #203
numStages is only sensible for single issue processors. In this commit, we introduce the ProcessorStructure type, a 2d mapping suitable for communicating more information about the datapath of a processor.
1 parent 99bf9ab commit 2048c66

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19 files changed

+416
-332
lines changed

19 files changed

+416
-332
lines changed

‎src/editor/codeeditor.cpp‎

Lines changed: 25 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -442,30 +442,34 @@ void CodeEditor::updateHighlighting() {
442442

443443
// Iterate over the processor stages and use the source mappings to determine
444444
// the source line which originated the instruction.
445-
const unsigned stages = proc->stageCount();
445+
const unsigned stages = proc->structure().numStages();
446446
auto colorGenerator = Colors::incrementalRedGenerator(stages);
447447

448-
for (unsigned sid = 0; sid < stages; sid++) {
449-
const auto stageInfo = proc->stageInfo(sid);
450-
QColor stageColor = colorGenerator();
451-
if (stageInfo.stage_valid) {
452-
auto mappingIt = sourceMapping.find(stageInfo.pc);
453-
if (mappingIt == sourceMapping.end()) {
454-
// No source line registerred for this PC.
455-
continue;
456-
}
457-
458-
for (auto sourceLine : mappingIt->second) {
459-
// Find block
460-
QTextBlock block = document()->findBlockByLineNumber(sourceLine);
461-
if (!block.isValid())
448+
for (auto laneIt : proc->structure()) {
449+
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
450+
StageIndex sid = StageIndex{laneIt.first, stageIdx};
451+
const auto stageInfo = proc->stageInfo(sid);
452+
QColor stageColor = colorGenerator();
453+
if (stageInfo.stage_valid) {
454+
auto mappingIt = sourceMapping.find(stageInfo.pc);
455+
if (mappingIt == sourceMapping.end()) {
456+
// No source line registerred for this PC.
462457
continue;
463-
464-
// Record the stage name for the highlighted block for later painting
465-
QString stageString = ProcessorHandler::getProcessor()->stageName(sid);
466-
if (!stageInfo.namedState.isEmpty())
467-
stageString += " (" + stageInfo.namedState + ")";
468-
highlightBlock(block, stageColor, stageString);
458+
}
459+
460+
for (auto sourceLine : mappingIt->second) {
461+
// Find block
462+
QTextBlock block = document()->findBlockByLineNumber(sourceLine);
463+
if (!block.isValid())
464+
continue;
465+
466+
// Record the stage name for the highlighted block for later painting
467+
QString stageString =
468+
ProcessorHandler::getProcessor()->stageName(sid);
469+
if (!stageInfo.namedState.isEmpty())
470+
stageString += " (" + stageInfo.namedState + ")";
471+
highlightBlock(block, stageColor, stageString);
472+
}
469473
}
470474
}
471475
}

‎src/instructionmodel.cpp‎

Lines changed: 32 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -27,10 +27,12 @@ int InstructionModel::addressToRow(AInt addr) const {
2727

2828
InstructionModel::InstructionModel(QObject *parent)
2929
: QAbstractTableModel(parent) {
30-
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
31-
++i) {
32-
m_stageNames << ProcessorHandler::getProcessor()->stageName(i);
33-
m_stageInfos[i];
30+
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
31+
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
32+
StageIndex idx = {laneIt.first, stageIdx};
33+
m_stageNames[idx] = ProcessorHandler::getProcessor()->stageName(idx);
34+
m_stageInfos[idx] = ProcessorHandler::getProcessor()->stageInfo(idx);
35+
}
3436
}
3537
connect(ProcessorHandler::get(), &ProcessorHandler::procStateChangedNonRun,
3638
this, &InstructionModel::updateStageInfo);
@@ -65,31 +67,33 @@ int InstructionModel::rowCount(const QModelIndex &) const { return m_rowCount; }
6567

6668
void InstructionModel::updateStageInfo() {
6769
bool firstStageChanged = false;
68-
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
69-
++i) {
70-
if (static_cast<unsigned>(m_stageInfos.size()) > i) {
71-
auto &oldStageInfo = m_stageInfos.at(i);
72-
if (i == 0) {
73-
if (oldStageInfo.pc !=
74-
ProcessorHandler::getProcessor()->stageInfo(i).pc) {
75-
firstStageChanged = true;
70+
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
71+
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
72+
StageIndex idx = {laneIt.first, stageIdx};
73+
auto stageInfoIt = m_stageInfos.find(idx);
74+
if (stageInfoIt != m_stageInfos.end()) {
75+
auto &oldStageInfo = m_stageInfos.at(idx);
76+
if (idx == StageIndex(0, 0)) {
77+
if (oldStageInfo.pc !=
78+
ProcessorHandler::getProcessor()->stageInfo(idx).pc) {
79+
firstStageChanged = true;
80+
}
81+
}
82+
const auto stageInfo = ProcessorHandler::getProcessor()->stageInfo(idx);
83+
const AInt oldAddress = oldStageInfo.pc;
84+
if (oldStageInfo != stageInfo) {
85+
oldStageInfo = stageInfo;
86+
const int oldRow = addressToRow(oldAddress);
87+
const int newRow = addressToRow(stageInfo.pc);
88+
const QModelIndex oldIdx = index(oldRow, Stage);
89+
const QModelIndex newIdx = index(newRow, Stage);
90+
emit dataChanged(oldIdx, oldIdx, {Qt::DisplayRole});
91+
emit dataChanged(newIdx, newIdx, {Qt::DisplayRole});
92+
}
93+
if (firstStageChanged) {
94+
emit firstStageInstrChanged(addressToRow(m_stageInfos.at({0, 0}).pc));
95+
firstStageChanged = false;
7696
}
77-
}
78-
const auto stageInfo = ProcessorHandler::getProcessor()->stageInfo(i);
79-
const AInt oldAddress = oldStageInfo.pc;
80-
const bool stageInfoChanged = oldStageInfo != stageInfo;
81-
oldStageInfo = stageInfo;
82-
if (stageInfoChanged) {
83-
const int oldRow = addressToRow(oldAddress);
84-
const int newRow = addressToRow(stageInfo.pc);
85-
const QModelIndex oldIdx = index(oldRow, Stage);
86-
const QModelIndex newIdx = index(newRow, Stage);
87-
emit dataChanged(oldIdx, oldIdx, {Qt::DisplayRole});
88-
emit dataChanged(newIdx, newIdx, {Qt::DisplayRole});
89-
}
90-
if (firstStageChanged) {
91-
emit firstStageInstrChanged(addressToRow(m_stageInfos.at(0).pc));
92-
firstStageChanged = false;
9397
}
9498
}
9599
}

‎src/instructionmodel.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,9 +52,9 @@ class InstructionModel : public QAbstractTableModel {
5252
void onProcessorReset();
5353

5454
std::shared_ptr<const Program> m_program;
55-
QStringList m_stageNames;
55+
std::map<StageIndex, QString> m_stageNames;
5656
using StageID = unsigned;
57-
std::map<StageID, StageInfo> m_stageInfos;
57+
std::map<StageIndex, StageInfo> m_stageInfos;
5858
int m_rowCount = 0;
5959
};
6060
} // namespace Ripes

‎src/pipelinediagrammodel.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -76,10 +76,12 @@ void PipelineDiagramModel::gatherStageInfo() {
7676
if (stageInfoForCycle == m_cycleStageInfos.end()) {
7777
return;
7878
}
79-
for (unsigned i = 0; i < ProcessorHandler::getProcessor()->stageCount();
80-
++i) {
81-
stageInfoForCycle->second[i] =
82-
ProcessorHandler::getProcessor()->stageInfo(i);
79+
for (auto laneIt : ProcessorHandler::getProcessor()->structure()) {
80+
for (unsigned stageIdx = 0; stageIdx < laneIt.second; stageIdx++) {
81+
StageIndex idx = {laneIt.first, stageIdx};
82+
stageInfoForCycle->second[idx] =
83+
ProcessorHandler::getProcessor()->stageInfo(idx);
84+
}
8385
}
8486
}
8587

‎src/pipelinediagrammodel.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ public slots:
3131
* @brief m_cycleStageInfos
3232
* map<cycle, map<stageId, stageInfo>>
3333
*/
34-
std::map<long long, std::map<unsigned, StageInfo>> m_cycleStageInfos;
34+
std::map<long long, std::map<StageIndex, StageInfo>> m_cycleStageInfos;
3535

3636
/**
3737
* @brief m_atMaxCycles

‎src/processorregistry.cpp‎

Lines changed: 54 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,10 @@ ProcessorRegistry::ProcessorRegistry() {
1919
// RISC-V single cycle
2020
layouts = {{"Standard",
2121
":/layouts/RISC-V/rvss/rv_ss_standard_layout.json",
22-
{QPointF{0.5, 0}}},
22+
{{{0, 0}, QPointF{0.5, 0}}}},
2323
{"Extended",
2424
":/layouts/RISC-V/rvss/rv_ss_extended_layout.json",
25-
{QPointF{0.5, 0}}}};
25+
{{{0, 0}, QPointF{0.5, 0}}}}};
2626
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
2727
addProcessor(ProcInfo<vsrtl::core::RVSS<uint32_t>>(
2828
ProcessorID::RV32_SS, "Single-cycle processor",
@@ -35,12 +35,18 @@ ProcessorRegistry::ProcessorRegistry() {
3535
layouts = {
3636
{"Standard",
3737
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_standard_layout.json",
38-
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.54, 0}, QPointF{0.73, 0},
39-
QPointF{0.88, 0}}},
38+
{{{0, 0}, QPointF{0.08, 0}},
39+
{{0, 1}, QPointF{0.3, 0}},
40+
{{0, 2}, QPointF{0.54, 0}},
41+
{{0, 3}, QPointF{0.73, 0}},
42+
{{0, 4}, QPointF{0.88, 0}}}},
4043
{"Extended",
4144
":/layouts/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_extended_layout.json",
42-
{QPointF{0.08, 0.0}, QPointF{0.31, 0.0}, QPointF{0.56, 0.0},
43-
QPointF{0.76, 0.0}, QPointF{0.9, 0.0}}}};
45+
{{{0, 0}, QPointF{0.08, 0.0}},
46+
{{0, 1}, QPointF{0.31, 0.0}},
47+
{{0, 2}, QPointF{0.56, 0.0}},
48+
{{0, 3}, QPointF{0.76, 0.0}},
49+
{{0, 4}, QPointF{0.9, 0.0}}}}};
4450
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
4551
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW_HZ<uint32_t>>(
4652
ProcessorID::RV32_5S_NO_FW_HZ,
@@ -58,12 +64,18 @@ ProcessorRegistry::ProcessorRegistry() {
5864
// RISC-V 5-stage without hazard detection
5965
layouts = {{"Standard",
6066
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_standard_layout.json",
61-
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0},
62-
QPointF{0.75, 0}, QPointF{0.88, 0}}},
67+
{{{0, 0}, QPointF{0.08, 0}},
68+
{{0, 1}, QPointF{0.3, 0}},
69+
{{0, 2}, QPointF{0.53, 0}},
70+
{{0, 3}, QPointF{0.75, 0}},
71+
{{0, 4}, QPointF{0.88, 0}}}},
6372
{"Extended",
6473
":/layouts/RISC-V/rv5s_no_hz/rv5s_no_hz_extended_layout.json",
65-
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0},
66-
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
74+
{{{0, 0}, QPointF{0.08, 0}},
75+
{{0, 1}, QPointF{0.28, 0}},
76+
{{0, 2}, QPointF{0.53, 0}},
77+
{{0, 3}, QPointF{0.78, 0}},
78+
{{0, 4}, QPointF{0.9, 0}}}}};
6779
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
6880
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_HZ<uint32_t>>(
6981
ProcessorID::RV32_5S_NO_HZ, "5-stage processor w/o hazard detection",
@@ -79,12 +91,18 @@ ProcessorRegistry::ProcessorRegistry() {
7991
// RISC-V 5-stage without forwarding unit
8092
layouts = {{"Standard",
8193
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_standard_layout.json",
82-
{QPointF{0.08, 0}, QPointF{0.3, 0}, QPointF{0.53, 0},
83-
QPointF{0.75, 0}, QPointF{0.88, 0}}},
94+
{{{0, 0}, QPointF{0.08, 0}},
95+
{{0, 1}, QPointF{0.3, 0}},
96+
{{0, 2}, QPointF{0.53, 0}},
97+
{{0, 3}, QPointF{0.75, 0}},
98+
{{0, 4}, QPointF{0.88, 0}}}},
8499
{"Extended",
85100
":/layouts/RISC-V/rv5s_no_fw/rv5s_no_fw_extended_layout.json",
86-
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.53, 0},
87-
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
101+
{{{0, 0}, QPointF{0.08, 0}},
102+
{{0, 1}, QPointF{0.28, 0}},
103+
{{0, 2}, QPointF{0.53, 0}},
104+
{{0, 3}, QPointF{0.78, 0}},
105+
{{0, 4}, QPointF{0.9, 0}}}}};
88106
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
89107
addProcessor(ProcInfo<vsrtl::core::RV5S_NO_FW<uint32_t>>(
90108
ProcessorID::RV32_5S_NO_FW, "5-Stage processor w/o forwarding unit",
@@ -100,12 +118,18 @@ ProcessorRegistry::ProcessorRegistry() {
100118
// RISC-V 5-stage
101119
layouts = {{"Standard",
102120
":/layouts/RISC-V/rv5s/rv5s_standard_layout.json",
103-
{QPointF{0.08, 0}, QPointF{0.29, 0}, QPointF{0.55, 0},
104-
QPointF{0.75, 0}, QPointF{0.87, 0}}},
121+
{{{0, 0}, QPointF{0.08, 0}},
122+
{{0, 1}, QPointF{0.29, 0}},
123+
{{0, 2}, QPointF{0.55, 0}},
124+
{{0, 3}, QPointF{0.75, 0}},
125+
{{0, 4}, QPointF{0.87, 0}}}},
105126
{"Extended",
106127
":/layouts/RISC-V/rv5s/rv5s_extended_layout.json",
107-
{QPointF{0.08, 0}, QPointF{0.28, 0}, QPointF{0.54, 0},
108-
QPointF{0.78, 0}, QPointF{0.9, 0}}}};
128+
{{{0, 1}, QPointF{0.08, 0}},
129+
{{0, 2}, QPointF{0.28, 0}},
130+
{{0, 3}, QPointF{0.54, 0}},
131+
{{0, 4}, QPointF{0.78, 0}},
132+
{{0, 5}, QPointF{0.9, 0}}}}};
109133
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
110134
addProcessor(ProcInfo<vsrtl::core::RV5S<uint32_t>>(
111135
ProcessorID::RV32_5S, "5-stage processor",
@@ -121,10 +145,18 @@ ProcessorRegistry::ProcessorRegistry() {
121145
// RISC-V 6-stage dual issue
122146
layouts = {{"Extended",
123147
":/layouts/RISC-V/rv6s_dual/rv6s_dual_extended_layout.json",
124-
{{QPointF{0.06, 0}, QPointF{0.06, 1}, QPointF{0.22, 0},
125-
QPointF{0.22, 1}, QPointF{0.40, 0}, QPointF{0.40, 1},
126-
QPointF{0.59, 0}, QPointF{0.59, 1}, QPointF{0.80, 0},
127-
QPointF{0.80, 1}, QPointF{0.90, 0}, QPointF{0.90, 1}}}}};
148+
{{{{0, 0}, QPointF{0.06, 0}},
149+
{{1, 0}, QPointF{0.06, 1}},
150+
{{0, 1}, QPointF{0.22, 0}},
151+
{{1, 1}, QPointF{0.22, 1}},
152+
{{0, 2}, QPointF{0.40, 0}},
153+
{{1, 2}, QPointF{0.40, 1}},
154+
{{0, 3}, QPointF{0.59, 0}},
155+
{{1, 3}, QPointF{0.59, 1}},
156+
{{0, 4}, QPointF{0.80, 0}},
157+
{{1, 4}, QPointF{0.80, 1}},
158+
{{0, 5}, QPointF{0.90, 0}},
159+
{{1, 5}, QPointF{0.90, 1}}}}}};
128160
defRegVals = {{2, 0x7ffffff0}, {3, 0x10000000}};
129161
addProcessor(ProcInfo<vsrtl::core::RV6S_DUAL<uint32_t>>(
130162
ProcessorID::RV32_6S_DUAL, "6-stage dual-issue processor",

‎src/processorregistry.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ struct Layout {
4545
* labels can be "stacked" over one another. Must contain an entry for each
4646
* stage in the processor model.
4747
*/
48-
std::vector<QPointF> stageLabelPositions;
48+
std::map<StageIndex, QPointF> stageLabelPositions;
4949
bool operator==(const Layout &rhs) const { return this->name == rhs.name; }
5050
};
5151

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