FreHD - leaving out BS170 #11
Description
Hi, my name is Brad. I've done a build of your repo on PCBWay (hope you got your commission!).
I have been studying the eliding of Q1 and R15 from the build. (I got a bit into it because it turns out that PCBWay installed R15, so I had to back it out.)
But as I've dug in, I'm concerned that shorting out Q1 could impact reliable operation. I wanted to share my thinking and get your feedback on it. I would not be at all surprised if I'm missing something.
What I found in my digging was:
- The SPI_SDI signal is connected to pin RC4.
- RC4 (and all of port C) have Schmitt trigger inputs (PCI datasheet section 9.3)
- VIH for Schmitt trigger inputs is spec'ed as 0.8VDD min (param "D041"), datasheet section 26.3), which is 4V
Thoughts? I understand why Q1 was left out - the gate is supposed to be tied directly to 3V3, rather than to SPI_SDI. I am wondering if the "best" fix for me would be to install Q1 but pull up the gate pin and haywire it to 3V3.