diff --git a/.gitignore b/.gitignore index c3415bbd5..f35844023 100644 --- a/.gitignore +++ b/.gitignore @@ -20,3 +20,7 @@ localrepos.cmake *.pyc .clang-format +**/.DS_Store + +# Python venv +venv diff --git a/bl2/ext/mcuboot/Kconfig b/bl2/ext/mcuboot/Kconfig index 21adf4525..28fe0b27c 100644 --- a/bl2/ext/mcuboot/Kconfig +++ b/bl2/ext/mcuboot/Kconfig @@ -137,6 +137,7 @@ config MCUBOOT_CONFIRM_IMAGE config MCUBOOT_DIRECT_XIP_REVERT bool "Enable the revert mechanism in direct-xip mode" default y + depends on MCUBOOT_UPGRADE_STRATEGY_DIRECT_XIP config MCUBOOT_HW_ROLLBACK_PROT bool "Enable security counter validation against non-volatile HW counters" diff --git a/bl2/ext/mcuboot/config/mcuboot-mbedtls-cfg.h b/bl2/ext/mcuboot/config/mcuboot-mbedtls-cfg.h index 4dcc50f95..6aaaf47d0 100644 --- a/bl2/ext/mcuboot/config/mcuboot-mbedtls-cfg.h +++ b/bl2/ext/mcuboot/config/mcuboot-mbedtls-cfg.h @@ -51,6 +51,7 @@ #define MBEDTLS_ENTROPY_C #define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG #define MBEDTLS_PSA_CRYPTO_CONFIG +#define MBEDTLS_PSA_CRYPTO_C #if defined(MCUBOOT_SIGN_EC256) #define MBEDTLS_PSA_P256M_DRIVER_ENABLED #endif diff --git a/bl2/ext/mcuboot/flash_map_extended.c b/bl2/ext/mcuboot/flash_map_extended.c index a139a0588..d942774e6 100644 --- a/bl2/ext/mcuboot/flash_map_extended.c +++ b/bl2/ext/mcuboot/flash_map_extended.c @@ -12,6 +12,7 @@ * Git SHA of the original version: ac55554059147fff718015be9f4bd3108123f50a */ +#include #include #include "target.h" #include "tfm_hal_device_header.h" @@ -28,6 +29,9 @@ __WEAK int flash_device_base(uint8_t fd_id, uintptr_t *ret) fd_id, FLASH_DEVICE_ID); return -1; } + + assert(ret != NULL); + *ret = FLASH_DEVICE_BASE; return 0; } @@ -73,6 +77,8 @@ int flash_area_id_to_image_slot(int area_id) uint8_t flash_area_erased_val(const struct flash_area *fap) { + assert(fap != NULL); + return DRV_FLASH_AREA(fap)->GetInfo()->erased_value; } @@ -100,3 +106,15 @@ int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off, return 1; } + +int flash_area_get_sector(const struct flash_area *fa, uint32_t off, + struct flash_sector *sector) +{ + assert ((fa != NULL) && (sector != NULL)); + + sector->fs_off = (off / DRV_FLASH_AREA(fa)->GetInfo()->sector_size) * + DRV_FLASH_AREA(fa)->GetInfo()->sector_size; + sector->fs_size = DRV_FLASH_AREA(fa)->GetInfo()->sector_size; + + return 0; +} diff --git a/bl2/ext/mcuboot/include/flash_map/flash_map.h b/bl2/ext/mcuboot/include/flash_map/flash_map.h index 40beab061..0168dafb4 100644 --- a/bl2/ext/mcuboot/include/flash_map/flash_map.h +++ b/bl2/ext/mcuboot/include/flash_map/flash_map.h @@ -64,11 +64,11 @@ extern "C" { /* * Shared data area between bootloader and runtime firmware. */ -#if (defined(BOOT_TFM_SHARED_DATA_BASE) && defined(BOOT_TFM_SHARED_DATA_SIZE)) -#define MCUBOOT_SHARED_DATA_BASE BOOT_TFM_SHARED_DATA_BASE -#define MCUBOOT_SHARED_DATA_SIZE BOOT_TFM_SHARED_DATA_SIZE +#if (defined(SHARED_BOOT_MEASUREMENT_BASE) && defined(SHARED_BOOT_MEASUREMENT_SIZE)) +#define MCUBOOT_SHARED_DATA_BASE SHARED_BOOT_MEASUREMENT_BASE +#define MCUBOOT_SHARED_DATA_SIZE SHARED_BOOT_MEASUREMENT_SIZE #else -#error "BOOT_TFM_SHARED_DATA_* must be defined by target." +#error "SHARED_BOOT_MEASUREMENT_* must be defined by target." #endif /** diff --git a/bl2/ext/mcuboot/mcuboot_default_config.cmake b/bl2/ext/mcuboot/mcuboot_default_config.cmake index 5d769f189..cab7a092d 100644 --- a/bl2/ext/mcuboot/mcuboot_default_config.cmake +++ b/bl2/ext/mcuboot/mcuboot_default_config.cmake @@ -35,7 +35,7 @@ set_property(CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS "OVERWRITE_ONLY;SWA # platforms requiring specific flash alignmnent set_property(CACHE MCUBOOT_ALIGN_VAL PROPERTY STRINGS "1;2;4;8;16;32") -set(MCUBOOT_DIRECT_XIP_REVERT ON CACHE BOOL "Enable the revert mechanism in direct-xip mode") +set(MCUBOOT_DIRECT_XIP_REVERT OFF CACHE BOOL "Enable the revert mechanism in direct-xip mode") set(MCUBOOT_HW_ROLLBACK_PROT ON CACHE BOOL "Enable security counter validation against non-volatile HW counters") set(MCUBOOT_ENC_IMAGES OFF CACHE BOOL "Enable encrypted image upgrade support") set(MCUBOOT_BOOTSTRAP OFF CACHE BOOL "Support initial state with empty primary slot and images installed from secondary slots") diff --git a/bl2/ext/mcuboot/scripts/wrapper/wrapper.py b/bl2/ext/mcuboot/scripts/wrapper/wrapper.py index 9622c4b84..378be606e 100644 --- a/bl2/ext/mcuboot/scripts/wrapper/wrapper.py +++ b/bl2/ext/mcuboot/scripts/wrapper/wrapper.py @@ -100,9 +100,9 @@ def wrap(key, align, version, header_size, pad_header, layout, pad, confirm, rom_fixed = macro_parser.evaluate_macro(layout, rom_fixed_re, 0, 1) if measured_boot_record: - if "_s" in layout: + if "_s.o" in layout: record_sw_type = "SPE" - elif "_ns" in layout: + elif "_ns.o" in layout: record_sw_type = "NSPE" else: record_sw_type = "NSPE_SPE" diff --git a/bl2/src/shared_data.c b/bl2/src/shared_data.c index 6eaeb1325..56321186b 100644 --- a/bl2/src/shared_data.c +++ b/bl2/src/shared_data.c @@ -170,15 +170,14 @@ static int collect_image_measurement_and_metadata( * @param[in] hdr Pointer to the image header stored in RAM. * @param[in] fap Pointer to the flash area where image is stored. * @param[in] active_slot Which slot is active (to boot). - * @param[in] max_app_size Maximum allowed size of application for update - * slot. + * @param[in] max_app_sizes The maximum sizes of images that can be loaded. * * @return 0 on success; nonzero on failure. */ int boot_save_shared_data(const struct image_header *hdr, const struct flash_area *fap, const uint8_t active_slot, - const int max_app_size) + const struct image_max_size *max_app_sizes) { const struct flash_area *temp_fap; uint8_t mcuboot_image_id = 0; @@ -201,7 +200,7 @@ int boot_save_shared_data(const struct image_header *hdr, #endif /* TFM_MEASURED_BOOT_API */ (void)active_slot; - (void)max_app_size; + (void)max_app_sizes; if (hdr == NULL || fap == NULL) { return -1; diff --git a/bl2/src/thin_psa_crypto_core.c b/bl2/src/thin_psa_crypto_core.c index 6fa03c929..6bf2f4461 100644 --- a/bl2/src/thin_psa_crypto_core.c +++ b/bl2/src/thin_psa_crypto_core.c @@ -165,9 +165,7 @@ psa_status_t psa_hash_setup(psa_hash_operation_t *operation, status = psa_driver_wrapper_hash_setup(operation, alg); - if (status != PSA_SUCCESS) { - psa_hash_abort(operation); - } + assert(status == PSA_SUCCESS); return status; } @@ -189,9 +187,7 @@ psa_status_t psa_hash_update(psa_hash_operation_t *operation, status = psa_driver_wrapper_hash_update(operation, input, input_length); - if (status != PSA_SUCCESS) { - psa_hash_abort(operation); - } + assert(status == PSA_SUCCESS); return status; } @@ -349,28 +345,6 @@ psa_status_t mbedtls_to_psa_error(int ret) } } -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -int mbedtls_psa_get_random(void *p_rng, - unsigned char *output, - size_t output_size) -{ - /* This function takes a pointer to the RNG state because that's what - * classic mbedtls functions using an RNG expect. The PSA RNG manages - * its own state internally and doesn't let the caller access that state. - * So we just ignore the state parameter, and in practice we'll pass - * NULL. - */ - (void) p_rng; - psa_status_t status = psa_generate_random(output, output_size); - - if (status == PSA_SUCCESS) { - return 0; - } else { - return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; - } -} -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - psa_status_t psa_generate_random(uint8_t *output, size_t output_size) { @@ -446,86 +420,6 @@ psa_status_t psa_verify_hash_builtin( return PSA_ERROR_NOT_SUPPORTED; } -/* Required when Mbed TLS backend converts from PSA to Mbed TLS native */ -mbedtls_ecp_group_id mbedtls_ecc_group_from_psa(psa_ecc_family_t family, - size_t bits) -{ - switch (family) { - case PSA_ECC_FAMILY_SECP_R1: - switch (bits) { -#if defined(PSA_WANT_ECC_SECP_R1_192) - case 192: - return MBEDTLS_ECP_DP_SECP192R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_224) - case 224: - return MBEDTLS_ECP_DP_SECP224R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_256) - case 256: - return MBEDTLS_ECP_DP_SECP256R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_384) - case 384: - return MBEDTLS_ECP_DP_SECP384R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_521) - case 521: - return MBEDTLS_ECP_DP_SECP521R1; -#endif - } - break; - - case PSA_ECC_FAMILY_BRAINPOOL_P_R1: - switch (bits) { -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) - case 256: - return MBEDTLS_ECP_DP_BP256R1; -#endif -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) - case 384: - return MBEDTLS_ECP_DP_BP384R1; -#endif -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) - case 512: - return MBEDTLS_ECP_DP_BP512R1; -#endif - } - break; - - case PSA_ECC_FAMILY_MONTGOMERY: - switch (bits) { -#if defined(PSA_WANT_ECC_MONTGOMERY_255) - case 255: - return MBEDTLS_ECP_DP_CURVE25519; -#endif -#if defined(PSA_WANT_ECC_MONTGOMERY_448) - case 448: - return MBEDTLS_ECP_DP_CURVE448; -#endif - } - break; - - case PSA_ECC_FAMILY_SECP_K1: - switch (bits) { -#if defined(PSA_WANT_ECC_SECP_K1_192) - case 192: - return MBEDTLS_ECP_DP_SECP192K1; -#endif -#if defined(PSA_WANT_ECC_SECP_K1_224) - /* secp224k1 is not and will not be supported in PSA (#3541). */ -#endif -#if defined(PSA_WANT_ECC_SECP_K1_256) - case 256: - return MBEDTLS_ECP_DP_SECP256K1; -#endif - } - break; - } - - return MBEDTLS_ECP_DP_NONE; -} - /* We don't need the full driver wrapper, we know the key is already a public key */ psa_status_t psa_driver_wrapper_export_public_key( const psa_key_attributes_t *attributes, diff --git a/cmake/install.cmake b/cmake/install.cmake index 0297080f1..30c3e6024 100644 --- a/cmake/install.cmake +++ b/cmake/install.cmake @@ -7,9 +7,6 @@ # #------------------------------------------------------------------------------- -# Skip "up-to-date" prints to avoid flooding the build output. Just print "installing" -set(CMAKE_INSTALL_MESSAGE LAZY) - install(DIRECTORY ${CMAKE_BINARY_DIR}/bin/ DESTINATION bin ) @@ -75,33 +72,40 @@ if (TFM_PARTITION_INTERNAL_TRUSTED_STORAGE) endif() if (TFM_PARTITION_CRYPTO) - install(FILES ${INTERFACE_INC_DIR}/psa/README.rst - ${INTERFACE_INC_DIR}/psa/build_info.h - ${INTERFACE_INC_DIR}/psa/crypto.h - ${INTERFACE_INC_DIR}/psa/crypto_adjust_auto_enabled.h - ${INTERFACE_INC_DIR}/psa/crypto_adjust_config_key_pair_types.h - ${INTERFACE_INC_DIR}/psa/crypto_adjust_config_synonyms.h - ${INTERFACE_INC_DIR}/psa/crypto_builtin_composites.h - ${INTERFACE_INC_DIR}/psa/crypto_builtin_key_derivation.h - ${INTERFACE_INC_DIR}/psa/crypto_builtin_primitives.h - ${INTERFACE_INC_DIR}/psa/crypto_compat.h - ${INTERFACE_INC_DIR}/psa/crypto_driver_common.h - ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_composites.h - ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_key_derivation.h - ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_primitives.h - ${INTERFACE_INC_DIR}/psa/crypto_extra.h - ${INTERFACE_INC_DIR}/psa/crypto_legacy.h - ${INTERFACE_INC_DIR}/psa/crypto_platform.h - ${INTERFACE_INC_DIR}/psa/crypto_se_driver.h - ${INTERFACE_INC_DIR}/psa/crypto_sizes.h - ${INTERFACE_INC_DIR}/psa/crypto_struct.h - ${INTERFACE_INC_DIR}/psa/crypto_types.h - ${INTERFACE_INC_DIR}/psa/crypto_values.h - DESTINATION ${INSTALL_INTERFACE_INC_DIR}/psa) - install(FILES ${INTERFACE_INC_DIR}/tfm_crypto_defs.h - DESTINATION ${INSTALL_INTERFACE_INC_DIR}) - install(DIRECTORY ${INTERFACE_INC_DIR}/mbedtls - DESTINATION ${INSTALL_INTERFACE_INC_DIR}) + if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core_install.cmake) + install(FILES ${INTERFACE_INC_DIR}/tfm_crypto_defs.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR}) + else() + install(FILES ${INTERFACE_INC_DIR}/psa/README.rst + ${INTERFACE_INC_DIR}/psa/build_info.h + ${INTERFACE_INC_DIR}/psa/crypto.h + ${INTERFACE_INC_DIR}/psa/crypto_adjust_auto_enabled.h + ${INTERFACE_INC_DIR}/psa/crypto_adjust_config_dependencies.h + ${INTERFACE_INC_DIR}/psa/crypto_adjust_config_key_pair_types.h + ${INTERFACE_INC_DIR}/psa/crypto_adjust_config_synonyms.h + ${INTERFACE_INC_DIR}/psa/crypto_builtin_composites.h + ${INTERFACE_INC_DIR}/psa/crypto_builtin_key_derivation.h + ${INTERFACE_INC_DIR}/psa/crypto_builtin_primitives.h + ${INTERFACE_INC_DIR}/psa/crypto_compat.h + ${INTERFACE_INC_DIR}/psa/crypto_driver_common.h + ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_composites.h + ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_key_derivation.h + ${INTERFACE_INC_DIR}/psa/crypto_driver_contexts_primitives.h + ${INTERFACE_INC_DIR}/psa/crypto_extra.h + ${INTERFACE_INC_DIR}/psa/crypto_legacy.h + ${INTERFACE_INC_DIR}/psa/crypto_platform.h + ${INTERFACE_INC_DIR}/psa/crypto_se_driver.h + ${INTERFACE_INC_DIR}/psa/crypto_sizes.h + ${INTERFACE_INC_DIR}/psa/crypto_struct.h + ${INTERFACE_INC_DIR}/psa/crypto_types.h + ${INTERFACE_INC_DIR}/psa/crypto_values.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR}/psa) + install(FILES ${INTERFACE_INC_DIR}/tfm_crypto_defs.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR}) + install(DIRECTORY ${INTERFACE_INC_DIR}/mbedtls + DESTINATION ${INSTALL_INTERFACE_INC_DIR}) + endif() endif() if (TFM_PARTITION_INITIAL_ATTESTATION) @@ -284,10 +288,11 @@ else() ) endif() +# PSA_CRYPTO_EXTERNAL_CORE target_include_directories(psa_interface INTERFACE $ - ) +) install(EXPORT tfm-config FILE spe_export.cmake diff --git a/cmake/spe-CMakeLists.cmake b/cmake/spe-CMakeLists.cmake index cb0d36e98..959912cbd 100644 --- a/cmake/spe-CMakeLists.cmake +++ b/cmake/spe-CMakeLists.cmake @@ -34,6 +34,15 @@ target_sources(tfm_api_ns ) # Include interface headers exported by TF-M +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_include_directories(tfm_api_ns + PUBLIC + ${INTERFACE_INC_DIR} + ) +endif() + target_include_directories(tfm_api_ns PUBLIC ${INTERFACE_INC_DIR} diff --git a/cmake/version.cmake b/cmake/version.cmake index a5f5d236c..5d77c6c45 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -6,28 +6,11 @@ #------------------------------------------------------------------------------- # The 'TFM_VERSION_MANUAL' is used for fallback when Git tags are not available -set(TFM_VERSION_MANUAL "2.1.0") +set(TFM_VERSION_MANUAL "2.1.2") -execute_process(COMMAND git describe --tags --always - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - OUTPUT_VARIABLE TFM_VERSION_FULL - OUTPUT_STRIP_TRAILING_WHITESPACE) - -# In a repository cloned with --no-tags option TFM_VERSION_FULL will be a hash -# only hence checking it for a tag format to accept as valid version. - -string(FIND ${TFM_VERSION_FULL} "TF-M" TFM_TAG) -if(TFM_TAG EQUAL -1) - set(TFM_VERSION_FULL v${TFM_VERSION_MANUAL}) - message(WARNING "Actual TF-M version is not available from Git repository. Settled to " ${TFM_VERSION_FULL}) -endif() +set(TFM_VERSION_FULL v${TFM_VERSION_MANUAL}) string(REGEX REPLACE "TF-M" "" TFM_VERSION_FULL ${TFM_VERSION_FULL}) # remove a commit number string(REGEX REPLACE "-[0-9]+-g" "+" TFM_VERSION_FULL ${TFM_VERSION_FULL}) string(REGEX MATCH "[0-9]+\\.[0-9]+\\.[0-9]+" TFM_VERSION ${TFM_VERSION_FULL}) - -# Check that manually set version is up to date -if (NOT TFM_VERSION_MANUAL STREQUAL TFM_VERSION) - message(WARNING "TFM_VERSION_MANUAL mismatches to actual TF-M version. Please update TFM_VERSION_MANUAL in cmake/version.cmake") -endif() diff --git a/config/check_config.cmake b/config/check_config.cmake index 1039b22f9..2bd1453ac 100644 --- a/config/check_config.cmake +++ b/config/check_config.cmake @@ -17,6 +17,8 @@ tfm_invalid_config(TFM_MULTI_CORE_TOPOLOGY AND TFM_NS_MANAGE_NSID) tfm_invalid_config(TFM_PLAT_SPECIFIC_MULTI_CORE_COMM AND NOT TFM_MULTI_CORE_TOPOLOGY) tfm_invalid_config(TFM_ISOLATION_LEVEL EQUAL 3 AND CONFIG_TFM_STACK_WATERMARKS) +tfm_invalid_config(CONFIG_TFM_LOG_SHARE_UART AND NOT SECURE_UART1) + ########################## BL1 ################################################# tfm_invalid_config(TFM_BL1_2_IN_OTP AND TFM_BL1_2_IN_FLASH) @@ -25,6 +27,7 @@ tfm_invalid_config(TFM_BL1_2_IN_OTP AND TFM_BL1_2_IN_FLASH) get_property(MCUBOOT_STRATEGY_LIST CACHE MCUBOOT_UPGRADE_STRATEGY PROPERTY STRINGS) tfm_invalid_config(BL2 AND (NOT MCUBOOT_UPGRADE_STRATEGY IN_LIST MCUBOOT_STRATEGY_LIST) AND NOT USE_KCONFIG_TOOL) +tfm_invalid_config(BL2 AND (NOT MCUBOOT_UPGRADE_STRATEGY STREQUAL "DIRECT_XIP" AND MCUBOOT_DIRECT_XIP_REVERT)) # Maximum number of MCUBoot images supported by TF-M NV counters and ROTPKs tfm_invalid_config(MCUBOOT_IMAGE_NUMBER GREATER 9) diff --git a/config/config_base.cmake b/config/config_base.cmake index 72f36bc15..748b590f2 100644 --- a/config/config_base.cmake +++ b/config/config_base.cmake @@ -30,16 +30,19 @@ set(INSTALL_PLATFORM_NS_DIR ${CMAKE_INSTALL_PREFIX}/platform) set(TFM_DEBUG_SYMBOLS ON CACHE BOOL "Add debug symbols. Note that setting CMAKE_BUILD_TYPE to Debug or RelWithDebInfo will also add debug symbols.") set(TFM_CODE_COVERAGE OFF CACHE BOOL "Whether to build the binary for lcov tools") +set(TFM_TESTS_REVISION_CHECKS ON CACHE BOOL "Whether to perform checks on the tf-m-tests repository revision.") + set(PROJECT_CONFIG_HEADER_FILE "" CACHE FILEPATH "User defined header file for TF-M config") # External libraries source and version set(MBEDCRYPTO_PATH "DOWNLOAD" CACHE PATH "Path to Mbed Crypto (or DOWNLOAD to fetch automatically") set(MBEDCRYPTO_FORCE_PATCH OFF CACHE BOOL "Always apply MBed Crypto patches") -set(MBEDCRYPTO_VERSION "mbedtls-3.6.0" CACHE STRING "The version of Mbed Crypto to use") +# TODO update to "mbedtls-3.6.3" after release, +set(MBEDCRYPTO_VERSION "f985bee" CACHE STRING "The version of Mbed Crypto to use") set(MBEDCRYPTO_GIT_REMOTE "https://github.com/Mbed-TLS/mbedtls.git" CACHE STRING "The URL (or path) to retrieve MbedTLS from.") set(MCUBOOT_PATH "DOWNLOAD" CACHE PATH "Path to MCUboot (or DOWNLOAD to fetch automatically") -set(MCUBOOT_VERSION "v2.1.0" CACHE STRING "The version of MCUboot to use") +set(MCUBOOT_VERSION "6071ceb" CACHE STRING "The version of MCUboot to use") set(PLATFORM_PSA_ADAC_SECURE_DEBUG FALSE CACHE BOOL "Whether to use psa-adac secure debug.") set(PLATFORM_PSA_ADAC_SOURCE_PATH "DOWNLOAD" CACHE PATH "Path to source dir of psa-adac.") @@ -88,6 +91,7 @@ set(CONFIG_TFM_HALT_ON_CORE_PANIC OFF CACHE BOOL "On fatal e set(CONFIG_TFM_STACK_WATERMARKS OFF CACHE BOOL "Whether to pre-fill partition stacks with a set value to help determine stack usage") +set(CONFIG_TFM_LOG_SHARE_UART OFF CACHE BOOL "Allow TF-M and the non-secure application to share the UART instance. TF-M will use it while it is booting, after which the non-secure application will use it until an eventual fatal error is handled and logged by TF-M. Logging from TF-M will therefore otherwise be suppressed") ############################ Platform ########################################## set(NUM_MAILBOX_QUEUE_SLOT 1 CACHE BOOL "Number of mailbox queue slots") @@ -115,6 +119,7 @@ set(PLATFORM_DEFAULT_OTP_WRITEABLE ON CACHE BOOL "Use OTP mem set(PLATFORM_DEFAULT_PROVISIONING ON CACHE BOOL "Use default provisioning implementation") set(PLATFORM_DEFAULT_SYSTEM_RESET_HALT ON CACHE BOOL "Use default system reset/halt implementation") set(PLATFORM_DEFAULT_IMAGE_SIGNING ON CACHE BOOL "Use default image signing implementation") +set(PLATFORM_DEFAULT_PROV_LINKER_SCRIPT ON CACHE BOOL "Use default provisioning linker script") set(TFM_DUMMY_PROVISIONING ON CACHE BOOL "Provision with dummy values. NOT to be used in production") @@ -128,6 +133,7 @@ set(BL2_TRAILER_SIZE 0x000 CACHE STRING "BL2 Trailer set(TFM_PARTITION_PROTECTED_STORAGE OFF CACHE BOOL "Enable Protected Storage partition") set(PS_ENCRYPTION ON CACHE BOOL "Enable encryption for Protected Storage partition") set(PS_CRYPTO_AEAD_ALG PSA_ALG_GCM CACHE STRING "The AEAD algorithm to use for authenticated encryption in Protected Storage") +set(PS_CRYPTO_KDF_ALG PSA_ALG_HKDF\(PSA_ALG_SHA_256\) CACHE STRING "KDF Algorithm to use for Protect Storage") set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE OFF CACHE BOOL "Enable Internal Trusted Storage partition") set(ITS_ENCRYPTION OFF CACHE BOOL "Enable authenticated encryption of ITS files using platform specific APIs") diff --git a/config/config_base.h b/config/config_base.h index ac96b743a..8488f402e 100644 --- a/config/config_base.h +++ b/config/config_base.h @@ -36,11 +36,12 @@ /* Crypto Partition Configs */ /* - * Heap size for the crypto backend - * CRYPTO_ENGINE_BUF_SIZE needs to be >8KB for EC signing by attest module. + * Heap size for the crypto backend. This is statically allocated + * inside the Crypto service and used as heap through the default + * Mbed TLS allocator */ #ifndef CRYPTO_ENGINE_BUF_SIZE -#define CRYPTO_ENGINE_BUF_SIZE 0x2080 +#define CRYPTO_ENGINE_BUF_SIZE 0x3000 #endif /* The max number of concurrent operations that can be active (allocated) at any time in Crypto */ @@ -111,9 +112,19 @@ #define CRYPTO_SINGLE_PART_FUNCS_DISABLED 0 #endif +/* + * The service assumes that the client interface and internal + * interface towards the library that provides the PSA Crypto + * core component maintain the same ABI. This is not the default + * when using the Mbed TLS reference implementation + */ +#ifndef CRYPTO_LIBRARY_ABI_COMPAT +#define CRYPTO_LIBRARY_ABI_COMPAT (0) +#endif + /* The stack size of the Crypto Secure Partition */ #ifndef CRYPTO_STACK_SIZE -#define CRYPTO_STACK_SIZE 0x1B00 +#define CRYPTO_STACK_SIZE 0x1800 #endif /* FWU Partition Configs */ @@ -197,6 +208,11 @@ #define TFM_ITS_AUTH_TAG_LENGTH 16 #endif +/* The size of the key used when authentication/encryption of ITS files is enabled */ +#ifndef TFM_ITS_KEY_LENGTH +#define TFM_ITS_KEY_LENGTH 16 +#endif + /* The size of the nonce used when ITS file encryption is enabled */ #ifndef TFM_ITS_ENC_NONCE_LENGTH #define TFM_ITS_ENC_NONCE_LENGTH 12 diff --git a/config/profile/config_profile_large.h b/config/profile/config_profile_large.h index 948b0407f..327de67a0 100644 --- a/config/profile/config_profile_large.h +++ b/config/profile/config_profile_large.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,11 +33,22 @@ /* Crypto Partition Configs */ /* - * Heap size for the crypto backend - * CRYPTO_ENGINE_BUF_SIZE needs to be >8KB for EC signing by attest module. + * The service assumes that the client interface and internal + * interface towards the library that provides the PSA Crypto + * core component maintain the same ABI. This is not the default + * when using the Mbed TLS reference implementation + */ +#ifndef CRYPTO_LIBRARY_ABI_COMPAT +#define CRYPTO_LIBRARY_ABI_COMPAT (0) +#endif + +/* + * Heap size for the crypto backend. This is statically allocated + * inside the Crypto service and used as heap through the default + * Mbed TLS allocator */ #ifndef CRYPTO_ENGINE_BUF_SIZE -#define CRYPTO_ENGINE_BUF_SIZE 0x2380 +#define CRYPTO_ENGINE_BUF_SIZE 0x3000 #endif /* The max number of concurrent operations that can be active (allocated) at any time in Crypto */ @@ -100,6 +111,11 @@ #define CRYPTO_NV_SEED 1 #endif +/* Use external RNG to provide entropy */ +#ifndef CRYPTO_EXT_RNG +#define CRYPTO_EXT_RNG 0 +#endif + /* * Only enable multi-part operations in Hash, MAC, AEAD and symmetric ciphers, * to optimize memory footprint in resource-constrained devices. @@ -110,7 +126,7 @@ /* The stack size of the Crypto Secure Partition */ #ifndef CRYPTO_STACK_SIZE -#define CRYPTO_STACK_SIZE 0x1B00 +#define CRYPTO_STACK_SIZE 0x1800 #endif /* FWU Partition Configs */ @@ -185,7 +201,11 @@ /* The stack size of the Internal Trusted Storage Secure Partition */ #ifndef ITS_STACK_SIZE +#ifndef ITS_ENCRYPTION #define ITS_STACK_SIZE 0x720 +#else +#define ITS_STACK_SIZE 0xC00 +#endif #endif /* PS Partition Configs */ diff --git a/config/profile/config_profile_medium.h b/config/profile/config_profile_medium.h index 4787c627f..56fd11985 100644 --- a/config/profile/config_profile_medium.h +++ b/config/profile/config_profile_medium.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,9 @@ /* Crypto Partition Configs */ /* - * Heap size for the crypto backend - * CRYPTO_ENGINE_BUF_SIZE needs to be >8KB for EC signing by attest module. + * Heap size for the crypto backend. This is statically allocated + * inside the Crypto service and used as heap through the default + * Mbed TLS allocator */ #ifndef CRYPTO_ENGINE_BUF_SIZE #define CRYPTO_ENGINE_BUF_SIZE 0x2080 @@ -100,6 +101,11 @@ #define CRYPTO_NV_SEED 1 #endif +/* Use external RNG to provide entropy */ +#ifndef CRYPTO_EXT_RNG +#define CRYPTO_EXT_RNG 0 +#endif + /* * Only enable multi-part operations in Hash, MAC, AEAD and symmetric ciphers, * to optimize memory footprint in resource-constrained devices. @@ -108,9 +114,19 @@ #define CRYPTO_SINGLE_PART_FUNCS_DISABLED 0 #endif +/* + * The service assumes that the client interface and internal + * interface towards the library that provides the PSA Crypto + * core component maintain the same ABI. This is not the default + * when using the Mbed TLS reference implementation + */ +#ifndef CRYPTO_LIBRARY_ABI_COMPAT +#define CRYPTO_LIBRARY_ABI_COMPAT (0) +#endif + /* The stack size of the Crypto Secure Partition */ #ifndef CRYPTO_STACK_SIZE -#define CRYPTO_STACK_SIZE 0x1B00 +#define CRYPTO_STACK_SIZE 0x1800 #endif /* FWU Partition Configs */ @@ -183,7 +199,11 @@ /* The stack size of the Internal Trusted Storage Secure Partition */ #ifndef ITS_STACK_SIZE +#ifndef ITS_ENCRYPTION #define ITS_STACK_SIZE 0x720 +#else +#define ITS_STACK_SIZE 0xC00 +#endif #endif /* PS Partition Configs */ diff --git a/config/profile/config_profile_medium_arotless.h b/config/profile/config_profile_medium_arotless.h index 77be11f6a..dc2210155 100644 --- a/config/profile/config_profile_medium_arotless.h +++ b/config/profile/config_profile_medium_arotless.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,9 @@ /* Crypto Partition Configs */ /* - * Heap size for the crypto backend - * CRYPTO_ENGINE_BUF_SIZE needs to be >8KB for EC signing by attest module. + * Heap size for the crypto backend. This is statically allocated + * inside the Crypto service and used as heap through the default + * Mbed TLS allocator */ #ifndef CRYPTO_ENGINE_BUF_SIZE #define CRYPTO_ENGINE_BUF_SIZE 0x2080 @@ -100,6 +101,11 @@ #define CRYPTO_NV_SEED 1 #endif +/* Use external RNG to provide entropy */ +#ifndef CRYPTO_EXT_RNG +#define CRYPTO_EXT_RNG 0 +#endif + /* * Only enable multi-part operations in Hash, MAC, AEAD and symmetric ciphers, * to optimize memory footprint in resource-constrained devices. @@ -108,9 +114,19 @@ #define CRYPTO_SINGLE_PART_FUNCS_DISABLED 0 #endif +/* + * The service assumes that the client interface and internal + * interface towards the library that provides the PSA Crypto + * core component maintain the same ABI. This is not the default + * when using the Mbed TLS reference implementation + */ +#ifndef CRYPTO_LIBRARY_ABI_COMPAT +#define CRYPTO_LIBRARY_ABI_COMPAT (0) +#endif + /* The stack size of the Crypto Secure Partition */ #ifndef CRYPTO_STACK_SIZE -#define CRYPTO_STACK_SIZE 0x1B00 +#define CRYPTO_STACK_SIZE 0x1800 #endif /* FWU Partition Configs */ @@ -183,7 +199,11 @@ /* The stack size of the Internal Trusted Storage Secure Partition */ #ifndef ITS_STACK_SIZE +#ifndef ITS_ENCRYPTION #define ITS_STACK_SIZE 0x720 +#else +#define ITS_STACK_SIZE 0xC00 +#endif #endif /* PS Partition Configs */ diff --git a/config/profile/config_profile_small.h b/config/profile/config_profile_small.h index 7ebc130ae..e7a0c7b11 100644 --- a/config/profile/config_profile_small.h +++ b/config/profile/config_profile_small.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -32,7 +32,11 @@ /* Crypto Partition Configs */ -/* Heap size for the crypto backend */ +/* + * Heap size for the crypto backend. This is statically allocated + * inside the Crypto service and used as heap through the default + * Mbed TLS allocator + */ #ifndef CRYPTO_ENGINE_BUF_SIZE #define CRYPTO_ENGINE_BUF_SIZE 0x400 #endif @@ -97,6 +101,11 @@ #define CRYPTO_NV_SEED 1 #endif +/* Use external RNG to provide entropy */ +#ifndef CRYPTO_EXT_RNG +#define CRYPTO_EXT_RNG 0 +#endif + /* * Only enable multi-part operations in Hash, MAC, AEAD and symmetric ciphers, * to optimize memory footprint in resource-constrained devices. @@ -105,9 +114,19 @@ #define CRYPTO_SINGLE_PART_FUNCS_DISABLED 1 #endif +/* + * The service assumes that the client interface and internal + * interface towards the library that provides the PSA Crypto + * core component maintain the same ABI. This is not the default + * when using the Mbed TLS reference implementation + */ +#ifndef CRYPTO_LIBRARY_ABI_COMPAT +#define CRYPTO_LIBRARY_ABI_COMPAT (0) +#endif + /* The stack size of the Crypto Secure Partition */ #ifndef CRYPTO_STACK_SIZE -#define CRYPTO_STACK_SIZE 0x1B00 +#define CRYPTO_STACK_SIZE 0x1800 #endif /* FWU Partition Configs */ @@ -180,7 +199,11 @@ /* The stack size of the Internal Trusted Storage Secure Partition */ #ifndef ITS_STACK_SIZE +#ifndef ITS_ENCRYPTION #define ITS_STACK_SIZE 0x720 +#else +#define ITS_STACK_SIZE 0xC00 +#endif #endif /* PS Partition Configs */ diff --git a/config/spe_config.cmake.in b/config/spe_config.cmake.in index a610738d0..5ca964003 100644 --- a/config/spe_config.cmake.in +++ b/config/spe_config.cmake.in @@ -75,5 +75,5 @@ set(CONFIG_TFM_LAZY_STACKING @CONFIG_TFM_LAZY_STACKING@ CACHE BO set(TFM_VERSION @TFM_VERSION@) set(TFM_NS_MANAGE_NSID @TFM_NS_MANAGE_NSID@) -# Recommended tf-m-tests version -set(RECOMMEND_TFM_TESTS_VERSION @TFM_TESTS_VERSION@) +set(RECOMMENDED_TFM_TESTS_VERSION @TFM_TESTS_VERSION@) +set(CHECK_TFM_TESTS_VERSION @TFM_TESTS_REVISION_CHECKS@) diff --git a/config/tfm_build_log_config.cmake b/config/tfm_build_log_config.cmake index a8e344ea9..70e572fa0 100644 --- a/config/tfm_build_log_config.cmake +++ b/config/tfm_build_log_config.cmake @@ -13,6 +13,7 @@ if(CONFIG_TFM_BUILD_LOG_QUIET) set(CONFIG_TFM_MEMORY_USAGE_QUIET ON CACHE BOOL "Disable the memory usage report") set(CONFIG_TFM_PARSE_MANIFEST_QUIET ON CACHE BOOL "Parse manifest quietly") else() + set(CMAKE_INSTALL_MESSAGE LAZY CACHE BOOL "Output installation message generated by the install() command[ALWAYS,LAZY,NEVER]") set(CONFIG_TFM_PARTITION_QUIET OFF CACHE BOOL "Disable printing of partition configuration during build") set(CONFIG_TFM_MEMORY_USAGE_QUIET OFF CACHE BOOL "Disable the memory usage report") set(CONFIG_TFM_PARSE_MANIFEST_QUIET OFF CACHE BOOL "Parse manifest quietly") diff --git a/docs/conf.py b/docs/conf.py index 9a353921a..825ad1ae9 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -20,7 +20,7 @@ # -- Project information ----------------------------------------------------- project = 'Trusted Firmware-M' -copyright = '2017-2024, ARM CE-OSS' +copyright = '2017-2025, ARM CE-OSS' author = 'ARM CE-OSS' title = 'User Guide' diff --git a/docs/contributing/maintainers.rst b/docs/contributing/maintainers.rst index 571c8bda8..58d92557e 100644 --- a/docs/contributing/maintainers.rst +++ b/docs/contributing/maintainers.rst @@ -21,11 +21,15 @@ Chris Brand :email: `Chris.Brand@cypress.com `__ :github: `UEWBot `__ +David Hu + :email: `David.Hu2@arm.com `__ + :github: `davidhuziji `__ + Code owners =========== -Bootloader and FWU -~~~~~~~~~~~~~~~~~~ +Bootloader +~~~~~~~~~~ Tamas Ban :email: `Tamas.Ban@arm.com `__ @@ -35,6 +39,13 @@ David Vincze :email: `David.Vincze@arm.com `__ :github: `davidvincze `__ +Firmware Update (FWU) +~~~~~~~~~~~~~~~~~~~~~ + +Maulik Patel + :email: `Maulik.Patel@arm.com `__ + :github: `maulik-arm `__ + BL1 immutable bootloader ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -45,9 +56,9 @@ Raef Coles Secure Storage ~~~~~~~~~~~~~~ -Jamie Fox - :email: `jamie.fox@arm.com `__ - :github: `jf549 `__ +Matthew Dalzell + :email: `Matthew.Dalzell@arm.com `__ + :github: `mdalzellarm `__ Crypto ~~~~~~ @@ -56,6 +67,10 @@ Antonio de Angelis :email: `Antonio.deAngelis@arm.com `__ :github: `adeaarm `__ +David Vincze + :email: `David.Vincze@arm.com `__ + :github: `davidvincze `__ + Framework (SPM, etc.) ~~~~~~~~~~~~~~~~~~~~~ @@ -70,6 +85,13 @@ Maulik Patel :email: `Maulik.Patel@arm.com `__ :github: `maulik-arm `__ +Platform Partition +~~~~~~~~~~~~~~~~~~ + +Nicola Mazzucato + :email: `Nicola.Mazzucato@arm.com `__ + :github: `nicola-mazzucato-arm `__ + Build System ~~~~~~~~~~~~ @@ -88,6 +110,13 @@ Matthew Dalzell :email: `Matthew.Dalzell@arm.com `__ :github: `mdalzellarm `__ +SCMI Partition (TF-M-Extras) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Nicola Mazzucato + :email: `Nicola.Mazzucato@arm.com `__ + :github: `nicola-mazzucato-arm `__ + Arm Platforms ~~~~~~~~~~~~~ @@ -101,9 +130,9 @@ David Hazi Corstone1000 ^^^^^^^^^^^^ -Xueliang Zhong - :email: `Xueliang.Zhong@arm.com `__ - :github: `xueliang-zhong `__ +Hugues Kamba Mpiana + :email: `Hugues.KambaMpiana@arm.com `__ + :github: `hugueskamba `__ Emekcan Aras :email: `Emekcan.Aras@arm.com `__ @@ -112,24 +141,42 @@ Emekcan Aras RSE ^^^ -Jamie Fox - :email: `jamie.fox@arm.com `__ - :github: `jf549 `__ +Raef Coles + :email: `Raef.Coles@arm.com `__ + :github: `RcColes `__ + +Antonio de Angelis + :email: `Antonio.deAngelis@arm.com `__ + :github: `adeaarm `__ + +Arm Automotive RD +""""""""""""""""" + +Diego Sueiro + :email: `diego.sueiro@arm.com `__ + :github: `diego-sueiro `__ + +Peter Hoyes + :email: `peter.hoyes@arm.com `__ + :github: `hoyes `__ + +Ziad Elhanafy + :email: `ziad.elhanafy@arm.com `__ + :github: `ZiadElhanafy `__ NXP Platforms ~~~~~~~~~~~~~ -Andrej Butok - :email: `Andrey.Butok@nxp.com `__ - :github: `butok `__ - -STM Platforms: DISCO_L562QE, NUCLEO_L552ZE_Q -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Ruchika Gupta + :email: `ruchika.gupta_1@nxp.com `__ + :github: `ruchi393 `__ -Michel JAOUEN - :email: `Michel.Jaouen@st.com `__ - :github: `jamike `__ +STM Platforms +~~~~~~~~~~~~~ +Ahmad EL JOUAID + :email: `ahmad.eljouaid@st.com `__ + :github: `ahmadstm `__ Infineon/Cypress Platforms ~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -138,8 +185,8 @@ Chris Brand :email: `Chris Brand@cypress.com `__ :github: `UEWBot `__ -Laird Connectivity Platforms: -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Laird Connectivity Platforms +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Greg Leach :email: `Greg.Leach@lairdconnect.com `__ @@ -152,24 +199,38 @@ Georgios Vasilakis :email: `georgios.vasilakis@nordicsemi.no `__ :github: `Vge0rge `__ - -Nuvoton Platform: -~~~~~~~~~~~~~~~~~ +Nuvoton Platform +~~~~~~~~~~~~~~~~ WS Chang :email: `MS20 WSChang0@nuvoton.com `__ :github: `wschang0 `__ - -ArmChina Platform: -~~~~~~~~~~~~~~~~~~ +ArmChina Platform +~~~~~~~~~~~~~~~~~ Jidong Mei :email: `Jidong.Mei@armchina.com `__ :github: `JidongMei `__ +Raspberry Pi Platform +~~~~~~~~~~~~~~~~~~~~~ + +William Vinnicombe + :email: `William.Vinnicombe@raspberrypi.com `__ + :github: `Raspberry Pi `__ + +Analog Devices Platform +~~~~~~~~~~~~~~~~~~~~~~~ + +Sadik Ozer + :email: `Sadik.Ozer@analog.com `__ + :github: `ozersa `__ + ============= .. _Project Maintenance Process: https://trusted-firmware-docs.readthedocs.io/en/latest/generic_processes/project_maintenance_process.html -*Copyright (c) 2017-2024, Arm Limited. All rights reserved.* +*SPDX-License-Identifier: BSD-3-Clause* + +*SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* diff --git a/docs/design_docs/services/tfm_its_service.rst b/docs/design_docs/services/tfm_its_service.rst index 765cdba67..efa9a2134 100644 --- a/docs/design_docs/services/tfm_its_service.rst +++ b/docs/design_docs/services/tfm_its_service.rst @@ -337,6 +337,15 @@ The key used to perform the AEAD operation must be derived from a long-term key-derivation key and the file id, which is used as a derivation label. The long-term key-derivation key must be managed by the target platform. +There is a generic implementation of the abovementioned functions under +``platform/ext/common/template/tfm_hal_its_encryption.c`` using PSA crypto calls +similar to Protected Storage solution. When used, the default NV seed template +under ``platform/ext/common/template/crypto_nv_seed.c`` must be disabled, as it +relies on ITS. If there is a need for NV seed usage, an ITS independent +implementation is required. If NV seed is not necessary, it can be turned off by +setting ``CRYPTO_NV_SEED=0``. + + -------------- -*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* diff --git a/docs/platform/adi/index.rst b/docs/platform/adi/index.rst new file mode 100644 index 000000000..3dad109b3 --- /dev/null +++ b/docs/platform/adi/index.rst @@ -0,0 +1,13 @@ +############################## +Analog Devices, Inc. Platforms +############################## + +.. toctree:: + :maxdepth: 1 + :titlesonly: + + MAX32657 + +-------------- + +*Copyright (c) 2025, Analog Devices, Inc. All rights reserved.* diff --git a/docs/platform/adi/max32657/README.rst b/docs/platform/adi/max32657/README.rst new file mode 100644 index 000000000..93024ad95 --- /dev/null +++ b/docs/platform/adi/max32657/README.rst @@ -0,0 +1,216 @@ +MAX32657 +======== + + +Introduction +------------ + +The MAX32657 microcontroller (MCU) is an advanced system-on-chip (SoC) +featuring an Arm® Cortex®-M33 core with single-precision floating point unit (FPU) +with digital signal processing (DSP) instructions, large flash and SRAM memories, +and the latest generation Bluetooth® 5.4 Low Energy (LE) radio. +The nano-power modes increase battery life substantially. + +MAX32657 1MB flash and 256KB RAM split to define section for MCUBoot, +TF-M (S), Zephyr (NS) and storage that used for secure services and configurations. +Default layout of MAX32657 is listed in below table. + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x1000000[64K] | MCU Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x1010000[320k] | Secure image slot0 (TF-M) | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x1060000[576k] | Non-secure image slot0 | ++----------+------------------+---------------------------------+ +| slot1 | 0x10F0000[0k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x10F0000[0k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x10f0000[64k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x30000000[64k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20010000[192k] | Non-Secure memory | ++----------------+------------------+-------------------+ + + +Secure Boot ROM +--------------- + +MAX32657 has Secure Boot ROM that used to authenticate user code via ECDSA 256 public key. +The Secure Boot ROM is disabled on default, to enable it user need to provision device first. + +ADI provides enable_secure_boot.py (under /lib/ext/tesa-toolkit-src/devices/max32657/scripts/bl1_provision) +script to simply provision the device. This script reads user certificate via command line parameter +then writes user key on the device and disables debug interface. + +To create pub & private key pair for MAX32657 run: + +.. code-block:: bash + + openssl ecparam -out -genkey -name prime256v1 + + +.. note:: + + Debug interface will be disabled after secure boot is enabled. + User must write final firmware before provisioning the device. It can + be written during device provision, Just add your final firmware hex file in + JLinkScript under /lib/ext/tesa-toolkit-src/devices/max32657/scripts/bl1_provision folder. + + +After secure boot has been enabled BL2 image must be signed with user certificate +otherwise Secure Boot ROM will not validate BL2 image and will not execute it. +The sign process will be done automatically if BL1 be ON ``-DBL1=ON`` +The sign key can be sepecified over command line option -DTFM_BL2_SIGNING_KEY_PATH= +or by setting the flag in /platform/ext/target/adi/max32657/config.cmake +Development purpose test certificate is here: +/lib/ext/tesa-toolkit-src/devices/max32657/keys/bl1_dummy.pem +It shall not been used for production purpose just for development purpose. + +.. note:: + + The signature generation depends on ecdsa that's have to be installed:: + + pip3 install ecdsa + + +Building TF-M +------------- + +This platform port supports TF-M regression tests (Secure and Non-secure) +with Isolation Level 1. + +To build S and NS application, run the following commands: + +.. note:: + + Only GNU toolchain is supported. + +.. note:: + + Only "profile_small" predefined profile is supported. + +Prepare the tf-m-tests repository inside the TF-M base folder. + +.. code-block:: bash + + cd + git clone https://git.trustedfirmware.org/TF-M/tf-m-tests.git + +.. code:: bash + + cd /tf-m-test/tests_reg + + cmake -S -B build_spe \ + -G"Unix Makefiles" \ + -DTFM_PLATFORM=adi/max32657 \ + -DTFM_TOOLCHAIN_FILE=[tf-m path]/toolchain_GNUARM.cmake \ + -DTEST_S=OFF \ + -DTEST_NS=ON \ + -DTFM_NS_REG_TEST=ON \ + -DMCUBOOT_LOG_LEVEL="INFO" \ + -DTFM_ISOLATION_LEVEL=1 + cmake --build build_spe -- install + + cmake -S . -B build_test \ + -G"Unix Makefiles" \ + -DCONFIG_SPE_PATH=[tf-m-tests path]/tests_reg/build_spe/api_ns \ + -DTFM_TOOLCHAIN_FILE=cmake/toolchain_ns_GNUARM.cmake \ + -DTFM_NS_REG_TEST=ON + cmake --build build_test + + +Merge and Flash Images +---------------------- + +Follow the steps below to program the flash with a compiled TF-M image (i.e. S, NS or both). + + +Generate Intel hex files from the output binary (bin) files as follows: + +.. code-block:: console + + srec_cat build_test/bin/tfm_ns_signed.bin -binary --offset 0x01060000 -o build_test/bin/tfm_ns_signed.hex -intel + + +Merge hex files as follows: + +.. code-block:: console + + srec_cat.exe build_spe/bin/bl2.hex -Intel build_spe/bin/tfm_s_signed.hex -Intel build_test/bin/tfm_ns_signed.hex -Intel -o tfm_merged.hex -Intel + +.. note:: + + Use bl2_signed.hex instead bl2.hex if Secure Boot ROM is enabled. + + +Flash them with JLink as follows: + +.. code-block:: console + + JLinkExe -device MAX32657 -if swd -speed 2000 -autoconnect 1 + J-Link>h + J-Link>r + J-Link>erase + J-Link>loadfile build_spe/bin/tfm_merged.hex + + +BL2 and TF-M Provisioning +------------------------- + +On default ``-DPLATFORM_DEFAULT_PROVISIONING=ON`` and ``-DTFM_DUMMY_PROVISIONING=ON`` +which will use default provisioning and dummpy keys, these configuration is fine +for development purpose but for production customer specific keys shall be used +Provisioning bundles can be generated with the ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` flag. +The provisioning bundle binary will be generated and it's going to contain +the provisioning code and provisioning values. + +If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and ``-DTFM_DUMMY_PROVISIONING=ON`` then the keys in +the ``tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake`` and the +default MCUBoot signing keys will be used for provisioning. + +If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and ``-DTFM_DUMMY_PROVISIONING=OFF`` are set +then unique values can be used for provisioning. The keys and seeds can be changed by +passing the new values to the build command, or by setting the ``-DPROVISIONING_KEYS_CONFIG`` flag +to a .cmake file that contains the keys. An example config cmake file can be seen at +``tf-m/platform/ext/target/common/provisioning/provisioning_config.cmake``. +Otherwise new random values are going to be generated and used. For the image signing +the ${MCUBOOT_KEY_S} and ${MCUBOOT_KEY_NS} will be used. These variables should point to +.pem files that contain the code signing private keys. The public keys are going to be generated +from these private keys and will be used for provisioning. The hash of the public key is going to +be written into the ``provisioning_data.c`` automatically. + +If ``-DMCUBOOT_GENERATE_SIGNING_KEYPAIR=ON`` is set then a new mcuboot signing public and private +keypair is going to be generated and it's going to be used to sign the S and NS binaries. + +The new generated keypair can be found in the ``/bin`` folder or in the +``/image_signing/keys`` after installation. +The generated provisioning_data.c file can be found at +``/platform/target/provisioning/provisioning_data.c`` + +.. note:: + + The provisioning bundle generation depends on pyelftools that's have to be installed:: + + pip3 install pyelftools + +UART Console +************ + +MAX32657 has one UART (UART0) peripheral which is routed for Non-Secure console output by default. +S and NS firmware can not use UART at the same time. +If TFM_S_REG_TEST been defined the UART console will be routed to the Secure side otherwise it will +be on NS side. + +-------------- + +*Copyright 2025 Analog Devices, Inc. All rights reserved. +*SPDX-License-Identifier: BSD-3-Clause* diff --git a/docs/platform/arm/mps3/corstone300/README.rst b/docs/platform/arm/mps3/corstone300/README.rst index 731c3d4bb..9f783d84e 100644 --- a/docs/platform/arm/mps3/corstone300/README.rst +++ b/docs/platform/arm/mps3/corstone300/README.rst @@ -154,7 +154,7 @@ The MPS3 board tested is HBI0309C. .. note:: If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` is set then the provisioning bundle has to - be placed on the ``0x10022400`` address by copying ``encrypted_provisioning_bundle.bin`` and + be placed on the ``0x10022400`` address by copying ``provisioning_bundle.bin`` and renaming it to ``prv.bin``, then extending the images.txt with:: IMAGE2UPDATE: AUTO @@ -220,7 +220,7 @@ The MPS3 board tested is HBI0309C. .. note:: If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` is set then the provisioning bundle has to - be placed on the ``0x10022400`` address by copying ``encrypted_provisioning_bundle.bin`` and + be placed on the ``0x10022400`` address by copying ``provisioning_bundle.bin`` and renaming it to ``prv.bin``, then extending the images.txt with:: IMAGE2UPDATE: AUTO @@ -268,9 +268,9 @@ FVP is available to download `here /tfm_s_ns_signed.bin"@0x38000000 --data "/encrypted_provisioning_bundle.bin"@0x10022000 + $ ./FVP_Corstone_SSE-300_Ethos-U55 -a cpu0*="/bl2.axf" --data "/tfm_s_ns_signed.bin"@0x38000000 --data "/provisioning_bundle.bin"@0x10022000 ------------- -*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2024, Arm Limited. All rights reserved.* diff --git a/docs/platform/arm/mps3/corstone310/README.rst b/docs/platform/arm/mps3/corstone310/README.rst index 8e631ee62..e45b5431f 100644 --- a/docs/platform/arm/mps3/corstone310/README.rst +++ b/docs/platform/arm/mps3/corstone310/README.rst @@ -155,7 +155,7 @@ The MPS3 board tested is HBI0309C. .. note:: If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` is set then the provisioning bundle has to - be placed on the ``0x11022400`` address by copying ``encrypted_provisioning_bundle.bin`` and + be placed on the ``0x11022400`` address by copying ``provisioning_bundle.bin`` and renaming it to ``prv.bin``, then extending the images.txt with:: IMAGE2UPDATE: RAM @@ -203,9 +203,9 @@ FVP is available to download `here /tfm_s_ns_signed.bin"@0x38000000 --data "/encrypted_provisioning_bundle.bin"@0x11022000 + $ ./FVP_Corstone_SSE-310 -a cpu0*="/bl2.axf" --data "/tfm_s_ns_signed.bin"@0x38000000 --data "/provisioning_bundle.bin"@0x11022000 ------------- -*Copyright (c) 2021-2023, Arm Limited. All rights reserved.* +*Copyright (c) 2021-2024, Arm Limited. All rights reserved.* diff --git a/docs/platform/arm/rse/index.rst b/docs/platform/arm/rse/index.rst index e956e2c9a..17452cd55 100644 --- a/docs/platform/arm/rse/index.rst +++ b/docs/platform/arm/rse/index.rst @@ -16,10 +16,10 @@ Previously known as Runtime Security Subsystem (RSS). RSE also includes the following extra partitions: -- :doc:`Authenticated Debug Access Control (ADAC) ` +- Authenticated Debug Access Control (ADAC) - :doc:`Measured boot partition ` - :doc:`Delegated attestation partition` -- :doc:`DICE Protection Environment partition ` +- DICE Protection Environment partition -------------- diff --git a/docs/platform/index.rst b/docs/platform/index.rst index 0aeca26fb..1efdf56c6 100644 --- a/docs/platform/index.rst +++ b/docs/platform/index.rst @@ -7,6 +7,7 @@ TF-M Platforms .. toctree:: :maxdepth: 2 + Analog Devices, Inc. Arm ArmChina Cypress @@ -14,8 +15,9 @@ TF-M Platforms Nordic Nuvoton NXP + Raspberry Pi STMICROELECTRONICS -------------- -*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2024, Arm Limited. All rights reserved.* diff --git a/docs/platform/lairdconnectivity/bl5340_dvk_cpuapp/README.rst b/docs/platform/lairdconnectivity/bl5340_dvk_cpuapp/README.rst index d23de9105..9af936604 100644 --- a/docs/platform/lairdconnectivity/bl5340_dvk_cpuapp/README.rst +++ b/docs/platform/lairdconnectivity/bl5340_dvk_cpuapp/README.rst @@ -24,7 +24,7 @@ The following links provide useful information about the BL5340 BL5340 website: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules -Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +Nordic Semiconductor TechDocs: https://docs.nordicsemi.com Building TF-M on BL5340 Application MCU --------------------------------------- @@ -74,17 +74,25 @@ To install the J-Link Software and documentation pack, follow the steps below: #. When connecting a J-Link-enabled board such as a BL5340 DVK, a serial port should come up -nRF Command-Line Tools Installation -*********************************** +nRF Util Installation +********************* -The nRF Command-line Tools allow you to control your BL5340 module from the +nRF Util allows you to control your BL5340 module from the command line, including resetting it, erasing or programming the flash memory and more. -To install them, visit `nRF Command-Line Tools`_ and select your operating -system. +To install nRF Util: -After installing, make sure that ``nrfjprog`` is somewhere in your executable +1. Visit `nRF Util product page`_. +2. Download the executable. +3. Follow the `nRF Util installation instructions`_. +4. Install ``nrfutil device`` subcommand for programming, flashing, and erasing devices: + + .. code-block:: console + + nrfutil install device + +After installing, make sure that ``nrfutil.exe`` is somewhere in your executable path to be able to invoke it from anywhere. BL2, S, and NS application images can be flashed into BL5340 separately or may @@ -95,7 +103,7 @@ Flashing the BL5340 DVK To program the flash with a compiled TF-M image (i.e. S, NS or both) after having followed the instructions to install the Segger J-Link Software and the -nRF Command-Line Tools, follow the steps below: +nRF Util, follow the steps below: Generate Intel hex files from the output binary (bin) files as follows: @@ -108,27 +116,27 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console - nrfjprog --eraseall -f nrf53 + nrfutil device erase --all --x-family nrf53 * Flash the BL2 and the TF-M image binaries from the sample folder of your choice: .. code-block:: console - nrfjprog --program /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/bl2.hex -f nrf53 --sectorerase - nrfjprog --program /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/tfm_s_ns_signed.hex -f nrf53 --sectorerase + nrfutil device program --x-family nrf53 --firmware /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/bl2.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE + nrfutil device program --x-family nrf53 --firmware /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/tfm_s_ns_signed.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE * Reset and start TF-M: .. code-block:: console - nrfjprog --reset -f nrf53 + nrfutil device reset --x-family nrf53 Flashing the BL5340 DVK (Secondary slot in QSPI, with BL2) ********************************************************** To program the flash with a compiled TF-M image (i.e. S, NS or both) after having followed the instructions to install the Segger J-Link Software and the -nRF Command-Line Tools to the secondary , follow the steps below: +nRF Util to the secondary , follow the steps below: Generate Intel hex files from the output binary (bin) files as follows: @@ -141,20 +149,20 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console - nrfjprog --eraseall -f nrf53 + nrfutil device erase --all --x-family nrf53 * Flash the BL2 and the TF-M image binaries from the sample folder of your choice: .. code-block:: console - nrfjprog --program /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/bl2.hex -f nrf53 --sectorerase - nrfjprog --program /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/tfm_s_ns_signed.hex -f nrf53 --qspisectorerase + nrfutil device program --x-family nrf53 --firmware /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/bl2.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE + nrfutil device program --x-family nrf53 --firmware /install/outputs/LAIRDCONNECTIVITY/BL5340_DVK_CPUAPP/tfm_s_ns_signed.hex --options ext_mem_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE * Reset and start TF-M: .. code-block:: console - nrfjprog --reset -f nrf53 + nrfutil device reset --x-family nrf53 Secure UART Console on BL5340 DVK @@ -169,7 +177,9 @@ Non-Secure console output is available via USART0. By default USART0 and USART1 outputs are routed to separate serial ports. -.. _nRF Command-Line Tools: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Command-Line-Tools +.. _nRF Util product page: https://www.nordicsemi.com/Products/Development-tools/nRF-Util/ + +.. _nRF Util installation instructions: https://docs.nordicsemi.com/bundle/nrfutil/page/guides/installing.html .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html diff --git a/docs/platform/nordic_nrf/nrf5340dk_nrf5340_cpuapp/README.rst b/docs/platform/nordic_nrf/nrf5340dk_nrf5340_cpuapp/README.rst index 97cdec140..4f355e8e2 100644 --- a/docs/platform/nordic_nrf/nrf5340dk_nrf5340_cpuapp/README.rst +++ b/docs/platform/nordic_nrf/nrf5340dk_nrf5340_cpuapp/README.rst @@ -22,7 +22,7 @@ The following links provide useful information about the nRF5340 nRF5340 DK website: https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF5340-DK -Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +Nordic Semiconductor TechDocs: https://docs.nordicsemi.com Building TF-M on nRF5340 Application MCU @@ -72,17 +72,25 @@ To install the J-Link Software and documentation pack, follow the steps below: #. When connecting a J-Link-enabled board such as an nRF5340 DK, a drive corresponding to a USB Mass Storage device as well as a serial port should come up -nRF Command-Line Tools Installation -************************************* +nRF Util Installation +********************* -The nRF Command-line Tools allow you to control your nRF5340 device from the command line, +nRF Util allows you to control your nRF5340 device from the command line, including resetting it, erasing or programming the flash memory and more. -To install them, visit `nRF Command-Line Tools`_ and select your operating -system. +To install nRF Util: -After installing, make sure that ``nrfjprog`` is somewhere in your executable path -to be able to invoke it from anywhere. +1. Visit `nRF Util product page`_. +2. Download the executable. +3. Follow the `nRF Util installation instructions`_. +4. Install ``nrfutil device`` subcommand for programming, flashing, and erasing devices: + + .. code-block:: console + + nrfutil install device + +After installing, make sure that ``nrfutil.exe`` is somewhere in your executable +path to be able to invoke it from anywhere. BL2, S, and NS application images can be flashed into nRF5340 separately or may be merged together into a single binary. @@ -106,27 +114,27 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console - nrfjprog --eraseall -f nrf53 + nrfutil device erase --all --x-family nrf53 * (Optionally) Erase the flash memory and reset flash protection and disable the read back protection mechanism if enabled. .. code-block:: console - nrfjprog --recover -f nrf53 + nrfutil device recover --x-family nrf53 * Flash the BL2 and the TF-M image binaries from the sample folder of your choice: .. code-block:: console - nrfjprog --program build_spe/bin/bl2.hex -f nrf53 --sectorerase - nrfjprog --program build_app/tfm_s_ns_signed.hex -f nrf53 --sectorerase + nrfutil device program --x-family nrf53 --firmware build_spe/bin/bl2.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE + nrfutil device program --x-family nrf53 --firmware build_app/tfm_s_ns_signed.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE * Reset and start TF-M: .. code-block:: console - nrfjprog --reset -f nrf53 + nrfutil device reset --x-family nrf53 Secure UART Console on nRF5340 DK @@ -141,7 +149,9 @@ Non-Secure console output is available via USART0. .. note:: By default USART0 and USART1 outputs are routed to separate serial ports. -.. _nRF Command-Line Tools: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Command-Line-Tools +.. _nRF Util product page: https://www.nordicsemi.com/Products/Development-tools/nRF-Util/ + +.. _nRF Util installation instructions: https://docs.nordicsemi.com/bundle/nrfutil/page/guides/installing.html .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html diff --git a/docs/platform/nordic_nrf/nrf9160dk_nrf9160/README.rst b/docs/platform/nordic_nrf/nrf9160dk_nrf9160/README.rst index da6d2079a..cc725ff3d 100644 --- a/docs/platform/nordic_nrf/nrf9160dk_nrf9160/README.rst +++ b/docs/platform/nordic_nrf/nrf9160dk_nrf9160/README.rst @@ -15,7 +15,7 @@ The following links provide useful information about the nRF9160 nRF9160 DK website: https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF9160-DK -Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +Nordic Semiconductor TechDocs: https://docs.nordicsemi.com Building TF-M on nRF9160 @@ -64,17 +64,26 @@ To install the J-Link Software and documentation pack, follow the steps below: #. When connecting a J-Link-enabled board such as an nRF9160 DK, a drive corresponding to a USB Mass Storage device as well as a serial port should come up -nRFx Command-Line Tools Installation -************************************* -The nRF Command-line Tools allow you to control your nRF9160 device from the command line, +nRF Util Installation +********************* + +nRF Util allows you to control your nRF9160 device from the command line, including resetting it, erasing or programming the flash memory and more. -To install them, visit `nRF Command-Line Tools`_ and select your operating -system. +To install nRF Util: + +1. Visit `nRF Util product page`_. +2. Download the executable. +3. Follow the `nRF Util installation instructions`_. +4. Install ``nrfutil device`` subcommand for programming, flashing, and erasing devices: + + .. code-block:: console -After installing, make sure that ``nrfjprog`` is somewhere in your executable path -to be able to invoke it from anywhere. + nrfutil install device + +After installing, make sure that ``nrfutil.exe`` is somewhere in your executable +path to be able to invoke it from anywhere. BL2, S, and NS application images can be flashed into nRF9160 separately or may be merged together into a single binary. @@ -98,27 +107,27 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console - nrfjprog --eraseall -f nrf91 + nrfutil device erase --all --x-family nrf91 * (Optionally) Erase the flash memory and reset flash protection and disable the read back protection mechanism if enabled. .. code-block:: console - nrfjprog --recover -f nrf91 + nrfutil device recover --x-family nrf91 * Flash the BL2 and TF-M image binaries from the sample folder of your choice: .. code-block:: console - nrfjprog --program build_spe/bin/bl2.hex -f nrf91 --sectorerase - nrfjprog --program build_app/tfm_s_ns_signed.hex -f nrf91 --sectorerase + nrfutil device program --x-family nrf91 --firmware build_spe/bin/bl2.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE + nrfutil device program --x-family nrf91 --firmware build_app/tfm_s_ns_signed.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE * Reset and start TF-M: .. code-block:: console - nrfjprog --reset -f nrf91 + nrfutil device reset --x-family nrf91 Secure UART Console on nRF9160 DK ********************************** @@ -131,7 +140,9 @@ Non-Secure console output is available via USART0. .. note:: By default USART0 and USART1 outputs are routed to separate serial ports. -.. _nRF Command-Line Tools: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Command-Line-Tools +.. _nRF Util product page: https://www.nordicsemi.com/Products/Development-tools/nRF-Util/ + +.. _nRF Util installation instructions: https://docs.nordicsemi.com/bundle/nrfutil/page/guides/installing.html .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html diff --git a/docs/platform/nordic_nrf/nrf9161dk_nrf9161/README.rst b/docs/platform/nordic_nrf/nrf9161dk_nrf9161/README.rst index a84e4c4ab..95e17f632 100644 --- a/docs/platform/nordic_nrf/nrf9161dk_nrf9161/README.rst +++ b/docs/platform/nordic_nrf/nrf9161dk_nrf9161/README.rst @@ -15,7 +15,7 @@ The following links provide useful information about the nRF9161 nRF9161 DK website: https://www.nordicsemi.com/products/nrf9161 -Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +Nordic Semiconductor TechDocs: https://docs.nordicsemi.com Building TF-M on nRF9161 @@ -64,17 +64,25 @@ To install the J-Link Software and documentation pack, follow the steps below: #. When connecting a J-Link-enabled board such as an nRF9161 DK, a drive corresponding to a USB Mass Storage device as well as a serial port should come up -nRFx Command-Line Tools Installation -************************************* +nRF Util Installation +********************* -The nRF Command-line Tools allow you to control your nRF9161 device from the command line, +nRF Util allows you to control your nRF9161 device from the command line, including resetting it, erasing or programming the flash memory and more. -To install them, visit `nRF Command-Line Tools`_ and select your operating -system. +To install nRF Util: -After installing, make sure that ``nrfjprog`` is somewhere in your executable path -to be able to invoke it from anywhere. +1. Visit `nRF Util product page`_. +2. Download the executable. +3. Follow the `nRF Util installation instructions`_. +4. Install ``nrfutil device`` subcommand for programming, flashing, and erasing devices: + + .. code-block:: console + + nrfutil install device + +After installing, make sure that ``nrfutil.exe`` is somewhere in your executable +path to be able to invoke it from anywhere. BL2, S, and NS application images can be flashed into nRF9161 separately or may be merged together into a single binary. @@ -98,27 +106,27 @@ Generate Intel hex files from the output binary (bin) files as follows: .. code-block:: console - nrfjprog --eraseall -f nrf91 + nrfutil device erase --all --x-family nrf91 * (Optionally) Erase the flash memory and reset flash protection and disable the read back protection mechanism if enabled. .. code-block:: console - nrfjprog --recover -f nrf91 + nrfutil device recover --x-family nrf91 * Flash the BL2 and TF-M image binaries from the sample folder of your choice: .. code-block:: console - nrfjprog --program build_spe/bin/bl2.hex -f nrf91 --sectorerase - nrfjprog --program build_app/tfm_s_ns_signed.hex -f nrf91 --sectorerase + nrfutil device program --x-family nrf91 --firmware build_spe/bin/bl2.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE + nrfutil device program --x-family nrf91 --firmware build_app/tfm_s_ns_signed.hex --options chip_erase_mode=ERASE_RANGES_TOUCHED_BY_FIRMWARE * Reset and start TF-M: .. code-block:: console - nrfjprog --reset -f nrf91 + nrfutil device reset --x-family nrf91 Secure UART Console on nRF9161 DK ********************************** @@ -131,7 +139,9 @@ Non-Secure console output is available via USART0. .. note:: By default USART0 and USART1 outputs are routed to separate serial ports. -.. _nRF Command-Line Tools: https://www.nordicsemi.com/Software-and-Tools/Development-Tools/nRF-Command-Line-Tools +.. _nRF Util product page: https://www.nordicsemi.com/Products/Development-tools/nRF-Util/ + +.. _nRF Util installation instructions: https://docs.nordicsemi.com/bundle/nrfutil/page/guides/installing.html .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html diff --git a/docs/platform/platform_introduction.rst b/docs/platform/platform_introduction.rst index 0075e73bc..283b3f2e4 100644 --- a/docs/platform/platform_introduction.rst +++ b/docs/platform/platform_introduction.rst @@ -47,6 +47,8 @@ Supported Platforms `_ - `BL5340 DVK (lairdconnectivity/bl5340_dvk_cpuapp). `_ + - `MAX32657 (adi/max32657). + `_ - Cortex-M23 system: diff --git a/docs/platform/rpi/index.rst b/docs/platform/rpi/index.rst new file mode 100644 index 000000000..6ad40a663 --- /dev/null +++ b/docs/platform/rpi/index.rst @@ -0,0 +1,14 @@ +###################### +Raspberry Pi platforms +###################### + +.. toctree:: + :maxdepth: 1 + :titlesonly: + + RP2350 + +-------------- + + *SPDX-License-Identifier: BSD-3-Clause* + *SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* diff --git a/docs/platform/rpi/rp2350/readme.rst b/docs/platform/rpi/rp2350/readme.rst new file mode 100644 index 000000000..5cb78395e --- /dev/null +++ b/docs/platform/rpi/rp2350/readme.rst @@ -0,0 +1,172 @@ +RP2350 +====== + +Introduction +------------ + +RP2350 features a dual-core Arm Cortex-M33 processor with 520 kiB on-chip SRAM, +support for up to 16MB of off-chip flash and a wide range of flexible I/O option +including I2C, SPI, and - uniquely - Programmable I/O (PIO). With its security +features RP2350 offers significant enhancements over RP2040. + +This platform port supports TF-M regression tests (Secure and Non-secure) +with Isolation Level 1 and 2. + +.. note:: + + Only GNU toolchain is supported. + +.. note:: + + Only "profile_medium" predefined profile is supported. + +Building TF-M +------------- + +Follow the instructions in :doc:`Building instructions `. +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Build instructions with platform name: rpi/rp2350 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +``-DTFM_PLATFORM=rpi/rp2350`` + +.. note:: + + This platform port relies on + `Raspberry Pi Pico SDK `__. + Make sure it is either cloned locally or available to download during build. + SDK version used for testing: SDK 2.1.1 release. + +.. note:: + + Building the default platform configuration requires the board to be + provisioned. For this the provision bundle needs to be built and run on the + board with ``-DPLATFORM_DEFAULT_PROVISIONING=OFF``. The binary must be + placed in flash at the address defined by ``PROVISIONING_BUNDLE_START``. One + way to do this is to generate a .uf2 file containing the bundle at the start + address and copy it to the board. There is an example in the provided + pico_uf2.sh script and in the description below. + + If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and + ``-DTFM_DUMMY_PROVISIONING=ON`` then the keys in the + ``/platform/ext/common/provisioning_bundle/provisioning_config.cmake`` + and the default MCUBoot signing keys will be used for provisioning. + + If ``-DPLATFORM_DEFAULT_PROVISIONING=OFF`` and + ``-DTFM_DUMMY_PROVISIONING=OFF`` are set then unique values can be used for + provisioning. The keys and seeds can be changed by passing the new values to + the build command, or by setting the ``-DPROVISIONING_KEYS_CONFIG`` flag to a + .cmake file that contains the keys. An example config cmake file can be seen + at + ``/platform/ext/common/provisioning_bundle/provisioning_config.cmake``. + Otherwise new random values are going to be generated and used. For the image + signing the ${MCUBOOT_KEY_S} and ${MCUBOOT_KEY_NS} will be used. These + variables should point to .pem files that contain the code signing private + keys. The public keys are going to be generated from these private keys and + will be used for provisioning. The hash of the public key is going to be + written into the ``provisioning_data.c`` automatically. + + If ``-DMCUBOOT_GENERATE_SIGNING_KEYPAIR=ON`` is set then a new mcuboot + signing public and private keypair is going to be generated and it's going to + be used to sign the S and NS binaries. + + The new generated keypair can be found in the ``/bin`` folder or + in the ``/image_signing/keys`` after installation. + The generated provisioning_data.c file can be found at + ``/platform/target/provisioning/provisioning_data.c`` + +.. note:: + + The provisioning bundle generation depends on pyelftools that needs to be + installed via:: + + pip3 install pyelftools + +Example of build instructions for regression tests with dummy keys: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Building Secure side with provisioning bundle: + +.. note:: + + Add optionally: + + - -DTFM_MULTI_CORE_TOPOLOGY=ON for multicore support + - -DPICO_SDK_PATH= for a pre-fetched Pico SDK + +.. code-block:: bash + + cmake -S /tests_reg/spe \ + -B /tests_reg/spe/build_rpi_single \ + -DTFM_PLATFORM=rpi/rp2350 \ + -DTFM_TOOLCHAIN_FILE=/toolchain_GNUARM.cmake \ + -DCONFIG_TFM_SOURCE_PATH= \ + -DTFM_PROFILE=profile_medium \ + -DPLATFORM_DEFAULT_PROVISIONING=OFF \ + -DTEST_S=ON \ + -DTEST_NS=ON + +.. code-block:: bash + + cmake --build /tests_reg/spe/build_rpi_single \ + -- -j8 install + + +Building Non-Secure side: + +.. code-block:: bash + + cmake -S /tests_reg \ + -B /tests_reg/build_rpi_single \ + -DCONFIG_SPE_PATH=/tests_reg/spe/build_rpi_single/api_ns \ + -DTFM_TOOLCHAIN_FILE=/tests_reg/spe/build_rpi_single/api_ns/cmake/toolchain_ns_GNUARM.cmake + +.. code-block:: bash + + cmake --build /tests_reg/build_rpi_single -- -j8 + +Binaries need to be converted with a small script pico_uf2.sh. +It requires uf2conv.py from here: +https://github.com/microsoft/uf2/blob/master/utils/uf2conv.py. +It depends on: +https://github.com/microsoft/uf2/blob/master/utils/uf2families.json. +Both the above files need to be copied into the same place where pico_uf2.sh +runs. +Also, you may need to give executable permissions to both pico_uf2.sh and +uf2conv.py. +The tool takes the combined and signed S and NS images in .bin format, and +generates the corresponding .uf2 file. It also generates the .uf2 for the +bootloader (bl2.uf2) and the provisioning bundle one. + +.. code-block:: bash + + pico_uf2.sh build_rpi_single + +Then just copy (drag-and-drop) the bl2.uf2 and tfm_s_ns_signed.uf2 files into +the board, one at time. It will run the BL2, S and NS tests and print the +results to the UART (Baudrate 115200). +If the board needs provisioning, the .uf2 file containing the provisioning +bundle needs to be copied before tfm_s_ns_signed.uf2. It only needs to be +done once. + +.. note:: + + If a different application was copied to the board before, erasing the flash + might be necessary. + +Erasing the flash: + +Generating flash sized image of zeros can be done with the truncate command, +then it can be converted to the uf2 format with the uf2conv.py utility. The +resulting uf2 file then needs to be copied to the board. Current platform flash +size is 2MB, please adjust size based on your board specs +( ``PICO_FLASH_SIZE_BYTES`` ): + +.. code-block:: bash + + truncate -s 2M nullbytes2M.bin + uf2conv.py nullbytes2M.bin --base 0x10000000 --convert --output nullbytes2M.uf2 --family 0xe48bff59 + +------------- + + *SPDX-License-Identifier: BSD-3-Clause* + *SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* diff --git a/docs/platform/stm/b_u585i_iot02a/readme.rst b/docs/platform/stm/b_u585i_iot02a/readme.rst index 28f5abe30..408bfae59 100644 --- a/docs/platform/stm/b_u585i_iot02a/readme.rst +++ b/docs/platform/stm/b_u585i_iot02a/readme.rst @@ -16,6 +16,9 @@ line arguments. Required arguments are noted below. The following instructions build multi-core TF-M with regression test suites in Isolation Level 1. +In common STM (``platform\ext\target\stm\common\build_stm``) +There are scripts that help users to build the TF-M project on all STM platforms + .. code-block:: bash diff --git a/docs/platform/stm/nucleo_l552ze_q/readme.rst b/docs/platform/stm/nucleo_l552ze_q/readme.rst index 7971a49f5..c0a2ee657 100644 --- a/docs/platform/stm/nucleo_l552ze_q/readme.rst +++ b/docs/platform/stm/nucleo_l552ze_q/readme.rst @@ -16,6 +16,9 @@ line arguments. Required arguments are noted below. The following instructions build multi-core TF-M with regression test suites in Isolation Level 1. +In common STM (``platform\ext\target\stm\common\build_stm``) +There are scripts that help users to build the TF-M project on all STM platforms + .. code-block:: bash diff --git a/docs/platform/stm/stm32h573i_dk/readme.rst b/docs/platform/stm/stm32h573i_dk/readme.rst index 1196560bd..01cbdb8d8 100644 --- a/docs/platform/stm/stm32h573i_dk/readme.rst +++ b/docs/platform/stm/stm32h573i_dk/readme.rst @@ -16,6 +16,9 @@ line arguments. Required arguments are noted below. The following instructions build multi-core TF-M with regression test suites in Isolation Level 1. +In common STM (``platform\ext\target\stm\common\build_stm``) +There are scripts that help users to build the TF-M project on all STM platforms + .. code-block:: bash diff --git a/docs/platform/stm/stm32l562e_dk/readme.rst b/docs/platform/stm/stm32l562e_dk/readme.rst index d3b9fd54f..4f256830d 100644 --- a/docs/platform/stm/stm32l562e_dk/readme.rst +++ b/docs/platform/stm/stm32l562e_dk/readme.rst @@ -16,6 +16,9 @@ line arguments. Required arguments are noted below. The following instructions build multi-core TF-M with regression test suites in Isolation Level 1. +In common STM (``platform\ext\target\stm\common\build_stm``) +There are scripts that help users to build the TF-M project on all STM platforms + .. code-block:: bash diff --git a/docs/releases/2.1.1.rst b/docs/releases/2.1.1.rst new file mode 100644 index 000000000..db680387a --- /dev/null +++ b/docs/releases/2.1.1.rst @@ -0,0 +1,34 @@ +************* +Version 2.1.1 +************* + +New features +============ + + - Mbed TLS upgrade to v3.6.2. + +New security advisories +======================= + +A new security vulnerability has been fixed in v2.1.1. +Refer to :doc:`TFMV-8 ` for more details. +The mitigation is included in this release. + +New platforms supported +======================= + + - :doc:`RP2350. ` + +Hotfixes +======== + + - Crypto: Additional checks for writes to avoid out-of-bound access + - Crypto: Prevent the scratch allocator from overflowing + - Crypto: Protect writes to avoid out-of-bound access + - SPM: mailbox_agent_api: Free connection if params association fails + + +-------------- + + *SPDX-License-Identifier: BSD-3-Clause* + *SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* \ No newline at end of file diff --git a/docs/releases/2.1.2.rst b/docs/releases/2.1.2.rst new file mode 100644 index 000000000..a6edf9321 --- /dev/null +++ b/docs/releases/2.1.2.rst @@ -0,0 +1,45 @@ +************* +Version 2.1.2 +************* + +New features +============ + + - Mbed TLS upgrade to v3.6.3. + +New platforms supported +======================= + + - :doc:`MAX32657 ` + +Hotfixes +======== + + - Protected Storage content can be lost if the storage is "full", psa_ps_set + is attempted and device is reset (twice). + - Fix wrapper to properly mark NSPE images as such + - SPM: Remove specific section for psa_interface_thread_fn_call + - SPM: interrupts: Add missing checks on fih_rc return value + - SPM: Services do not unmap IOVECS + - SPM: SPM does not return PSA_ERROR on refused psa_connect + - SPM: Fixes for invalid connection retention after psa_close + - SPM: Fixes for reverse-handle + +Known issues +============ + +Some open issues are not fixed in this release. + +.. list-table:: + :header-rows: 1 + + * - Descriptions + - Issue links + * - SPM does not automatically unmap mm-iovecs. + - https://github.com/TrustedFirmware-M/trusted-firmware-m/issues/20 + +-------------- + + *SPDX-License-Identifier: BSD-3-Clause* + + *SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* diff --git a/docs/releases/index.rst b/docs/releases/index.rst index 1457814fa..f3d5888d7 100644 --- a/docs/releases/index.rst +++ b/docs/releases/index.rst @@ -4,6 +4,8 @@ Releases .. toctree:: :hidden: + v2.1.2 <2.1.2> + v2.1.1 <2.1.1> v2.1.0 <2.1.0> v2.0.0 <2.0.0> v1.8.1 <1.8.1> @@ -13,7 +15,11 @@ Releases +--------------------------------------+--------------+----------------------------+ | Version | Date | PSA-arch tag/hash | +======================================+==============+============================+ -| :doc:`v2.1.0 ` | | v23.06_API1.5_ADAC_EAC | +| :doc:`v2.1.2 ` | 2025-04-14 | v23.06_API1.5_ADAC_EAC | ++--------------------------------------+--------------+----------------------------+ +| :doc:`v2.1.1 ` | 2024-11-01 | v23.06_API1.5_ADAC_EAC | ++--------------------------------------+--------------+----------------------------+ +| :doc:`v2.1.0 ` | 2024-05-13 | v23.06_API1.5_ADAC_EAC | +--------------------------------------+--------------+----------------------------+ | :doc:`v2.0.0 ` | 2023-11-28 | v23.06_API1.5_ADAC_EAC | +--------------------------------------+--------------+----------------------------+ @@ -48,7 +54,9 @@ The dates below are tentative and subject to change. +--------------------------------------+-----------------+---------------+ | Version | Feature Freeze | Release | +======================================+=================+===============+ -| v2.2.0 | | | +| v2.3.0-LTS | 2025-10-27 | 2025-11-17 | ++--------------------------------------+-----------------+---------------+ +| v2.4.0 | 2026-07-13 | 2026-07-24 | +--------------------------------------+-----------------+---------------+ Please refer to @@ -57,4 +65,7 @@ interpreting version numbers. -------------- -*Copyright (c) 2020-2024, Arm Limited. All rights reserved.* +*SPDX-License-Identifier: BSD-3-Clause* + +*SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors* + diff --git a/docs/security/security_advisories/index.rst b/docs/security/security_advisories/index.rst index c7829cedf..23145e774 100644 --- a/docs/security/security_advisories/index.rst +++ b/docs/security/security_advisories/index.rst @@ -13,6 +13,7 @@ Security Advisories fwu_write_vulnerability cc3xx_partial_tag_compare_on_chacha20_poly1305 debug_log_vulnerability + user_pointers_mailbox_vectors_vulnerability +------------+-----------------------------------------------------------------+ | ID | Title | @@ -36,6 +37,9 @@ Security Advisories +------------+-----------------------------------------------------------------+ | |TFMV-7| | ARoT can access PRoT data via debug logging functionality | +------------+-----------------------------------------------------------------+ +| |TFMV-8| | Unchecked user-supplied pointer via mailbox messages may cause | +| | write of arbitrary address | ++------------+-----------------------------------------------------------------+ .. |TFMV-1| replace:: :doc:`TFMV-1 ` .. |TFMV-2| replace:: :doc:`TFMV-2 ` @@ -44,7 +48,8 @@ Security Advisories .. |TFMV-5| replace:: :doc:`TFMV-5 ` .. |TFMV-6| replace:: :doc:`TFMV-6 ` .. |TFMV-7| replace:: :doc:`TFMV-7 ` +.. |TFMV-8| replace:: :doc:`TFMV-8 ` -------------- -*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2024, Arm Limited. All rights reserved.* diff --git a/docs/security/security_advisories/user_pointers_mailbox_vectors_vulnerability.rst b/docs/security/security_advisories/user_pointers_mailbox_vectors_vulnerability.rst new file mode 100644 index 000000000..1fe12a357 --- /dev/null +++ b/docs/security/security_advisories/user_pointers_mailbox_vectors_vulnerability.rst @@ -0,0 +1,69 @@ +Advisory TFMV-8 +=============== + ++-----------------+------------------------------------------------------------+ +| Title | Unchecked user-supplied pointer via mailbox messages may | +| | cause write of arbitrary address. | ++=================+============================================================+ +| CVE ID | `CVE-2024-45746`_ | ++-----------------+------------------------------------------------------------+ +| Public | October 02, 2024 | +| Disclosure Date | | ++-----------------+------------------------------------------------------------+ +| Versions | All version from TF-Mv1.6.0 up to TF-Mv2.1.0 inclusive | +| Affected | | ++-----------------+------------------------------------------------------------+ +| Configurations | Platforms with standard mailbox dispatcher | +| | ``tfm_spe_mailbox``. | ++-----------------+------------------------------------------------------------+ +| Impact | The mailbox message could contain arbitrary pointers which,| +| | in case of psa_call failure, would lead to write to a | +| | user-specified adddress in memory. | ++-----------------+------------------------------------------------------------+ +| Fix Version | 5ae0a02e8 TF-M v2.1.1 | ++-----------------+------------------------------------------------------------+ +| Credit | Infineon Technologies AG, in collaboration with: Tobias | +| | Scharnowski, Simon Wörner and Johannes Willbold from | +| | fuzzware.io. | ++-----------------+------------------------------------------------------------+ + +Background +---------- + +The psa_call message through the mailbox contains input/output vectors along +with their respective lengths. This message is provided by a NSPE client. +SPE takes the message and pass it to the mailbox dispatcher (tfm_spe_mailbox), +which handles the message by performing a copy of the i/o vectors into local +arrays. When either the client_id translation or the psa_call fails, the +dispatcher replies immediately to the client. At that moment, the outvec is +written back for its given length, which may not have been sanitized beforehand, +resulting in arbitrary access of memory if the provided length goes beyond the +legit vector size. + +Impact +------ + +When the dispatcher in tfm_spe_mailbox is used, a user through mailbox could +write into arbitrary address by first placing the malicious data into the local +vectors with a bad message, then subsequently sending a psa_call with an invalid +vector length. If both calls fail, the reply routine in tfm_spe_mailbox could +take the injected data and write it into a desired location specified by the +invalid length. +Note that the above sequence would require sending the two mesages through two +different mailbox slots. + +Mitigation +---------- + +Ensure that the outvec is written back only when the psa operation is +successful. Any errors ahead of replying must be taken as a hint to avoid such +write-back since they may be due to wrong supplied user-data in the vectors +(pointers, length etc). +To achieve the above, proper sanitization of input data must also be performed +and related errors propagated to the reply subroutine. + +.. _CVE-2024-45746: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2024-45746 + +--------------------- + +*Copyright (c) 2024, Arm Limited. All rights reserved.* diff --git a/interface/CMakeLists.txt b/interface/CMakeLists.txt index 97711e8f2..94be57a12 100644 --- a/interface/CMakeLists.txt +++ b/interface/CMakeLists.txt @@ -19,6 +19,15 @@ configure_file(${CMAKE_CURRENT_SOURCE_DIR}/include/psa/framework_feature.h.in add_library(psa_interface INTERFACE) +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_include_directories(psa_interface + INTERFACE + $ + ) +endif() + target_include_directories(psa_interface INTERFACE $ diff --git a/interface/include/mbedtls/bignum.h b/interface/include/mbedtls/bignum.h index 71d7b9767..8367cd34e 100644 --- a/interface/include/mbedtls/bignum.h +++ b/interface/include/mbedtls/bignum.h @@ -880,7 +880,7 @@ int mbedtls_mpi_mod_int(mbedtls_mpi_uint *r, const mbedtls_mpi *A, mbedtls_mpi_sint b); /** - * \brief Perform a sliding-window exponentiation: X = A^E mod N + * \brief Perform a modular exponentiation: X = A^E mod N * * \param X The destination MPI. This must point to an initialized MPI. * This must not alias E or N. diff --git a/interface/include/mbedtls/build_info.h b/interface/include/mbedtls/build_info.h index eab167f38..e70c4d7cc 100644 --- a/interface/include/mbedtls/build_info.h +++ b/interface/include/mbedtls/build_info.h @@ -26,16 +26,16 @@ */ #define MBEDTLS_VERSION_MAJOR 3 #define MBEDTLS_VERSION_MINOR 6 -#define MBEDTLS_VERSION_PATCH 0 +#define MBEDTLS_VERSION_PATCH 3 /** * The single version number has the following structure: * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x03060000 -#define MBEDTLS_VERSION_STRING "3.6.0" -#define MBEDTLS_VERSION_STRING_FULL "Mbed TLS 3.6.0" +#define MBEDTLS_VERSION_NUMBER 0x03060300 +#define MBEDTLS_VERSION_STRING "3.6.3" +#define MBEDTLS_VERSION_STRING_FULL "Mbed TLS 3.6.3" /* Macros for build-time platform detection */ @@ -101,6 +101,13 @@ #define inline __inline #endif +#if defined(MBEDTLS_CONFIG_FILES_READ) +#error "Something went wrong: MBEDTLS_CONFIG_FILES_READ defined before reading the config files!" +#endif +#if defined(MBEDTLS_CONFIG_IS_FINALIZED) +#error "Something went wrong: MBEDTLS_CONFIG_IS_FINALIZED defined before reading the config files!" +#endif + /* X.509, TLS and non-PSA crypto configuration */ #if !defined(MBEDTLS_CONFIG_FILE) #include "mbedtls/mbedtls_config.h" @@ -135,6 +142,12 @@ #endif #endif /* defined(MBEDTLS_PSA_CRYPTO_CONFIG) */ +/* Indicate that all configuration files have been read. + * It is now time to adjust the configuration (follow through on dependencies, + * make PSA and legacy crypto consistent, etc.). + */ +#define MBEDTLS_CONFIG_FILES_READ + /* Auto-enable MBEDTLS_CTR_DRBG_USE_128_BIT_KEY if * MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH and MBEDTLS_CTR_DRBG_C defined * to ensure a 128-bit key size in CTR_DRBG. @@ -169,8 +182,13 @@ #include "mbedtls/config_adjust_ssl.h" -/* Make sure all configuration symbols are set before including check_config.h, - * even the ones that are calculated programmatically. */ +/* Indicate that all configuration symbols are set, + * even the ones that are calculated programmatically. + * It is now safe to query the configuration (to check it, to size buffers, + * etc.). + */ +#define MBEDTLS_CONFIG_IS_FINALIZED + #include "mbedtls/check_config.h" #endif /* MBEDTLS_BUILD_INFO_H */ diff --git a/interface/include/mbedtls/check_config.h b/interface/include/mbedtls/check_config.h index b3c038dd2..aec5050b7 100644 --- a/interface/include/mbedtls/check_config.h +++ b/interface/include/mbedtls/check_config.h @@ -2,6 +2,13 @@ * \file check_config.h * * \brief Consistency checks for configuration options + * + * This is an internal header. Do not include it directly. + * + * This header is included automatically by all public Mbed TLS headers + * (via mbedtls/build_info.h). Do not include it directly in a configuration + * file such as mbedtls/mbedtls_config.h or #MBEDTLS_USER_CONFIG_FILE! + * It would run at the wrong time due to missing derived symbols. */ /* * Copyright The Mbed TLS Contributors @@ -12,6 +19,13 @@ #define MBEDTLS_CHECK_CONFIG_H /* *INDENT-OFF* */ + +#if !defined(MBEDTLS_CONFIG_IS_FINALIZED) +#warning "Do not include mbedtls/check_config.h manually! " \ + "This may cause spurious errors. " \ + "It is included automatically at the right point since Mbed TLS 3.0." +#endif /* !MBEDTLS_CONFIG_IS_FINALIZED */ + /* * We assume CHAR_BIT is 8 in many places. In practice, this is true on our * target platforms, so not an issue, but let's just be extra sure. @@ -233,6 +247,9 @@ #if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) && !defined(MBEDTLS_HAS_MEMSAN) #error "MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN requires building with MemorySanitizer" #endif +#if defined(MBEDTLS_HAS_MEMSAN) && defined(MBEDTLS_HAVE_ASM) +#error "MemorySanitizer does not support assembly implementation" +#endif #undef MBEDTLS_HAS_MEMSAN // temporary macro defined above #if defined(MBEDTLS_CCM_C) && \ @@ -724,6 +741,11 @@ #error "MBEDTLS_PSA_INJECT_ENTROPY is not compatible with MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG" #endif +#if defined(MBEDTLS_PSA_KEY_STORE_DYNAMIC) && \ + defined(MBEDTLS_PSA_STATIC_KEY_SLOTS) +#error "MBEDTLS_PSA_KEY_STORE_DYNAMIC and MBEDTLS_PSA_STATIC_KEY_SLOTS cannot be defined simultaneously" +#endif + #if defined(MBEDTLS_PSA_ITS_FILE_C) && \ !defined(MBEDTLS_FS_IO) #error "MBEDTLS_PSA_ITS_FILE_C defined, but not all prerequisites" diff --git a/interface/include/mbedtls/config_adjust_legacy_crypto.h b/interface/include/mbedtls/config_adjust_legacy_crypto.h index 9b0604122..331ac9b2d 100644 --- a/interface/include/mbedtls/config_adjust_legacy_crypto.h +++ b/interface/include/mbedtls/config_adjust_legacy_crypto.h @@ -2,7 +2,9 @@ * \file mbedtls/config_adjust_legacy_crypto.h * \brief Adjust legacy configuration configuration * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * This is an internal header. Do not include it directly. + * + * Automatically enable certain dependencies. Generally, MBEDTLS_xxx * configurations need to be explicitly enabled by the user: enabling * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a * compilation error. However, we do automatically enable certain options @@ -22,6 +24,14 @@ #ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H #define MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + /* Ideally, we'd set those as defaults in mbedtls_config.h, but * putting an #ifdef _WIN32 in mbedtls_config.h would confuse config.py. * @@ -38,6 +48,13 @@ #endif #endif /* _MINGW32__ || (_MSC_VER && (_MSC_VER <= 1900)) */ +/* If MBEDTLS_PSA_CRYPTO_C is defined, make sure MBEDTLS_PSA_CRYPTO_CLIENT + * is defined as well to include all PSA code. + */ +#if defined(MBEDTLS_PSA_CRYPTO_C) +#define MBEDTLS_PSA_CRYPTO_CLIENT +#endif /* MBEDTLS_PSA_CRYPTO_C */ + /* Auto-enable CIPHER_C when any of the unauthenticated ciphers is builtin * in PSA. */ #if defined(MBEDTLS_PSA_CRYPTO_C) && \ @@ -48,7 +65,8 @@ defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) || \ defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) || \ defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG)) + defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC)) #define MBEDTLS_CIPHER_C #endif @@ -147,7 +165,66 @@ #define MBEDTLS_MD_SHA3_512_VIA_PSA #define MBEDTLS_MD_SOME_PSA #endif -#endif /* MBEDTLS_PSA_CRYPTO_C */ + +#elif defined(MBEDTLS_PSA_CRYPTO_CLIENT) + +#if defined(PSA_WANT_ALG_MD5) +#define MBEDTLS_MD_CAN_MD5 +#define MBEDTLS_MD_MD5_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_1) +#define MBEDTLS_MD_CAN_SHA1 +#define MBEDTLS_MD_SHA1_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_224) +#define MBEDTLS_MD_CAN_SHA224 +#define MBEDTLS_MD_SHA224_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_256) +#define MBEDTLS_MD_CAN_SHA256 +#define MBEDTLS_MD_SHA256_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_384) +#define MBEDTLS_MD_CAN_SHA384 +#define MBEDTLS_MD_SHA384_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_512) +#define MBEDTLS_MD_CAN_SHA512 +#define MBEDTLS_MD_SHA512_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_RIPEMD160) +#define MBEDTLS_MD_CAN_RIPEMD160 +#define MBEDTLS_MD_RIPEMD160_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA3_224) +#define MBEDTLS_MD_CAN_SHA3_224 +#define MBEDTLS_MD_SHA3_224_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA3_256) +#define MBEDTLS_MD_CAN_SHA3_256 +#define MBEDTLS_MD_SHA3_256_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA3_384) +#define MBEDTLS_MD_CAN_SHA3_384 +#define MBEDTLS_MD_SHA3_384_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA3_512) +#define MBEDTLS_MD_CAN_SHA3_512 +#define MBEDTLS_MD_SHA3_512_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif + +#endif /* !MBEDTLS_PSA_CRYPTO_CLIENT && !MBEDTLS_PSA_CRYPTO_C */ /* Built-in implementations */ #if defined(MBEDTLS_MD5_C) @@ -293,6 +370,14 @@ #define MBEDTLS_ECP_LIGHT #endif +/* Backward compatibility: after #8740 the RSA module offers functions to parse + * and write RSA private/public keys without relying on the PK one. Of course + * this needs ASN1 support to do so, so we enable it here. */ +#if defined(MBEDTLS_RSA_C) +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#endif + /* MBEDTLS_PK_PARSE_EC_COMPRESSED is introduced in Mbed TLS version 3.5, while * in previous version compressed points were automatically supported as long * as PK_PARSE_C and ECP_C were enabled. As a consequence, for backward @@ -333,13 +418,6 @@ #define MBEDTLS_PK_CAN_ECDSA_SOME #endif -/* If MBEDTLS_PSA_CRYPTO_C is defined, make sure MBEDTLS_PSA_CRYPTO_CLIENT - * is defined as well to include all PSA code. - */ -#if defined(MBEDTLS_PSA_CRYPTO_C) -#define MBEDTLS_PSA_CRYPTO_CLIENT -#endif /* MBEDTLS_PSA_CRYPTO_C */ - /* Helpers to state that each key is supported either on the builtin or PSA side. */ #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_521) #define MBEDTLS_ECP_HAVE_SECP521R1 @@ -409,12 +487,12 @@ /* psa_util file features some ECDSA conversion functions, to convert between * legacy's ASN.1 DER format and PSA's raw one. */ -#if defined(MBEDTLS_ECDSA_C) || (defined(MBEDTLS_PSA_CRYPTO_C) && \ +#if (defined(MBEDTLS_PSA_CRYPTO_CLIENT) && \ (defined(PSA_WANT_ALG_ECDSA) || defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA))) #define MBEDTLS_PSA_UTIL_HAVE_ECDSA #endif -/* Some internal helpers to determine which keys are availble. */ +/* Some internal helpers to determine which keys are available. */ #if (!defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_AES_C)) || \ (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_KEY_TYPE_AES)) #define MBEDTLS_SSL_HAVE_AES @@ -428,7 +506,7 @@ #define MBEDTLS_SSL_HAVE_CAMELLIA #endif -/* Some internal helpers to determine which operation modes are availble. */ +/* Some internal helpers to determine which operation modes are available. */ #if (!defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_CIPHER_MODE_CBC)) || \ (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_ALG_CBC_NO_PADDING)) #define MBEDTLS_SSL_HAVE_CBC diff --git a/interface/include/mbedtls/config_adjust_legacy_from_psa.h b/interface/include/mbedtls/config_adjust_legacy_from_psa.h index 0091e246b..48f1bab1e 100644 --- a/interface/include/mbedtls/config_adjust_legacy_from_psa.h +++ b/interface/include/mbedtls/config_adjust_legacy_from_psa.h @@ -2,6 +2,8 @@ * \file mbedtls/config_adjust_legacy_from_psa.h * \brief Adjust PSA configuration: activate legacy implementations * + * This is an internal header. Do not include it directly. + * * When MBEDTLS_PSA_CRYPTO_CONFIG is enabled, activate legacy implementations * of cryptographic mechanisms as needed to fulfill the needs of the PSA * configuration. Generally speaking, we activate a legacy mechanism if @@ -16,6 +18,14 @@ #ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H #define MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + /* Define appropriate ACCEL macros for the p256-m driver. * In the future, those should be generated from the drivers JSON description. */ @@ -59,7 +69,6 @@ (defined(PSA_WANT_ECC_SECP_R1_384) && !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384)) || \ (defined(PSA_WANT_ECC_SECP_R1_521) && !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521)) || \ (defined(PSA_WANT_ECC_SECP_K1_192) && !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_192)) || \ - (defined(PSA_WANT_ECC_SECP_K1_224) && !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224)) || \ (defined(PSA_WANT_ECC_SECP_K1_256) && !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256)) #define MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES #define MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_WEIERSTRASS_CURVES @@ -215,17 +224,6 @@ #endif /* missing accel */ #endif /* PSA_WANT_ECC_SECP_K1_192 */ -#if defined(PSA_WANT_ECC_SECP_K1_224) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_224 1 -#define MBEDTLS_ECP_DP_SECP224K1_ENABLED -/* https://github.com/Mbed-TLS/mbedtls/issues/3541 */ -#error "SECP224K1 is buggy via the PSA API in Mbed TLS." -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_K1_224 */ - #if defined(PSA_WANT_ECC_SECP_K1_256) #if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256) || \ defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ @@ -498,7 +496,6 @@ * The PSA implementation has its own implementation of HKDF, separate from * hkdf.c. No need to enable MBEDTLS_HKDF_C here. */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 #define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 #endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF */ #endif /* PSA_WANT_ALG_HKDF */ @@ -509,7 +506,6 @@ * The PSA implementation has its own implementation of HKDF, separate from * hkdf.c. No need to enable MBEDTLS_HKDF_C here. */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 #define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT 1 #endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT */ #endif /* PSA_WANT_ALG_HKDF_EXTRACT */ @@ -520,7 +516,6 @@ * The PSA implementation has its own implementation of HKDF, separate from * hkdf.c. No need to enable MBEDTLS_HKDF_C here. */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 #define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND 1 #endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND */ #endif /* PSA_WANT_ALG_HKDF_EXPAND */ @@ -630,9 +625,6 @@ #if !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_HMAC) #define MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC 1 #define PSA_HAVE_SOFT_PBKDF2_HMAC 1 -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ #endif /* !MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ #endif /* PSA_WANT_ALG_PBKDF2_HMAC */ @@ -778,13 +770,6 @@ #define PSA_HAVE_SOFT_BLOCK_CIPHER 1 #endif -#if defined(PSA_WANT_ALG_CBC_MAC) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) -#error "CBC-MAC is not yet supported via the PSA API in Mbed TLS." -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_MAC 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_CBC_MAC */ -#endif /* PSA_WANT_ALG_CBC_MAC */ - #if defined(PSA_WANT_ALG_CMAC) #if !defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) || \ defined(PSA_HAVE_SOFT_BLOCK_CIPHER) diff --git a/interface/include/mbedtls/config_adjust_psa_from_legacy.h b/interface/include/mbedtls/config_adjust_psa_from_legacy.h index 345661594..14ca14696 100644 --- a/interface/include/mbedtls/config_adjust_psa_from_legacy.h +++ b/interface/include/mbedtls/config_adjust_psa_from_legacy.h @@ -2,6 +2,8 @@ * \file mbedtls/config_adjust_psa_from_legacy.h * \brief Adjust PSA configuration: construct PSA configuration from legacy * + * This is an internal header. Do not include it directly. + * * When MBEDTLS_PSA_CRYPTO_CONFIG is disabled, we automatically enable * cryptographic mechanisms through the PSA interface when the corresponding * legacy mechanism is enabled. In many cases, this just enables the PSA @@ -18,6 +20,14 @@ #ifndef MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H #define MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + /* * Ensure PSA_WANT_* defines are setup properly if MBEDTLS_PSA_CRYPTO_CONFIG * is not defined diff --git a/interface/include/mbedtls/config_adjust_psa_superset_legacy.h b/interface/include/mbedtls/config_adjust_psa_superset_legacy.h index 3a55c3f6e..1a232cbb8 100644 --- a/interface/include/mbedtls/config_adjust_psa_superset_legacy.h +++ b/interface/include/mbedtls/config_adjust_psa_superset_legacy.h @@ -2,6 +2,8 @@ * \file mbedtls/config_adjust_psa_superset_legacy.h * \brief Adjust PSA configuration: automatic enablement from legacy * + * This is an internal header. Do not include it directly. + * * To simplify some edge cases, we automatically enable certain cryptographic * mechanisms in the PSA API if they are enabled in the legacy API. The general * idea is that if legacy module M uses mechanism A internally, and A has @@ -17,6 +19,14 @@ #ifndef MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H #define MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + /****************************************************************/ /* Hashes that are built in are also enabled in PSA. * This simplifies dependency declarations especially @@ -126,13 +136,6 @@ #endif /* PSA_WANT_ECC_SECP_K1_192 */ #endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ -/* SECP224K1 is buggy via the PSA API (https://github.com/Mbed-TLS/mbedtls/issues/3541) */ -#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_K1_224) -#define PSA_WANT_ECC_SECP_K1_224 1 -#endif /* PSA_WANT_ECC_SECP_K1_224 */ -#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ - #if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) #if !defined(PSA_WANT_ECC_SECP_K1_256) #define PSA_WANT_ECC_SECP_K1_256 1 diff --git a/interface/include/mbedtls/config_adjust_ssl.h b/interface/include/mbedtls/config_adjust_ssl.h index 39c7b3b11..1f82d9c00 100644 --- a/interface/include/mbedtls/config_adjust_ssl.h +++ b/interface/include/mbedtls/config_adjust_ssl.h @@ -2,7 +2,9 @@ * \file mbedtls/config_adjust_ssl.h * \brief Adjust TLS configuration * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * This is an internal header. Do not include it directly. + * + * Automatically enable certain dependencies. Generally, MBEDTLS_xxx * configurations need to be explicitly enabled by the user: enabling * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a * compilation error. However, we do automatically enable certain options @@ -22,6 +24,14 @@ #ifndef MBEDTLS_CONFIG_ADJUST_SSL_H #define MBEDTLS_CONFIG_ADJUST_SSL_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + /* The following blocks make it easier to disable all of TLS, * or of TLS 1.2 or 1.3 or DTLS, without having to manually disable all * key exchanges, options and extensions related to them. */ diff --git a/interface/include/mbedtls/config_adjust_x509.h b/interface/include/mbedtls/config_adjust_x509.h index 346c8ae6d..cfb2d8891 100644 --- a/interface/include/mbedtls/config_adjust_x509.h +++ b/interface/include/mbedtls/config_adjust_x509.h @@ -2,7 +2,9 @@ * \file mbedtls/config_adjust_x509.h * \brief Adjust X.509 configuration * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * This is an internal header. Do not include it directly. + * + * Automatically enable certain dependencies. Generally, MBEDTLS_xxx * configurations need to be explicitly enabled by the user: enabling * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a * compilation error. However, we do automatically enable certain options @@ -22,4 +24,12 @@ #ifndef MBEDTLS_CONFIG_ADJUST_X509_H #define MBEDTLS_CONFIG_ADJUST_X509_H +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include mbedtls/config_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + #endif /* MBEDTLS_CONFIG_ADJUST_X509_H */ diff --git a/interface/include/mbedtls/config_psa.h b/interface/include/mbedtls/config_psa.h index 17da61b3e..5f3d0f3d5 100644 --- a/interface/include/mbedtls/config_psa.h +++ b/interface/include/mbedtls/config_psa.h @@ -22,6 +22,8 @@ #include "psa/crypto_adjust_config_synonyms.h" +#include "psa/crypto_adjust_config_dependencies.h" + #include "mbedtls/config_adjust_psa_superset_legacy.h" #if defined(MBEDTLS_PSA_CRYPTO_CONFIG) @@ -32,7 +34,11 @@ * before we deduce what built-ins are required. */ #include "psa/crypto_adjust_config_key_pair_types.h" +#if defined(MBEDTLS_PSA_CRYPTO_C) +/* If we are implementing PSA crypto ourselves, then we want to enable the + * required built-ins. Otherwise, PSA features will be provided by the server. */ #include "mbedtls/config_adjust_legacy_from_psa.h" +#endif #else /* MBEDTLS_PSA_CRYPTO_CONFIG */ diff --git a/interface/include/mbedtls/ctr_drbg.h b/interface/include/mbedtls/ctr_drbg.h index c00756df1..0b7cce192 100644 --- a/interface/include/mbedtls/ctr_drbg.h +++ b/interface/include/mbedtls/ctr_drbg.h @@ -32,12 +32,27 @@ #include "mbedtls/build_info.h" -/* In case AES_C is defined then it is the primary option for backward - * compatibility purposes. If that's not available, PSA is used instead */ -#if defined(MBEDTLS_AES_C) -#include "mbedtls/aes.h" -#else +/* The CTR_DRBG implementation can either directly call the low-level AES + * module (gated by MBEDTLS_AES_C) or call the PSA API to perform AES + * operations. Calling the AES module directly is the default, both for + * maximum backward compatibility and because it's a bit more efficient + * (less glue code). + * + * When MBEDTLS_AES_C is disabled, the CTR_DRBG module calls PSA crypto and + * thus benefits from the PSA AES accelerator driver. + * It is technically possible to enable MBEDTLS_CTR_DRBG_USE_PSA_CRYPTO + * to use PSA even when MBEDTLS_AES_C is enabled, but there is very little + * reason to do so other than testing purposes and this is not officially + * supported. + */ +#if !defined(MBEDTLS_AES_C) +#define MBEDTLS_CTR_DRBG_USE_PSA_CRYPTO +#endif + +#if defined(MBEDTLS_CTR_DRBG_USE_PSA_CRYPTO) #include "psa/crypto.h" +#else +#include "mbedtls/aes.h" #endif #include "entropy.h" @@ -157,7 +172,7 @@ extern "C" { #define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN (MBEDTLS_CTR_DRBG_ENTROPY_LEN + 1) / 2 #endif -#if !defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_CTR_DRBG_USE_PSA_CRYPTO) typedef struct mbedtls_ctr_drbg_psa_context { mbedtls_svc_key_id_t key_id; psa_cipher_operation_t operation; @@ -189,10 +204,10 @@ typedef struct mbedtls_ctr_drbg_context { * This is the maximum number of requests * that can be made between reseedings. */ -#if defined(MBEDTLS_AES_C) - mbedtls_aes_context MBEDTLS_PRIVATE(aes_ctx); /*!< The AES context. */ -#else +#if defined(MBEDTLS_CTR_DRBG_USE_PSA_CRYPTO) mbedtls_ctr_drbg_psa_context MBEDTLS_PRIVATE(psa_ctx); /*!< The PSA context. */ +#else + mbedtls_aes_context MBEDTLS_PRIVATE(aes_ctx); /*!< The AES context. */ #endif /* diff --git a/interface/include/mbedtls/debug.h b/interface/include/mbedtls/debug.h index 424ed4b3f..e6f5dadb1 100644 --- a/interface/include/mbedtls/debug.h +++ b/interface/include/mbedtls/debug.h @@ -108,16 +108,16 @@ * * This module provides debugging functions. */ -#if (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) +#if defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER < 1900) #include #define MBEDTLS_PRINTF_SIZET PRIuPTR #define MBEDTLS_PRINTF_LONGLONG "I64d" #else \ - /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ + /* defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER < 1900) */ #define MBEDTLS_PRINTF_SIZET "zu" #define MBEDTLS_PRINTF_LONGLONG "lld" #endif \ - /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ + /* defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER < 1900) */ #if !defined(MBEDTLS_PRINTF_MS_TIME) #include diff --git a/interface/include/mbedtls/ecdh.h b/interface/include/mbedtls/ecdh.h index a0909d6b4..a6a506933 100644 --- a/interface/include/mbedtls/ecdh.h +++ b/interface/include/mbedtls/ecdh.h @@ -325,7 +325,7 @@ int mbedtls_ecdh_read_params(mbedtls_ecdh_context *ctx, * \brief This function sets up an ECDH context from an EC key. * * It is used by clients and servers in place of the - * ServerKeyEchange for static ECDH, and imports ECDH + * ServerKeyExchange for static ECDH, and imports ECDH * parameters from the EC key information of a certificate. * * \see ecp.h diff --git a/interface/include/mbedtls/ecp.h b/interface/include/mbedtls/ecp.h index d8f73ae96..623910bcb 100644 --- a/interface/include/mbedtls/ecp.h +++ b/interface/include/mbedtls/ecp.h @@ -216,7 +216,7 @@ mbedtls_ecp_point; * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer * which is congruent mod \p P to the given MPI, and is close enough to \p pbits * in size, so that it may be efficiently brought in the 0..P-1 range by a few - * additions or subtractions. Therefore, it is only an approximative modular + * additions or subtractions. Therefore, it is only an approximate modular * reduction. It must return 0 on success and non-zero on failure. * * \note Alternative implementations of the ECP module must obey the diff --git a/interface/include/mbedtls/entropy.h b/interface/include/mbedtls/entropy.h index 20fd6872b..6c64e3e4e 100644 --- a/interface/include/mbedtls/entropy.h +++ b/interface/include/mbedtls/entropy.h @@ -17,12 +17,13 @@ #include "md.h" -#if defined(MBEDTLS_MD_CAN_SHA512) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) +#if (defined(MBEDTLS_MD_CAN_SHA512) || defined(PSA_WANT_ALG_SHA_512)) && \ + !defined(MBEDTLS_ENTROPY_FORCE_SHA256) #define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR #define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA512 #define MBEDTLS_ENTROPY_BLOCK_SIZE 64 /**< Block size of entropy accumulator (SHA-512) */ #else -#if defined(MBEDTLS_MD_CAN_SHA256) +#if (defined(MBEDTLS_MD_CAN_SHA256) || defined(PSA_WANT_ALG_SHA_256)) #define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR #define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA256 #define MBEDTLS_ENTROPY_BLOCK_SIZE 32 /**< Block size of entropy accumulator (SHA-256) */ diff --git a/interface/include/mbedtls/error.h b/interface/include/mbedtls/error.h index 186589ac5..635f7cd84 100644 --- a/interface/include/mbedtls/error.h +++ b/interface/include/mbedtls/error.h @@ -81,7 +81,7 @@ * MD 5 5 * HKDF 5 1 (Started from top) * PKCS7 5 12 (Started from 0x5300) - * SSL 5 2 (Started from 0x5F00) + * SSL 5 3 (Started from 0x5F00) * CIPHER 6 8 (Started from 0x6080) * SSL 6 22 (Started from top, plus 0x6000) * SSL 7 20 (Started from 0x7000, gaps at diff --git a/interface/include/mbedtls/gcm.h b/interface/include/mbedtls/gcm.h index 98faa4361..390ed4c6d 100644 --- a/interface/include/mbedtls/gcm.h +++ b/interface/include/mbedtls/gcm.h @@ -115,10 +115,9 @@ int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, /** * \brief This function performs GCM encryption or decryption of a buffer. * - * \note For encryption, the output buffer can be the same as the - * input buffer. For decryption, the output buffer cannot be - * the same as input buffer. If the buffers overlap, the output - * buffer must trail at least 8 Bytes behind the input buffer. + * \note The output buffer \p output can be the same as the input + * buffer \p input. If \p output is greater than \p input, they + * cannot overlap. * * \warning When this function performs a decryption, it outputs the * authentication tag and does not verify that the data is @@ -179,9 +178,11 @@ int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, * \brief This function performs a GCM authenticated decryption of a * buffer. * - * \note For decryption, the output buffer cannot be the same as - * input buffer. If the buffers overlap, the output buffer - * must trail at least 8 Bytes behind the input buffer. + * \note The output buffer \p output can be the same as the input + * buffer \p input. If \p output is greater than \p input, they + * cannot overlap. Implementations which require + * MBEDTLS_GCM_ALT to be enabled may not provide support for + * overlapping buffers. * * \param ctx The GCM context. This must be initialized. * \param length The length of the ciphertext to decrypt, which is also @@ -287,9 +288,11 @@ int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, * to this function during an operation, then it is * correct to use \p output_size = \p input_length. * - * \note For decryption, the output buffer cannot be the same as - * input buffer. If the buffers overlap, the output buffer - * must trail at least 8 Bytes behind the input buffer. + * \note The output buffer \p output can be the same as the input + * buffer \p input. If \p output is greater than \p input, they + * cannot overlap. Implementations which require + * MBEDTLS_GCM_ALT to be enabled may not provide support for + * overlapping buffers. * * \param ctx The GCM context. This must be initialized. * \param input The buffer holding the input data. If \p input_length diff --git a/interface/include/mbedtls/net_sockets.h b/interface/include/mbedtls/net_sockets.h index 85c11971d..8e69bc0fb 100644 --- a/interface/include/mbedtls/net_sockets.h +++ b/interface/include/mbedtls/net_sockets.h @@ -229,7 +229,7 @@ int mbedtls_net_recv(void *ctx, unsigned char *buf, size_t len); /** * \brief Write at most 'len' characters. If no error occurs, - * the actual amount read is returned. + * the actual amount written is returned. * * \param ctx Socket * \param buf The buffer to read from diff --git a/interface/include/mbedtls/pk.h b/interface/include/mbedtls/pk.h index fde302f87..52f4cc6c9 100644 --- a/interface/include/mbedtls/pk.h +++ b/interface/include/mbedtls/pk.h @@ -359,32 +359,40 @@ int mbedtls_pk_setup(mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info); #if defined(MBEDTLS_USE_PSA_CRYPTO) /** - * \brief Initialize a PK context to wrap a PSA key. - * - * \note This function replaces mbedtls_pk_setup() for contexts - * that wrap a (possibly opaque) PSA key instead of - * storing and manipulating the key material directly. - * - * \param ctx The context to initialize. It must be empty (type NONE). - * \param key The PSA key to wrap, which must hold an ECC or RSA key - * pair (see notes below). - * - * \note The wrapped key must remain valid as long as the - * wrapping PK context is in use, that is at least between - * the point this function is called and the point - * mbedtls_pk_free() is called on this context. The wrapped - * key might then be independently used or destroyed. - * - * \note This function is currently only available for ECC or RSA - * key pairs (that is, keys containing private key material). - * Support for other key types may be added later. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input - * (context already used, invalid key identifier). - * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the key is not an - * ECC key pair. - * \return #MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. + * \brief Initialize a PK context to wrap a PSA key. + * + * This function creates a PK context which wraps a PSA key. The PSA wrapped + * key must be an EC or RSA key pair (DH is not suported in the PK module). + * + * Under the hood PSA functions will be used to perform the required + * operations and, based on the key type, used algorithms will be: + * * EC: + * * verify, verify_ext, sign, sign_ext: ECDSA. + * * RSA: + * * sign, decrypt: use the primary algorithm in the wrapped PSA key; + * * sign_ext: RSA PSS if the pk_type is #MBEDTLS_PK_RSASSA_PSS, otherwise + * it falls back to the sign() case; + * * verify, verify_ext, encrypt: not supported. + * + * In order for the above operations to succeed, the policy of the wrapped PSA + * key must allow the specified algorithm. + * + * Opaque PK contexts wrapping an EC keys also support \c mbedtls_pk_check_pair(), + * whereas RSA ones do not. + * + * \warning The PSA wrapped key must remain valid as long as the wrapping PK + * context is in use, that is at least between the point this function + * is called and the point mbedtls_pk_free() is called on this context. + * + * \param ctx The context to initialize. It must be empty (type NONE). + * \param key The PSA key to wrap, which must hold an ECC or RSA key pair. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input (context already + * used, invalid key identifier). + * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the key is not an ECC or + * RSA key pair. + * \return #MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. */ int mbedtls_pk_setup_opaque(mbedtls_pk_context *ctx, const mbedtls_svc_key_id_t key); diff --git a/interface/include/mbedtls/psa_util.h b/interface/include/mbedtls/psa_util.h index c78cc2333..b898f1f8d 100644 --- a/interface/include/mbedtls/psa_util.h +++ b/interface/include/mbedtls/psa_util.h @@ -161,6 +161,16 @@ static inline mbedtls_md_type_t mbedtls_md_type_from_psa_alg(psa_algorithm_t psa * \param[out] der_len On success it contains the amount of valid data * (in bytes) written to \p der. It's undefined * in case of failure. + * + * \note The behavior is undefined if \p der is null, + * even if \p der_size is 0. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_BUF_TOO_SMALL if \p der_size + * is too small or if \p bits is larger than the + * largest supported curve. + * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if one of the + * numbers in the signature is 0. */ int mbedtls_ecdsa_raw_to_der(size_t bits, const unsigned char *raw, size_t raw_len, unsigned char *der, size_t der_size, size_t *der_len); @@ -177,6 +187,15 @@ int mbedtls_ecdsa_raw_to_der(size_t bits, const unsigned char *raw, size_t raw_l * \param[out] raw_len On success it is updated with the amount of valid * data (in bytes) written to \p raw. It's undefined * in case of failure. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_BUF_TOO_SMALL if \p raw_size + * is too small or if \p bits is larger than the + * largest supported curve. + * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if the data in + * \p der is inconsistent with \p bits. + * \return An \c MBEDTLS_ERR_ASN1_xxx error code if + * \p der is malformed. */ int mbedtls_ecdsa_der_to_raw(size_t bits, const unsigned char *der, size_t der_len, unsigned char *raw, size_t raw_size, size_t *raw_len); diff --git a/interface/include/mbedtls/ssl.h b/interface/include/mbedtls/ssl.h index 172d4693b..f9b103e38 100644 --- a/interface/include/mbedtls/ssl.h +++ b/interface/include/mbedtls/ssl.h @@ -83,10 +83,7 @@ /** Processing of the Certificate handshake message failed. */ #define MBEDTLS_ERR_SSL_BAD_CERTIFICATE -0x7A00 /* Error space gap */ -/** - * Received NewSessionTicket Post Handshake Message. - * This error code is experimental and may be changed or removed without notice. - */ +/** A TLS 1.3 NewSessionTicket message has been received. */ #define MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET -0x7B00 /** Not possible to read early data */ #define MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA -0x7B80 @@ -169,6 +166,42 @@ #define MBEDTLS_ERR_SSL_VERSION_MISMATCH -0x5F00 /** Invalid value in SSL config */ #define MBEDTLS_ERR_SSL_BAD_CONFIG -0x5E80 +/* Error space gap */ +/** Attempt to verify a certificate without an expected hostname. + * This is usually insecure. + * + * In TLS clients, when a client authenticates a server through its + * certificate, the client normally checks three things: + * - the certificate chain must be valid; + * - the chain must start from a trusted CA; + * - the certificate must cover the server name that is expected by the client. + * + * Omitting any of these checks is generally insecure, and can allow a + * malicious server to impersonate a legitimate server. + * + * The third check may be safely skipped in some unusual scenarios, + * such as networks where eavesdropping is a risk but not active attacks, + * or a private PKI where the client equally trusts all servers that are + * accredited by the root CA. + * + * You should call mbedtls_ssl_set_hostname() with the expected server name + * before starting a TLS handshake on a client (unless the client is + * set up to only use PSK-based authentication, which does not rely on the + * host name). If you have determined that server name verification is not + * required for security in your scenario, call mbedtls_ssl_set_hostname() + * with \p NULL as the server name. + * + * This error is raised if all of the following conditions are met: + * + * - A TLS client is configured with the authentication mode + * #MBEDTLS_SSL_VERIFY_REQUIRED (default). + * - Certificate authentication is enabled. + * - The client does not call mbedtls_ssl_set_hostname(). + * - The configuration option + * #MBEDTLS_SSL_CLI_ALLOW_WEAK_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME + * is not enabled. + */ +#define MBEDTLS_ERR_SSL_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME -0x5D80 /* * Constants from RFC 8446 for TLS 1.3 PSK modes @@ -324,6 +357,9 @@ #define MBEDTLS_SSL_SESSION_TICKETS_DISABLED 0 #define MBEDTLS_SSL_SESSION_TICKETS_ENABLED 1 +#define MBEDTLS_SSL_TLS1_3_SIGNAL_NEW_SESSION_TICKETS_DISABLED 0 +#define MBEDTLS_SSL_TLS1_3_SIGNAL_NEW_SESSION_TICKETS_ENABLED 1 + #define MBEDTLS_SSL_PRESET_DEFAULT 0 #define MBEDTLS_SSL_PRESET_SUITEB 2 @@ -1446,6 +1482,12 @@ struct mbedtls_ssl_config { #endif #if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ defined(MBEDTLS_SSL_CLI_C) + /** Encodes two booleans, one stating whether TLS 1.2 session tickets are + * enabled or not, the other one whether the handling of TLS 1.3 + * NewSessionTicket messages is enabled or not. They are respectively set + * by mbedtls_ssl_conf_session_tickets() and + * mbedtls_ssl_conf_tls13_enable_signal_new_session_tickets(). + */ uint8_t MBEDTLS_PRIVATE(session_tickets); /*!< use session tickets? */ #endif @@ -1718,7 +1760,16 @@ struct mbedtls_ssl_context { int MBEDTLS_PRIVATE(early_data_state); #endif - unsigned MBEDTLS_PRIVATE(badmac_seen); /*!< records with a bad MAC received */ + /** Multipurpose field. + * + * - DTLS: records with a bad MAC received. + * - TLS: accumulated length of handshake fragments (up to \c in_hslen). + * + * This field is multipurpose in order to preserve the ABI in the + * Mbed TLS 3.6 LTS branch. Until 3.6.2, it was only used in DTLS + * and called `badmac_seen`. + */ + unsigned MBEDTLS_PRIVATE(badmac_seen_or_in_hsfraglen); #if defined(MBEDTLS_X509_CRT_PARSE_C) /** Callback to customize X.509 certificate chain verification */ @@ -1878,8 +1929,35 @@ struct mbedtls_ssl_context { * User settings */ #if defined(MBEDTLS_X509_CRT_PARSE_C) - char *MBEDTLS_PRIVATE(hostname); /*!< expected peer CN for verification - (and SNI if available) */ + /** Expected peer CN for verification. + * + * Also used on clients for SNI, + * and for TLS 1.3 session resumption using tickets. + * + * The value of this field can be: + * - \p NULL in a newly initialized or reset context. + * - A heap-allocated copy of the last value passed to + * mbedtls_ssl_set_hostname(), if the last call had a non-null + * \p hostname argument. + * - A special value to indicate that mbedtls_ssl_set_hostname() + * was called with \p NULL (as opposed to never having been called). + * See `mbedtls_ssl_get_hostname_pointer()` in `ssl_tls.c`. + * + * If this field contains the value \p NULL and the configuration option + * #MBEDTLS_SSL_CLI_ALLOW_WEAK_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME + * is unset, on a TLS client, attempting to verify a server certificate + * results in the error + * #MBEDTLS_ERR_SSL_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME. + * + * If this field contains the special value described above, or if + * the value is \p NULL and the configuration option + * #MBEDTLS_SSL_CLI_ALLOW_WEAK_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME + * is set, then the peer name verification is skipped, which may be + * insecure, especially on a client. Furthermore, on a client, the + * server_name extension is not sent, and the server name is ignored + * in TLS 1.3 session resumption using tickets. + */ + char *MBEDTLS_PRIVATE(hostname); #endif /* MBEDTLS_X509_CRT_PARSE_C */ #if defined(MBEDTLS_SSL_ALPN) @@ -1987,6 +2065,14 @@ void mbedtls_ssl_init(mbedtls_ssl_context *ssl); * Calling mbedtls_ssl_setup again is not supported, even * if no session is active. * + * \warning After setting up a client context, if certificate-based + * authentication is enabled, you should call + * mbedtls_ssl_set_hostname() to specifiy the expected + * name of the server. Without this, in most scenarios, + * the TLS connection is insecure. See + * #MBEDTLS_ERR_SSL_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME + * for more information. + * * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto * subsystem must have been initialized by calling * psa_crypto_init() before calling this function. @@ -2364,7 +2450,7 @@ int mbedtls_ssl_set_cid(mbedtls_ssl_context *ssl, */ int mbedtls_ssl_get_own_cid(mbedtls_ssl_context *ssl, int *enabled, - unsigned char own_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX], + unsigned char own_cid[MBEDTLS_SSL_CID_IN_LEN_MAX], size_t *own_cid_len); /** @@ -3216,16 +3302,16 @@ void mbedtls_ssl_conf_session_cache(mbedtls_ssl_config *conf, * a full handshake. * * \note This function can handle a variety of mechanisms for session - * resumption: For TLS 1.2, both session ID-based resumption and - * ticket-based resumption will be considered. For TLS 1.3, - * once implemented, sessions equate to tickets, and loading - * one or more sessions via this call will lead to their - * corresponding tickets being advertised as resumption PSKs - * by the client. - * - * \note Calling this function multiple times will only be useful - * once TLS 1.3 is supported. For TLS 1.2 connections, this - * function should be called at most once. + * resumption: For TLS 1.2, both session ID-based resumption + * and ticket-based resumption will be considered. For TLS 1.3, + * sessions equate to tickets, and loading one session by + * calling this function will lead to its corresponding ticket + * being advertised as resumption PSK by the client. This + * depends on session tickets being enabled (see + * #MBEDTLS_SSL_SESSION_TICKETS configuration option) though. + * If session tickets are disabled, a call to this function + * with a TLS 1.3 session, will not have any effect on the next + * handshake for the SSL context \p ssl. * * \param ssl The SSL context representing the connection which should * be attempted to be setup using session resumption. This @@ -3240,9 +3326,10 @@ void mbedtls_ssl_conf_session_cache(mbedtls_ssl_config *conf, * * \return \c 0 if successful. * \return \c MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if the session - * could not be loaded because of an implementation limitation. - * This error is non-fatal, and has no observable effect on - * the SSL context or the session that was attempted to be loaded. + * could not be loaded because one session has already been + * loaded. This error is non-fatal, and has no observable + * effect on the SSL context or the session that was attempted + * to be loaded. * \return Another negative error code on other kinds of failure. * * \sa mbedtls_ssl_get_session() @@ -3309,8 +3396,16 @@ int mbedtls_ssl_session_load(mbedtls_ssl_session *session, * to determine the necessary size by calling this function * with \p buf set to \c NULL and \p buf_len to \c 0. * + * \note For TLS 1.3 sessions, this feature is supported only if the + * MBEDTLS_SSL_SESSION_TICKETS configuration option is enabled, + * as in TLS 1.3 session resumption is possible only with + * tickets. + * * \return \c 0 if successful. * \return #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL if \p buf is too small. + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if the + * MBEDTLS_SSL_SESSION_TICKETS configuration option is disabled + * and the session is a TLS 1.3 session. */ int mbedtls_ssl_session_save(const mbedtls_ssl_session *session, unsigned char *buf, @@ -3952,16 +4047,29 @@ void mbedtls_ssl_conf_sig_algs(mbedtls_ssl_config *conf, #if defined(MBEDTLS_X509_CRT_PARSE_C) /** * \brief Set or reset the hostname to check against the received - * server certificate. It sets the ServerName TLS extension, - * too, if that extension is enabled. (client-side only) + * peer certificate. On a client, this also sets the + * ServerName TLS extension, if that extension is enabled. + * On a TLS 1.3 client, this also sets the server name in + * the session resumption ticket, if that feature is enabled. * * \param ssl SSL context - * \param hostname the server hostname, may be NULL to clear hostname - - * \note Maximum hostname length MBEDTLS_SSL_MAX_HOST_NAME_LEN. - * - * \return 0 if successful, MBEDTLS_ERR_SSL_ALLOC_FAILED on - * allocation failure, MBEDTLS_ERR_SSL_BAD_INPUT_DATA on + * \param hostname The server hostname. This may be \c NULL to clear + * the hostname. + * + * \note Maximum hostname length #MBEDTLS_SSL_MAX_HOST_NAME_LEN. + * + * \note If the hostname is \c NULL on a client, then the server + * is not authenticated: it only needs to have a valid + * certificate, not a certificate matching its name. + * Therefore you should always call this function on a client, + * unless the connection is set up to only allow + * pre-shared keys, or in scenarios where server + * impersonation is not a concern. See the documentation of + * #MBEDTLS_ERR_SSL_CERTIFICATE_VERIFICATION_WITHOUT_HOSTNAME + * for more details. + * + * \return 0 if successful, #MBEDTLS_ERR_SSL_ALLOC_FAILED on + * allocation failure, #MBEDTLS_ERR_SSL_BAD_INPUT_DATA on * too long input hostname. * * Hostname set to the one provided on success (cleared @@ -4425,6 +4533,10 @@ void mbedtls_ssl_conf_cert_req_ca_list(mbedtls_ssl_config *conf, * with \c mbedtls_ssl_read()), not handshake messages. * With DTLS, this affects both ApplicationData and handshake. * + * \note Defragmentation of TLS handshake messages is supported + * with some limitations. See the documentation of + * mbedtls_ssl_handshake() for details. + * * \note This sets the maximum length for a record's payload, * excluding record overhead that will be added to it, see * \c mbedtls_ssl_get_record_expansion(). @@ -4456,21 +4568,50 @@ int mbedtls_ssl_conf_max_frag_len(mbedtls_ssl_config *conf, unsigned char mfl_co void mbedtls_ssl_conf_preference_order(mbedtls_ssl_config *conf, int order); #endif /* MBEDTLS_SSL_SRV_C */ -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_CLI_C) +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C) /** - * \brief Enable / Disable session tickets (client only). - * (Default: MBEDTLS_SSL_SESSION_TICKETS_ENABLED.) + * \brief Enable / Disable TLS 1.2 session tickets (client only, + * TLS 1.2 only). Enabled by default. * * \note On server, use \c mbedtls_ssl_conf_session_tickets_cb(). * * \param conf SSL configuration - * \param use_tickets Enable or disable (MBEDTLS_SSL_SESSION_TICKETS_ENABLED or - * MBEDTLS_SSL_SESSION_TICKETS_DISABLED) + * \param use_tickets Enable or disable (#MBEDTLS_SSL_SESSION_TICKETS_ENABLED or + * #MBEDTLS_SSL_SESSION_TICKETS_DISABLED) */ void mbedtls_ssl_conf_session_tickets(mbedtls_ssl_config *conf, int use_tickets); -#endif /* MBEDTLS_SSL_SESSION_TICKETS && - MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) +/** + * \brief Enable / Disable handling of TLS 1.3 NewSessionTicket messages + * (client only, TLS 1.3 only). + * + * The handling of TLS 1.3 NewSessionTicket messages is disabled by + * default. + * + * In TLS 1.3, servers may send a NewSessionTicket message at any time, + * and may send multiple NewSessionTicket messages. By default, TLS 1.3 + * clients ignore NewSessionTicket messages. + * + * To support session tickets in TLS 1.3 clients, call this function + * with #MBEDTLS_SSL_TLS1_3_SIGNAL_NEW_SESSION_TICKETS_ENABLED. When + * this is enabled, when a client receives a NewSessionTicket message, + * the next call to a message processing functions (notably + * mbedtls_ssl_handshake() and mbedtls_ssl_read()) will return + * #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET. The client should then + * call mbedtls_ssl_get_session() to retrieve the session ticket before + * calling the same message processing function again. + * + * \param conf SSL configuration + * \param signal_new_session_tickets Enable or disable + * (#MBEDTLS_SSL_TLS1_3_SIGNAL_NEW_SESSION_TICKETS_ENABLED or + * #MBEDTLS_SSL_TLS1_3_SIGNAL_NEW_SESSION_TICKETS_DISABLED) + */ +void mbedtls_ssl_conf_tls13_enable_signal_new_session_tickets( + mbedtls_ssl_config *conf, int signal_new_session_tickets); + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ +#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */ #if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ defined(MBEDTLS_SSL_SRV_C) && \ @@ -4837,23 +4978,16 @@ const mbedtls_x509_crt *mbedtls_ssl_get_peer_cert(const mbedtls_ssl_context *ssl * \note This function can handle a variety of mechanisms for session * resumption: For TLS 1.2, both session ID-based resumption and * ticket-based resumption will be considered. For TLS 1.3, - * once implemented, sessions equate to tickets, and calling - * this function multiple times will export the available - * tickets one a time until no further tickets are available, - * in which case MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE will - * be returned. - * - * \note Calling this function multiple times will only be useful - * once TLS 1.3 is supported. For TLS 1.2 connections, this - * function should be called at most once. + * sessions equate to tickets, and if session tickets are + * enabled (see #MBEDTLS_SSL_SESSION_TICKETS configuration + * option), this function exports the last received ticket and + * the exported session may be used to resume the TLS 1.3 + * session. If session tickets are disabled, exported sessions + * cannot be used to resume a TLS 1.3 session. * * \return \c 0 if successful. In this case, \p session can be used for * session resumption by passing it to mbedtls_ssl_set_session(), * and serialized for storage via mbedtls_ssl_session_save(). - * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no further session - * is available for export. - * This error is a non-fatal, and has no observable effect on - * the SSL context or the destination session. * \return Another negative error code on other kinds of failure. * * \sa mbedtls_ssl_set_session() @@ -4885,6 +5019,10 @@ int mbedtls_ssl_get_session(const mbedtls_ssl_context *ssl, * \return #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED if DTLS is in use * and the client did not demonstrate reachability yet - in * this case you must stop using the context (see below). + * \return #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET if a TLS 1.3 + * NewSessionTicket message has been received. See the + * documentation of mbedtls_ssl_read() for more information + * about this error code. * \return #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA if early data, as * defined in RFC 8446 (TLS 1.3 specification), has been * received as part of the handshake. This is server specific @@ -4901,6 +5039,7 @@ int mbedtls_ssl_get_session(const mbedtls_ssl_context *ssl, * #MBEDTLS_ERR_SSL_WANT_WRITE, * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET or * #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA, * you must stop using the SSL context for reading or writing, * and either free it or call \c mbedtls_ssl_session_reset() @@ -4921,10 +5060,31 @@ int mbedtls_ssl_get_session(const mbedtls_ssl_context *ssl, * currently being processed might or might not contain further * DTLS records. * - * \note If the context is configured to allow TLS 1.3, or if - * #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto * subsystem must have been initialized by calling * psa_crypto_init() before calling this function. + * Otherwise, the handshake may call psa_crypto_init() + * if a negotiation involving TLS 1.3 takes place (this may + * be the case even if TLS 1.3 is offered but eventually + * not selected). + * + * \note In TLS, reception of fragmented handshake messages is + * supported with some limitations (those limitations do + * not apply to DTLS, where defragmentation is fully + * supported): + * - On an Mbed TLS server that only accepts TLS 1.2, + * the initial ClientHello message must not be fragmented. + * A TLS 1.2 ClientHello may be fragmented if the server + * also accepts TLS 1.3 connections (meaning + * that #MBEDTLS_SSL_PROTO_TLS1_3 enabled, and the + * accepted versions have not been restricted with + * mbedtls_ssl_conf_max_tls_version() or the like). + * - The first fragment of a handshake message must be + * at least 4 bytes long. + * - Non-handshake records must not be interleaved between + * the fragments of a handshake message. (This is permitted + * in TLS 1.2 but not in TLS 1.3, but Mbed TLS rejects it + * even in TLS 1.2.) */ int mbedtls_ssl_handshake(mbedtls_ssl_context *ssl); @@ -4972,6 +5132,7 @@ static inline int mbedtls_ssl_is_handshake_over(mbedtls_ssl_context *ssl) * #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE, * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET or * #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA, you must stop using * the SSL context for reading or writing, and either free it * or call \c mbedtls_ssl_session_reset() on it before @@ -5040,6 +5201,17 @@ int mbedtls_ssl_renegotiate(mbedtls_ssl_context *ssl); * \return #MBEDTLS_ERR_SSL_CLIENT_RECONNECT if we're at the server * side of a DTLS connection and the client is initiating a * new connection using the same source port. See below. + * \return #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET if a TLS 1.3 + * NewSessionTicket message has been received. + * This error code is only returned on the client side. It is + * only returned if handling of TLS 1.3 NewSessionTicket + * messages has been enabled through + * mbedtls_ssl_conf_tls13_enable_signal_new_session_tickets(). + * This error code indicates that a TLS 1.3 NewSessionTicket + * message has been received and parsed successfully by the + * client. The ticket data can be retrieved from the SSL + * context by calling mbedtls_ssl_get_session(). It remains + * available until the next call to mbedtls_ssl_read(). * \return #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA if early data, as * defined in RFC 8446 (TLS 1.3 specification), has been * received as part of the handshake. This is server specific @@ -5057,6 +5229,7 @@ int mbedtls_ssl_renegotiate(mbedtls_ssl_context *ssl); * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, * #MBEDTLS_ERR_SSL_CLIENT_RECONNECT or + * #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET or * #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA, * you must stop using the SSL context for reading or writing, * and either free it or call \c mbedtls_ssl_session_reset() @@ -5122,6 +5295,10 @@ int mbedtls_ssl_read(mbedtls_ssl_context *ssl, unsigned char *buf, size_t len); * operation is in progress (see mbedtls_ecp_set_max_ops()) - * in this case you must call this function again to complete * the handshake when you're done attending other tasks. + * \return #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET if a TLS 1.3 + * NewSessionTicket message has been received. See the + * documentation of mbedtls_ssl_read() for more information + * about this error code. * \return #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA if early data, as * defined in RFC 8446 (TLS 1.3 specification), has been * received as part of the handshake. This is server specific @@ -5138,6 +5315,7 @@ int mbedtls_ssl_read(mbedtls_ssl_context *ssl, unsigned char *buf, size_t len); * #MBEDTLS_ERR_SSL_WANT_WRITE, * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET or * #MBEDTLS_ERR_SSL_RECEIVED_EARLY_DATA, * you must stop using the SSL context for reading or writing, * and either free it or call \c mbedtls_ssl_session_reset() diff --git a/interface/include/mbedtls/threading.h b/interface/include/mbedtls/threading.h index d50d04ead..b4df0e38b 100644 --- a/interface/include/mbedtls/threading.h +++ b/interface/include/mbedtls/threading.h @@ -30,7 +30,7 @@ typedef struct mbedtls_threading_mutex_t { pthread_mutex_t MBEDTLS_PRIVATE(mutex); /* WARNING - state should only be accessed when holding the mutex lock in - * tests/src/threading_helpers.c, otherwise corruption can occur. + * framework/tests/src/threading_helpers.c, otherwise corruption can occur. * state will be 0 after a failed init or a free, and nonzero after a * successful init. This field is for testing only and thus not considered * part of the public API of Mbed TLS and may change without notice.*/ diff --git a/interface/include/psa/build_info.h b/interface/include/psa/build_info.h deleted file mode 100644 index 3ee6cd7b1..000000000 --- a/interface/include/psa/build_info.h +++ /dev/null @@ -1,20 +0,0 @@ -/** - * \file psa/build_info.h - * - * \brief Build-time PSA configuration info - * - * Include this file if you need to depend on the - * configuration options defined in mbedtls_config.h or MBEDTLS_CONFIG_FILE - * in PSA cryptography core specific files. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_BUILD_INFO_H -#define PSA_CRYPTO_BUILD_INFO_H - -#include "mbedtls/build_info.h" - -#endif /* PSA_CRYPTO_BUILD_INFO_H */ diff --git a/interface/include/psa/client.h b/interface/include/psa/client.h index b4e8b0970..61722e3ad 100644 --- a/interface/include/psa/client.h +++ b/interface/include/psa/client.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, Arm Limited. All rights reserved. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors * * SPDX-License-Identifier: BSD-3-Clause * @@ -21,6 +21,13 @@ extern "C" { #define IOVEC_LEN(arr) ((uint32_t)(sizeof(arr)/sizeof(arr[0]))) #endif +/** + * Type definitions equivalent to size_t as defined in the RoT Service + * environment. + */ +typedef uint32_t rot_size_t; +#define ROT_SIZE_MAX UINT32_MAX + /*********************** PSA Client Macros and Types *************************/ /** @@ -180,13 +187,9 @@ psa_status_t psa_call(psa_handle_t handle, int32_t type, * \param[in] handle A handle to an established connection, or the * null handle. * - * \retval void Success. - * \retval "PROGRAMMER ERROR" The call is a PROGRAMMER ERROR if one or more - * of the following are true: - * \arg An invalid handle was provided that is not - * the null handle. - * \arg The connection is currently handling a - * request. + * \note The call is a PROGRAMMER ERROR if one or more of the following occurs: + * - An invalid handle was provided that is not the null handle. + * - The connection is currently handling a request. */ void psa_close(psa_handle_t handle); diff --git a/interface/include/psa/crypto.h b/interface/include/psa/crypto.h deleted file mode 100644 index 7083bd911..000000000 --- a/interface/include/psa/crypto.h +++ /dev/null @@ -1,4835 +0,0 @@ -/** - * \file psa/crypto.h - * \brief Platform Security Architecture cryptography module - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_H -#define PSA_CRYPTO_H - -#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) -#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE -#else -#include "crypto_platform.h" -#endif - -#include - -#ifdef __DOXYGEN_ONLY__ -/* This __DOXYGEN_ONLY__ block contains mock definitions for things that - * must be defined in the crypto_platform.h header. These mock definitions - * are present in this file as a convenience to generate pretty-printed - * documentation that includes those definitions. */ - -/** \defgroup platform Implementation-specific definitions - * @{ - */ - -/**@}*/ -#endif /* __DOXYGEN_ONLY__ */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The file "crypto_types.h" declares types that encode errors, - * algorithms, key types, policies, etc. */ -#include "crypto_types.h" - -/** \defgroup version API version - * @{ - */ - -/** - * The major version of this implementation of the PSA Crypto API - */ -#define PSA_CRYPTO_API_VERSION_MAJOR 1 - -/** - * The minor version of this implementation of the PSA Crypto API - */ -#define PSA_CRYPTO_API_VERSION_MINOR 0 - -/**@}*/ - -/* The file "crypto_values.h" declares macros to build and analyze values - * of integral types defined in "crypto_types.h". */ -#include "crypto_values.h" - -/** \defgroup initialization Library initialization - * @{ - */ - -/** - * \brief Library initialization. - * - * Applications must call this function before calling any other - * function in this module. - * - * Applications may call this function more than once. Once a call - * succeeds, subsequent calls are guaranteed to succeed. - * - * If the application calls other functions before calling psa_crypto_init(), - * the behavior is undefined. Implementations are encouraged to either perform - * the operation as if the library had been initialized or to return - * #PSA_ERROR_BAD_STATE or some other applicable error. In particular, - * implementations should not return a success status if the lack of - * initialization may have security implications, for example due to improper - * seeding of the random number generator. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -psa_status_t psa_crypto_init(void); - -/**@}*/ - -/** \addtogroup attributes - * @{ - */ - -/** \def PSA_KEY_ATTRIBUTES_INIT - * - * This macro returns a suitable initializer for a key attribute structure - * of type #psa_key_attributes_t. - */ - -/** Return an initial value for a key attributes structure. - */ -static psa_key_attributes_t psa_key_attributes_init(void); - -/** Declare a key as persistent and set its key identifier. - * - * If the attribute structure currently declares the key as volatile (which - * is the default content of an attribute structure), this function sets - * the lifetime attribute to #PSA_KEY_LIFETIME_PERSISTENT. - * - * This function does not access storage, it merely stores the given - * value in the structure. - * The persistent key will be written to storage when the attribute - * structure is passed to a key creation function such as - * psa_import_key(), psa_generate_key(), psa_generate_key_ext(), - * psa_key_derivation_output_key(), psa_key_derivation_output_key_ext() - * or psa_copy_key(). - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param key The persistent identifier for the key. - */ -static void psa_set_key_id(psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t key); - -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER -/** Set the owner identifier of a key. - * - * When key identifiers encode key owner identifiers, psa_set_key_id() does - * not allow to define in key attributes the owner of volatile keys as - * psa_set_key_id() enforces the key to be persistent. - * - * This function allows to set in key attributes the owner identifier of a - * key. It is intended to be used for volatile keys. For persistent keys, - * it is recommended to use the PSA Cryptography API psa_set_key_id() to define - * the owner of a key. - * - * \param[out] attributes The attribute structure to write to. - * \param owner The key owner identifier. - */ -static void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, - mbedtls_key_owner_id_t owner); -#endif - -/** Set the location of a persistent key. - * - * To make a key persistent, you must give it a persistent key identifier - * with psa_set_key_id(). By default, a key that has a persistent identifier - * is stored in the default storage area identifier by - * #PSA_KEY_LIFETIME_PERSISTENT. Call this function to choose a storage - * area, or to explicitly declare the key as volatile. - * - * This function does not access storage, it merely stores the given - * value in the structure. - * The persistent key will be written to storage when the attribute - * structure is passed to a key creation function such as - * psa_import_key(), psa_generate_key(), psa_generate_key_ext(), - * psa_key_derivation_output_key(), psa_key_derivation_output_key_ext() - * or psa_copy_key(). - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param lifetime The lifetime for the key. - * If this is #PSA_KEY_LIFETIME_VOLATILE, the - * key will be volatile, and the key identifier - * attribute is reset to 0. - */ -static void psa_set_key_lifetime(psa_key_attributes_t *attributes, - psa_key_lifetime_t lifetime); - -/** Retrieve the key identifier from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The persistent identifier stored in the attribute structure. - * This value is unspecified if the attribute structure declares - * the key as volatile. - */ -static mbedtls_svc_key_id_t psa_get_key_id( - const psa_key_attributes_t *attributes); - -/** Retrieve the lifetime from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The lifetime value stored in the attribute structure. - */ -static psa_key_lifetime_t psa_get_key_lifetime( - const psa_key_attributes_t *attributes); - -/** Declare usage flags for a key. - * - * Usage flags are part of a key's usage policy. They encode what - * kind of operations are permitted on the key. For more details, - * refer to the documentation of the type #psa_key_usage_t. - * - * This function overwrites any usage flags - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param usage_flags The usage flags to write. - */ -static void psa_set_key_usage_flags(psa_key_attributes_t *attributes, - psa_key_usage_t usage_flags); - -/** Retrieve the usage flags from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The usage flags stored in the attribute structure. - */ -static psa_key_usage_t psa_get_key_usage_flags( - const psa_key_attributes_t *attributes); - -/** Declare the permitted algorithm policy for a key. - * - * The permitted algorithm policy of a key encodes which algorithm or - * algorithms are permitted to be used with this key. The following - * algorithm policies are supported: - * - 0 does not allow any cryptographic operation with the key. The key - * may be used for non-cryptographic actions such as exporting (if - * permitted by the usage flags). - * - An algorithm value permits this particular algorithm. - * - An algorithm wildcard built from #PSA_ALG_ANY_HASH allows the specified - * signature scheme with any hash algorithm. - * - An algorithm built from #PSA_ALG_AT_LEAST_THIS_LENGTH_MAC allows - * any MAC algorithm from the same base class (e.g. CMAC) which - * generates/verifies a MAC length greater than or equal to the length - * encoded in the wildcard algorithm. - * - An algorithm built from #PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG - * allows any AEAD algorithm from the same base class (e.g. CCM) which - * generates/verifies a tag length greater than or equal to the length - * encoded in the wildcard algorithm. - * - * This function overwrites any algorithm policy - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param alg The permitted algorithm policy to write. - */ -static void psa_set_key_algorithm(psa_key_attributes_t *attributes, - psa_algorithm_t alg); - - -/** Retrieve the algorithm policy from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The algorithm stored in the attribute structure. - */ -static psa_algorithm_t psa_get_key_algorithm( - const psa_key_attributes_t *attributes); - -/** Declare the type of a key. - * - * This function overwrites any key type - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param type The key type to write. - * If this is 0, the key type in \p attributes - * becomes unspecified. - */ -static void psa_set_key_type(psa_key_attributes_t *attributes, - psa_key_type_t type); - - -/** Declare the size of a key. - * - * This function overwrites any key size previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param bits The key size in bits. - * If this is 0, the key size in \p attributes - * becomes unspecified. Keys of size 0 are - * not supported. - */ -static void psa_set_key_bits(psa_key_attributes_t *attributes, - size_t bits); - -/** Retrieve the key type from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The key type stored in the attribute structure. - */ -static psa_key_type_t psa_get_key_type(const psa_key_attributes_t *attributes); - -/** Retrieve the key size from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The key size stored in the attribute structure, in bits. - */ -static size_t psa_get_key_bits(const psa_key_attributes_t *attributes); - -/** Retrieve the attributes of a key. - * - * This function first resets the attribute structure as with - * psa_reset_key_attributes(). It then copies the attributes of - * the given key into the given attribute structure. - * - * \note This function may allocate memory or other resources. - * Once you have called this function on an attribute structure, - * you must call psa_reset_key_attributes() to free these resources. - * - * \param[in] key Identifier of the key to query. - * \param[in,out] attributes On success, the attributes of the key. - * On failure, equivalent to a - * freshly-initialized structure. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, - psa_key_attributes_t *attributes); - -/** Reset a key attribute structure to a freshly initialized state. - * - * You must initialize the attribute structure as described in the - * documentation of the type #psa_key_attributes_t before calling this - * function. Once the structure has been initialized, you may call this - * function at any time. - * - * This function frees any auxiliary resources that the structure - * may contain. - * - * \param[in,out] attributes The attribute structure to reset. - */ -void psa_reset_key_attributes(psa_key_attributes_t *attributes); - -/**@}*/ - -/** \defgroup key_management Key management - * @{ - */ - -/** Remove non-essential copies of key material from memory. - * - * If the key identifier designates a volatile key, this functions does not do - * anything and returns successfully. - * - * If the key identifier designates a persistent key, then this function will - * free all resources associated with the key in volatile memory. The key - * data in persistent storage is not affected and the key can still be used. - * - * \param key Identifier of the key to purge. - * - * \retval #PSA_SUCCESS - * The key material will have been removed from memory if it is not - * currently required. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not a valid key identifier. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_purge_key(mbedtls_svc_key_id_t key); - -/** Make a copy of a key. - * - * Copy key material from one location to another. - * - * This function is primarily useful to copy a key from one location - * to another, since it populates a key using the material from - * another key which may have a different lifetime. - * - * This function may be used to share a key with a different party, - * subject to implementation-defined restrictions on key sharing. - * - * The policy on the source key must have the usage flag - * #PSA_KEY_USAGE_COPY set. - * This flag is sufficient to permit the copy if the key has the lifetime - * #PSA_KEY_LIFETIME_VOLATILE or #PSA_KEY_LIFETIME_PERSISTENT. - * Some secure elements do not provide a way to copy a key without - * making it extractable from the secure element. If a key is located - * in such a secure element, then the key must have both usage flags - * #PSA_KEY_USAGE_COPY and #PSA_KEY_USAGE_EXPORT in order to make - * a copy of the key outside the secure element. - * - * The resulting key may only be used in a way that conforms to - * both the policy of the original key and the policy specified in - * the \p attributes parameter: - * - The usage flags on the resulting key are the bitwise-and of the - * usage flags on the source policy and the usage flags in \p attributes. - * - If both allow the same algorithm or wildcard-based - * algorithm policy, the resulting key has the same algorithm policy. - * - If either of the policies allows an algorithm and the other policy - * allows a wildcard-based algorithm policy that includes this algorithm, - * the resulting key allows the same algorithm. - * - If the policies do not allow any algorithm in common, this function - * fails with the status #PSA_ERROR_INVALID_ARGUMENT. - * - * The effect of this function on implementation-defined attributes is - * implementation-defined. - * - * \param source_key The key to copy. It must allow the usage - * #PSA_KEY_USAGE_COPY. If a private or secret key is - * being copied outside of a secure element it must - * also allow #PSA_KEY_USAGE_EXPORT. - * \param[in] attributes The attributes for the new key. - * They are used as follows: - * - The key type and size may be 0. If either is - * nonzero, it must match the corresponding - * attribute of the source key. - * - The key location (the lifetime and, for - * persistent keys, the key identifier) is - * used directly. - * - The policy constraints (usage flags and - * algorithm policy) are combined from - * the source key and \p attributes so that - * both sets of restrictions apply, as - * described in the documentation of this function. - * \param[out] target_key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE - * \p source_key is invalid. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The lifetime or identifier in \p attributes are invalid, or - * the policy constraints on the source and specified in - * \p attributes are incompatible, or - * \p attributes specifies a key type or key size - * which does not match the attributes of the source key. - * \retval #PSA_ERROR_NOT_PERMITTED - * The source key does not have the #PSA_KEY_USAGE_COPY usage flag, or - * the source key is not exportable and its lifetime does not - * allow copying it to the target's lifetime. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, - const psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t *target_key); - - -/** - * \brief Destroy a key. - * - * This function destroys a key from both volatile - * memory and, if applicable, non-volatile storage. Implementations shall - * make a best effort to ensure that the key material cannot be recovered. - * - * This function also erases any metadata such as policies and frees - * resources associated with the key. - * - * If a key is currently in use in a multipart operation, then destroying the - * key will cause the multipart operation to fail. - * - * \warning We can only guarantee that the the key material will - * eventually be wiped from memory. With threading enabled - * and during concurrent execution, copies of the key material may - * still exist until all threads have finished using the key. - * - * \param key Identifier of the key to erase. If this is \c 0, do nothing and - * return #PSA_SUCCESS. - * - * \retval #PSA_SUCCESS - * \p key was a valid identifier and the key material that it - * referred to has been erased. Alternatively, \p key is \c 0. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key cannot be erased because it is - * read-only, either due to a policy or due to physical restrictions. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p key is not a valid identifier nor \c 0. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * There was a failure in communication with the cryptoprocessor. - * The key material may still be present in the cryptoprocessor. - * \retval #PSA_ERROR_DATA_INVALID - * This error is typically a result of either storage corruption on a - * cleartext storage backend, or an attempt to read data that was - * written by an incompatible version of the library. - * \retval #PSA_ERROR_STORAGE_FAILURE - * The storage is corrupted. Implementations shall make a best effort - * to erase key material even in this stage, however applications - * should be aware that it may be impossible to guarantee that the - * key material is not recoverable in such cases. - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * An unexpected condition which is not a storage corruption or - * a communication failure occurred. The cryptoprocessor may have - * been compromised. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_destroy_key(mbedtls_svc_key_id_t key); - -/**@}*/ - -/** \defgroup import_export Key import and export - * @{ - */ - -/** - * \brief Import a key in binary format. - * - * This function supports any output from psa_export_key(). Refer to the - * documentation of psa_export_public_key() for the format of public keys - * and to the documentation of psa_export_key() for the format for - * other key types. - * - * The key data determines the key size. The attributes may optionally - * specify a key size; in this case it must match the size determined - * from the key data. A key size of 0 in \p attributes indicates that - * the key size is solely determined by the key data. - * - * Implementations must reject an attempt to import a key of size 0. - * - * This specification supports a single format for each key type. - * Implementations may support other formats as long as the standard - * format is supported. Implementations that support other formats - * should ensure that the formats are clearly unambiguous so as to - * minimize the risk that an invalid input is accidentally interpreted - * according to a different format. - * - * \param[in] attributes The attributes for the new key. - * The key size is always determined from the - * \p data buffer. - * If the key size in \p attributes is nonzero, - * it must be equal to the size from \p data. - * \param[out] key On success, an identifier to the newly created key. - * For persistent keys, this is the key identifier - * defined in \p attributes. - * \c 0 on failure. - * \param[in] data Buffer containing the key data. The content of this - * buffer is interpreted according to the type declared - * in \p attributes. - * All implementations must support at least the format - * described in the documentation - * of psa_export_key() or psa_export_public_key() for - * the chosen type. Implementations may allow other - * formats, but should be conservative: implementations - * should err on the side of rejecting content if it - * may be erroneous (e.g. wrong type or truncated data). - * \param data_length Size of the \p data buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size is not supported, either by the - * implementation in general or in this particular persistent location. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key attributes, as a whole, are invalid, or - * the key data is not correctly formatted, or - * the size in \p attributes is nonzero and does not match the size - * of the key data. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_import_key(const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - mbedtls_svc_key_id_t *key); - - - -/** - * \brief Export a key in binary format. - * - * The output of this function can be passed to psa_import_key() to - * create an equivalent object. - * - * If the implementation of psa_import_key() supports other formats - * beyond the format specified here, the output from psa_export_key() - * must use the representation specified here, not the original - * representation. - * - * For standard key types, the output format is as follows: - * - * - For symmetric keys (including MAC keys), the format is the - * raw bytes of the key. - * - For DES, the key data consists of 8 bytes. The parity bits must be - * correct. - * - For Triple-DES, the format is the concatenation of the - * two or three DES keys. - * - For RSA key pairs (#PSA_KEY_TYPE_RSA_KEY_PAIR), the format - * is the non-encrypted DER encoding of the representation defined by - * PKCS\#1 (RFC 8017) as `RSAPrivateKey`, version 0. - * ``` - * RSAPrivateKey ::= SEQUENCE { - * version INTEGER, -- must be 0 - * modulus INTEGER, -- n - * publicExponent INTEGER, -- e - * privateExponent INTEGER, -- d - * prime1 INTEGER, -- p - * prime2 INTEGER, -- q - * exponent1 INTEGER, -- d mod (p-1) - * exponent2 INTEGER, -- d mod (q-1) - * coefficient INTEGER, -- (inverse of q) mod p - * } - * ``` - * - For elliptic curve key pairs (key types for which - * #PSA_KEY_TYPE_IS_ECC_KEY_PAIR is true), the format is - * a representation of the private value as a `ceiling(m/8)`-byte string - * where `m` is the bit size associated with the curve, i.e. the bit size - * of the order of the curve's coordinate field. This byte string is - * in little-endian order for Montgomery curves (curve types - * `PSA_ECC_FAMILY_CURVEXXX`), and in big-endian order for Weierstrass - * curves (curve types `PSA_ECC_FAMILY_SECTXXX`, `PSA_ECC_FAMILY_SECPXXX` - * and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`). - * For Weierstrass curves, this is the content of the `privateKey` field of - * the `ECPrivateKey` format defined by RFC 5915. For Montgomery curves, - * the format is defined by RFC 7748, and output is masked according to §5. - * For twisted Edwards curves, the private key is as defined by RFC 8032 - * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). - * - For Diffie-Hellman key exchange key pairs (key types for which - * #PSA_KEY_TYPE_IS_DH_KEY_PAIR is true), the - * format is the representation of the private key `x` as a big-endian byte - * string. The length of the byte string is the private key size in bytes - * (leading zeroes are not stripped). - * - For public keys (key types for which #PSA_KEY_TYPE_IS_PUBLIC_KEY is - * true), the format is the same as for psa_export_public_key(). - * - * The policy on the key must have the usage flag #PSA_KEY_USAGE_EXPORT set. - * - * \param key Identifier of the key to export. It must allow the - * usage #PSA_KEY_USAGE_EXPORT, unless it is a public - * key. - * \param[out] data Buffer where the key data is to be written. - * \param data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_EXPORT flag. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p data buffer is too small. You can determine a - * sufficient buffer size by calling - * #PSA_EXPORT_KEY_OUTPUT_SIZE(\c type, \c bits) - * where \c type is the key type - * and \c bits is the key size in bits. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_export_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** - * \brief Export a public key or the public part of a key pair in binary format. - * - * The output of this function can be passed to psa_import_key() to - * create an object that is equivalent to the public key. - * - * This specification supports a single format for each key type. - * Implementations may support other formats as long as the standard - * format is supported. Implementations that support other formats - * should ensure that the formats are clearly unambiguous so as to - * minimize the risk that an invalid input is accidentally interpreted - * according to a different format. - * - * For standard key types, the output format is as follows: - * - For RSA public keys (#PSA_KEY_TYPE_RSA_PUBLIC_KEY), the DER encoding of - * the representation defined by RFC 3279 §2.3.1 as `RSAPublicKey`. - * ``` - * RSAPublicKey ::= SEQUENCE { - * modulus INTEGER, -- n - * publicExponent INTEGER } -- e - * ``` - * - For elliptic curve keys on a twisted Edwards curve (key types for which - * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true and #PSA_KEY_TYPE_ECC_GET_FAMILY - * returns #PSA_ECC_FAMILY_TWISTED_EDWARDS), the public key is as defined - * by RFC 8032 - * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). - * - For other elliptic curve public keys (key types for which - * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true), the format is the uncompressed - * representation defined by SEC1 §2.3.3 as the content of an ECPoint. - * Let `m` be the bit size associated with the curve, i.e. the bit size of - * `q` for a curve over `F_q`. The representation consists of: - * - The byte 0x04; - * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; - * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. - * - For Diffie-Hellman key exchange public keys (key types for which - * #PSA_KEY_TYPE_IS_DH_PUBLIC_KEY is true), - * the format is the representation of the public key `y = g^x mod p` as a - * big-endian byte string. The length of the byte string is the length of the - * base prime `p` in bytes. - * - * Exporting a public key object or the public part of a key pair is - * always permitted, regardless of the key's usage flags. - * - * \param key Identifier of the key to export. - * \param[out] data Buffer where the key data is to be written. - * \param data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key is neither a public key nor a key pair. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p data buffer is too small. You can determine a - * sufficient buffer size by calling - * #PSA_EXPORT_KEY_OUTPUT_SIZE(#PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\c type), \c bits) - * where \c type is the key type - * and \c bits is the key size in bits. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length); - - - -/**@}*/ - -/** \defgroup hash Message digests - * @{ - */ - -/** Calculate the hash (digest) of a message. - * - * \note To verify the hash of a message against an - * expected value, use psa_hash_compare() instead. - * - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * \param[in] input Buffer containing the message to hash. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\p alg). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p hash_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_compute(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Calculate the hash (digest) of a message and compare it with a - * reference value. - * - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * \param[in] input Buffer containing the message to hash. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] hash Buffer containing the expected hash value. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected hash is identical to the actual hash of the input. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The hash of the message was calculated successfully, but it - * differs from the expected hash. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p input_length or \p hash_length do not match the hash size for \p alg - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_compare(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *hash, - size_t hash_length); - -/** The type of the state data structure for multipart hash operations. - * - * Before calling any function on a hash operation object, the application must - * initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_hash_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_hash_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_HASH_OPERATION_INIT, - * for example: - * \code - * psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_hash_operation_init() - * to the structure, for example: - * \code - * psa_hash_operation_t operation; - * operation = psa_hash_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_hash_operation_s psa_hash_operation_t; - -/** \def PSA_HASH_OPERATION_INIT - * - * This macro returns a suitable initializer for a hash operation object - * of type #psa_hash_operation_t. - */ - -/** Return an initial value for a hash operation object. - */ -static psa_hash_operation_t psa_hash_operation_init(void); - -/** Set up a multipart hash operation. - * - * The sequence of operations to calculate a hash (message digest) - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_hash_operation_t, e.g. #PSA_HASH_OPERATION_INIT. - * -# Call psa_hash_setup() to specify the algorithm. - * -# Call psa_hash_update() zero, one or more times, passing a fragment - * of the message each time. The hash that is calculated is the hash - * of the concatenation of these messages in order. - * -# To calculate the hash, call psa_hash_finish(). - * To compare the hash with an expected value, call psa_hash_verify(). - * - * If an error occurs at any step after a call to psa_hash_setup(), the - * operation will need to be reset by a call to psa_hash_abort(). The - * application may call psa_hash_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_hash_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_hash_finish() or psa_hash_verify(). - * - A call to psa_hash_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_hash_operation_t and not yet in use. - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a hash algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_setup(psa_hash_operation_t *operation, - psa_algorithm_t alg); - -/** Add a message fragment to a multipart hash operation. - * - * The application must call psa_hash_setup() before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \param[in,out] operation Active hash operation. - * \param[in] input Buffer containing the message fragment to hash. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_update(psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the hash of a message. - * - * The application must call psa_hash_setup() before calling this function. - * This function calculates the hash of the message formed by concatenating - * the inputs passed to preceding calls to psa_hash_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \warning Applications should not call this function if they expect - * a specific value for the hash. Call psa_hash_verify() instead. - * Beware that comparing integrity or authenticity data such as - * hash values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the hashed data which could allow an attacker to guess - * a valid hash and thereby bypass security controls. - * - * \param[in,out] operation Active hash operation. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\c alg) where \c alg is the - * hash algorithm that is calculated. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p hash buffer is too small. You can determine a - * sufficient buffer size by calling #PSA_HASH_LENGTH(\c alg) - * where \c alg is the hash algorithm that is calculated. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_finish(psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Finish the calculation of the hash of a message and compare it with - * an expected value. - * - * The application must call psa_hash_setup() before calling this function. - * This function calculates the hash of the message formed by concatenating - * the inputs passed to preceding calls to psa_hash_update(). It then - * compares the calculated hash with the expected hash passed as a - * parameter to this function. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual hash and the expected hash is performed - * in constant time. - * - * \param[in,out] operation Active hash operation. - * \param[in] hash Buffer containing the expected hash value. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected hash is identical to the actual hash of the message. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The hash of the message was calculated successfully, but it - * differs from the expected hash. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_verify(psa_hash_operation_t *operation, - const uint8_t *hash, - size_t hash_length); - -/** Abort a hash operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_hash_setup() again. - * - * You may call this function any time after the operation object has - * been initialized by one of the methods described in #psa_hash_operation_t. - * - * In particular, calling psa_hash_abort() after the operation has been - * terminated by a call to psa_hash_abort(), psa_hash_finish() or - * psa_hash_verify() is safe and has no effect. - * - * \param[in,out] operation Initialized hash operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_abort(psa_hash_operation_t *operation); - -/** Clone a hash operation. - * - * This function copies the state of an ongoing hash operation to - * a new operation object. In other words, this function is equivalent - * to calling psa_hash_setup() on \p target_operation with the same - * algorithm that \p source_operation was set up for, then - * psa_hash_update() on \p target_operation with the same input that - * that was passed to \p source_operation. After this function returns, the - * two objects are independent, i.e. subsequent calls involving one of - * the objects do not affect the other object. - * - * \param[in] source_operation The active hash operation to clone. - * \param[in,out] target_operation The operation object to set up. - * It must be initialized but not active. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The \p source_operation state is not valid (it must be active), or - * the \p target_operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, - psa_hash_operation_t *target_operation); - -/**@}*/ - -/** \defgroup MAC Message authentication codes - * @{ - */ - -/** Calculate the MAC (message authentication code) of a message. - * - * \note To verify the MAC of a message against an - * expected value, use psa_mac_verify() instead. - * Beware that comparing integrity or authenticity data such as - * MAC values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the MAC value which could allow an attacker to guess - * a valid MAC and thereby bypass security controls. - * - * \param key Identifier of the key to use for the operation. It - * must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * \param[in] input Buffer containing the input message. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Size of the \p mac buffer in bytes. - * \param[out] mac_length On success, the number of bytes - * that make up the MAC value. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p mac_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Calculate the MAC of a message and compare it with a reference value. - * - * \param key Identifier of the key to use for the operation. It - * must allow the usage PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * \param[in] input Buffer containing the input message. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] mac Buffer containing the expected MAC value. - * \param mac_length Size of the \p mac buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected MAC is identical to the actual MAC of the input. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The MAC of the message was calculated successfully, but it - * differs from the expected value. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *mac, - size_t mac_length); - -/** The type of the state data structure for multipart MAC operations. - * - * Before calling any function on a MAC operation object, the application must - * initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_mac_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_mac_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_MAC_OPERATION_INIT, - * for example: - * \code - * psa_mac_operation_t operation = PSA_MAC_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_mac_operation_init() - * to the structure, for example: - * \code - * psa_mac_operation_t operation; - * operation = psa_mac_operation_init(); - * \endcode - * - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_mac_operation_s psa_mac_operation_t; - -/** \def PSA_MAC_OPERATION_INIT - * - * This macro returns a suitable initializer for a MAC operation object of type - * #psa_mac_operation_t. - */ - -/** Return an initial value for a MAC operation object. - */ -static psa_mac_operation_t psa_mac_operation_init(void); - -/** Set up a multipart MAC calculation operation. - * - * This function sets up the calculation of the MAC - * (message authentication code) of a byte string. - * To verify the MAC of a message against an - * expected value, use psa_mac_verify_setup() instead. - * - * The sequence of operations to calculate a MAC is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. - * -# Call psa_mac_sign_setup() to specify the algorithm and key. - * -# Call psa_mac_update() zero, one or more times, passing a fragment - * of the message each time. The MAC that is calculated is the MAC - * of the concatenation of these messages in order. - * -# At the end of the message, call psa_mac_sign_finish() to finish - * calculating the MAC value and retrieve it. - * - * If an error occurs at any step after a call to psa_mac_sign_setup(), the - * operation will need to be reset by a call to psa_mac_abort(). The - * application may call psa_mac_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_mac_sign_setup(), the application must - * eventually terminate the operation through one of the following methods: - * - A successful call to psa_mac_sign_finish(). - * - A call to psa_mac_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_mac_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. It - * must remain valid until the operation terminates. - * It must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set up a multipart MAC verification operation. - * - * This function sets up the verification of the MAC - * (message authentication code) of a byte string against an expected value. - * - * The sequence of operations to verify a MAC is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. - * -# Call psa_mac_verify_setup() to specify the algorithm and key. - * -# Call psa_mac_update() zero, one or more times, passing a fragment - * of the message each time. The MAC that is calculated is the MAC - * of the concatenation of these messages in order. - * -# At the end of the message, call psa_mac_verify_finish() to finish - * calculating the actual MAC of the message and verify it against - * the expected value. - * - * If an error occurs at any step after a call to psa_mac_verify_setup(), the - * operation will need to be reset by a call to psa_mac_abort(). The - * application may call psa_mac_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_mac_verify_setup(), the application must - * eventually terminate the operation through one of the following methods: - * - A successful call to psa_mac_verify_finish(). - * - A call to psa_mac_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_mac_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. It - * must remain valid until the operation terminates. - * It must allow the usage - * PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c key is not compatible with \c alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Add a message fragment to a multipart MAC operation. - * - * The application must call psa_mac_sign_setup() or psa_mac_verify_setup() - * before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \param[in,out] operation Active MAC operation. - * \param[in] input Buffer containing the message fragment to add to - * the MAC calculation. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_update(psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the MAC of a message. - * - * The application must call psa_mac_sign_setup() before calling this function. - * This function calculates the MAC of the message formed by concatenating - * the inputs passed to preceding calls to psa_mac_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \warning Applications should not call this function if they expect - * a specific value for the MAC. Call psa_mac_verify_finish() instead. - * Beware that comparing integrity or authenticity data such as - * MAC values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the MAC value which could allow an attacker to guess - * a valid MAC and thereby bypass security controls. - * - * \param[in,out] operation Active MAC operation. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Size of the \p mac buffer in bytes. - * \param[out] mac_length On success, the number of bytes - * that make up the MAC value. This is always - * #PSA_MAC_LENGTH(\c key_type, \c key_bits, \c alg) - * where \c key_type and \c key_bits are the type and - * bit-size respectively of the key and \c alg is the - * MAC algorithm that is calculated. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p mac buffer is too small. You can determine a - * sufficient buffer size by calling PSA_MAC_LENGTH(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac sign - * operation), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_sign_finish(psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Finish the calculation of the MAC of a message and compare it with - * an expected value. - * - * The application must call psa_mac_verify_setup() before calling this function. - * This function calculates the MAC of the message formed by concatenating - * the inputs passed to preceding calls to psa_mac_update(). It then - * compares the calculated MAC with the expected MAC passed as a - * parameter to this function. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual MAC and the expected MAC is performed - * in constant time. - * - * \param[in,out] operation Active MAC operation. - * \param[in] mac Buffer containing the expected MAC value. - * \param mac_length Size of the \p mac buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected MAC is identical to the actual MAC of the message. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The MAC of the message was calculated successfully, but it - * differs from the expected MAC. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac verify - * operation), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify_finish(psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length); - -/** Abort a MAC operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_mac_sign_setup() or psa_mac_verify_setup() again. - * - * You may call this function any time after the operation object has - * been initialized by one of the methods described in #psa_mac_operation_t. - * - * In particular, calling psa_mac_abort() after the operation has been - * terminated by a call to psa_mac_abort(), psa_mac_sign_finish() or - * psa_mac_verify_finish() is safe and has no effect. - * - * \param[in,out] operation Initialized MAC operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_abort(psa_mac_operation_t *operation); - -/**@}*/ - -/** \defgroup cipher Symmetric ciphers - * @{ - */ - -/** Encrypt a message using a symmetric cipher. - * - * This function encrypts a message with a random IV (initialization - * vector). Use the multipart operation interface with a - * #psa_cipher_operation_t object to provide other forms of IV. - * - * \param key Identifier of the key to use for the operation. - * It must allow the usage #PSA_KEY_USAGE_ENCRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to encrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * The output contains the IV followed by - * the ciphertext proper. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Decrypt a message using a symmetric cipher. - * - * This function decrypts a message encrypted with a symmetric cipher. - * - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to decrypt. - * This consists of the IV followed by the - * ciphertext proper. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the plaintext is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** The type of the state data structure for multipart cipher operations. - * - * Before calling any function on a cipher operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_cipher_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_cipher_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_CIPHER_OPERATION_INIT, - * for example: - * \code - * psa_cipher_operation_t operation = PSA_CIPHER_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_cipher_operation_init() - * to the structure, for example: - * \code - * psa_cipher_operation_t operation; - * operation = psa_cipher_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_cipher_operation_s psa_cipher_operation_t; - -/** \def PSA_CIPHER_OPERATION_INIT - * - * This macro returns a suitable initializer for a cipher operation object of - * type #psa_cipher_operation_t. - */ - -/** Return an initial value for a cipher operation object. - */ -static psa_cipher_operation_t psa_cipher_operation_init(void); - -/** Set the key for a multipart symmetric encryption operation. - * - * The sequence of operations to encrypt a message with a symmetric cipher - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_cipher_operation_t, e.g. - * #PSA_CIPHER_OPERATION_INIT. - * -# Call psa_cipher_encrypt_setup() to specify the algorithm and key. - * -# Call either psa_cipher_generate_iv() or psa_cipher_set_iv() to - * generate or set the IV (initialization vector). You should use - * psa_cipher_generate_iv() unless the protocol you are implementing - * requires a specific IV value. - * -# Call psa_cipher_update() zero, one or more times, passing a fragment - * of the message each time. - * -# Call psa_cipher_finish(). - * - * If an error occurs at any step after a call to psa_cipher_encrypt_setup(), - * the operation will need to be reset by a call to psa_cipher_abort(). The - * application may call psa_cipher_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_cipher_encrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_cipher_finish(). - * - A call to psa_cipher_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set the key for a multipart symmetric decryption operation. - * - * The sequence of operations to decrypt a message with a symmetric cipher - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_cipher_operation_t, e.g. - * #PSA_CIPHER_OPERATION_INIT. - * -# Call psa_cipher_decrypt_setup() to specify the algorithm and key. - * -# Call psa_cipher_set_iv() with the IV (initialization vector) for the - * decryption. If the IV is prepended to the ciphertext, you can call - * psa_cipher_update() on a buffer containing the IV followed by the - * beginning of the message. - * -# Call psa_cipher_update() zero, one or more times, passing a fragment - * of the message each time. - * -# Call psa_cipher_finish(). - * - * If an error occurs at any step after a call to psa_cipher_decrypt_setup(), - * the operation will need to be reset by a call to psa_cipher_abort(). The - * application may call psa_cipher_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_cipher_decrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_cipher_finish(). - * - A call to psa_cipher_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Generate an IV for a symmetric encryption operation. - * - * This function generates a random IV (initialization vector), nonce - * or initial counter value for the encryption operation as appropriate - * for the chosen algorithm, key type and key size. - * - * The application must call psa_cipher_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[out] iv Buffer where the generated IV is to be written. - * \param iv_size Size of the \p iv buffer in bytes. - * \param[out] iv_length On success, the number of bytes of the - * generated IV. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p iv buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with no IV set), - * or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_generate_iv(psa_cipher_operation_t *operation, - uint8_t *iv, - size_t iv_size, - size_t *iv_length); - -/** Set the IV for a symmetric encryption or decryption operation. - * - * This function sets the IV (initialization vector), nonce - * or initial counter value for the encryption or decryption operation. - * - * The application must call psa_cipher_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \note When encrypting, applications should use psa_cipher_generate_iv() - * instead of this function, unless implementing a protocol that requires - * a non-random IV. - * - * \param[in,out] operation Active cipher operation. - * \param[in] iv Buffer containing the IV to use. - * \param iv_length Size of the IV in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p iv is not acceptable for the chosen algorithm, - * or the chosen algorithm does not use an IV. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active cipher - * encrypt operation, with no IV set), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_set_iv(psa_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length); - -/** Encrypt or decrypt a message fragment in an active cipher operation. - * - * Before calling this function, you must: - * 1. Call either psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup(). - * The choice of setup function determines whether this function - * encrypts or decrypts its input. - * 2. If the algorithm requires an IV, call psa_cipher_generate_iv() - * (recommended when encrypting) or psa_cipher_set_iv(). - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with an IV set - * if required for the algorithm), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_update(psa_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Finish encrypting or decrypting a message in a cipher operation. - * - * The application must call psa_cipher_encrypt_setup() or - * psa_cipher_decrypt_setup() before calling this function. The choice - * of setup function determines whether this function encrypts or - * decrypts its input. - * - * This function finishes the encryption or decryption of the message - * formed by concatenating the inputs passed to preceding calls to - * psa_cipher_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total input size passed to this operation is not valid for - * this particular algorithm. For example, the algorithm is a based - * on block cipher and requires a whole number of blocks, but the - * total input size is not a multiple of the block size. - * \retval #PSA_ERROR_INVALID_PADDING - * This is a decryption operation for an algorithm that includes - * padding, and the ciphertext does not contain valid padding. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with an IV set - * if required for the algorithm), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_finish(psa_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Abort a cipher operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup() again. - * - * You may call this function any time after the operation object has - * been initialized as described in #psa_cipher_operation_t. - * - * In particular, calling psa_cipher_abort() after the operation has been - * terminated by a call to psa_cipher_abort() or psa_cipher_finish() - * is safe and has no effect. - * - * \param[in,out] operation Initialized cipher operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); - -/**@}*/ - -/** \defgroup aead Authenticated encryption with associated data (AEAD) - * @{ - */ - -/** Process an authenticated encryption operation. - * - * \param key Identifier of the key to use for the - * operation. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the \p nonce buffer in bytes. - * \param[in] additional_data Additional data that will be authenticated - * but not encrypted. - * \param additional_data_length Size of \p additional_data in bytes. - * \param[in] plaintext Data that will be authenticated and - * encrypted. - * \param plaintext_length Size of \p plaintext in bytes. - * \param[out] ciphertext Output buffer for the authenticated and - * encrypted data. The additional data is not - * part of this output. For algorithms where the - * encrypted data and the authentication tag - * are defined as separate outputs, the - * authentication tag is appended to the - * encrypted data. - * \param ciphertext_size Size of the \p ciphertext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, - * \p alg, \p plaintext_length) where - * \c key_type is the type of \p key. - * - #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p - * plaintext_length) evaluates to the maximum - * ciphertext size of any supported AEAD - * encryption. - * \param[out] ciphertext_length On success, the size of the output - * in the \p ciphertext buffer. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p ciphertext_size is too small. - * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, \p alg, - * \p plaintext_length) or - * #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length) can be used to - * determine the required buffer size. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length); - -/** Process an authenticated decryption operation. - * - * \param key Identifier of the key to use for the - * operation. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the \p nonce buffer in bytes. - * \param[in] additional_data Additional data that has been authenticated - * but not encrypted. - * \param additional_data_length Size of \p additional_data in bytes. - * \param[in] ciphertext Data that has been authenticated and - * encrypted. For algorithms where the - * encrypted data and the authentication tag - * are defined as separate inputs, the buffer - * must contain the encrypted data followed - * by the authentication tag. - * \param ciphertext_length Size of \p ciphertext in bytes. - * \param[out] plaintext Output buffer for the decrypted data. - * \param plaintext_size Size of the \p plaintext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, - * \p alg, \p ciphertext_length) where - * \c key_type is the type of \p key. - * - #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p - * ciphertext_length) evaluates to the maximum - * plaintext size of any supported AEAD - * decryption. - * \param[out] plaintext_length On success, the size of the output - * in the \p plaintext buffer. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The ciphertext is not authentic. - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p plaintext_size is too small. - * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, \p alg, - * \p ciphertext_length) or - * #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length) can be used - * to determine the required buffer size. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -/** The type of the state data structure for multipart AEAD operations. - * - * Before calling any function on an AEAD operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_aead_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_aead_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_AEAD_OPERATION_INIT, - * for example: - * \code - * psa_aead_operation_t operation = PSA_AEAD_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_aead_operation_init() - * to the structure, for example: - * \code - * psa_aead_operation_t operation; - * operation = psa_aead_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_aead_operation_s psa_aead_operation_t; - -/** \def PSA_AEAD_OPERATION_INIT - * - * This macro returns a suitable initializer for an AEAD operation object of - * type #psa_aead_operation_t. - */ - -/** Return an initial value for an AEAD operation object. - */ -static psa_aead_operation_t psa_aead_operation_init(void); - -/** Set the key for a multipart authenticated encryption operation. - * - * The sequence of operations to encrypt a message with authentication - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_aead_operation_t, e.g. - * #PSA_AEAD_OPERATION_INIT. - * -# Call psa_aead_encrypt_setup() to specify the algorithm and key. - * -# If needed, call psa_aead_set_lengths() to specify the length of the - * inputs to the subsequent calls to psa_aead_update_ad() and - * psa_aead_update(). See the documentation of psa_aead_set_lengths() - * for details. - * -# Call either psa_aead_generate_nonce() or psa_aead_set_nonce() to - * generate or set the nonce. You should use - * psa_aead_generate_nonce() unless the protocol you are implementing - * requires a specific nonce value. - * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment - * of the non-encrypted additional authenticated data each time. - * -# Call psa_aead_update() zero, one or more times, passing a fragment - * of the message to encrypt each time. - * -# Call psa_aead_finish(). - * - * If an error occurs at any step after a call to psa_aead_encrypt_setup(), - * the operation will need to be reset by a call to psa_aead_abort(). The - * application may call psa_aead_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_aead_encrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_aead_finish(). - * - A call to psa_aead_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_aead_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set the key for a multipart authenticated decryption operation. - * - * The sequence of operations to decrypt a message with authentication - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_aead_operation_t, e.g. - * #PSA_AEAD_OPERATION_INIT. - * -# Call psa_aead_decrypt_setup() to specify the algorithm and key. - * -# If needed, call psa_aead_set_lengths() to specify the length of the - * inputs to the subsequent calls to psa_aead_update_ad() and - * psa_aead_update(). See the documentation of psa_aead_set_lengths() - * for details. - * -# Call psa_aead_set_nonce() with the nonce for the decryption. - * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment - * of the non-encrypted additional authenticated data each time. - * -# Call psa_aead_update() zero, one or more times, passing a fragment - * of the ciphertext to decrypt each time. - * -# Call psa_aead_verify(). - * - * If an error occurs at any step after a call to psa_aead_decrypt_setup(), - * the operation will need to be reset by a call to psa_aead_abort(). The - * application may call psa_aead_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_aead_decrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_aead_verify(). - * - A call to psa_aead_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_aead_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Generate a random nonce for an authenticated encryption operation. - * - * This function generates a random nonce for the authenticated encryption - * operation with an appropriate size for the chosen algorithm, key type - * and key size. - * - * The application must call psa_aead_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[out] nonce Buffer where the generated nonce is to be - * written. - * \param nonce_size Size of the \p nonce buffer in bytes. - * \param[out] nonce_length On success, the number of bytes of the - * generated nonce. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p nonce buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active aead encrypt - * operation, with no nonce set), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_generate_nonce(psa_aead_operation_t *operation, - uint8_t *nonce, - size_t nonce_size, - size_t *nonce_length); - -/** Set the nonce for an authenticated encryption or decryption operation. - * - * This function sets the nonce for the authenticated - * encryption or decryption operation. - * - * The application must call psa_aead_encrypt_setup() or - * psa_aead_decrypt_setup() before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \note When encrypting, applications should use psa_aead_generate_nonce() - * instead of this function, unless implementing a protocol that requires - * a non-random IV. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] nonce Buffer containing the nonce to use. - * \param nonce_length Size of the nonce in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p nonce is not acceptable for the chosen algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with no nonce - * set), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_set_nonce(psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length); - -/** Declare the lengths of the message and additional data for AEAD. - * - * The application must call this function before calling - * psa_aead_update_ad() or psa_aead_update() if the algorithm for - * the operation requires it. If the algorithm does not require it, - * calling this function is optional, but if this function is called - * then the implementation must enforce the lengths. - * - * You may call this function before or after setting the nonce with - * psa_aead_set_nonce() or psa_aead_generate_nonce(). - * - * - For #PSA_ALG_CCM, calling this function is required. - * - For the other AEAD algorithms defined in this specification, calling - * this function is not required. - * - For vendor-defined algorithm, refer to the vendor documentation. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param ad_length Size of the non-encrypted additional - * authenticated data in bytes. - * \param plaintext_length Size of the plaintext to encrypt in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * At least one of the lengths is not acceptable for the chosen - * algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and - * psa_aead_update_ad() and psa_aead_update() must not have been - * called yet), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_set_lengths(psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length); - -/** Pass additional data to an active AEAD operation. - * - * Additional data is authenticated, but not encrypted. - * - * You may call this function multiple times to pass successive fragments - * of the additional data. You may not call this function after passing - * data to encrypt or decrypt with psa_aead_update(). - * - * Before calling this function, you must: - * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). - * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, - * there is no guarantee that the input is valid. Therefore, until - * you have called psa_aead_verify() and it has returned #PSA_SUCCESS, - * treat the input as untrusted and prepare to undo any action that - * depends on the input if psa_aead_verify() returns an error status. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the fragment of - * additional data. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total input length overflows the additional data length that - * was previously specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, have a nonce - * set, have lengths set if required by the algorithm, and - * psa_aead_update() must not have been called yet), or the library - * has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_update_ad(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Encrypt or decrypt a message fragment in an active AEAD operation. - * - * Before calling this function, you must: - * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). - * The choice of setup function determines whether this function - * encrypts or decrypts its input. - * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). - * 3. Call psa_aead_update_ad() to pass all the additional data. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, - * there is no guarantee that the input is valid. Therefore, until - * you have called psa_aead_verify() and it has returned #PSA_SUCCESS: - * - Do not use the output in any way other than storing it in a - * confidential location. If you take any action that depends - * on the tentative decrypted data, this action will need to be - * undone if the input turns out not to be valid. Furthermore, - * if an adversary can observe that this action took place - * (for example through timing), they may be able to use this - * fact as an oracle to decrypt any message encrypted with the - * same key. - * - In particular, do not copy the output anywhere but to a - * memory or storage space that you have exclusive access to. - * - * This function does not require the input to be aligned to any - * particular block boundary. If the implementation can only process - * a whole block at a time, it must consume all the input provided, but - * it may delay the end of the corresponding output until a subsequent - * call to psa_aead_update(), psa_aead_finish() or psa_aead_verify() - * provides sufficient input. The amount of data that can be delayed - * in this way is bounded by #PSA_AEAD_UPDATE_OUTPUT_SIZE. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, - * \c alg, \p input_length) where - * \c key_type is the type of key and \c alg is - * the algorithm that were used to set up the - * operation. - * - #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p - * input_length) evaluates to the maximum - * output size of any supported AEAD - * algorithm. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, \c alg, \p input_length) or - * #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length) can be used to - * determine the required buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total input length overflows the plaintext length that - * was previously specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, have a nonce - * set, and have lengths set if required by the algorithm), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_update(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Finish encrypting a message in an AEAD operation. - * - * The operation must have been set up with psa_aead_encrypt_setup(). - * - * This function finishes the authentication of the additional data - * formed by concatenating the inputs passed to preceding calls to - * psa_aead_update_ad() with the plaintext formed by concatenating the - * inputs passed to preceding calls to psa_aead_update(). - * - * This function has two output buffers: - * - \p ciphertext contains trailing ciphertext that was buffered from - * preceding calls to psa_aead_update(). - * - \p tag contains the authentication tag. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[out] ciphertext Buffer where the last part of the ciphertext - * is to be written. - * \param ciphertext_size Size of the \p ciphertext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, - * \c alg) where \c key_type is the type of key - * and \c alg is the algorithm that were used to - * set up the operation. - * - #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE evaluates to - * the maximum output size of any supported AEAD - * algorithm. - * \param[out] ciphertext_length On success, the number of bytes of - * returned ciphertext. - * \param[out] tag Buffer where the authentication tag is - * to be written. - * \param tag_size Size of the \p tag buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - The exact tag size is #PSA_AEAD_TAG_LENGTH(\c - * key_type, \c key_bits, \c alg) where - * \c key_type and \c key_bits are the type and - * bit-size of the key, and \c alg is the - * algorithm that were used in the call to - * psa_aead_encrypt_setup(). - * - #PSA_AEAD_TAG_MAX_SIZE evaluates to the - * maximum tag size of any supported AEAD - * algorithm. - * \param[out] tag_length On success, the number of bytes - * that make up the returned tag. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p ciphertext or \p tag buffer is too small. - * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, \c alg) or - * #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE can be used to determine the - * required \p ciphertext buffer size. #PSA_AEAD_TAG_LENGTH(\c key_type, - * \c key_bits, \c alg) or #PSA_AEAD_TAG_MAX_SIZE can be used to - * determine the required \p tag buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total length of input to psa_aead_update() so far is - * less than the plaintext length that was previously - * specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active encryption - * operation with a nonce set), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_finish(psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length); - -/** Finish authenticating and decrypting a message in an AEAD operation. - * - * The operation must have been set up with psa_aead_decrypt_setup(). - * - * This function finishes the authenticated decryption of the message - * components: - * - * - The additional data consisting of the concatenation of the inputs - * passed to preceding calls to psa_aead_update_ad(). - * - The ciphertext consisting of the concatenation of the inputs passed to - * preceding calls to psa_aead_update(). - * - The tag passed to this function call. - * - * If the authentication tag is correct, this function outputs any remaining - * plaintext and reports success. If the authentication tag is not correct, - * this function returns #PSA_ERROR_INVALID_SIGNATURE. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual tag and the expected tag is performed - * in constant time. - * - * \param[in,out] operation Active AEAD operation. - * \param[out] plaintext Buffer where the last part of the plaintext - * is to be written. This is the remaining data - * from previous calls to psa_aead_update() - * that could not be processed until the end - * of the input. - * \param plaintext_size Size of the \p plaintext buffer in bytes. - * This must be appropriate for the selected algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, - * \c alg) where \c key_type is the type of key - * and \c alg is the algorithm that were used to - * set up the operation. - * - #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE evaluates to - * the maximum output size of any supported AEAD - * algorithm. - * \param[out] plaintext_length On success, the number of bytes of - * returned plaintext. - * \param[in] tag Buffer containing the authentication tag. - * \param tag_length Size of the \p tag buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculations were successful, but the authentication tag is - * not correct. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p plaintext buffer is too small. - * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, \c alg) or - * #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE can be used to determine the - * required buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total length of input to psa_aead_update() so far is - * less than the plaintext length that was previously - * specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active decryption - * operation with a nonce set), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_verify(psa_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length); - -/** Abort an AEAD operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_aead_encrypt_setup() or psa_aead_decrypt_setup() again. - * - * You may call this function any time after the operation object has - * been initialized as described in #psa_aead_operation_t. - * - * In particular, calling psa_aead_abort() after the operation has been - * terminated by a call to psa_aead_abort(), psa_aead_finish() or - * psa_aead_verify() is safe and has no effect. - * - * \param[in,out] operation Initialized AEAD operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_abort(psa_aead_operation_t *operation); - -/**@}*/ - -/** \defgroup asymmetric Asymmetric cryptography - * @{ - */ - -/** - * \brief Sign a message with a private key. For hash-and-sign algorithms, - * this includes the hashing step. - * - * \note To perform a multi-part hash-and-sign signature algorithm, first use - * a multi-part hash operation and then pass the resulting hash to - * psa_sign_hash(). PSA_ALG_GET_HASH(\p alg) can be used to determine the - * hash algorithm to use. - * - * \param[in] key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_MESSAGE. - * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) - * is true), that is compatible with the type of - * \p key. - * \param[in] input The input message to sign. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. This - * must be appropriate for the selected - * algorithm and key: - * - The required signature size is - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and - * bit-size respectively of key. - * - #PSA_SIGNATURE_MAX_SIZE evaluates to the - * maximum signature size of any supported - * signature algorithm. - * \param[out] signature_length On success, the number of bytes that make up - * the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, - * or it does not permit the requested algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); - -/** \brief Verify the signature of a message with a public key, using - * a hash-and-sign verification algorithm. - * - * \note To perform a multi-part hash-and-sign signature verification - * algorithm, first use a multi-part hash operation to hash the message - * and then pass the resulting hash to psa_verify_hash(). - * PSA_ALG_GET_HASH(\p alg) can be used to determine the hash algorithm - * to use. - * - * \param[in] key Identifier of the key to use for the operation. - * It must be a public key or an asymmetric key - * pair. The key must allow the usage - * #PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) - * is true), that is compatible with the type of - * \p key. - * \param[in] input The message whose signature is to be verified. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, - * or it does not permit the requested algorithm. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed signature - * is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length); - -/** - * \brief Sign a hash or short message with a private key. - * - * Note that to perform a hash-and-sign signature algorithm, you must - * first calculate the hash by calling psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). - * Then pass the resulting hash as the \p hash - * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) - * to determine the hash algorithm to use. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_HASH. - * \param alg A signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message to sign. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); - -/** - * \brief Verify the signature of a hash or short message using a public key. - * - * Note that to perform a hash-and-sign signature algorithm, you must - * first calculate the hash by calling psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). - * Then pass the resulting hash as the \p hash - * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) - * to determine the hash algorithm to use. - * - * \param key Identifier of the key to use for the operation. It - * must be a public key or an asymmetric key pair. The - * key must allow the usage - * #PSA_KEY_USAGE_VERIFY_HASH. - * \param alg A signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message whose signature is to be - * verified. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length); - -/** - * \brief Encrypt a short message with a public key. - * - * \param key Identifier of the key to use for the operation. - * It must be a public key or an asymmetric key - * pair. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p key. - * \param[in] input The message to encrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the encrypted message is to - * be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** - * \brief Decrypt a short message with a private key. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. It must - * allow the usage #PSA_KEY_USAGE_DECRYPT. - * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p key. - * \param[in] input The message to decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the decrypted message is to - * be written. - * \param output_size Size of the \c output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INVALID_PADDING \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/**@}*/ - -/** \defgroup key_derivation Key derivation and pseudorandom generation - * @{ - */ - -/** The type of the state data structure for key derivation operations. - * - * Before calling any function on a key derivation operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_key_derivation_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_key_derivation_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_KEY_DERIVATION_OPERATION_INIT, - * for example: - * \code - * psa_key_derivation_operation_t operation = PSA_KEY_DERIVATION_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_key_derivation_operation_init() - * to the structure, for example: - * \code - * psa_key_derivation_operation_t operation; - * operation = psa_key_derivation_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. - */ -typedef struct psa_key_derivation_s psa_key_derivation_operation_t; - -/** \def PSA_KEY_DERIVATION_OPERATION_INIT - * - * This macro returns a suitable initializer for a key derivation operation - * object of type #psa_key_derivation_operation_t. - */ - -/** Return an initial value for a key derivation operation object. - */ -static psa_key_derivation_operation_t psa_key_derivation_operation_init(void); - -/** Set up a key derivation operation. - * - * A key derivation algorithm takes some inputs and uses them to generate - * a byte stream in a deterministic way. - * This byte stream can be used to produce keys and other - * cryptographic material. - * - * To derive a key: - * -# Start with an initialized object of type #psa_key_derivation_operation_t. - * -# Call psa_key_derivation_setup() to select the algorithm. - * -# Provide the inputs for the key derivation by calling - * psa_key_derivation_input_bytes() or psa_key_derivation_input_key() - * as appropriate. Which inputs are needed, in what order, and whether - * they may be keys and if so of what type depends on the algorithm. - * -# Optionally set the operation's maximum capacity with - * psa_key_derivation_set_capacity(). You may do this before, in the middle - * of or after providing inputs. For some algorithms, this step is mandatory - * because the output depends on the maximum capacity. - * -# To derive a key, call psa_key_derivation_output_key() or - * psa_key_derivation_output_key_ext(). - * To derive a byte string for a different purpose, call - * psa_key_derivation_output_bytes(). - * Successive calls to these functions use successive output bytes - * calculated by the key derivation algorithm. - * -# Clean up the key derivation operation object with - * psa_key_derivation_abort(). - * - * If this function returns an error, the key derivation operation object is - * not changed. - * - * If an error occurs at any step after a call to psa_key_derivation_setup(), - * the operation will need to be reset by a call to psa_key_derivation_abort(). - * - * Implementations must reject an attempt to derive a key of size 0. - * - * \param[in,out] operation The key derivation operation object - * to set up. It must - * have been initialized but not set up yet. - * \param alg The key derivation algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c alg is not a key derivation algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a key derivation algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_setup( - psa_key_derivation_operation_t *operation, - psa_algorithm_t alg); - -/** Retrieve the current capacity of a key derivation operation. - * - * The capacity of a key derivation is the maximum number of bytes that it can - * return. When you get *N* bytes of output from a key derivation operation, - * this reduces its capacity by *N*. - * - * \param[in] operation The operation to query. - * \param[out] capacity On success, the capacity of the operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_get_capacity( - const psa_key_derivation_operation_t *operation, - size_t *capacity); - -/** Set the maximum capacity of a key derivation operation. - * - * The capacity of a key derivation operation is the maximum number of bytes - * that the key derivation operation can return from this point onwards. - * - * \param[in,out] operation The key derivation operation object to modify. - * \param capacity The new capacity of the operation. - * It must be less or equal to the operation's - * current capacity. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p capacity is larger than the operation's current capacity. - * In this case, the operation object remains valid and its capacity - * remains unchanged. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_set_capacity( - psa_key_derivation_operation_t *operation, - size_t capacity); - -/** Use the maximum possible capacity for a key derivation operation. - * - * Use this value as the capacity argument when setting up a key derivation - * to indicate that the operation should have the maximum possible capacity. - * The value of the maximum possible capacity depends on the key derivation - * algorithm. - */ -#define PSA_KEY_DERIVATION_UNLIMITED_CAPACITY ((size_t) (-1)) - -/** Provide an input for key derivation or key agreement. - * - * Which inputs are required and in what order depends on the algorithm. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function passes direct inputs, which is usually correct for - * non-secret inputs. To pass a secret input, which should be in a key - * object, call psa_key_derivation_input_key() instead of this function. - * Refer to the documentation of individual step types - * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) - * for more information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param[in] data Input data to use. - * \param data_length Size of the \p data buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow direct inputs. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_bytes( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length); - -/** Provide a numeric input for key derivation or key agreement. - * - * Which inputs are required and in what order depends on the algorithm. - * However, when an algorithm requires a particular order, numeric inputs - * usually come first as they tend to be configuration parameters. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function is used for inputs which are fixed-size non-negative - * integers. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param[in] value The value of the numeric input. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow numeric inputs. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_integer( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - uint64_t value); - -/** Provide an input for key derivation in the form of a key. - * - * Which inputs are required and in what order depends on the algorithm. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function obtains input from a key object, which is usually correct for - * secret inputs or for non-secret personalization strings kept in the key - * store. To pass a non-secret parameter which is not in the key store, - * call psa_key_derivation_input_bytes() instead of this function. - * Refer to the documentation of individual step types - * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) - * for more information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param key Identifier of the key. It must have an - * appropriate type for step and must allow the - * usage #PSA_KEY_USAGE_DERIVE or - * #PSA_KEY_USAGE_VERIFY_DERIVATION (see note) - * and the algorithm used by the operation. - * - * \note Once all inputs steps are completed, the operations will allow: - * - psa_key_derivation_output_bytes() if each input was either a direct input - * or a key with #PSA_KEY_USAGE_DERIVE set; - * - psa_key_derivation_output_key() or psa_key_derivation_output_key_ext() - * if the input for step - * #PSA_KEY_DERIVATION_INPUT_SECRET or #PSA_KEY_DERIVATION_INPUT_PASSWORD - * was from a key slot with #PSA_KEY_USAGE_DERIVE and each other input was - * either a direct input or a key with #PSA_KEY_USAGE_DERIVE set; - * - psa_key_derivation_verify_bytes() if each input was either a direct input - * or a key with #PSA_KEY_USAGE_VERIFY_DERIVATION set; - * - psa_key_derivation_verify_key() under the same conditions as - * psa_key_derivation_verify_bytes(). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key allows neither #PSA_KEY_USAGE_DERIVE nor - * #PSA_KEY_USAGE_VERIFY_DERIVATION, or it doesn't allow this - * algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow key inputs of the given type - * or does not allow key inputs at all. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_key( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t key); - -/** Perform a key agreement and use the shared secret as input to a key - * derivation. - * - * A key agreement algorithm takes two inputs: a private key \p private_key - * a public key \p peer_key. - * The result of this function is passed as input to a key derivation. - * The output of this key derivation can be extracted by reading from the - * resulting operation to produce keys and other cryptographic material. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() with a - * key agreement and derivation algorithm - * \c alg (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_KEY_AGREEMENT(\c alg) is true - * and #PSA_ALG_IS_RAW_KEY_AGREEMENT(\c alg) - * is false). - * The operation must be ready for an - * input of the type given by \p step. - * \param step Which step the input data is for. - * \param private_key Identifier of the private key to use. It must - * allow the usage #PSA_KEY_USAGE_DERIVE. - * \param[in] peer_key Public key of the peer. The peer key must be in the - * same format that psa_import_key() accepts for the - * public key type corresponding to the type of - * private_key. That is, this function performs the - * equivalent of - * #psa_import_key(..., - * `peer_key`, `peer_key_length`) where - * with key attributes indicating the public key - * type corresponding to the type of `private_key`. - * For example, for EC keys, this means that peer_key - * is interpreted as a point on the curve that the - * private key is on. The standard formats for public - * keys are documented in the documentation of - * psa_export_public_key(). - * \param peer_key_length Size of \p peer_key in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c private_key is not compatible with \c alg, - * or \p peer_key is not valid for \c alg or not compatible with - * \c private_key, or \c step does not allow an input resulting - * from a key agreement. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a key derivation algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this key agreement \p step, - * or the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_key_agreement( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length); - -/** Read some data from a key derivation operation. - * - * This function calculates output bytes from a key derivation algorithm and - * return those bytes. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the requested number of bytes from the - * stream. - * The operation's capacity decreases by the number of bytes read. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[out] output Buffer where the output will be written. - * \param output_length Number of bytes to output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * One of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_DERIVE. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * \p output_length bytes. Note that in this case, - * no output is written to the output buffer. - * The operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller output buffer. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_output_bytes( - psa_key_derivation_operation_t *operation, - uint8_t *output, - size_t output_length); - -/** Derive a key from an ongoing key derivation operation. - * - * This function calculates output bytes from a key derivation algorithm - * and uses those bytes to generate a key deterministically. - * The key's location, usage policy, type and size are taken from - * \p attributes. - * - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads as many bytes as required from the - * stream. - * The operation's capacity decreases by the number of bytes read. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * How much output is produced and consumed from the operation, and how - * the key is derived, depends on the key type and on the key size - * (denoted \c bits below): - * - * - For key types for which the key is an arbitrary sequence of bytes - * of a given size, this function is functionally equivalent to - * calling #psa_key_derivation_output_bytes - * and passing the resulting output to #psa_import_key. - * However, this function has a security benefit: - * if the implementation provides an isolation boundary then - * the key material is not exposed outside the isolation boundary. - * As a consequence, for these key types, this function always consumes - * exactly (\c bits / 8) bytes from the operation. - * The following key types defined in this specification follow this scheme: - * - * - #PSA_KEY_TYPE_AES; - * - #PSA_KEY_TYPE_ARIA; - * - #PSA_KEY_TYPE_CAMELLIA; - * - #PSA_KEY_TYPE_DERIVE; - * - #PSA_KEY_TYPE_HMAC; - * - #PSA_KEY_TYPE_PASSWORD_HASH. - * - * - For ECC keys on a Montgomery elliptic curve - * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a - * Montgomery curve), this function always draws a byte string whose - * length is determined by the curve, and sets the mandatory bits - * accordingly. That is: - * - * - Curve25519 (#PSA_ECC_FAMILY_MONTGOMERY, 255 bits): draw a 32-byte - * string and process it as specified in RFC 7748 §5. - * - Curve448 (#PSA_ECC_FAMILY_MONTGOMERY, 448 bits): draw a 56-byte - * string and process it as specified in RFC 7748 §5. - * - * - For key types for which the key is represented by a single sequence of - * \c bits bits with constraints as to which bit sequences are acceptable, - * this function draws a byte string of length (\c bits / 8) bytes rounded - * up to the nearest whole number of bytes. If the resulting byte string - * is acceptable, it becomes the key, otherwise the drawn bytes are discarded. - * This process is repeated until an acceptable byte string is drawn. - * The byte string drawn from the operation is interpreted as specified - * for the output produced by psa_export_key(). - * The following key types defined in this specification follow this scheme: - * - * - #PSA_KEY_TYPE_DES. - * Force-set the parity bits, but discard forbidden weak keys. - * For 2-key and 3-key triple-DES, the three keys are generated - * successively (for example, for 3-key triple-DES, - * if the first 8 bytes specify a weak key and the next 8 bytes do not, - * discard the first 8 bytes, use the next 8 bytes as the first key, - * and continue reading output from the operation to derive the other - * two keys). - * - Finite-field Diffie-Hellman keys (#PSA_KEY_TYPE_DH_KEY_PAIR(\c group) - * where \c group designates any Diffie-Hellman group) and - * ECC keys on a Weierstrass elliptic curve - * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a - * Weierstrass curve). - * For these key types, interpret the byte string as integer - * in big-endian order. Discard it if it is not in the range - * [0, *N* - 2] where *N* is the boundary of the private key domain - * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, - * or the order of the curve's base point for ECC). - * Add 1 to the resulting integer and use this as the private key *x*. - * This method allows compliance to NIST standards, specifically - * the methods titled "key-pair generation by testing candidates" - * in NIST SP 800-56A §5.6.1.1.4 for Diffie-Hellman, - * in FIPS 186-4 §B.1.2 for DSA, and - * in NIST SP 800-56A §5.6.1.2.2 or - * FIPS 186-4 §B.4.2 for elliptic curve keys. - * - * - For other key types, including #PSA_KEY_TYPE_RSA_KEY_PAIR, - * the way in which the operation output is consumed is - * implementation-defined. - * - * In all cases, the data that is read is discarded from the operation. - * The operation's capacity is decreased by the number of bytes read. - * - * For algorithms that take an input step #PSA_KEY_DERIVATION_INPUT_SECRET, - * the input to that step must be provided with psa_key_derivation_input_key(). - * Future versions of this specification may include additional restrictions - * on the derived key based on the attributes and strength of the secret key. - * - * \note This function is equivalent to calling - * psa_key_derivation_output_key_ext() - * with the production parameters #PSA_KEY_PRODUCTION_PARAMETERS_INIT - * and `params_data_length == 0` (i.e. `params->data` is empty). - * - * \param[in] attributes The attributes for the new key. - * If the key type to be created is - * #PSA_KEY_TYPE_PASSWORD_HASH then the algorithm in - * the policy must be the same as in the current - * operation. - * \param[in,out] operation The key derivation operation object to read from. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * There was not enough data to create the desired key. - * Note that in this case, no output is written to the output buffer. - * The operation's capacity is set to 0, thus subsequent calls to - * this function will not succeed, even with a smaller output buffer. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size is not supported, either by the - * implementation in general or in this particular location. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The provided key attributes are not valid for the operation. - * \retval #PSA_ERROR_NOT_PERMITTED - * The #PSA_KEY_DERIVATION_INPUT_SECRET or - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input was not provided through a - * key; or one of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_DERIVE. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_output_key( - const psa_key_attributes_t *attributes, - psa_key_derivation_operation_t *operation, - mbedtls_svc_key_id_t *key); - -/** Derive a key from an ongoing key derivation operation with custom - * production parameters. - * - * See the description of psa_key_derivation_out_key() for the operation of - * this function with the default production parameters. - * Mbed TLS currently does not currently support any non-default production - * parameters. - * - * \note This function is experimental and may change in future minor - * versions of Mbed TLS. - * - * \param[in] attributes The attributes for the new key. - * If the key type to be created is - * #PSA_KEY_TYPE_PASSWORD_HASH then the algorithm in - * the policy must be the same as in the current - * operation. - * \param[in,out] operation The key derivation operation object to read from. - * \param[in] params Customization parameters for the key derivation. - * When this is #PSA_KEY_PRODUCTION_PARAMETERS_INIT - * with \p params_data_length = 0, - * this function is equivalent to - * psa_key_derivation_output_key(). - * Mbed TLS currently only supports the default - * production parameters, i.e. - * #PSA_KEY_PRODUCTION_PARAMETERS_INIT, - * for all key types. - * \param params_data_length - * Length of `params->data` in bytes. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * There was not enough data to create the desired key. - * Note that in this case, no output is written to the output buffer. - * The operation's capacity is set to 0, thus subsequent calls to - * this function will not succeed, even with a smaller output buffer. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size is not supported, either by the - * implementation in general or in this particular location. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The provided key attributes are not valid for the operation. - * \retval #PSA_ERROR_NOT_PERMITTED - * The #PSA_KEY_DERIVATION_INPUT_SECRET or - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input was not provided through a - * key; or one of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_DERIVE. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_output_key_ext( - const psa_key_attributes_t *attributes, - psa_key_derivation_operation_t *operation, - const psa_key_production_parameters_t *params, - size_t params_data_length, - mbedtls_svc_key_id_t *key); - -/** Compare output data from a key derivation operation to an expected value. - * - * This function calculates output bytes from a key derivation algorithm and - * compares those bytes to an expected value in constant time. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the expected number of bytes from the - * stream before comparing them. - * The operation's capacity decreases by the number of bytes read. - * - * This is functionally equivalent to the following code: - * \code - * psa_key_derivation_output_bytes(operation, tmp, output_length); - * if (memcmp(output, tmp, output_length) != 0) - * return PSA_ERROR_INVALID_SIGNATURE; - * \endcode - * except (1) it works even if the key's policy does not allow outputting the - * bytes, and (2) the comparison will be done in constant time. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, - * the operation enters an error state and must be aborted by calling - * psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[in] expected_output Buffer containing the expected derivation output. - * \param output_length Length of the expected output; this is also the - * number of bytes that will be read. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The output was read successfully, but it differs from the expected - * output. - * \retval #PSA_ERROR_NOT_PERMITTED - * One of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_VERIFY_DERIVATION. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * \p output_length bytes. Note that in this case, - * the operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller expected output. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_verify_bytes( - psa_key_derivation_operation_t *operation, - const uint8_t *expected_output, - size_t output_length); - -/** Compare output data from a key derivation operation to an expected value - * stored in a key object. - * - * This function calculates output bytes from a key derivation algorithm and - * compares those bytes to an expected value, provided as key of type - * #PSA_KEY_TYPE_PASSWORD_HASH. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the number of bytes corresponding to the - * length of the expected value from the stream before comparing them. - * The operation's capacity decreases by the number of bytes read. - * - * This is functionally equivalent to exporting the key and calling - * psa_key_derivation_verify_bytes() on the result, except that it - * works even if the key cannot be exported. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, - * the operation enters an error state and must be aborted by calling - * psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[in] expected A key of type #PSA_KEY_TYPE_PASSWORD_HASH - * containing the expected output. Its policy must - * include the #PSA_KEY_USAGE_VERIFY_DERIVATION flag - * and the permitted algorithm must match the - * operation. The value of this key was likely - * computed by a previous call to - * psa_key_derivation_output_key() or - * psa_key_derivation_output_key_ext(). - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The output was read successfully, but if differs from the expected - * output. - * \retval #PSA_ERROR_INVALID_HANDLE - * The key passed as the expected value does not exist. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key passed as the expected value has an invalid type. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key passed as the expected value does not allow this usage or - * this algorithm; or one of the inputs was a key whose policy didn't - * allow #PSA_KEY_USAGE_VERIFY_DERIVATION. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * the length of the expected value. In this case, - * the operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller expected output. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_verify_key( - psa_key_derivation_operation_t *operation, - psa_key_id_t expected); - -/** Abort a key derivation operation. - * - * Aborting an operation frees all associated resources except for the \c - * operation structure itself. Once aborted, the operation object can be reused - * for another operation by calling psa_key_derivation_setup() again. - * - * This function may be called at any time after the operation - * object has been initialized as described in #psa_key_derivation_operation_t. - * - * In particular, it is valid to call psa_key_derivation_abort() twice, or to - * call psa_key_derivation_abort() on an operation that has not been set up. - * - * \param[in,out] operation The operation to abort. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_abort( - psa_key_derivation_operation_t *operation); - -/** Perform a key agreement and return the raw shared secret. - * - * \warning The raw result of a key agreement algorithm such as finite-field - * Diffie-Hellman or elliptic curve Diffie-Hellman has biases and should - * not be used directly as key material. It should instead be passed as - * input to a key derivation algorithm. To chain a key agreement with - * a key derivation, use psa_key_derivation_key_agreement() and other - * functions from the key derivation interface. - * - * \param alg The key agreement algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_RAW_KEY_AGREEMENT(\p alg) - * is true). - * \param private_key Identifier of the private key to use. It must - * allow the usage #PSA_KEY_USAGE_DERIVE. - * \param[in] peer_key Public key of the peer. It must be - * in the same format that psa_import_key() - * accepts. The standard formats for public - * keys are documented in the documentation - * of psa_export_public_key(). - * \param peer_key_length Size of \p peer_key in bytes. - * \param[out] output Buffer where the decrypted message is to - * be written. - * \param output_size Size of the \c output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a key agreement algorithm, or - * \p private_key is not compatible with \p alg, - * or \p peer_key is not valid for \p alg or not compatible with - * \p private_key. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p output_size is too small - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported key agreement algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/**@}*/ - -/** \defgroup random Random generation - * @{ - */ - -/** - * \brief Generate random bytes. - * - * \warning This function **can** fail! Callers MUST check the return status - * and MUST NOT use the content of the output buffer if the return - * status is not #PSA_SUCCESS. - * - * \note To generate a key, use psa_generate_key() instead. - * - * \param[out] output Output buffer for the generated data. - * \param output_size Number of bytes to generate and output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_generate_random(uint8_t *output, - size_t output_size); - -/** - * \brief Generate a key or key pair. - * - * The key is generated randomly. - * Its location, usage policy, type and size are taken from \p attributes. - * - * Implementations must reject an attempt to generate a key of size 0. - * - * The following type-specific considerations apply: - * - For RSA keys (#PSA_KEY_TYPE_RSA_KEY_PAIR), - * the public exponent is 65537. - * The modulus is a product of two probabilistic primes - * between 2^{n-1} and 2^n where n is the bit size specified in the - * attributes. - * - * \note This function is equivalent to calling psa_generate_key_ext() - * with the production parameters #PSA_KEY_PRODUCTION_PARAMETERS_INIT - * and `params_data_length == 0` (i.e. `params->data` is empty). - * - * \param[in] attributes The attributes for the new key. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t *key); - -/** - * \brief Generate a key or key pair using custom production parameters. - * - * See the description of psa_generate_key() for the operation of this - * function with the default production parameters. In addition, this function - * supports the following production customizations, described in more detail - * in the documentation of ::psa_key_production_parameters_t: - * - * - RSA keys: generation with a custom public exponent. - * - * \note This function is experimental and may change in future minor - * versions of Mbed TLS. - * - * \param[in] attributes The attributes for the new key. - * \param[in] params Customization parameters for the key generation. - * When this is #PSA_KEY_PRODUCTION_PARAMETERS_INIT - * with \p params_data_length = 0, - * this function is equivalent to - * psa_generate_key(). - * \param params_data_length - * Length of `params->data` in bytes. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_generate_key_ext(const psa_key_attributes_t *attributes, - const psa_key_production_parameters_t *params, - size_t params_data_length, - mbedtls_svc_key_id_t *key); - -/**@}*/ - -/** \defgroup interruptible_hash Interruptible sign/verify hash - * @{ - */ - -/** The type of the state data structure for interruptible hash - * signing operations. - * - * Before calling any function on a sign hash operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer - * #PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation = - * PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; - * \endcode - * - Assign the result of the function - * psa_sign_hash_interruptible_operation_init() to the structure, for - * example: - * \code - * psa_sign_hash_interruptible_operation_t operation; - * operation = psa_sign_hash_interruptible_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_sign_hash_interruptible_operation_s psa_sign_hash_interruptible_operation_t; - -/** The type of the state data structure for interruptible hash - * verification operations. - * - * Before calling any function on a sign hash operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer - * #PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation = - * PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; - * \endcode - * - Assign the result of the function - * psa_verify_hash_interruptible_operation_init() to the structure, for - * example: - * \code - * psa_verify_hash_interruptible_operation_t operation; - * operation = psa_verify_hash_interruptible_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_verify_hash_interruptible_operation_s psa_verify_hash_interruptible_operation_t; - -/** - * \brief Set the maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note The time taken to execute a single op is - * implementation specific and depends on - * software, hardware, the algorithm, key type and - * curve chosen. Even within a single operation, - * successive ops can take differing amounts of - * time. The only guarantee is that lower values - * for \p max_ops means functions will block for a - * lesser maximum amount of time. The functions - * \c psa_sign_interruptible_get_num_ops() and - * \c psa_verify_interruptible_get_num_ops() are - * provided to help with tuning this value. - * - * \note This value defaults to - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, which - * means the whole operation will be done in one - * go, regardless of the number of ops required. - * - * \note If more ops are needed to complete a - * computation, #PSA_OPERATION_INCOMPLETE will be - * returned by the function performing the - * computation. It is then the caller's - * responsibility to either call again with the - * same operation context until it returns 0 or an - * error code; or to call the relevant abort - * function if the answer is no longer required. - * - * \note The interpretation of \p max_ops is also - * implementation defined. On a hard real time - * system, this can indicate a hard deadline, as a - * real-time system needs a guarantee of not - * spending more than X time, however care must be - * taken in such an implementation to avoid the - * situation whereby calls just return, not being - * able to do any actual work within the allotted - * time. On a non-real-time system, the - * implementation can be more relaxed, but again - * whether this number should be interpreted as as - * hard or soft limit or even whether a less than - * or equals as regards to ops executed in a - * single call is implementation defined. - * - * \note For keys in local storage when no accelerator - * driver applies, please see also the - * documentation for \c mbedtls_ecp_set_max_ops(), - * which is the internal implementation in these - * cases. - * - * \warning With implementations that interpret this number - * as a hard limit, setting this number too small - * may result in an infinite loop, whereby each - * call results in immediate return with no ops - * done (as there is not enough time to execute - * any), and thus no result will ever be achieved. - * - * \note This only applies to functions whose - * documentation mentions they may return - * #PSA_OPERATION_INCOMPLETE. - * - * \param max_ops The maximum number of ops to be executed in a - * single call. This can be a number from 0 to - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, where 0 - * is the least amount of work done per call. - */ -void psa_interruptible_set_max_ops(uint32_t max_ops); - -/** - * \brief Get the maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. This will return the last - * value set by - * \c psa_interruptible_set_max_ops() or - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED if - * that function has never been called. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \return Maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. - */ -uint32_t psa_interruptible_get_max_ops(void); - -/** - * \brief Get the number of ops that a hash signing - * operation has taken so far. If the operation - * has completed, then this will represent the - * number of ops required for the entire - * operation. After initialization or calling - * \c psa_sign_hash_interruptible_abort() on - * the operation, a value of 0 will be returned. - * - * \note This interface is guaranteed re-entrant and - * thus may be called from driver code. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * This is a helper provided to help you tune the - * value passed to \c - * psa_interruptible_set_max_ops(). - * - * \param operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \return Number of ops that the operation has taken so - * far. - */ -uint32_t psa_sign_hash_get_num_ops( - const psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Get the number of ops that a hash verification - * operation has taken so far. If the operation - * has completed, then this will represent the - * number of ops required for the entire - * operation. After initialization or calling \c - * psa_verify_hash_interruptible_abort() on the - * operation, a value of 0 will be returned. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * This is a helper provided to help you tune the - * value passed to \c - * psa_interruptible_set_max_ops(). - * - * \param operation The \c - * psa_verify_hash_interruptible_operation_t to - * use. This must be initialized first. - * - * \return Number of ops that the operation has taken so - * far. - */ -uint32_t psa_verify_hash_get_num_ops( - const psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Start signing a hash or short message with a - * private key, in an interruptible manner. - * - * \see \c psa_sign_hash_complete() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_sign_hash_complete() is equivalent to - * \c psa_sign_hash() but - * \c psa_sign_hash_complete() can return early and - * resume according to the limit set with \c - * psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function call. - * - * \note Users should call \c psa_sign_hash_complete() - * repeatedly on the same context after a - * successful call to this function until \c - * psa_sign_hash_complete() either returns 0 or an - * error. \c psa_sign_hash_complete() will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_sign_hash_abort() at any point if they no - * longer want the result. - * - * \note If this function returns an error status, the - * operation enters an error state and must be - * aborted by calling \c psa_sign_hash_abort(). - * - * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_HASH. - * \param alg A signature algorithm (\c PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message to sign. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - call \c psa_sign_hash_complete() - * with the same context to complete the operation - * - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_HASH flag, or it does - * not permit the requested algorithm. - * \retval #PSA_ERROR_BAD_STATE - * An operation has previously been started on this context, and is - * still in progress. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash_start( - psa_sign_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length); - -/** - * \brief Continue and eventually complete the action of - * signing a hash or short message with a private - * key, in an interruptible manner. - * - * \see \c psa_sign_hash_start() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_sign_hash_start() is equivalent to - * \c psa_sign_hash() but this function can return - * early and resume according to the limit set with - * \c psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function call. - * - * \note Users should call this function on the same - * operation object repeatedly until it either - * returns 0 or an error. This function will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_sign_hash_abort() at any point if they no - * longer want the result. - * - * \note When this function returns successfully, the - * operation becomes inactive. If this function - * returns an error status, the operation enters an - * error state and must be aborted by calling - * \c psa_sign_hash_abort(). - * - * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first, and have - * had \c psa_sign_hash_start() called with it - * first. - * - * \param[out] signature Buffer where the signature is to be written. - * \param signature_size Size of the \p signature buffer in bytes. This - * must be appropriate for the selected - * algorithm and key: - * - The required signature size is - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c - * key_bits, \c alg) where \c key_type and \c - * key_bits are the type and bit-size - * respectively of key. - * - #PSA_SIGNATURE_MAX_SIZE evaluates to the - * maximum signature size of any supported - * signature algorithm. - * \param[out] signature_length On success, the number of bytes that make up - * the returned signature value. - * - * \retval #PSA_SUCCESS - * Operation completed successfully - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(). There is still work to be done. - * Call this function again with the same operation object. - * - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \c alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \c key. - * - * \retval #PSA_ERROR_BAD_STATE - * An operation was not previously started on this context via - * \c psa_sign_hash_start(). - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has either not been previously initialized by - * psa_crypto_init() or you did not previously call - * psa_sign_hash_start() with this operation object. It is - * implementation-dependent whether a failure to initialize results in - * this error code. - */ -psa_status_t psa_sign_hash_complete( - psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length); - -/** - * \brief Abort a sign hash operation. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function is the only function that clears - * the number of ops completed as part of the - * operation. Please ensure you copy this value via - * \c psa_sign_hash_get_num_ops() if required - * before calling. - * - * \note Aborting an operation frees all associated - * resources except for the \p operation structure - * itself. Once aborted, the operation object can - * be reused for another operation by calling \c - * psa_sign_hash_start() again. - * - * \note You may call this function any time after the - * operation object has been initialized. In - * particular, calling \c psa_sign_hash_abort() - * after the operation has already been terminated - * by a call to \c psa_sign_hash_abort() or - * psa_sign_hash_complete() is safe. - * - * \param[in,out] operation Initialized sign hash operation. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash_abort( - psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Start reading and verifying a hash or short - * message, in an interruptible manner. - * - * \see \c psa_verify_hash_complete() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_verify_hash_complete() is equivalent to - * \c psa_verify_hash() but \c - * psa_verify_hash_complete() can return early and - * resume according to the limit set with \c - * psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function. - * - * \note Users should call \c psa_verify_hash_complete() - * repeatedly on the same operation object after a - * successful call to this function until \c - * psa_verify_hash_complete() either returns 0 or - * an error. \c psa_verify_hash_complete() will - * return #PSA_OPERATION_INCOMPLETE if there is - * more work to do. Alternatively users can call - * \c psa_verify_hash_abort() at any point if they - * no longer want the result. - * - * \note If this function returns an error status, the - * operation enters an error state and must be - * aborted by calling \c psa_verify_hash_abort(). - * - * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \param key Identifier of the key to use for the operation. - * The key must allow the usage - * #PSA_KEY_USAGE_VERIFY_HASH. - * \param alg A signature algorithm (\c PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash whose signature is to be verified. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - please call \c - * psa_verify_hash_complete() with the same context to complete the - * operation. - * - * \retval #PSA_ERROR_BAD_STATE - * Another operation has already been started on this context, and is - * still in progress. - * - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_VERIFY_HASH flag, or it does - * not permit the requested algorithm. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash_start( - psa_verify_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - -/** - * \brief Continue and eventually complete the action of - * reading and verifying a hash or short message - * signed with a private key, in an interruptible - * manner. - * - * \see \c psa_verify_hash_start() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_verify_hash_start() is equivalent to - * \c psa_verify_hash() but this function can - * return early and resume according to the limit - * set with \c psa_interruptible_set_max_ops() to - * reduce the maximum time spent in a function - * call. - * - * \note Users should call this function on the same - * operation object repeatedly until it either - * returns 0 or an error. This function will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_verify_hash_abort() at any point if they - * no longer want the result. - * - * \note When this function returns successfully, the - * operation becomes inactive. If this function - * returns an error status, the operation enters an - * error state and must be aborted by calling - * \c psa_verify_hash_abort(). - * - * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first, and have - * had \c psa_verify_hash_start() called with it - * first. - * - * \retval #PSA_SUCCESS - * Operation completed successfully, and the passed signature is valid. - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(). There is still work to be done. - * Call this function again with the same operation object. - * - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_BAD_STATE - * An operation was not previously started on this context via - * \c psa_verify_hash_start(). - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has either not been previously initialized by - * psa_crypto_init() or you did not previously call - * psa_verify_hash_start() on this object. It is - * implementation-dependent whether a failure to initialize results in - * this error code. - */ -psa_status_t psa_verify_hash_complete( - psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Abort a verify hash operation. - * - * \warning This is a beta API, and thus subject to change at - * any point. It is not bound by the usual interface - * stability promises. - * - * \note This function is the only function that clears the - * number of ops completed as part of the operation. - * Please ensure you copy this value via - * \c psa_verify_hash_get_num_ops() if required - * before calling. - * - * \note Aborting an operation frees all associated - * resources except for the operation structure - * itself. Once aborted, the operation object can be - * reused for another operation by calling \c - * psa_verify_hash_start() again. - * - * \note You may call this function any time after the - * operation object has been initialized. - * In particular, calling \c psa_verify_hash_abort() - * after the operation has already been terminated by - * a call to \c psa_verify_hash_abort() or - * psa_verify_hash_complete() is safe. - * - * \param[in,out] operation Initialized verify hash operation. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash_abort( - psa_verify_hash_interruptible_operation_t *operation); - - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -/* The file "crypto_sizes.h" contains definitions for size calculation - * macros whose definitions are implementation-specific. */ -#include "crypto_sizes.h" - -/* The file "crypto_struct.h" contains definitions for - * implementation-specific structs that are declared above. */ -#if defined(MBEDTLS_PSA_CRYPTO_STRUCT_FILE) -#include MBEDTLS_PSA_CRYPTO_STRUCT_FILE -#else -#include "crypto_struct.h" -#endif - -/* The file "crypto_extra.h" contains vendor-specific definitions. This - * can include vendor-defined algorithms, extra functions, etc. */ -#include "crypto_extra.h" - -#endif /* PSA_CRYPTO_H */ diff --git a/interface/include/psa/crypto_adjust_auto_enabled.h b/interface/include/psa/crypto_adjust_auto_enabled.h deleted file mode 100644 index 63fb29e85..000000000 --- a/interface/include/psa/crypto_adjust_auto_enabled.h +++ /dev/null @@ -1,21 +0,0 @@ -/** - * \file psa/crypto_adjust_auto_enabled.h - * \brief Adjust PSA configuration: enable always-on features - * - * Always enable certain features which require a negligible amount of code - * to implement, to avoid some edge cases in the configuration combinatorics. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_ADJUST_AUTO_ENABLED_H -#define PSA_CRYPTO_ADJUST_AUTO_ENABLED_H - -#define PSA_WANT_KEY_TYPE_DERIVE 1 -#define PSA_WANT_KEY_TYPE_PASSWORD 1 -#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 -#define PSA_WANT_KEY_TYPE_RAW_DATA 1 - -#endif /* PSA_CRYPTO_ADJUST_AUTO_ENABLED_H */ diff --git a/interface/include/psa/crypto_adjust_config_dependencies.h b/interface/include/psa/crypto_adjust_config_dependencies.h new file mode 100644 index 000000000..92e9c4de2 --- /dev/null +++ b/interface/include/psa/crypto_adjust_config_dependencies.h @@ -0,0 +1,51 @@ +/** + * \file psa/crypto_adjust_config_dependencies.h + * \brief Adjust PSA configuration by resolving some dependencies. + * + * This is an internal header. Do not include it directly. + * + * See docs/proposed/psa-conditional-inclusion-c.md. + * If the Mbed TLS implementation of a cryptographic mechanism A depends on a + * cryptographic mechanism B then if the cryptographic mechanism A is enabled + * and not accelerated enable B. Note that if A is enabled and accelerated, it + * is not necessary to enable B for A support. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + */ + +#ifndef PSA_CRYPTO_ADJUST_CONFIG_DEPENDENCIES_H +#define PSA_CRYPTO_ADJUST_CONFIG_DEPENDENCIES_H + +#if !defined(MBEDTLS_CONFIG_FILES_READ) +#error "Do not include psa/crypto_adjust_*.h manually! This can lead to problems, " \ + "up to and including runtime errors such as buffer overflows. " \ + "If you're trying to fix a complaint from check_config.h, just remove " \ + "it from your configuration file: since Mbed TLS 3.0, it is included " \ + "automatically at the right point." +#endif /* */ + +#if (defined(PSA_WANT_ALG_TLS12_PRF) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF)) || \ + (defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS)) || \ + (defined(PSA_WANT_ALG_HKDF) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF)) || \ + (defined(PSA_WANT_ALG_HKDF_EXTRACT) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT)) || \ + (defined(PSA_WANT_ALG_HKDF_EXPAND) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND)) || \ + (defined(PSA_WANT_ALG_PBKDF2_HMAC) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_HMAC)) +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_KEY_TYPE_HMAC 1 +#endif + +#if (defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_AES_CMAC_PRF_128)) +#define PSA_WANT_KEY_TYPE_AES 1 +#define PSA_WANT_ALG_CMAC 1 +#endif + +#endif /* PSA_CRYPTO_ADJUST_CONFIG_DEPENDENCIES_H */ diff --git a/interface/include/psa/crypto_adjust_config_key_pair_types.h b/interface/include/psa/crypto_adjust_config_key_pair_types.h deleted file mode 100644 index 63afc0e40..000000000 --- a/interface/include/psa/crypto_adjust_config_key_pair_types.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file psa/crypto_adjust_config_key_pair_types.h - * \brief Adjust PSA configuration for key pair types. - * - * See docs/proposed/psa-conditional-inclusion-c.md. - * - Support non-basic operations in a keypair type implicitly enables basic - * support for that keypair type. - * - Support for a keypair type implicitly enables the corresponding public - * key type. - * - Basic support for a keypair type implicilty enables import/export support - * for that keypair type. Warning: this is implementation-specific (mainly - * for the benefit of testing) and may change in the future! - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H -#define PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H - -/***************************************************************** - * ANYTHING -> BASIC - ****************************************************************/ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#endif - -/***************************************************************** - * BASIC -> corresponding PUBLIC - ****************************************************************/ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 -#endif - -/***************************************************************** - * BASIC -> IMPORT+EXPORT - * - * (Implementation-specific, may change in the future.) - ****************************************************************/ - -/* Even though KEY_PAIR symbols' feature several level of support (BASIC, IMPORT, - * EXPORT, GENERATE, DERIVE) we're not planning to have support only for BASIC - * without IMPORT/EXPORT since these last 2 features are strongly used in tests. - * In general it is allowed to include more feature than what is strictly - * requested. - * As a consequence IMPORT and EXPORT features will be automatically enabled - * as soon as the BASIC one is. */ -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#endif - -#endif /* PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H */ diff --git a/interface/include/psa/crypto_adjust_config_synonyms.h b/interface/include/psa/crypto_adjust_config_synonyms.h deleted file mode 100644 index 332b622c9..000000000 --- a/interface/include/psa/crypto_adjust_config_synonyms.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * \file psa/crypto_adjust_config_synonyms.h - * \brief Adjust PSA configuration: enable quasi-synonyms - * - * When two features require almost the same code, we automatically enable - * both when either one is requested, to reduce the combinatorics of - * possible configurations. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H -#define PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H - -/****************************************************************/ -/* De facto synonyms */ -/****************************************************************/ - -#if defined(PSA_WANT_ALG_ECDSA_ANY) && !defined(PSA_WANT_ALG_ECDSA) -#define PSA_WANT_ALG_ECDSA PSA_WANT_ALG_ECDSA_ANY -#elif !defined(PSA_WANT_ALG_ECDSA_ANY) && defined(PSA_WANT_ALG_ECDSA) -#define PSA_WANT_ALG_ECDSA_ANY PSA_WANT_ALG_ECDSA -#endif - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW -#elif !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW PSA_WANT_ALG_RSA_PKCS1V15_SIGN -#endif - -#if defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && !defined(PSA_WANT_ALG_RSA_PSS) -#define PSA_WANT_ALG_RSA_PSS PSA_WANT_ALG_RSA_PSS_ANY_SALT -#elif !defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && defined(PSA_WANT_ALG_RSA_PSS) -#define PSA_WANT_ALG_RSA_PSS_ANY_SALT PSA_WANT_ALG_RSA_PSS -#endif - -#endif /* PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H */ diff --git a/interface/include/psa/crypto_compat.h b/interface/include/psa/crypto_compat.h deleted file mode 100644 index 2a226c01a..000000000 --- a/interface/include/psa/crypto_compat.h +++ /dev/null @@ -1,230 +0,0 @@ -/** - * \file psa/crypto_compat.h - * - * \brief PSA cryptography module: Backward compatibility aliases - * - * This header declares alternative names for macro and functions. - * New application code should not use these names. - * These names may be removed in a future version of Mbed TLS. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_COMPAT_H -#define PSA_CRYPTO_COMPAT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * To support both openless APIs and psa_open_key() temporarily, define - * psa_key_handle_t to be equal to mbedtls_svc_key_id_t. Do not mark the - * type and its utility macros and functions deprecated yet. This will be done - * in a subsequent phase. - */ -typedef mbedtls_svc_key_id_t psa_key_handle_t; - -#define PSA_KEY_HANDLE_INIT MBEDTLS_SVC_KEY_ID_INIT - -/** Check whether a handle is null. - * - * \param handle Handle - * - * \return Non-zero if the handle is null, zero otherwise. - */ -static inline int psa_key_handle_is_null(psa_key_handle_t handle) -{ - return mbedtls_svc_key_id_is_null(handle); -} - -/** Open a handle to an existing persistent key. - * - * Open a handle to a persistent key. A key is persistent if it was created - * with a lifetime other than #PSA_KEY_LIFETIME_VOLATILE. A persistent key - * always has a nonzero key identifier, set with psa_set_key_id() when - * creating the key. Implementations may provide additional pre-provisioned - * keys that can be opened with psa_open_key(). Such keys have an application - * key identifier in the vendor range, as documented in the description of - * #psa_key_id_t. - * - * The application must eventually close the handle with psa_close_key() or - * psa_destroy_key() to release associated resources. If the application dies - * without calling one of these functions, the implementation should perform - * the equivalent of a call to psa_close_key(). - * - * Some implementations permit an application to open the same key multiple - * times. If this is successful, each call to psa_open_key() will return a - * different key handle. - * - * \note This API is not part of the PSA Cryptography API Release 1.0.0 - * specification. It was defined in the 1.0 Beta 3 version of the - * specification but was removed in the 1.0.0 released version. This API is - * kept for the time being to not break applications relying on it. It is not - * deprecated yet but will be in the near future. - * - * \note Applications that rely on opening a key multiple times will not be - * portable to implementations that only permit a single key handle to be - * opened. See also :ref:\`key-handles\`. - * - * - * \param key The persistent identifier of the key. - * \param[out] handle On success, a handle to the key. - * - * \retval #PSA_SUCCESS - * Success. The application can now use the value of `*handle` - * to access the key. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * The implementation does not have sufficient resources to open the - * key. This can be due to reaching an implementation limit on the - * number of open keys, the number of open key handles, or available - * memory. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no persistent key with key identifier \p key. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not a valid persistent key identifier. - * \retval #PSA_ERROR_NOT_PERMITTED - * The specified key exists, but the application does not have the - * permission to access it. Note that this specification does not - * define any way to create such a key, but it may be possible - * through implementation-specific means. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_open_key(mbedtls_svc_key_id_t key, - psa_key_handle_t *handle); - -/** Close a key handle. - * - * If the handle designates a volatile key, this will destroy the key material - * and free all associated resources, just like psa_destroy_key(). - * - * If this is the last open handle to a persistent key, then closing the handle - * will free all resources associated with the key in volatile memory. The key - * data in persistent storage is not affected and can be opened again later - * with a call to psa_open_key(). - * - * Closing the key handle makes the handle invalid, and the key handle - * must not be used again by the application. - * - * \note This API is not part of the PSA Cryptography API Release 1.0.0 - * specification. It was defined in the 1.0 Beta 3 version of the - * specification but was removed in the 1.0.0 released version. This API is - * kept for the time being to not break applications relying on it. It is not - * deprecated yet but will be in the near future. - * - * \note If the key handle was used to set up an active - * :ref:\`multipart operation \`, then closing the - * key handle can cause the multipart operation to fail. Applications should - * maintain the key handle until after the multipart operation has finished. - * - * \param handle The key handle to close. - * If this is \c 0, do nothing and return \c PSA_SUCCESS. - * - * \retval #PSA_SUCCESS - * \p handle was a valid handle or \c 0. It is now closed. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p handle is not a valid handle nor \c 0. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_close_key(psa_key_handle_t handle); - -/** \addtogroup attributes - * @{ - */ - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** Custom Diffie-Hellman group. - * - * Mbed TLS does not support custom DH groups. - * - * \deprecated This value is not useful, so this macro will be removed in - * a future version of the library. - */ -#define PSA_DH_FAMILY_CUSTOM \ - ((psa_dh_family_t) MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(0x7e)) - -/** - * \brief Set domain parameters for a key. - * - * \deprecated Mbed TLS no longer supports any domain parameters. - * This function only does the equivalent of - * psa_set_key_type() and will be removed in a future version - * of the library. - * - * \param[in,out] attributes Attribute structure where \p type will be set. - * \param type Key type (a \c PSA_KEY_TYPE_XXX value). - * \param[in] data Ignored. - * \param data_length Must be 0. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -static inline psa_status_t MBEDTLS_DEPRECATED psa_set_key_domain_parameters( - psa_key_attributes_t *attributes, - psa_key_type_t type, const uint8_t *data, size_t data_length) -{ - (void) data; - if (data_length != 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - psa_set_key_type(attributes, type); - return PSA_SUCCESS; -} - -/** - * \brief Get domain parameters for a key. - * - * \deprecated Mbed TLS no longer supports any domain parameters. - * This function alwaya has an empty output and will be - * removed in a future version of the library. - - * \param[in] attributes Ignored. - * \param[out] data Ignored. - * \param data_size Ignored. - * \param[out] data_length Set to 0. - * - * \retval #PSA_SUCCESS \emptydescription - */ -static inline psa_status_t MBEDTLS_DEPRECATED psa_get_key_domain_parameters( - const psa_key_attributes_t *attributes, - uint8_t *data, size_t data_size, size_t *data_length) -{ - (void) attributes; - (void) data; - (void) data_size; - *data_length = 0; - return PSA_SUCCESS; -} - -/** Safe output buffer size for psa_get_key_domain_parameters(). - * - */ -#define PSA_KEY_DOMAIN_PARAMETERS_SIZE(key_type, key_bits) \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(1u) -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_COMPAT_H */ diff --git a/interface/include/psa/crypto_driver_common.h b/interface/include/psa/crypto_driver_common.h deleted file mode 100644 index cc11d3b9a..000000000 --- a/interface/include/psa/crypto_driver_common.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * \file psa/crypto_driver_common.h - * \brief Definitions for all PSA crypto drivers - * - * This file contains common definitions shared by all PSA crypto drivers. - * Do not include it directly: instead, include the header file(s) for - * the type(s) of driver that you are implementing. For example, if - * you are writing a dynamically registered driver for a secure element, - * include `psa/crypto_se_driver.h`. - * - * This file is part of the PSA Crypto Driver Model, containing functions for - * driver developers to implement to enable hardware to be called in a - * standardized way by a PSA Cryptographic API implementation. The functions - * comprising the driver model, which driver authors implement, are not - * intended to be called by application developers. - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ -#ifndef PSA_CRYPTO_DRIVER_COMMON_H -#define PSA_CRYPTO_DRIVER_COMMON_H - -#include -#include - -/* Include type definitions (psa_status_t, psa_algorithm_t, - * psa_key_type_t, etc.) and macros to build and analyze values - * of these types. */ -#include "crypto_types.h" -#include "crypto_values.h" -/* Include size definitions which are used to size some arrays in operation - * structures. */ -#include - -/** For encrypt-decrypt functions, whether the operation is an encryption - * or a decryption. */ -typedef enum { - PSA_CRYPTO_DRIVER_DECRYPT, - PSA_CRYPTO_DRIVER_ENCRYPT -} psa_encrypt_or_decrypt_t; - -#endif /* PSA_CRYPTO_DRIVER_COMMON_H */ diff --git a/interface/include/psa/crypto_driver_contexts_composites.h b/interface/include/psa/crypto_driver_contexts_composites.h deleted file mode 100644 index f6a54aefd..000000000 --- a/interface/include/psa/crypto_driver_contexts_composites.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for 'composite' - * operations, i.e. those operations which need to make use of other operations - * from the primitives (crypto_driver_contexts_primitives.h) - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_composites.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -#if defined(PSA_CRYPTO_DRIVER_CC3XX) -#include "cc3xx_crypto_primitives_private.h" -#endif - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) -#include -#endif - -#if defined(PSA_CRYPTO_DRIVER_TEST) -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC) -typedef libtestdriver1_mbedtls_psa_mac_operation_t - mbedtls_transparent_test_driver_mac_operation_t; -typedef libtestdriver1_mbedtls_psa_mac_operation_t - mbedtls_opaque_test_driver_mac_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT - -#else -typedef mbedtls_psa_mac_operation_t - mbedtls_transparent_test_driver_mac_operation_t; -typedef mbedtls_psa_mac_operation_t - mbedtls_opaque_test_driver_mac_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ - MBEDTLS_PSA_MAC_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ - MBEDTLS_PSA_MAC_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD) -typedef libtestdriver1_mbedtls_psa_aead_operation_t - mbedtls_transparent_test_driver_aead_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_AEAD_OPERATION_INIT -#else -typedef mbedtls_psa_aead_operation_t - mbedtls_transparent_test_driver_aead_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ - MBEDTLS_PSA_AEAD_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE) - -typedef libtestdriver1_mbedtls_psa_pake_operation_t - mbedtls_transparent_test_driver_pake_operation_t; -typedef libtestdriver1_mbedtls_psa_pake_operation_t - mbedtls_opaque_test_driver_pake_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT - -#else -typedef mbedtls_psa_pake_operation_t - mbedtls_transparent_test_driver_pake_operation_t; -typedef mbedtls_psa_pake_operation_t - mbedtls_opaque_test_driver_pake_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ - MBEDTLS_PSA_PAKE_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ - MBEDTLS_PSA_PAKE_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ - -/* Define the context to be used for an operation that is executed through the - * PSA Driver wrapper layer as the union of all possible driver's contexts. - * - * The union members are the driver's context structures, and the member names - * are formatted as `'drivername'_ctx`. This allows for procedural generation - * of both this file and the content of psa_crypto_driver_wrappers.h */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_mac_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_mac_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_mac_operation_t opaque_test_driver_ctx; -#endif -#if defined(PSA_CRYPTO_DRIVER_CC3XX) - cc3xx_mac_operation_t cc3xx_driver_ctx; -#endif -} psa_driver_mac_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_aead_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_aead_operation_t transparent_test_driver_ctx; -#endif -#if defined(PSA_CRYPTO_DRIVER_CC3XX) - cc3xx_aead_operation_t cc3xx_driver_ctx; -#endif /* PSA_CRYPTO_DRIVER_CC3XX */ -} psa_driver_aead_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_sign_hash_interruptible_operation_t mbedtls_ctx; -} psa_driver_sign_hash_interruptible_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_verify_hash_interruptible_operation_t mbedtls_ctx; -} psa_driver_verify_hash_interruptible_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_pake_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_pake_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_pake_operation_t opaque_test_driver_ctx; -#endif -} psa_driver_pake_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H */ -/* End of automatically generated file. */ diff --git a/interface/include/psa/crypto_driver_contexts_key_derivation.h b/interface/include/psa/crypto_driver_contexts_key_derivation.h deleted file mode 100644 index 21190515c..000000000 --- a/interface/include/psa/crypto_driver_contexts_key_derivation.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for key derivation - * operations. - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_key_derivation.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - psa_hkdf_key_derivation_t MBEDTLS_PRIVATE(hkdf); -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - psa_tls12_prf_key_derivation_t MBEDTLS_PRIVATE(tls12_prf); -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - psa_tls12_ecjpake_to_pms_t MBEDTLS_PRIVATE(tls12_ecjpake_to_pms); -#endif -#if defined(PSA_HAVE_SOFT_PBKDF2) - psa_pbkdf2_key_derivation_t MBEDTLS_PRIVATE(pbkdf2); -#endif -} psa_driver_key_derivation_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H */ -/* End of automatically generated file. */ diff --git a/interface/include/psa/crypto_driver_contexts_primitives.h b/interface/include/psa/crypto_driver_contexts_primitives.h deleted file mode 100644 index 3f00006f8..000000000 --- a/interface/include/psa/crypto_driver_contexts_primitives.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for 'primitive' - * operations, i.e. those operations which do not rely on other contexts. - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_primitives.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -#if defined(PSA_CRYPTO_DRIVER_CC3XX) -#include "cc3xx_crypto_primitives_private.h" -#endif /* PSA_CRYPTO_DRIVER_CC3XX */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) -#include -#endif - -#if defined(PSA_CRYPTO_DRIVER_TEST) - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER) -typedef libtestdriver1_mbedtls_psa_cipher_operation_t - mbedtls_transparent_test_driver_cipher_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_CIPHER_OPERATION_INIT -#else -typedef mbedtls_psa_cipher_operation_t - mbedtls_transparent_test_driver_cipher_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ - MBEDTLS_PSA_CIPHER_OPERATION_INIT -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && - LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH) -typedef libtestdriver1_mbedtls_psa_hash_operation_t - mbedtls_transparent_test_driver_hash_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_HASH_OPERATION_INIT -#else -typedef mbedtls_psa_hash_operation_t - mbedtls_transparent_test_driver_hash_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ - MBEDTLS_PSA_HASH_OPERATION_INIT -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && - LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH */ - -typedef struct { - unsigned int initialised : 1; - mbedtls_transparent_test_driver_cipher_operation_t ctx; -} mbedtls_opaque_test_driver_cipher_operation_t; - -#define MBEDTLS_OPAQUE_TEST_DRIVER_CIPHER_OPERATION_INIT \ - { 0, MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT } - -#endif /* PSA_CRYPTO_DRIVER_TEST */ - -/* Define the context to be used for an operation that is executed through the - * PSA Driver wrapper layer as the union of all possible driver's contexts. - * - * The union members are the driver's context structures, and the member names - * are formatted as `'drivername'_ctx`. This allows for procedural generation - * of both this file and the content of psa_crypto_driver_wrappers.h */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_hash_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_hash_operation_t test_driver_ctx; -#endif -#if defined(PSA_CRYPTO_DRIVER_CC3XX) - cc3xx_hash_operation_t cc3xx_driver_ctx; -#endif -} psa_driver_hash_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_cipher_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_cipher_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_cipher_operation_t opaque_test_driver_ctx; -#endif -#if defined(PSA_CRYPTO_DRIVER_CC3XX) - cc3xx_cipher_operation_t cc3xx_driver_ctx; -#endif -} psa_driver_cipher_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H */ -/* End of automatically generated file. */ diff --git a/interface/include/psa/crypto_extra.h b/interface/include/psa/crypto_extra.h deleted file mode 100644 index 6ed1f6c43..000000000 --- a/interface/include/psa/crypto_extra.h +++ /dev/null @@ -1,1883 +0,0 @@ -/** - * \file psa/crypto_extra.h - * - * \brief PSA cryptography module: Mbed TLS vendor extensions - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file is reserved for vendor-specific definitions. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_EXTRA_H -#define PSA_CRYPTO_EXTRA_H -#include "mbedtls/private_access.h" - -#include "crypto_types.h" -#include "crypto_compat.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* UID for secure storage seed */ -#define PSA_CRYPTO_ITS_RANDOM_SEED_UID 0xFFFFFF52 - -/* See mbedtls_config.h for definition */ -#if !defined(MBEDTLS_PSA_KEY_SLOT_COUNT) -#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 -#endif - -/** \addtogroup attributes - * @{ - */ - -/** \brief Declare the enrollment algorithm for a key. - * - * An operation on a key may indifferently use the algorithm set with - * psa_set_key_algorithm() or with this function. - * - * \param[out] attributes The attribute structure to write to. - * \param alg2 A second algorithm that the key may be used - * for, in addition to the algorithm set with - * psa_set_key_algorithm(). - * - * \warning Setting an enrollment algorithm is not recommended, because - * using the same key with different algorithms can allow some - * attacks based on arithmetic relations between different - * computations made with the same key, or can escalate harmless - * side channels into exploitable ones. Use this function only - * if it is necessary to support a protocol for which it has been - * verified that the usage of the key with multiple algorithms - * is safe. - */ -static inline void psa_set_key_enrollment_algorithm( - psa_key_attributes_t *attributes, - psa_algorithm_t alg2) -{ - attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2) = alg2; -} - -/** Retrieve the enrollment algorithm policy from key attributes. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The enrollment algorithm stored in the attribute structure. - */ -static inline psa_algorithm_t psa_get_key_enrollment_algorithm( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2); -} - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - -/** Retrieve the slot number where a key is stored. - * - * A slot number is only defined for keys that are stored in a secure - * element. - * - * This information is only useful if the secure element is not entirely - * managed through the PSA Cryptography API. It is up to the secure - * element driver to decide how PSA slot numbers map to any other interface - * that the secure element may have. - * - * \param[in] attributes The key attribute structure to query. - * \param[out] slot_number On success, the slot number containing the key. - * - * \retval #PSA_SUCCESS - * The key is located in a secure element, and \p *slot_number - * indicates the slot number that contains it. - * \retval #PSA_ERROR_NOT_PERMITTED - * The caller is not permitted to query the slot number. - * Mbed TLS currently does not return this error. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key is not located in a secure element. - */ -psa_status_t psa_get_key_slot_number( - const psa_key_attributes_t *attributes, - psa_key_slot_number_t *slot_number); - -/** Choose the slot number where a key is stored. - * - * This function declares a slot number in the specified attribute - * structure. - * - * A slot number is only meaningful for keys that are stored in a secure - * element. It is up to the secure element driver to decide how PSA slot - * numbers map to any other interface that the secure element may have. - * - * \note Setting a slot number in key attributes for a key creation can - * cause the following errors when creating the key: - * - #PSA_ERROR_NOT_SUPPORTED if the selected secure element does - * not support choosing a specific slot number. - * - #PSA_ERROR_NOT_PERMITTED if the caller is not permitted to - * choose slot numbers in general or to choose this specific slot. - * - #PSA_ERROR_INVALID_ARGUMENT if the chosen slot number is not - * valid in general or not valid for this specific key. - * - #PSA_ERROR_ALREADY_EXISTS if there is already a key in the - * selected slot. - * - * \param[out] attributes The attribute structure to write to. - * \param slot_number The slot number to set. - */ -static inline void psa_set_key_slot_number( - psa_key_attributes_t *attributes, - psa_key_slot_number_t slot_number) -{ - attributes->MBEDTLS_PRIVATE(has_slot_number) = 1; - attributes->MBEDTLS_PRIVATE(slot_number) = slot_number; -} - -/** Remove the slot number attribute from a key attribute structure. - * - * This function undoes the action of psa_set_key_slot_number(). - * - * \param[out] attributes The attribute structure to write to. - */ -static inline void psa_clear_key_slot_number( - psa_key_attributes_t *attributes) -{ - attributes->MBEDTLS_PRIVATE(has_slot_number) = 0; -} - -/** Register a key that is already present in a secure element. - * - * The key must be located in a secure element designated by the - * lifetime field in \p attributes, in the slot set with - * psa_set_key_slot_number() in the attribute structure. - * This function makes the key available through the key identifier - * specified in \p attributes. - * - * \param[in] attributes The attributes of the existing key. - * - * \retval #PSA_SUCCESS - * The key was successfully registered. - * Note that depending on the design of the driver, this may or may - * not guarantee that a key actually exists in the designated slot - * and is compatible with the specified attributes. - * \retval #PSA_ERROR_ALREADY_EXISTS - * There is already a key with the identifier specified in - * \p attributes. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The secure element driver for the specified lifetime does not - * support registering a key. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The identifier in \p attributes is invalid, namely the identifier is - * not in the user range, or - * \p attributes specifies a lifetime which is not located - * in a secure element, or no slot number is specified in \p attributes, - * or the specified slot number is not valid. - * \retval #PSA_ERROR_NOT_PERMITTED - * The caller is not authorized to register the specified key slot. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t mbedtls_psa_register_se_key( - const psa_key_attributes_t *attributes); - -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -/**@}*/ - -/** - * \brief Library deinitialization. - * - * This function clears all data associated with the PSA layer, - * including the whole key store. - * This function is not thread safe, it wipes every key slot regardless of - * state and reader count. It should only be called when no slot is in use. - * - * This is an Mbed TLS extension. - */ -void mbedtls_psa_crypto_free(void); - -/** \brief Statistics about - * resource consumption related to the PSA keystore. - * - * \note The content of this structure is not part of the stable API and ABI - * of Mbed TLS and may change arbitrarily from version to version. - */ -typedef struct mbedtls_psa_stats_s { - /** Number of slots containing key material for a volatile key. */ - size_t MBEDTLS_PRIVATE(volatile_slots); - /** Number of slots containing key material for a key which is in - * internal persistent storage. */ - size_t MBEDTLS_PRIVATE(persistent_slots); - /** Number of slots containing a reference to a key in a - * secure element. */ - size_t MBEDTLS_PRIVATE(external_slots); - /** Number of slots which are occupied, but do not contain - * key material yet. */ - size_t MBEDTLS_PRIVATE(half_filled_slots); - /** Number of slots that contain cache data. */ - size_t MBEDTLS_PRIVATE(cache_slots); - /** Number of slots that are not used for anything. */ - size_t MBEDTLS_PRIVATE(empty_slots); - /** Number of slots that are locked. */ - size_t MBEDTLS_PRIVATE(locked_slots); - /** Largest key id value among open keys in internal persistent storage. */ - psa_key_id_t MBEDTLS_PRIVATE(max_open_internal_key_id); - /** Largest key id value among open keys in secure elements. */ - psa_key_id_t MBEDTLS_PRIVATE(max_open_external_key_id); -} mbedtls_psa_stats_t; - -/** \brief Get statistics about - * resource consumption related to the PSA keystore. - * - * \note When Mbed TLS is built as part of a service, with isolation - * between the application and the keystore, the service may or - * may not expose this function. - */ -void mbedtls_psa_get_stats(mbedtls_psa_stats_t *stats); - -/** - * \brief Inject an initial entropy seed for the random generator into - * secure storage. - * - * This function injects data to be used as a seed for the random generator - * used by the PSA Crypto implementation. On devices that lack a trusted - * entropy source (preferably a hardware random number generator), - * the Mbed PSA Crypto implementation uses this value to seed its - * random generator. - * - * On devices without a trusted entropy source, this function must be - * called exactly once in the lifetime of the device. On devices with - * a trusted entropy source, calling this function is optional. - * In all cases, this function may only be called before calling any - * other function in the PSA Crypto API, including psa_crypto_init(). - * - * When this function returns successfully, it populates a file in - * persistent storage. Once the file has been created, this function - * can no longer succeed. - * - * If any error occurs, this function does not change the system state. - * You can call this function again after correcting the reason for the - * error if possible. - * - * \warning This function **can** fail! Callers MUST check the return status. - * - * \warning If you use this function, you should use it as part of a - * factory provisioning process. The value of the injected seed - * is critical to the security of the device. It must be - * *secret*, *unpredictable* and (statistically) *unique per device*. - * You should be generate it randomly using a cryptographically - * secure random generator seeded from trusted entropy sources. - * You should transmit it securely to the device and ensure - * that its value is not leaked or stored anywhere beyond the - * needs of transmitting it from the point of generation to - * the call of this function, and erase all copies of the value - * once this function returns. - * - * This is an Mbed TLS extension. - * - * \note This function is only available on the following platforms: - * * If the compile-time option MBEDTLS_PSA_INJECT_ENTROPY is enabled. - * Note that you must provide compatible implementations of - * mbedtls_nv_seed_read and mbedtls_nv_seed_write. - * * In a client-server integration of PSA Cryptography, on the client side, - * if the server supports this feature. - * \param[in] seed Buffer containing the seed value to inject. - * \param[in] seed_size Size of the \p seed buffer. - * The size of the seed in bytes must be greater - * or equal to both #MBEDTLS_ENTROPY_BLOCK_SIZE - * and the value of \c MBEDTLS_ENTROPY_MIN_PLATFORM - * in `library/entropy_poll.h` in the Mbed TLS source - * code. - * It must be less or equal to - * #MBEDTLS_ENTROPY_MAX_SEED_SIZE. - * - * \retval #PSA_SUCCESS - * The seed value was injected successfully. The random generator - * of the PSA Crypto implementation is now ready for use. - * You may now call psa_crypto_init() and use the PSA Crypto - * implementation. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p seed_size is out of range. - * \retval #PSA_ERROR_STORAGE_FAILURE - * There was a failure reading or writing from storage. - * \retval #PSA_ERROR_NOT_PERMITTED - * The library has already been initialized. It is no longer - * possible to call this function. - */ -psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, - size_t seed_size); - -/** \addtogroup crypto_types - * @{ - */ - -/** DSA public key. - * - * The import and export format is the - * representation of the public key `y = g^x mod p` as a big-endian byte - * string. The length of the byte string is the length of the base prime `p` - * in bytes. - */ -#define PSA_KEY_TYPE_DSA_PUBLIC_KEY ((psa_key_type_t) 0x4002) - -/** DSA key pair (private and public key). - * - * The import and export format is the - * representation of the private key `x` as a big-endian byte string. The - * length of the byte string is the private key size in bytes (leading zeroes - * are not stripped). - * - * Deterministic DSA key derivation with psa_generate_derived_key follows - * FIPS 186-4 §B.1.2: interpret the byte string as integer - * in big-endian order. Discard it if it is not in the range - * [0, *N* - 2] where *N* is the boundary of the private key domain - * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, - * or the order of the curve's base point for ECC). - * Add 1 to the resulting integer and use this as the private key *x*. - * - */ -#define PSA_KEY_TYPE_DSA_KEY_PAIR ((psa_key_type_t) 0x7002) - -/** Whether a key type is a DSA key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_DSA(type) \ - (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY) - -#define PSA_ALG_DSA_BASE ((psa_algorithm_t) 0x06000400) -/** DSA signature with hashing. - * - * This is the signature scheme defined by FIPS 186-4, - * with a random per-message secret number (*k*). - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding DSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DSA(hash_alg) \ - (PSA_ALG_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t) 0x06000500) -#define PSA_ALG_DSA_DETERMINISTIC_FLAG PSA_ALG_ECDSA_DETERMINISTIC_FLAG -/** Deterministic DSA signature with hashing. - * - * This is the deterministic variant defined by RFC 6979 of - * the signature scheme defined by FIPS 186-4. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding DSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DETERMINISTIC_DSA(hash_alg) \ - (PSA_ALG_DETERMINISTIC_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_IS_DSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_DSA_DETERMINISTIC_FLAG) == \ - PSA_ALG_DSA_BASE) -#define PSA_ALG_DSA_IS_DETERMINISTIC(alg) \ - (((alg) & PSA_ALG_DSA_DETERMINISTIC_FLAG) != 0) -#define PSA_ALG_IS_DETERMINISTIC_DSA(alg) \ - (PSA_ALG_IS_DSA(alg) && PSA_ALG_DSA_IS_DETERMINISTIC(alg)) -#define PSA_ALG_IS_RANDOMIZED_DSA(alg) \ - (PSA_ALG_IS_DSA(alg) && !PSA_ALG_DSA_IS_DETERMINISTIC(alg)) - - -/* We need to expand the sample definition of this macro from - * the API definition. */ -#undef PSA_ALG_IS_VENDOR_HASH_AND_SIGN -#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) \ - PSA_ALG_IS_DSA(alg) - -/**@}*/ - -/** \addtogroup attributes - * @{ - */ - -/** PAKE operation stages. */ -#define PSA_PAKE_OPERATION_STAGE_SETUP 0 -#define PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS 1 -#define PSA_PAKE_OPERATION_STAGE_COMPUTATION 2 - -/**@}*/ - - -/** \defgroup psa_external_rng External random generator - * @{ - */ - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -/** External random generator function, implemented by the platform. - * - * When the compile-time option #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is enabled, - * this function replaces Mbed TLS's entropy and DRBG modules for all - * random generation triggered via PSA crypto interfaces. - * - * \note This random generator must deliver random numbers with cryptographic - * quality and high performance. It must supply unpredictable numbers - * with a uniform distribution. The implementation of this function - * is responsible for ensuring that the random generator is seeded - * with sufficient entropy. If you have a hardware TRNG which is slow - * or delivers non-uniform output, declare it as an entropy source - * with mbedtls_entropy_add_source() instead of enabling this option. - * - * \param[in,out] context Pointer to the random generator context. - * This is all-bits-zero on the first call - * and preserved between successive calls. - * \param[out] output Output buffer. On success, this buffer - * contains random data with a uniform - * distribution. - * \param output_size The size of the \p output buffer in bytes. - * \param[out] output_length On success, set this value to \p output_size. - * - * \retval #PSA_SUCCESS - * Success. The output buffer contains \p output_size bytes of - * cryptographic-quality random data, and \c *output_length is - * set to \p output_size. - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY - * The random generator requires extra entropy and there is no - * way to obtain entropy under current environment conditions. - * This error should not happen under normal circumstances since - * this function is responsible for obtaining as much entropy as - * it needs. However implementations of this function may return - * #PSA_ERROR_INSUFFICIENT_ENTROPY if there is no way to obtain - * entropy without blocking indefinitely. - * \retval #PSA_ERROR_HARDWARE_FAILURE - * A failure of the random generator hardware that isn't covered - * by #PSA_ERROR_INSUFFICIENT_ENTROPY. - */ -psa_status_t mbedtls_psa_external_get_random( - mbedtls_psa_external_random_context_t *context, - uint8_t *output, size_t output_size, size_t *output_length); -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -/**@}*/ - -/** \defgroup psa_builtin_keys Built-in keys - * @{ - */ - -/** The minimum value for a key identifier that is built into the - * implementation. - * - * The range of key identifiers from #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN - * to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX within the range from - * #PSA_KEY_ID_VENDOR_MIN and #PSA_KEY_ID_VENDOR_MAX and must not intersect - * with any other set of implementation-chosen key identifiers. - * - * This value is part of the library's ABI since changing it would invalidate - * the values of built-in key identifiers in applications. - */ -#define MBEDTLS_PSA_KEY_ID_BUILTIN_MIN ((psa_key_id_t) 0x7fff0000) - -/** The maximum value for a key identifier that is built into the - * implementation. - * - * See #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN for more information. - */ -#define MBEDTLS_PSA_KEY_ID_BUILTIN_MAX ((psa_key_id_t) 0x7fffefff) - -/** A slot number identifying a key in a driver. - * - * Values of this type are used to identify built-in keys. - */ -typedef uint64_t psa_drv_slot_number_t; - -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) -/** Test whether a key identifier belongs to the builtin key range. - * - * \param key_id Key identifier to test. - * - * \retval 1 - * The key identifier is a builtin key identifier. - * \retval 0 - * The key identifier is not a builtin key identifier. - */ -static inline int psa_key_id_is_builtin(psa_key_id_t key_id) -{ - return (key_id >= MBEDTLS_PSA_KEY_ID_BUILTIN_MIN) && - (key_id <= MBEDTLS_PSA_KEY_ID_BUILTIN_MAX); -} - -/** Platform function to obtain the location and slot number of a built-in key. - * - * An application-specific implementation of this function must be provided if - * #MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS is enabled. This would typically be provided - * as part of a platform's system image. - * - * #MBEDTLS_SVC_KEY_ID_GET_KEY_ID(\p key_id) needs to be in the range from - * #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX. - * - * In a multi-application configuration - * (\c MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER is defined), - * this function should check that #MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(\p key_id) - * is allowed to use the given key. - * - * \param key_id The key ID for which to retrieve the - * location and slot attributes. - * \param[out] lifetime On success, the lifetime associated with the key - * corresponding to \p key_id. Lifetime is a - * combination of which driver contains the key, - * and with what persistence level the key is - * intended to be used. If the platform - * implementation does not contain specific - * information about the intended key persistence - * level, the persistence level may be reported as - * #PSA_KEY_PERSISTENCE_DEFAULT. - * \param[out] slot_number On success, the slot number known to the driver - * registered at the lifetime location reported - * through \p lifetime which corresponds to the - * requested built-in key. - * - * \retval #PSA_SUCCESS - * The requested key identifier designates a built-in key. - * In a multi-application configuration, the requested owner - * is allowed to access it. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * The requested key identifier is not a built-in key which is known - * to this function. If a key exists in the key storage with this - * identifier, the data from the storage will be used. - * \return (any other error) - * Any other error is propagated to the function that requested the key. - * Common errors include: - * - #PSA_ERROR_NOT_PERMITTED: the key exists but the requested owner - * is not allowed to access it. - */ -psa_status_t mbedtls_psa_platform_get_builtin_key( - mbedtls_svc_key_id_t key_id, - psa_key_lifetime_t *lifetime, - psa_drv_slot_number_t *slot_number); -#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - -/** @} */ - -/** \addtogroup crypto_types - * @{ - */ - -#define PSA_ALG_CATEGORY_PAKE ((psa_algorithm_t) 0x0a000000) - -/** Whether the specified algorithm is a password-authenticated key exchange. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a password-authenticated key exchange (PAKE) - * algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_PAKE(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_PAKE) - -/** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. - * - * This is J-PAKE as defined by RFC 8236, instantiated with the following - * parameters: - * - * - The group can be either an elliptic curve or defined over a finite field. - * - Schnorr NIZK proof as defined by RFC 8235 and using the same group as the - * J-PAKE algorithm. - * - A cryptographic hash function. - * - * To select these parameters and set up the cipher suite, call these functions - * in any order: - * - * \code - * psa_pake_cs_set_algorithm(cipher_suite, PSA_ALG_JPAKE); - * psa_pake_cs_set_primitive(cipher_suite, - * PSA_PAKE_PRIMITIVE(type, family, bits)); - * psa_pake_cs_set_hash(cipher_suite, hash); - * \endcode - * - * For more information on how to set a specific curve or field, refer to the - * documentation of the individual \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - * - * After initializing a J-PAKE operation, call - * - * \code - * psa_pake_setup(operation, cipher_suite); - * psa_pake_set_user(operation, ...); - * psa_pake_set_peer(operation, ...); - * psa_pake_set_password_key(operation, ...); - * \endcode - * - * The password is provided as a key. This can be the password text itself, - * in an agreed character encoding, or some value derived from the password - * as required by a higher level protocol. - * - * (The implementation converts the key material to a number as described in - * Section 2.3.8 of _SEC 1: Elliptic Curve Cryptography_ - * (https://www.secg.org/sec1-v2.pdf), before reducing it modulo \c q. Here - * \c q is order of the group defined by the primitive set in the cipher suite. - * The \c psa_pake_set_password_key() function returns an error if the result - * of the reduction is 0.) - * - * The key exchange flow for J-PAKE is as follows: - * -# To get the first round data that needs to be sent to the peer, call - * \code - * // Get g1 - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get the ZKP public key for x1 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get the ZKP proof for x1 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * // Get g2 - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get the ZKP public key for x2 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get the ZKP proof for x2 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To provide the first round data received from the peer to the operation, - * call - * \code - * // Set g3 - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set the ZKP public key for x3 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set the ZKP proof for x3 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * // Set g4 - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set the ZKP public key for x4 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set the ZKP proof for x4 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To get the second round data that needs to be sent to the peer, call - * \code - * // Get A - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get ZKP public key for x2*s - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get ZKP proof for x2*s - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To provide the second round data received from the peer to the operation, - * call - * \code - * // Set B - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set ZKP public key for x4*s - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set ZKP proof for x4*s - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To access the shared secret call - * \code - * // Get Ka=Kb=K - * psa_pake_get_implicit_key() - * \endcode - * - * For more information consult the documentation of the individual - * \c PSA_PAKE_STEP_XXX constants. - * - * At this point there is a cryptographic guarantee that only the authenticated - * party who used the same password is able to compute the key. But there is no - * guarantee that the peer is the party it claims to be and was able to do so. - * - * That is, the authentication is only implicit (the peer is not authenticated - * at this point, and no action should be taken that assume that they are - like - * for example accessing restricted files). - * - * To make the authentication explicit there are various methods, see Section 5 - * of RFC 8236 for two examples. - * - */ -#define PSA_ALG_JPAKE ((psa_algorithm_t) 0x0a000100) - -/** @} */ - -/** \defgroup pake Password-authenticated key exchange (PAKE) - * - * This is a proposed PAKE interface for the PSA Crypto API. It is not part of - * the official PSA Crypto API yet. - * - * \note The content of this section is not part of the stable API and ABI - * of Mbed TLS and may change arbitrarily from version to version. - * Same holds for the corresponding macros #PSA_ALG_CATEGORY_PAKE and - * #PSA_ALG_JPAKE. - * @{ - */ - -/** \brief Encoding of the application role of PAKE - * - * Encodes the application's role in the algorithm is being executed. For more - * information see the documentation of individual \c PSA_PAKE_ROLE_XXX - * constants. - */ -typedef uint8_t psa_pake_role_t; - -/** Encoding of input and output indicators for PAKE. - * - * Some PAKE algorithms need to exchange more data than just a single key share. - * This type is for encoding additional input and output data for such - * algorithms. - */ -typedef uint8_t psa_pake_step_t; - -/** Encoding of the type of the PAKE's primitive. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional types must use an encoding in this range. - * - * For more information see the documentation of individual - * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - */ -typedef uint8_t psa_pake_primitive_type_t; - -/** \brief Encoding of the family of the primitive associated with the PAKE. - * - * For more information see the documentation of individual - * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - */ -typedef uint8_t psa_pake_family_t; - -/** \brief Encoding of the primitive associated with the PAKE. - * - * For more information see the documentation of the #PSA_PAKE_PRIMITIVE macro. - */ -typedef uint32_t psa_pake_primitive_t; - -/** A value to indicate no role in a PAKE algorithm. - * This value can be used in a call to psa_pake_set_role() for symmetric PAKE - * algorithms which do not assign roles. - */ -#define PSA_PAKE_ROLE_NONE ((psa_pake_role_t) 0x00) - -/** The first peer in a balanced PAKE. - * - * Although balanced PAKE algorithms are symmetric, some of them needs an - * ordering of peers for the transcript calculations. If the algorithm does not - * need this, both #PSA_PAKE_ROLE_FIRST and #PSA_PAKE_ROLE_SECOND are - * accepted. - */ -#define PSA_PAKE_ROLE_FIRST ((psa_pake_role_t) 0x01) - -/** The second peer in a balanced PAKE. - * - * Although balanced PAKE algorithms are symmetric, some of them needs an - * ordering of peers for the transcript calculations. If the algorithm does not - * need this, either #PSA_PAKE_ROLE_FIRST or #PSA_PAKE_ROLE_SECOND are - * accepted. - */ -#define PSA_PAKE_ROLE_SECOND ((psa_pake_role_t) 0x02) - -/** The client in an augmented PAKE. - * - * Augmented PAKE algorithms need to differentiate between client and server. - */ -#define PSA_PAKE_ROLE_CLIENT ((psa_pake_role_t) 0x11) - -/** The server in an augmented PAKE. - * - * Augmented PAKE algorithms need to differentiate between client and server. - */ -#define PSA_PAKE_ROLE_SERVER ((psa_pake_role_t) 0x12) - -/** The PAKE primitive type indicating the use of elliptic curves. - * - * The values of the \c family and \c bits fields of the cipher suite identify a - * specific elliptic curve, using the same mapping that is used for ECC - * (::psa_ecc_family_t) keys. - * - * (Here \c family means the value returned by psa_pake_cs_get_family() and - * \c bits means the value returned by psa_pake_cs_get_bits().) - * - * Input and output during the operation can involve group elements and scalar - * values: - * -# The format for group elements is the same as for public keys on the - * specific curve would be. For more information, consult the documentation of - * psa_export_public_key(). - * -# The format for scalars is the same as for private keys on the specific - * curve would be. For more information, consult the documentation of - * psa_export_key(). - */ -#define PSA_PAKE_PRIMITIVE_TYPE_ECC ((psa_pake_primitive_type_t) 0x01) - -/** The PAKE primitive type indicating the use of Diffie-Hellman groups. - * - * The values of the \c family and \c bits fields of the cipher suite identify - * a specific Diffie-Hellman group, using the same mapping that is used for - * Diffie-Hellman (::psa_dh_family_t) keys. - * - * (Here \c family means the value returned by psa_pake_cs_get_family() and - * \c bits means the value returned by psa_pake_cs_get_bits().) - * - * Input and output during the operation can involve group elements and scalar - * values: - * -# The format for group elements is the same as for public keys on the - * specific group would be. For more information, consult the documentation of - * psa_export_public_key(). - * -# The format for scalars is the same as for private keys on the specific - * group would be. For more information, consult the documentation of - * psa_export_key(). - */ -#define PSA_PAKE_PRIMITIVE_TYPE_DH ((psa_pake_primitive_type_t) 0x02) - -/** Construct a PAKE primitive from type, family and bit-size. - * - * \param pake_type The type of the primitive - * (value of type ::psa_pake_primitive_type_t). - * \param pake_family The family of the primitive - * (the type and interpretation of this parameter depends - * on \p pake_type, for more information consult the - * documentation of individual ::psa_pake_primitive_type_t - * constants). - * \param pake_bits The bit-size of the primitive - * (Value of type \c size_t. The interpretation - * of this parameter depends on \p pake_family, for more - * information consult the documentation of individual - * ::psa_pake_primitive_type_t constants). - * - * \return The constructed primitive value of type ::psa_pake_primitive_t. - * Return 0 if the requested primitive can't be encoded as - * ::psa_pake_primitive_t. - */ -#define PSA_PAKE_PRIMITIVE(pake_type, pake_family, pake_bits) \ - ((pake_bits & 0xFFFF) != pake_bits) ? 0 : \ - ((psa_pake_primitive_t) (((pake_type) << 24 | \ - (pake_family) << 16) | (pake_bits))) - -/** The key share being sent to or received from the peer. - * - * The format for both input and output at this step is the same as for public - * keys on the group determined by the primitive (::psa_pake_primitive_t) would - * be. - * - * For more information on the format, consult the documentation of - * psa_export_public_key(). - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_KEY_SHARE ((psa_pake_step_t) 0x01) - -/** A Schnorr NIZKP public key. - * - * This is the ephemeral public key in the Schnorr Non-Interactive - * Zero-Knowledge Proof (the value denoted by the letter 'V' in RFC 8235). - * - * The format for both input and output at this step is the same as for public - * keys on the group determined by the primitive (::psa_pake_primitive_t) would - * be. - * - * For more information on the format, consult the documentation of - * psa_export_public_key(). - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_ZK_PUBLIC ((psa_pake_step_t) 0x02) - -/** A Schnorr NIZKP proof. - * - * This is the proof in the Schnorr Non-Interactive Zero-Knowledge Proof (the - * value denoted by the letter 'r' in RFC 8235). - * - * Both for input and output, the value at this step is an integer less than - * the order of the group selected in the cipher suite. The format depends on - * the group as well: - * - * - For Montgomery curves, the encoding is little endian. - * - For everything else the encoding is big endian (see Section 2.3.8 of - * _SEC 1: Elliptic Curve Cryptography_ at https://www.secg.org/sec1-v2.pdf). - * - * In both cases leading zeroes are allowed as long as the length in bytes does - * not exceed the byte length of the group order. - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_ZK_PROOF ((psa_pake_step_t) 0x03) - -/** The type of the data structure for PAKE cipher suites. - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. - */ -typedef struct psa_pake_cipher_suite_s psa_pake_cipher_suite_t; - -/** Return an initial value for a PAKE cipher suite object. - */ -static psa_pake_cipher_suite_t psa_pake_cipher_suite_init(void); - -/** Retrieve the PAKE algorithm from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE algorithm stored in the cipher suite structure. - */ -static psa_algorithm_t psa_pake_cs_get_algorithm( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the PAKE algorithm for the cipher suite. - * - * This function overwrites any PAKE algorithm - * previously set in \p cipher_suite. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param algorithm The PAKE algorithm to write. - * (`PSA_ALG_XXX` values of type ::psa_algorithm_t - * such that #PSA_ALG_IS_PAKE(\c alg) is true.) - * If this is 0, the PAKE algorithm in - * \p cipher_suite becomes unspecified. - */ -static void psa_pake_cs_set_algorithm(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t algorithm); - -/** Retrieve the primitive from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The primitive stored in the cipher suite structure. - */ -static psa_pake_primitive_t psa_pake_cs_get_primitive( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the primitive for a PAKE cipher suite. - * - * This function overwrites any primitive previously set in \p cipher_suite. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param primitive The primitive to write. If this is 0, the - * primitive type in \p cipher_suite becomes - * unspecified. - */ -static void psa_pake_cs_set_primitive(psa_pake_cipher_suite_t *cipher_suite, - psa_pake_primitive_t primitive); - -/** Retrieve the PAKE family from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE family stored in the cipher suite structure. - */ -static psa_pake_family_t psa_pake_cs_get_family( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Retrieve the PAKE primitive bit-size from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE primitive bit-size stored in the cipher suite structure. - */ -static uint16_t psa_pake_cs_get_bits( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Retrieve the hash algorithm from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The hash algorithm stored in the cipher suite structure. The return - * value is 0 if the PAKE is not parametrised by a hash algorithm or if - * the hash algorithm is not set. - */ -static psa_algorithm_t psa_pake_cs_get_hash( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the hash algorithm for a PAKE cipher suite. - * - * This function overwrites any hash algorithm - * previously set in \p cipher_suite. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param hash The hash involved in the cipher suite. - * (`PSA_ALG_XXX` values of type ::psa_algorithm_t - * such that #PSA_ALG_IS_HASH(\c alg) is true.) - * If this is 0, the hash algorithm in - * \p cipher_suite becomes unspecified. - */ -static void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t hash); - -/** The type of the state data structure for PAKE operations. - * - * Before calling any function on a PAKE operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_pake_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_pake_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_PAKE_OPERATION_INIT, - * for example: - * \code - * psa_pake_operation_t operation = PSA_PAKE_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_pake_operation_init() - * to the structure, for example: - * \code - * psa_pake_operation_t operation; - * operation = psa_pake_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_pake_operation_s psa_pake_operation_t; - -/** The type of input values for PAKE operations. */ -typedef struct psa_crypto_driver_pake_inputs_s psa_crypto_driver_pake_inputs_t; - -/** The type of computation stage for J-PAKE operations. */ -typedef struct psa_jpake_computation_stage_s psa_jpake_computation_stage_t; - -/** Return an initial value for a PAKE operation object. - */ -static psa_pake_operation_t psa_pake_operation_init(void); - -/** Get the length of the password in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] password_len Password length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Password hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_password_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *password_len); - -/** Get the password from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] buffer Return buffer for password. - * \param buffer_size Size of the return buffer in bytes. - * \param[out] buffer_length Actual size of the password in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Password hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_password( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *buffer, size_t buffer_size, size_t *buffer_length); - -/** Get the length of the user id in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] user_len User id length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * User id hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_user_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *user_len); - -/** Get the length of the peer id in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] peer_len Peer id length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Peer id hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_peer_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *peer_len); - -/** Get the user id from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] user_id User id. - * \param user_id_size Size of \p user_id in bytes. - * \param[out] user_id_len Size of the user id in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * User id hasn't been set yet. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p user_id is too small. - */ -psa_status_t psa_crypto_driver_pake_get_user( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *user_id, size_t user_id_size, size_t *user_id_len); - -/** Get the peer id from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] peer_id Peer id. - * \param peer_id_size Size of \p peer_id in bytes. - * \param[out] peer_id_length Size of the peer id in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Peer id hasn't been set yet. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p peer_id is too small. - */ -psa_status_t psa_crypto_driver_pake_get_peer( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *peer_id, size_t peer_id_size, size_t *peer_id_length); - -/** Get the cipher suite from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] cipher_suite Return buffer for role. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Cipher_suite hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_cipher_suite( - const psa_crypto_driver_pake_inputs_t *inputs, - psa_pake_cipher_suite_t *cipher_suite); - -/** Set the session information for a password-authenticated key exchange. - * - * The sequence of operations to set up a password-authenticated key exchange - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_pake_operation_t, e.g. - * #PSA_PAKE_OPERATION_INIT. - * -# Call psa_pake_setup() to specify the cipher suite. - * -# Call \c psa_pake_set_xxx() functions on the operation to complete the - * setup. The exact sequence of \c psa_pake_set_xxx() functions that needs - * to be called depends on the algorithm in use. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * A typical sequence of calls to perform a password-authenticated key - * exchange: - * -# Call psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to get the - * key share that needs to be sent to the peer. - * -# Call psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to provide - * the key share that was received from the peer. - * -# Depending on the algorithm additional calls to psa_pake_output() and - * psa_pake_input() might be necessary. - * -# Call psa_pake_get_implicit_key() for accessing the shared secret. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * If an error occurs at any step after a call to psa_pake_setup(), - * the operation will need to be reset by a call to psa_pake_abort(). The - * application may call psa_pake_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_pake_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A call to psa_pake_abort(). - * - A successful call to psa_pake_get_implicit_key(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized but not set up yet. - * \param[in] cipher_suite The cipher suite to use. (A cipher suite fully - * characterizes a PAKE algorithm and determines - * the algorithm as well.) - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The algorithm in \p cipher_suite is not a PAKE algorithm, or the - * PAKE primitive in \p cipher_suite is not compatible with the - * PAKE algorithm, or the hash algorithm in \p cipher_suite is invalid - * or not compatible with the PAKE algorithm and primitive. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The algorithm in \p cipher_suite is not a supported PAKE algorithm, - * or the PAKE primitive in \p cipher_suite is not supported or not - * compatible with the PAKE algorithm, or the hash algorithm in - * \p cipher_suite is not supported or not compatible with the PAKE - * algorithm and primitive. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_setup(psa_pake_operation_t *operation, - const psa_pake_cipher_suite_t *cipher_suite); - -/** Set the password for a password-authenticated key exchange from key ID. - * - * Call this function when the password, or a value derived from the password, - * is already present in the key store. - * - * \param[in,out] operation The operation object to set the password for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the password hasn't - * been set yet (psa_pake_set_password_key() - * hasn't been called yet). - * \param password Identifier of the key holding the password or a - * value derived from the password (eg. by a - * memory-hard function). It must remain valid - * until the operation terminates. It must be of - * type #PSA_KEY_TYPE_PASSWORD or - * #PSA_KEY_TYPE_PASSWORD_HASH. It has to allow - * the usage #PSA_KEY_USAGE_DERIVE. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p password is not a valid key identifier. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_DERIVE flag, or it does not - * permit the \p operation's algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key type for \p password is not #PSA_KEY_TYPE_PASSWORD or - * #PSA_KEY_TYPE_PASSWORD_HASH, or \p password is not compatible with - * the \p operation's cipher suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size of \p password is not supported with the - * \p operation's cipher suite. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must have been set up.), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_password_key(psa_pake_operation_t *operation, - mbedtls_svc_key_id_t password); - -/** Set the user ID for a password-authenticated key exchange. - * - * Call this function to set the user ID. For PAKE algorithms that associate a - * user identifier with each side of the session you need to call - * psa_pake_set_peer() as well. For PAKE algorithms that associate a single - * user identifier with the session, call psa_pake_set_user() only. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to set the user ID for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the user ID hasn't - * been set (psa_pake_set_user() hasn't been - * called yet). - * \param[in] user_id The user ID to authenticate with. - * \param user_id_len Size of the \p user_id buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p user_id is not valid for the \p operation's algorithm and cipher - * suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The value of \p user_id is not supported by the implementation. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_user(psa_pake_operation_t *operation, - const uint8_t *user_id, - size_t user_id_len); - -/** Set the peer ID for a password-authenticated key exchange. - * - * Call this function in addition to psa_pake_set_user() for PAKE algorithms - * that associate a user identifier with each side of the session. For PAKE - * algorithms that associate a single user identifier with the session, call - * psa_pake_set_user() only. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to set the peer ID for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the peer ID hasn't - * been set (psa_pake_set_peer() hasn't been - * called yet). - * \param[in] peer_id The peer's ID to authenticate. - * \param peer_id_len Size of the \p peer_id buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p peer_id is not valid for the \p operation's algorithm and cipher - * suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The algorithm doesn't associate a second identity with the session. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * Calling psa_pake_set_peer() is invalid with the \p operation's - * algorithm, the operation state is not valid, or the library has not - * been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_peer(psa_pake_operation_t *operation, - const uint8_t *peer_id, - size_t peer_id_len); - -/** Set the application role for a password-authenticated key exchange. - * - * Not all PAKE algorithms need to differentiate the communicating entities. - * It is optional to call this function for PAKEs that don't require a role - * to be specified. For such PAKEs the application role parameter is ignored, - * or #PSA_PAKE_ROLE_NONE can be passed as \c role. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to specify the - * application's role for. It must have been set up - * by psa_pake_setup() and not yet in use (neither - * psa_pake_output() nor psa_pake_input() has been - * called yet). It must be on operation for which - * the application's role hasn't been specified - * (psa_pake_set_role() hasn't been called yet). - * \param role A value of type ::psa_pake_role_t indicating the - * application's role in the PAKE the algorithm - * that is being set up. For more information see - * the documentation of \c PSA_PAKE_ROLE_XXX - * constants. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The \p role is not a valid PAKE role in the \p operation’s algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The \p role for this algorithm is not supported or is not valid. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_role(psa_pake_operation_t *operation, - psa_pake_role_t role); - -/** Get output for a step of a password-authenticated key exchange. - * - * Depending on the algorithm being executed, you might need to call this - * function several times or you might not need to call this at all. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_pake_abort(). - * - * \param[in,out] operation Active PAKE operation. - * \param step The step of the algorithm for which the output is - * requested. - * \param[out] output Buffer where the output is to be written in the - * format appropriate for this \p step. Refer to - * the documentation of the individual - * \c PSA_PAKE_STEP_XXX constants for more - * information. - * \param output_size Size of the \p output buffer in bytes. This must - * be at least #PSA_PAKE_OUTPUT_SIZE(\c alg, \c - * primitive, \p output_step) where \c alg and - * \p primitive are the PAKE algorithm and primitive - * in the operation's cipher suite, and \p step is - * the output step. - * - * \param[out] output_length On success, the number of bytes of the returned - * output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p step is not compatible with the operation's algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p step is not supported with the operation's algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and fully set - * up, and this call must conform to the algorithm's requirements - * for ordering of input and output steps), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_output(psa_pake_operation_t *operation, - psa_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Provide input for a step of a password-authenticated key exchange. - * - * Depending on the algorithm being executed, you might need to call this - * function several times or you might not need to call this at all. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_pake_abort(). - * - * \param[in,out] operation Active PAKE operation. - * \param step The step for which the input is provided. - * \param[in] input Buffer containing the input in the format - * appropriate for this \p step. Refer to the - * documentation of the individual - * \c PSA_PAKE_STEP_XXX constants for more - * information. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The verification fails for a #PSA_PAKE_STEP_ZK_PROOF input step. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p input_length is not compatible with the \p operation’s algorithm, - * or the \p input is not valid for the \p operation's algorithm, - * cipher suite or \p step. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p step p is not supported with the \p operation's algorithm, or the - * \p input is not supported for the \p operation's algorithm, cipher - * suite or \p step. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and fully set - * up, and this call must conform to the algorithm's requirements - * for ordering of input and output steps), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_input(psa_pake_operation_t *operation, - psa_pake_step_t step, - const uint8_t *input, - size_t input_length); - -/** Get implicitly confirmed shared secret from a PAKE. - * - * At this point there is a cryptographic guarantee that only the authenticated - * party who used the same password is able to compute the key. But there is no - * guarantee that the peer is the party it claims to be and was able to do so. - * - * That is, the authentication is only implicit. Since the peer is not - * authenticated yet, no action should be taken yet that assumes that the peer - * is who it claims to be. For example, do not access restricted files on the - * peer's behalf until an explicit authentication has succeeded. - * - * This function can be called after the key exchange phase of the operation - * has completed. It imports the shared secret output of the PAKE into the - * provided derivation operation. The input step - * #PSA_KEY_DERIVATION_INPUT_SECRET is used when placing the shared key - * material in the key derivation operation. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * When this function returns successfully, \p operation becomes inactive. - * If this function returns an error status, both \p operation - * and \c key_derivation operations enter an error state and must be aborted by - * calling psa_pake_abort() and psa_key_derivation_abort() respectively. - * - * \param[in,out] operation Active PAKE operation. - * \param[out] output A key derivation operation that is ready - * for an input step of type - * #PSA_KEY_DERIVATION_INPUT_SECRET. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * #PSA_KEY_DERIVATION_INPUT_SECRET is not compatible with the - * algorithm in the \p output key derivation operation. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Input from a PAKE is not supported by the algorithm in the \p output - * key derivation operation. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The PAKE operation state is not valid (it must be active, but beyond - * that validity is specific to the algorithm), or - * the library has not been previously initialized by psa_crypto_init(), - * or the state of \p output is not valid for - * the #PSA_KEY_DERIVATION_INPUT_SECRET step. This can happen if the - * step is out of order or the application has done this step already - * and it may not be repeated. - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_get_implicit_key(psa_pake_operation_t *operation, - psa_key_derivation_operation_t *output); - -/** Abort a PAKE operation. - * - * Aborting an operation frees all associated resources except for the \c - * operation structure itself. Once aborted, the operation object can be reused - * for another operation by calling psa_pake_setup() again. - * - * This function may be called at any time after the operation - * object has been initialized as described in #psa_pake_operation_t. - * - * In particular, calling psa_pake_abort() after the operation has been - * terminated by a call to psa_pake_abort() or psa_pake_get_implicit_key() - * is safe and has no effect. - * - * \param[in,out] operation The operation to abort. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_abort(psa_pake_operation_t *operation); - -/**@}*/ - -/** A sufficient output buffer size for psa_pake_output(). - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_pake_output() will not fail due to an insufficient output buffer - * size. The actual size of the output might be smaller in any given call. - * - * See also #PSA_PAKE_OUTPUT_MAX_SIZE - * - * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_PAKE(\p alg) is true). - * \param primitive A primitive of type ::psa_pake_primitive_t that is - * compatible with algorithm \p alg. - * \param output_step A value of type ::psa_pake_step_t that is valid for the - * algorithm \p alg. - * \return A sufficient output buffer size for the specified - * PAKE algorithm, primitive, and output step. If the - * PAKE algorithm, primitive, or output step is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_PAKE_OUTPUT_SIZE(alg, primitive, output_step) \ - (alg == PSA_ALG_JPAKE && \ - primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ - PSA_ECC_FAMILY_SECP_R1, 256) ? \ - ( \ - output_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ - output_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ - 32 \ - ) : \ - 0) - -/** A sufficient input buffer size for psa_pake_input(). - * - * The value returned by this macro is guaranteed to be large enough for any - * valid input to psa_pake_input() in an operation with the specified - * parameters. - * - * See also #PSA_PAKE_INPUT_MAX_SIZE - * - * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_PAKE(\p alg) is true). - * \param primitive A primitive of type ::psa_pake_primitive_t that is - * compatible with algorithm \p alg. - * \param input_step A value of type ::psa_pake_step_t that is valid for the - * algorithm \p alg. - * \return A sufficient input buffer size for the specified - * input, cipher suite and algorithm. If the cipher suite, - * the input type or PAKE algorithm is not recognized, or - * the parameters are incompatible, return 0. - */ -#define PSA_PAKE_INPUT_SIZE(alg, primitive, input_step) \ - (alg == PSA_ALG_JPAKE && \ - primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ - PSA_ECC_FAMILY_SECP_R1, 256) ? \ - ( \ - input_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ - input_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ - 32 \ - ) : \ - 0) - -/** Output buffer size for psa_pake_output() for any of the supported PAKE - * algorithm and primitive suites and output step. - * - * This macro must expand to a compile-time constant integer. - * - * The value of this macro must be at least as large as the largest value - * returned by PSA_PAKE_OUTPUT_SIZE() - * - * See also #PSA_PAKE_OUTPUT_SIZE(\p alg, \p primitive, \p output_step). - */ -#define PSA_PAKE_OUTPUT_MAX_SIZE 65 - -/** Input buffer size for psa_pake_input() for any of the supported PAKE - * algorithm and primitive suites and input step. - * - * This macro must expand to a compile-time constant integer. - * - * The value of this macro must be at least as large as the largest value - * returned by PSA_PAKE_INPUT_SIZE() - * - * See also #PSA_PAKE_INPUT_SIZE(\p alg, \p primitive, \p output_step). - */ -#define PSA_PAKE_INPUT_MAX_SIZE 65 - -/** Returns a suitable initializer for a PAKE cipher suite object of type - * psa_pake_cipher_suite_t. - */ -#define PSA_PAKE_CIPHER_SUITE_INIT { PSA_ALG_NONE, 0, 0, 0, PSA_ALG_NONE } - -/** Returns a suitable initializer for a PAKE operation object of type - * psa_pake_operation_t. - */ -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_PAKE_OPERATION_INIT { 0 } -#else -#define PSA_PAKE_OPERATION_INIT { 0, PSA_ALG_NONE, 0, PSA_PAKE_OPERATION_STAGE_SETUP, \ - { 0 }, { { 0 } } } -#endif - -struct psa_pake_cipher_suite_s { - psa_algorithm_t algorithm; - psa_pake_primitive_type_t type; - psa_pake_family_t family; - uint16_t bits; - psa_algorithm_t hash; -}; - -static inline psa_algorithm_t psa_pake_cs_get_algorithm( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->algorithm; -} - -static inline void psa_pake_cs_set_algorithm( - psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t algorithm) -{ - if (!PSA_ALG_IS_PAKE(algorithm)) { - cipher_suite->algorithm = 0; - } else { - cipher_suite->algorithm = algorithm; - } -} - -static inline psa_pake_primitive_t psa_pake_cs_get_primitive( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return PSA_PAKE_PRIMITIVE(cipher_suite->type, cipher_suite->family, - cipher_suite->bits); -} - -static inline void psa_pake_cs_set_primitive( - psa_pake_cipher_suite_t *cipher_suite, - psa_pake_primitive_t primitive) -{ - cipher_suite->type = (psa_pake_primitive_type_t) (primitive >> 24); - cipher_suite->family = (psa_pake_family_t) (0xFF & (primitive >> 16)); - cipher_suite->bits = (uint16_t) (0xFFFF & primitive); -} - -static inline psa_pake_family_t psa_pake_cs_get_family( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->family; -} - -static inline uint16_t psa_pake_cs_get_bits( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->bits; -} - -static inline psa_algorithm_t psa_pake_cs_get_hash( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->hash; -} - -static inline void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t hash) -{ - if (!PSA_ALG_IS_HASH(hash)) { - cipher_suite->hash = 0; - } else { - cipher_suite->hash = hash; - } -} - -struct psa_crypto_driver_pake_inputs_s { - uint8_t *MBEDTLS_PRIVATE(password); - size_t MBEDTLS_PRIVATE(password_len); - uint8_t *MBEDTLS_PRIVATE(user); - size_t MBEDTLS_PRIVATE(user_len); - uint8_t *MBEDTLS_PRIVATE(peer); - size_t MBEDTLS_PRIVATE(peer_len); - psa_key_attributes_t MBEDTLS_PRIVATE(attributes); - psa_pake_cipher_suite_t MBEDTLS_PRIVATE(cipher_suite); -}; - -typedef enum psa_crypto_driver_pake_step { - PSA_JPAKE_STEP_INVALID = 0, /* Invalid step */ - PSA_JPAKE_X1_STEP_KEY_SHARE = 1, /* Round 1: input/output key share (for ephemeral private key X1).*/ - PSA_JPAKE_X1_STEP_ZK_PUBLIC = 2, /* Round 1: input/output Schnorr NIZKP public key for the X1 key */ - PSA_JPAKE_X1_STEP_ZK_PROOF = 3, /* Round 1: input/output Schnorr NIZKP proof for the X1 key */ - PSA_JPAKE_X2_STEP_KEY_SHARE = 4, /* Round 1: input/output key share (for ephemeral private key X2).*/ - PSA_JPAKE_X2_STEP_ZK_PUBLIC = 5, /* Round 1: input/output Schnorr NIZKP public key for the X2 key */ - PSA_JPAKE_X2_STEP_ZK_PROOF = 6, /* Round 1: input/output Schnorr NIZKP proof for the X2 key */ - PSA_JPAKE_X2S_STEP_KEY_SHARE = 7, /* Round 2: output X2S key (our key) */ - PSA_JPAKE_X2S_STEP_ZK_PUBLIC = 8, /* Round 2: output Schnorr NIZKP public key for the X2S key (our key) */ - PSA_JPAKE_X2S_STEP_ZK_PROOF = 9, /* Round 2: output Schnorr NIZKP proof for the X2S key (our key) */ - PSA_JPAKE_X4S_STEP_KEY_SHARE = 10, /* Round 2: input X4S key (from peer) */ - PSA_JPAKE_X4S_STEP_ZK_PUBLIC = 11, /* Round 2: input Schnorr NIZKP public key for the X4S key (from peer) */ - PSA_JPAKE_X4S_STEP_ZK_PROOF = 12 /* Round 2: input Schnorr NIZKP proof for the X4S key (from peer) */ -} psa_crypto_driver_pake_step_t; - -typedef enum psa_jpake_round { - PSA_JPAKE_FIRST = 0, - PSA_JPAKE_SECOND = 1, - PSA_JPAKE_FINISHED = 2 -} psa_jpake_round_t; - -typedef enum psa_jpake_io_mode { - PSA_JPAKE_INPUT = 0, - PSA_JPAKE_OUTPUT = 1 -} psa_jpake_io_mode_t; - -struct psa_jpake_computation_stage_s { - /* The J-PAKE round we are currently on */ - psa_jpake_round_t MBEDTLS_PRIVATE(round); - /* The 'mode' we are currently in (inputting or outputting) */ - psa_jpake_io_mode_t MBEDTLS_PRIVATE(io_mode); - /* The number of completed inputs so far this round */ - uint8_t MBEDTLS_PRIVATE(inputs); - /* The number of completed outputs so far this round */ - uint8_t MBEDTLS_PRIVATE(outputs); - /* The next expected step (KEY_SHARE, ZK_PUBLIC or ZK_PROOF) */ - psa_pake_step_t MBEDTLS_PRIVATE(step); -}; - -#define PSA_JPAKE_EXPECTED_INPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ - ((round) == PSA_JPAKE_FIRST ? 2 : 1)) -#define PSA_JPAKE_EXPECTED_OUTPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ - ((round) == PSA_JPAKE_FIRST ? 2 : 1)) - -struct psa_pake_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - /* Algorithm of the PAKE operation */ - psa_algorithm_t MBEDTLS_PRIVATE(alg); - /* A primitive of type compatible with algorithm */ - psa_pake_primitive_t MBEDTLS_PRIVATE(primitive); - /* Stage of the PAKE operation: waiting for the setup, collecting inputs - * or computing. */ - uint8_t MBEDTLS_PRIVATE(stage); - /* Holds computation stage of the PAKE algorithms. */ - union { - uint8_t MBEDTLS_PRIVATE(dummy); -#if defined(PSA_WANT_ALG_JPAKE) - psa_jpake_computation_stage_t MBEDTLS_PRIVATE(jpake); -#endif - } MBEDTLS_PRIVATE(computation_stage); - union { - psa_driver_pake_context_t MBEDTLS_PRIVATE(ctx); - psa_crypto_driver_pake_inputs_t MBEDTLS_PRIVATE(inputs); - } MBEDTLS_PRIVATE(data); -#endif -}; - -static inline struct psa_pake_cipher_suite_s psa_pake_cipher_suite_init(void) -{ - const struct psa_pake_cipher_suite_s v = PSA_PAKE_CIPHER_SUITE_INIT; - return v; -} - -static inline struct psa_pake_operation_s psa_pake_operation_init(void) -{ - const struct psa_pake_operation_s v = PSA_PAKE_OPERATION_INIT; - return v; -} - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_EXTRA_H */ diff --git a/interface/include/psa/crypto_legacy.h b/interface/include/psa/crypto_legacy.h deleted file mode 100644 index 7df3614d6..000000000 --- a/interface/include/psa/crypto_legacy.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file psa/crypto_legacy.h - * - * \brief Add temporary suppport for deprecated symbols before they are - * removed from the library. - * - * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR and MBEDTLS_PSA_ACCEL_KEY_TYPE_xxx_KEY_PAIR - * symbols are deprecated. - * New symols add a suffix to that base name in order to clearly state what is - * the expected use for the key (use, import, export, generate, derive). - * Here we define some backward compatibility support for uses stil using - * the legacy symbols. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef MBEDTLS_PSA_CRYPTO_LEGACY_H -#define MBEDTLS_PSA_CRYPTO_LEGACY_H - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) //no-check-names -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 -#endif -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) //no-check-names -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -#endif -#endif - -#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) //no-check-names -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE -#endif -#endif - -#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR) //no-check-names -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE -#endif -#endif - -#endif /* MBEDTLS_PSA_CRYPTO_LEGACY_H */ diff --git a/interface/include/psa/crypto_platform.h b/interface/include/psa/crypto_platform.h deleted file mode 100644 index a871ee124..000000000 --- a/interface/include/psa/crypto_platform.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file psa/crypto_platform.h - * - * \brief PSA cryptography module: Mbed TLS platform definitions - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains platform-dependent type definitions. - * - * In implementations with isolation between the application and the - * cryptography module, implementers should take care to ensure that - * the definitions that are exposed to applications match what the - * module implements. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_PLATFORM_H -#define PSA_CRYPTO_PLATFORM_H -#include "mbedtls/private_access.h" - -/* - * Include the build-time configuration information header. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * TF-PSA-Crypto repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -/* PSA requires several types which C99 provides in stdint.h. */ -#include - -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - -/* Building for the PSA Crypto service on a PSA platform, a key owner is a PSA - * partition identifier. - * - * The function psa_its_identifier_of_slot() in psa_crypto_storage.c that - * translates a key identifier to a key storage file name assumes that - * mbedtls_key_owner_id_t is a 32-bit integer. This function thus needs - * reworking if mbedtls_key_owner_id_t is not defined as a 32-bit integer - * here anymore. - */ -typedef int32_t mbedtls_key_owner_id_t; - -/** Compare two key owner identifiers. - * - * \param id1 First key owner identifier. - * \param id2 Second key owner identifier. - * - * \return Non-zero if the two key owner identifiers are equal, zero otherwise. - */ -static inline int mbedtls_key_owner_id_equal(mbedtls_key_owner_id_t id1, - mbedtls_key_owner_id_t id2) -{ - return id1 == id2; -} - -#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/* - * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is being built for SPM - * (Secure Partition Manager) integration which separates the code into two - * parts: NSPE (Non-Secure Processing Environment) and SPE (Secure Processing - * Environment). When building for the SPE, an additional header file should be - * included. - */ -#if defined(MBEDTLS_PSA_CRYPTO_SPM) -#define PSA_CRYPTO_SECURE 1 -#include "crypto_spe.h" -#endif // MBEDTLS_PSA_CRYPTO_SPM - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -/** The type of the context passed to mbedtls_psa_external_get_random(). - * - * Mbed TLS initializes the context to all-bits-zero before calling - * mbedtls_psa_external_get_random() for the first time. - * - * The definition of this type in the Mbed TLS source code is for - * demonstration purposes. Implementers of mbedtls_psa_external_get_random() - * are expected to replace it with a custom definition. - */ -typedef struct { - uintptr_t MBEDTLS_PRIVATE(opaque)[2]; -} mbedtls_psa_external_random_context_t; -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -/** The type of the client handle used in context structures - * - * When a client view of the multipart context structures is required, - * this handle is used to keep a mapping with the service side of the - * context which contains the actual data. - */ -typedef uint32_t mbedtls_psa_client_handle_t; -#endif - -#endif /* PSA_CRYPTO_PLATFORM_H */ diff --git a/interface/include/psa/crypto_se_driver.h b/interface/include/psa/crypto_se_driver.h deleted file mode 100644 index 9ce14bba6..000000000 --- a/interface/include/psa/crypto_se_driver.h +++ /dev/null @@ -1,1383 +0,0 @@ -/** - * \file psa/crypto_se_driver.h - * \brief PSA external cryptoprocessor driver module - * - * This header declares types and function signatures for cryptography - * drivers that access key material via opaque references. - * This is meant for cryptoprocessors that have a separate key storage from the - * space in which the PSA Crypto implementation runs, typically secure - * elements (SEs). - * - * This file is part of the PSA Crypto Driver HAL (hardware abstraction layer), - * containing functions for driver developers to implement to enable hardware - * to be called in a standardized way by a PSA Cryptography API - * implementation. The functions comprising the driver HAL, which driver - * authors implement, are not intended to be called by application developers. - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ -#ifndef PSA_CRYPTO_SE_DRIVER_H -#define PSA_CRYPTO_SE_DRIVER_H -#include "mbedtls/private_access.h" - -#include "crypto_driver_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup se_init Secure element driver initialization - */ -/**@{*/ - -/** \brief Driver context structure - * - * Driver functions receive a pointer to this structure. - * Each registered driver has one instance of this structure. - * - * Implementations must include the fields specified here and - * may include other fields. - */ -typedef struct { - /** A read-only pointer to the driver's persistent data. - * - * Drivers typically use this persistent data to keep track of - * which slot numbers are available. This is only a guideline: - * drivers may use the persistent data for any purpose, keeping - * in mind the restrictions on when the persistent data is saved - * to storage: the persistent data is only saved after calling - * certain functions that receive a writable pointer to the - * persistent data. - * - * The core allocates a memory buffer for the persistent data. - * The pointer is guaranteed to be suitably aligned for any data type, - * like a pointer returned by `malloc` (but the core can use any - * method to allocate the buffer, not necessarily `malloc`). - * - * The size of this buffer is in the \c persistent_data_size field of - * this structure. - * - * Before the driver is initialized for the first time, the content of - * the persistent data is all-bits-zero. After a driver upgrade, if the - * size of the persistent data has increased, the original data is padded - * on the right with zeros; if the size has decreased, the original data - * is truncated to the new size. - * - * This pointer is to read-only data. Only a few driver functions are - * allowed to modify the persistent data. These functions receive a - * writable pointer. These functions are: - * - psa_drv_se_t::p_init - * - psa_drv_se_key_management_t::p_allocate - * - psa_drv_se_key_management_t::p_destroy - * - * The PSA Cryptography core saves the persistent data from one - * session to the next. It does this before returning from API functions - * that call a driver method that is allowed to modify the persistent - * data, specifically: - * - psa_crypto_init() causes a call to psa_drv_se_t::p_init, and may call - * psa_drv_se_key_management_t::p_destroy to complete an action - * that was interrupted by a power failure. - * - Key creation functions cause a call to - * psa_drv_se_key_management_t::p_allocate, and may cause a call to - * psa_drv_se_key_management_t::p_destroy in case an error occurs. - * - psa_destroy_key() causes a call to - * psa_drv_se_key_management_t::p_destroy. - */ - const void *const MBEDTLS_PRIVATE(persistent_data); - - /** The size of \c persistent_data in bytes. - * - * This is always equal to the value of the `persistent_data_size` field - * of the ::psa_drv_se_t structure when the driver is registered. - */ - const size_t MBEDTLS_PRIVATE(persistent_data_size); - - /** Driver transient data. - * - * The core initializes this value to 0 and does not read or modify it - * afterwards. The driver may store whatever it wants in this field. - */ - uintptr_t MBEDTLS_PRIVATE(transient_data); -} psa_drv_se_context_t; - -/** \brief A driver initialization function. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param location The location value for which this driver - * is registered. The driver will be invoked - * for all keys whose lifetime is in this - * location. - * - * \retval #PSA_SUCCESS - * The driver is operational. - * The core will update the persistent data in storage. - * \return - * Any other return value prevents the driver from being used in - * this session. - * The core will NOT update the persistent data in storage. - */ -typedef psa_status_t (*psa_drv_se_init_t)(psa_drv_se_context_t *drv_context, - void *persistent_data, - psa_key_location_t location); - -#if defined(__DOXYGEN_ONLY__) || !defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* Mbed TLS with secure element support enabled defines this type in - * crypto_types.h because it is also visible to applications through an - * implementation-specific extension. - * For the PSA Cryptography specification, this type is only visible - * via crypto_se_driver.h. */ -/** An internal designation of a key slot between the core part of the - * PSA Crypto implementation and the driver. The meaning of this value - * is driver-dependent. */ -typedef uint64_t psa_key_slot_number_t; -#endif /* __DOXYGEN_ONLY__ || !MBEDTLS_PSA_CRYPTO_SE_C */ - -/**@}*/ - -/** \defgroup se_mac Secure Element Message Authentication Codes - * Generation and authentication of Message Authentication Codes (MACs) using - * a secure element can be done either as a single function call (via the - * `psa_drv_se_mac_generate_t` or `psa_drv_se_mac_verify_t` functions), or in - * parts using the following sequence: - * - `psa_drv_se_mac_setup_t` - * - `psa_drv_se_mac_update_t` - * - `psa_drv_se_mac_update_t` - * - ... - * - `psa_drv_se_mac_finish_t` or `psa_drv_se_mac_finish_verify_t` - * - * If a previously started secure element MAC operation needs to be terminated, - * it should be done so by the `psa_drv_se_mac_abort_t`. Failure to do so may - * result in allocated resources not being freed or in other undefined - * behavior. - */ -/**@{*/ -/** \brief A function that starts a secure element MAC operation for a PSA - * Crypto Driver implementation - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A structure that will contain the - * hardware-specific MAC context - * \param[in] key_slot The slot of the key to be used for the - * operation - * \param[in] algorithm The algorithm to be used to underly the MAC - * operation - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm); - -/** \brief A function that continues a previously started secure element MAC - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously-established MAC operation to be - * updated - * \param[in] p_input A buffer containing the message to be appended - * to the MAC operation - * \param[in] input_length The size in bytes of the input message buffer - */ -typedef psa_status_t (*psa_drv_se_mac_update_t)(void *op_context, - const uint8_t *p_input, - size_t input_length); - -/** \brief a function that completes a previously started secure element MAC - * operation by returning the resulting MAC. - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started MAC operation to be - * finished - * \param[out] p_mac A buffer where the generated MAC will be - * placed - * \param[in] mac_size The size in bytes of the buffer that has been - * allocated for the `output` buffer - * \param[out] p_mac_length After completion, will contain the number of - * bytes placed in the `p_mac` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_finish_t)(void *op_context, - uint8_t *p_mac, - size_t mac_size, - size_t *p_mac_length); - -/** \brief A function that completes a previously started secure element MAC - * operation by comparing the resulting MAC against a provided value - * - * \param[in,out] op_context A hardware-specific structure for the previously - * started MAC operation to be finished - * \param[in] p_mac The MAC value against which the resulting MAC - * will be compared against - * \param[in] mac_length The size in bytes of the value stored in `p_mac` - * - * \retval #PSA_SUCCESS - * The operation completed successfully and the MACs matched each - * other - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The operation completed successfully, but the calculated MAC did - * not match the provided MAC - */ -typedef psa_status_t (*psa_drv_se_mac_finish_verify_t)(void *op_context, - const uint8_t *p_mac, - size_t mac_length); - -/** \brief A function that aborts a previous started secure element MAC - * operation - * - * \param[in,out] op_context A hardware-specific structure for the previously - * started MAC operation to be aborted - */ -typedef psa_status_t (*psa_drv_se_mac_abort_t)(void *op_context); - -/** \brief A function that performs a secure element MAC operation in one - * command and returns the calculated MAC - * - * \param[in,out] drv_context The driver context structure. - * \param[in] p_input A buffer containing the message to be MACed - * \param[in] input_length The size in bytes of `p_input` - * \param[in] key_slot The slot of the key to be used - * \param[in] alg The algorithm to be used to underlie the MAC - * operation - * \param[out] p_mac A buffer where the generated MAC will be - * placed - * \param[in] mac_size The size in bytes of the `p_mac` buffer - * \param[out] p_mac_length After completion, will contain the number of - * bytes placed in the `output` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_generate_t)(psa_drv_se_context_t *drv_context, - const uint8_t *p_input, - size_t input_length, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - uint8_t *p_mac, - size_t mac_size, - size_t *p_mac_length); - -/** \brief A function that performs a secure element MAC operation in one - * command and compares the resulting MAC against a provided value - * - * \param[in,out] drv_context The driver context structure. - * \param[in] p_input A buffer containing the message to be MACed - * \param[in] input_length The size in bytes of `input` - * \param[in] key_slot The slot of the key to be used - * \param[in] alg The algorithm to be used to underlie the MAC - * operation - * \param[in] p_mac The MAC value against which the resulting MAC will - * be compared against - * \param[in] mac_length The size in bytes of `mac` - * - * \retval #PSA_SUCCESS - * The operation completed successfully and the MACs matched each - * other - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The operation completed successfully, but the calculated MAC did - * not match the provided MAC - */ -typedef psa_status_t (*psa_drv_se_mac_verify_t)(psa_drv_se_context_t *drv_context, - const uint8_t *p_input, - size_t input_length, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_mac, - size_t mac_length); - -/** \brief A struct containing all of the function pointers needed to - * perform secure element MAC operations - * - * PSA Crypto API implementations should populate the table as appropriate - * upon startup. - * - * If one of the functions is not implemented (such as - * `psa_drv_se_mac_generate_t`), it should be set to NULL. - * - * Driver implementers should ensure that they implement all of the functions - * that make sense for their hardware, and that they provide a full solution - * (for example, if they support `p_setup`, they should also support - * `p_update` and at least one of `p_finish` or `p_finish_verify`). - * - */ -typedef struct { - /**The size in bytes of the hardware-specific secure element MAC context - * structure - */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a MAC setup operation - */ - psa_drv_se_mac_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that performs a MAC update operation - */ - psa_drv_se_mac_update_t MBEDTLS_PRIVATE(p_update); - /** Function that completes a MAC operation - */ - psa_drv_se_mac_finish_t MBEDTLS_PRIVATE(p_finish); - /** Function that completes a MAC operation with a verify check - */ - psa_drv_se_mac_finish_verify_t MBEDTLS_PRIVATE(p_finish_verify); - /** Function that aborts a previously started MAC operation - */ - psa_drv_se_mac_abort_t MBEDTLS_PRIVATE(p_abort); - /** Function that performs a MAC operation in one call - */ - psa_drv_se_mac_generate_t MBEDTLS_PRIVATE(p_mac); - /** Function that performs a MAC and verify operation in one call - */ - psa_drv_se_mac_verify_t MBEDTLS_PRIVATE(p_mac_verify); -} psa_drv_se_mac_t; -/**@}*/ - -/** \defgroup se_cipher Secure Element Symmetric Ciphers - * - * Encryption and Decryption using secure element keys in block modes other - * than ECB must be done in multiple parts, using the following flow: - * - `psa_drv_se_cipher_setup_t` - * - `psa_drv_se_cipher_set_iv_t` (optional depending upon block mode) - * - `psa_drv_se_cipher_update_t` - * - `psa_drv_se_cipher_update_t` - * - ... - * - `psa_drv_se_cipher_finish_t` - * - * If a previously started secure element Cipher operation needs to be - * terminated, it should be done so by the `psa_drv_se_cipher_abort_t`. Failure - * to do so may result in allocated resources not being freed or in other - * undefined behavior. - * - * In situations where a PSA Cryptographic API implementation is using a block - * mode not-supported by the underlying hardware or driver, it can construct - * the block mode itself, while calling the `psa_drv_se_cipher_ecb_t` function - * for the cipher operations. - */ -/**@{*/ - -/** \brief A function that provides the cipher setup function for a - * secure element driver - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A structure that will contain the - * hardware-specific cipher context. - * \param[in] key_slot The slot of the key to be used for the - * operation - * \param[in] algorithm The algorithm to be used in the cipher - * operation - * \param[in] direction Indicates whether the operation is an encrypt - * or decrypt - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - psa_encrypt_or_decrypt_t direction); - -/** \brief A function that sets the initialization vector (if - * necessary) for a secure element cipher operation - * - * Rationale: The `psa_se_cipher_*` operation in the PSA Cryptographic API has - * two IV functions: one to set the IV, and one to generate it internally. The - * generate function is not necessary for the drivers to implement as the PSA - * Crypto implementation can do the generation using its RNG features. - * - * \param[in,out] op_context A structure that contains the previously set up - * hardware-specific cipher context - * \param[in] p_iv A buffer containing the initialization vector - * \param[in] iv_length The size (in bytes) of the `p_iv` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_set_iv_t)(void *op_context, - const uint8_t *p_iv, - size_t iv_length); - -/** \brief A function that continues a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - * \param[in] p_input A buffer containing the data to be - * encrypted/decrypted - * \param[in] input_size The size in bytes of the buffer pointed to - * by `p_input` - * \param[out] p_output The caller-allocated buffer where the - * output will be placed - * \param[in] output_size The allocated size in bytes of the - * `p_output` buffer - * \param[out] p_output_length After completion, will contain the number - * of bytes placed in the `p_output` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_update_t)(void *op_context, - const uint8_t *p_input, - size_t input_size, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** \brief A function that completes a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - * \param[out] p_output The caller-allocated buffer where the output - * will be placed - * \param[in] output_size The allocated size in bytes of the `p_output` - * buffer - * \param[out] p_output_length After completion, will contain the number of - * bytes placed in the `p_output` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_finish_t)(void *op_context, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** \brief A function that aborts a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - */ -typedef psa_status_t (*psa_drv_se_cipher_abort_t)(void *op_context); - -/** \brief A function that performs the ECB block mode for secure element - * cipher operations - * - * Note: this function should only be used with implementations that do not - * provide a needed higher-level operation. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot The slot of the key to be used for the operation - * \param[in] algorithm The algorithm to be used in the cipher operation - * \param[in] direction Indicates whether the operation is an encrypt or - * decrypt - * \param[in] p_input A buffer containing the data to be - * encrypted/decrypted - * \param[in] input_size The size in bytes of the buffer pointed to by - * `p_input` - * \param[out] p_output The caller-allocated buffer where the output - * will be placed - * \param[in] output_size The allocated size in bytes of the `p_output` - * buffer - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_ecb_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - psa_encrypt_or_decrypt_t direction, - const uint8_t *p_input, - size_t input_size, - uint8_t *p_output, - size_t output_size); - -/** - * \brief A struct containing all of the function pointers needed to implement - * cipher operations using secure elements. - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented (such as - * `psa_drv_se_cipher_ecb_t`), it should be set to NULL. - */ -typedef struct { - /** The size in bytes of the hardware-specific secure element cipher - * context structure - */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a cipher setup operation */ - psa_drv_se_cipher_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that sets a cipher IV (if necessary) */ - psa_drv_se_cipher_set_iv_t MBEDTLS_PRIVATE(p_set_iv); - /** Function that performs a cipher update operation */ - psa_drv_se_cipher_update_t MBEDTLS_PRIVATE(p_update); - /** Function that completes a cipher operation */ - psa_drv_se_cipher_finish_t MBEDTLS_PRIVATE(p_finish); - /** Function that aborts a cipher operation */ - psa_drv_se_cipher_abort_t MBEDTLS_PRIVATE(p_abort); - /** Function that performs ECB mode for a cipher operation - * (Danger: ECB mode should not be used directly by clients of the PSA - * Crypto Client API) - */ - psa_drv_se_cipher_ecb_t MBEDTLS_PRIVATE(p_ecb); -} psa_drv_se_cipher_t; - -/**@}*/ - -/** \defgroup se_asymmetric Secure Element Asymmetric Cryptography - * - * Since the amount of data that can (or should) be encrypted or signed using - * asymmetric keys is limited by the key size, asymmetric key operations using - * keys in a secure element must be done in single function calls. - */ -/**@{*/ - -/** - * \brief A function that signs a hash or short message with a private key in - * a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of an asymmetric key pair - * \param[in] alg A signature algorithm that is compatible - * with the type of `key` - * \param[in] p_hash The hash to sign - * \param[in] hash_length Size of the `p_hash` buffer in bytes - * \param[out] p_signature Buffer where the signature is to be written - * \param[in] signature_size Size of the `p_signature` buffer in bytes - * \param[out] p_signature_length On success, the number of bytes - * that make up the returned signature value - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_sign_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_hash, - size_t hash_length, - uint8_t *p_signature, - size_t signature_size, - size_t *p_signature_length); - -/** - * \brief A function that verifies the signature a hash or short message using - * an asymmetric public key in a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of a public key or an asymmetric key - * pair - * \param[in] alg A signature algorithm that is compatible with - * the type of `key` - * \param[in] p_hash The hash whose signature is to be verified - * \param[in] hash_length Size of the `p_hash` buffer in bytes - * \param[in] p_signature Buffer containing the signature to verify - * \param[in] signature_length Size of the `p_signature` buffer in bytes - * - * \retval #PSA_SUCCESS - * The signature is valid. - */ -typedef psa_status_t (*psa_drv_se_asymmetric_verify_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_hash, - size_t hash_length, - const uint8_t *p_signature, - size_t signature_length); - -/** - * \brief A function that encrypts a short message with an asymmetric public - * key in a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of a public key or an asymmetric key - * pair - * \param[in] alg An asymmetric encryption algorithm that is - * compatible with the type of `key` - * \param[in] p_input The message to encrypt - * \param[in] input_length Size of the `p_input` buffer in bytes - * \param[in] p_salt A salt or label, if supported by the - * encryption algorithm - * If the algorithm does not support a - * salt, pass `NULL`. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass `NULL`. - * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param[in] salt_length Size of the `p_salt` buffer in bytes - * If `p_salt` is `NULL`, pass 0. - * \param[out] p_output Buffer where the encrypted message is to - * be written - * \param[in] output_size Size of the `p_output` buffer in bytes - * \param[out] p_output_length On success, the number of bytes that make up - * the returned output - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_encrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_input, - size_t input_length, - const uint8_t *p_salt, - size_t salt_length, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A function that decrypts a short message with an asymmetric private - * key in a secure element. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of an asymmetric key pair - * \param[in] alg An asymmetric encryption algorithm that is - * compatible with the type of `key` - * \param[in] p_input The message to decrypt - * \param[in] input_length Size of the `p_input` buffer in bytes - * \param[in] p_salt A salt or label, if supported by the - * encryption algorithm - * If the algorithm does not support a - * salt, pass `NULL`. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass `NULL`. - * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param[in] salt_length Size of the `p_salt` buffer in bytes - * If `p_salt` is `NULL`, pass 0. - * \param[out] p_output Buffer where the decrypted message is to - * be written - * \param[in] output_size Size of the `p_output` buffer in bytes - * \param[out] p_output_length On success, the number of bytes - * that make up the returned output - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_decrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_input, - size_t input_length, - const uint8_t *p_salt, - size_t salt_length, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A struct containing all of the function pointers needed to implement - * asymmetric cryptographic operations using secure elements. - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that performs an asymmetric sign operation */ - psa_drv_se_asymmetric_sign_t MBEDTLS_PRIVATE(p_sign); - /** Function that performs an asymmetric verify operation */ - psa_drv_se_asymmetric_verify_t MBEDTLS_PRIVATE(p_verify); - /** Function that performs an asymmetric encrypt operation */ - psa_drv_se_asymmetric_encrypt_t MBEDTLS_PRIVATE(p_encrypt); - /** Function that performs an asymmetric decrypt operation */ - psa_drv_se_asymmetric_decrypt_t MBEDTLS_PRIVATE(p_decrypt); -} psa_drv_se_asymmetric_t; - -/**@}*/ - -/** \defgroup se_aead Secure Element Authenticated Encryption with Additional Data - * Authenticated Encryption with Additional Data (AEAD) operations with secure - * elements must be done in one function call. While this creates a burden for - * implementers as there must be sufficient space in memory for the entire - * message, it prevents decrypted data from being made available before the - * authentication operation is complete and the data is known to be authentic. - */ -/**@{*/ - -/** \brief A function that performs a secure element authenticated encryption - * operation - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Slot containing the key to use. - * \param[in] algorithm The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(`alg`) is true) - * \param[in] p_nonce Nonce or IV to use - * \param[in] nonce_length Size of the `p_nonce` buffer in bytes - * \param[in] p_additional_data Additional data that will be - * authenticated but not encrypted - * \param[in] additional_data_length Size of `p_additional_data` in bytes - * \param[in] p_plaintext Data that will be authenticated and - * encrypted - * \param[in] plaintext_length Size of `p_plaintext` in bytes - * \param[out] p_ciphertext Output buffer for the authenticated and - * encrypted data. The additional data is - * not part of this output. For algorithms - * where the encrypted data and the - * authentication tag are defined as - * separate outputs, the authentication - * tag is appended to the encrypted data. - * \param[in] ciphertext_size Size of the `p_ciphertext` buffer in - * bytes - * \param[out] p_ciphertext_length On success, the size of the output in - * the `p_ciphertext` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_aead_encrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - const uint8_t *p_nonce, - size_t nonce_length, - const uint8_t *p_additional_data, - size_t additional_data_length, - const uint8_t *p_plaintext, - size_t plaintext_length, - uint8_t *p_ciphertext, - size_t ciphertext_size, - size_t *p_ciphertext_length); - -/** A function that performs a secure element authenticated decryption operation - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Slot containing the key to use - * \param[in] algorithm The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(`alg`) is true) - * \param[in] p_nonce Nonce or IV to use - * \param[in] nonce_length Size of the `p_nonce` buffer in bytes - * \param[in] p_additional_data Additional data that has been - * authenticated but not encrypted - * \param[in] additional_data_length Size of `p_additional_data` in bytes - * \param[in] p_ciphertext Data that has been authenticated and - * encrypted. - * For algorithms where the encrypted data - * and the authentication tag are defined - * as separate inputs, the buffer must - * contain the encrypted data followed by - * the authentication tag. - * \param[in] ciphertext_length Size of `p_ciphertext` in bytes - * \param[out] p_plaintext Output buffer for the decrypted data - * \param[in] plaintext_size Size of the `p_plaintext` buffer in - * bytes - * \param[out] p_plaintext_length On success, the size of the output in - * the `p_plaintext` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_aead_decrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - const uint8_t *p_nonce, - size_t nonce_length, - const uint8_t *p_additional_data, - size_t additional_data_length, - const uint8_t *p_ciphertext, - size_t ciphertext_length, - uint8_t *p_plaintext, - size_t plaintext_size, - size_t *p_plaintext_length); - -/** - * \brief A struct containing all of the function pointers needed to implement - * secure element Authenticated Encryption with Additional Data operations - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that performs the AEAD encrypt operation */ - psa_drv_se_aead_encrypt_t MBEDTLS_PRIVATE(p_encrypt); - /** Function that performs the AEAD decrypt operation */ - psa_drv_se_aead_decrypt_t MBEDTLS_PRIVATE(p_decrypt); -} psa_drv_se_aead_t; -/**@}*/ - -/** \defgroup se_key_management Secure Element Key Management - * Currently, key management is limited to importing keys in the clear, - * destroying keys, and exporting keys in the clear. - * Whether a key may be exported is determined by the key policies in place - * on the key slot. - */ -/**@{*/ - -/** An enumeration indicating how a key is created. - */ -typedef enum { - PSA_KEY_CREATION_IMPORT, /**< During psa_import_key() */ - PSA_KEY_CREATION_GENERATE, /**< During psa_generate_key() */ - PSA_KEY_CREATION_DERIVE, /**< During psa_key_derivation_output_key() */ - PSA_KEY_CREATION_COPY, /**< During psa_copy_key() */ - -#ifndef __DOXYGEN_ONLY__ - /** A key is being registered with mbedtls_psa_register_se_key(). - * - * The core only passes this value to - * psa_drv_se_key_management_t::p_validate_slot_number, not to - * psa_drv_se_key_management_t::p_allocate. The call to - * `p_validate_slot_number` is not followed by any other call to the - * driver: the key is considered successfully registered if the call to - * `p_validate_slot_number` succeeds, or if `p_validate_slot_number` is - * null. - * - * With this creation method, the driver must return #PSA_SUCCESS if - * the given attributes are compatible with the existing key in the slot, - * and #PSA_ERROR_DOES_NOT_EXIST if the driver can determine that there - * is no key with the specified slot number. - * - * This is an Mbed TLS extension. - */ - PSA_KEY_CREATION_REGISTER, -#endif -} psa_key_creation_method_t; - -/** \brief A function that allocates a slot for a key. - * - * To create a key in a specific slot in a secure element, the core - * first calls this function to determine a valid slot number, - * then calls a function to create the key material in that slot. - * In nominal conditions (that is, if no error occurs), - * the effect of a call to a key creation function in the PSA Cryptography - * API with a lifetime that places the key in a secure element is the - * following: - * -# The core calls psa_drv_se_key_management_t::p_allocate - * (or in some implementations - * psa_drv_se_key_management_t::p_validate_slot_number). The driver - * selects (or validates) a suitable slot number given the key attributes - * and the state of the secure element. - * -# The core calls a key creation function in the driver. - * - * The key creation functions in the PSA Cryptography API are: - * - psa_import_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_IMPORT - * then a call to psa_drv_se_key_management_t::p_import. - * - psa_generate_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_GENERATE - * then a call to psa_drv_se_key_management_t::p_import. - * - psa_key_derivation_output_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_DERIVE - * then a call to psa_drv_se_key_derivation_t::p_derive. - * - psa_copy_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_COPY - * then a call to psa_drv_se_key_management_t::p_export. - * - * In case of errors, other behaviors are possible. - * - If the PSA Cryptography subsystem dies after the first step, - * for example because the device has lost power abruptly, - * the second step may never happen, or may happen after a reset - * and re-initialization. Alternatively, after a reset and - * re-initialization, the core may call - * psa_drv_se_key_management_t::p_destroy on the slot number that - * was allocated (or validated) instead of calling a key creation function. - * - If an error occurs, the core may call - * psa_drv_se_key_management_t::p_destroy on the slot number that - * was allocated (or validated) instead of calling a key creation function. - * - * Errors and system resets also have an impact on the driver's persistent - * data. If a reset happens before the overall key creation process is - * completed (before or after the second step above), it is unspecified - * whether the persistent data after the reset is identical to what it - * was before or after the call to `p_allocate` (or `p_validate_slot_number`). - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param[in] attributes Attributes of the key. - * \param method The way in which the key is being created. - * \param[out] key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * - * \retval #PSA_SUCCESS - * Success. - * The core will record \c *key_slot as the key slot where the key - * is stored and will update the persistent data in storage. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - */ -typedef psa_status_t (*psa_drv_se_allocate_key_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_key_slot_number_t *key_slot); - -/** \brief A function that determines whether a slot number is valid - * for a key. - * - * To create a key in a specific slot in a secure element, the core - * first calls this function to validate the choice of slot number, - * then calls a function to create the key material in that slot. - * See the documentation of #psa_drv_se_allocate_key_t for more details. - * - * As of the PSA Cryptography API specification version 1.0, there is no way - * for applications to trigger a call to this function. However some - * implementations offer the capability to create or declare a key in - * a specific slot via implementation-specific means, generally for the - * sake of initial device provisioning or onboarding. Such a mechanism may - * be added to a future version of the PSA Cryptography API specification. - * - * This function may update the driver's persistent data through - * \p persistent_data. The core will save the updated persistent data at the - * end of the key creation process. See the description of - * ::psa_drv_se_allocate_key_t for more information. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param[in] attributes Attributes of the key. - * \param method The way in which the key is being created. - * \param[in] key_slot Slot where the key is to be stored. - * - * \retval #PSA_SUCCESS - * The given slot number is valid for a key with the given - * attributes. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The given slot number is not valid for a key with the - * given attributes. This includes the case where the slot - * number is not valid at all. - * \retval #PSA_ERROR_ALREADY_EXISTS - * There is already a key with the specified slot number. - * Drivers may choose to return this error from the key - * creation function instead. - */ -typedef psa_status_t (*psa_drv_se_validate_slot_number_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_key_slot_number_t key_slot); - -/** \brief A function that imports a key into a secure element in binary format - * - * This function can support any output from psa_export_key(). Refer to the - * documentation of psa_export_key() for the format for each key type. - * - * \param[in,out] drv_context The driver context structure. - * \param key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * \param[in] attributes The key attributes, including the lifetime, - * the key type and the usage policy. - * Drivers should not access the key size stored - * in the attributes: it may not match the - * data passed in \p data. - * Drivers can call psa_get_key_lifetime(), - * psa_get_key_type(), - * psa_get_key_usage_flags() and - * psa_get_key_algorithm() to access this - * information. - * \param[in] data Buffer containing the key data. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] bits On success, the key size in bits. The driver - * must determine this value after parsing the - * key according to the key type. - * This value is not used if the function fails. - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_import_key_t)( - psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - size_t *bits); - -/** - * \brief A function that destroys a secure element key and restore the slot to - * its default state - * - * This function destroys the content of the key from a secure element. - * Implementations shall make a best effort to ensure that any previous content - * of the slot is unrecoverable. - * - * This function returns the specified slot to its default state. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param key_slot The key slot to erase. - * - * \retval #PSA_SUCCESS - * The slot's content, if any, has been erased. - */ -typedef psa_status_t (*psa_drv_se_destroy_key_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - psa_key_slot_number_t key_slot); - -/** - * \brief A function that exports a secure element key in binary format - * - * The output of this function can be passed to psa_import_key() to - * create an equivalent object. - * - * If a key is created with `psa_import_key()` and then exported with - * this function, it is not guaranteed that the resulting data is - * identical: the implementation may choose a different representation - * of the same key if the format permits it. - * - * This function should generate output in the same format that - * `psa_export_key()` does. Refer to the - * documentation of `psa_export_key()` for the format for each key type. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key Slot whose content is to be exported. This must - * be an occupied key slot. - * \param[out] p_data Buffer where the key data is to be written. - * \param[in] data_size Size of the `p_data` buffer in bytes. - * \param[out] p_data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_export_key_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key, - uint8_t *p_data, - size_t data_size, - size_t *p_data_length); - -/** - * \brief A function that generates a symmetric or asymmetric key on a secure - * element - * - * If the key type \c type recorded in \p attributes - * is asymmetric (#PSA_KEY_TYPE_IS_ASYMMETRIC(\c type) = 1), - * the driver may export the public key at the time of generation, - * in the format documented for psa_export_public_key() by writing it - * to the \p pubkey buffer. - * This is optional, intended for secure elements that output the - * public key at generation time and that cannot export the public key - * later. Drivers that do not need this feature should leave - * \p *pubkey_length set to 0 and should - * implement the psa_drv_key_management_t::p_export_public function. - * Some implementations do not support this feature, in which case - * \p pubkey is \c NULL and \p pubkey_size is 0. - * - * \param[in,out] drv_context The driver context structure. - * \param key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * \param[in] attributes The key attributes, including the lifetime, - * the key type and size, and the usage policy. - * Drivers can call psa_get_key_lifetime(), - * psa_get_key_type(), psa_get_key_bits(), - * psa_get_key_usage_flags() and - * psa_get_key_algorithm() to access this - * information. - * \param[out] pubkey A buffer where the driver can write the - * public key, when generating an asymmetric - * key pair. - * This is \c NULL when generating a symmetric - * key or if the core does not support - * exporting the public key at generation time. - * \param pubkey_size The size of the `pubkey` buffer in bytes. - * This is 0 when generating a symmetric - * key or if the core does not support - * exporting the public key at generation time. - * \param[out] pubkey_length On entry, this is always 0. - * On success, the number of bytes written to - * \p pubkey. If this is 0 or unchanged on return, - * the core will not read the \p pubkey buffer, - * and will instead call the driver's - * psa_drv_key_management_t::p_export_public - * function to export the public key when needed. - */ -typedef psa_status_t (*psa_drv_se_generate_key_t)( - psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - const psa_key_attributes_t *attributes, - uint8_t *pubkey, size_t pubkey_size, size_t *pubkey_length); - -/** - * \brief A struct containing all of the function pointers needed to for secure - * element key management - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that allocates a slot for a key. */ - psa_drv_se_allocate_key_t MBEDTLS_PRIVATE(p_allocate); - /** Function that checks the validity of a slot for a key. */ - psa_drv_se_validate_slot_number_t MBEDTLS_PRIVATE(p_validate_slot_number); - /** Function that performs a key import operation */ - psa_drv_se_import_key_t MBEDTLS_PRIVATE(p_import); - /** Function that performs a generation */ - psa_drv_se_generate_key_t MBEDTLS_PRIVATE(p_generate); - /** Function that performs a key destroy operation */ - psa_drv_se_destroy_key_t MBEDTLS_PRIVATE(p_destroy); - /** Function that performs a key export operation */ - psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export); - /** Function that performs a public key export operation */ - psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export_public); -} psa_drv_se_key_management_t; - -/**@}*/ - -/** \defgroup driver_derivation Secure Element Key Derivation and Agreement - * Key derivation is the process of generating new key material using an - * existing key and additional parameters, iterating through a basic - * cryptographic function, such as a hash. - * Key agreement is a part of cryptographic protocols that allows two parties - * to agree on the same key value, but starting from different original key - * material. - * The flows are similar, and the PSA Crypto Driver Model uses the same functions - * for both of the flows. - * - * There are two different final functions for the flows, - * `psa_drv_se_key_derivation_derive` and `psa_drv_se_key_derivation_export`. - * `psa_drv_se_key_derivation_derive` is used when the key material should be - * placed in a slot on the hardware and not exposed to the caller. - * `psa_drv_se_key_derivation_export` is used when the key material should be - * returned to the PSA Cryptographic API implementation. - * - * Different key derivation algorithms require a different number of inputs. - * Instead of having an API that takes as input variable length arrays, which - * can be problematic to manage on embedded platforms, the inputs are passed - * to the driver via a function, `psa_drv_se_key_derivation_collateral`, that - * is called multiple times with different `collateral_id`s. Thus, for a key - * derivation algorithm that required 3 parameter inputs, the flow would look - * something like: - * ~~~~~~~~~~~~~{.c} - * psa_drv_se_key_derivation_setup(kdf_algorithm, source_key, dest_key_size_bytes); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_0, - * p_collateral_0, - * collateral_0_size); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_1, - * p_collateral_1, - * collateral_1_size); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_2, - * p_collateral_2, - * collateral_2_size); - * psa_drv_se_key_derivation_derive(); - * ~~~~~~~~~~~~~ - * - * key agreement example: - * ~~~~~~~~~~~~~{.c} - * psa_drv_se_key_derivation_setup(alg, source_key. dest_key_size_bytes); - * psa_drv_se_key_derivation_collateral(DHE_PUBKEY, p_pubkey, pubkey_size); - * psa_drv_se_key_derivation_export(p_session_key, - * session_key_size, - * &session_key_length); - * ~~~~~~~~~~~~~ - */ -/**@{*/ - -/** \brief A function that Sets up a secure element key derivation operation by - * specifying the algorithm and the source key sot - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] kdf_alg The algorithm to be used for the key derivation - * \param[in] source_key The key to be used as the source material for - * the key derivation - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_algorithm_t kdf_alg, - psa_key_slot_number_t source_key); - -/** \brief A function that provides collateral (parameters) needed for a secure - * element key derivation or key agreement operation - * - * Since many key derivation algorithms require multiple parameters, it is - * expected that this function may be called multiple times for the same - * operation, each with a different algorithm-specific `collateral_id` - * - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] collateral_id An ID for the collateral being provided - * \param[in] p_collateral A buffer containing the collateral data - * \param[in] collateral_size The size in bytes of the collateral - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_collateral_t)(void *op_context, - uint32_t collateral_id, - const uint8_t *p_collateral, - size_t collateral_size); - -/** \brief A function that performs the final secure element key derivation - * step and place the generated key material in a slot - * - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] dest_key The slot where the generated key material - * should be placed - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_derive_t)(void *op_context, - psa_key_slot_number_t dest_key); - -/** \brief A function that performs the final step of a secure element key - * agreement and place the generated key material in a buffer - * - * \param[out] p_output Buffer in which to place the generated key - * material - * \param[in] output_size The size in bytes of `p_output` - * \param[out] p_output_length Upon success, contains the number of bytes of - * key material placed in `p_output` - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_export_t)(void *op_context, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A struct containing all of the function pointers needed to for secure - * element key derivation and agreement - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** The driver-specific size of the key derivation context */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a key derivation setup */ - psa_drv_se_key_derivation_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that sets key derivation collateral */ - psa_drv_se_key_derivation_collateral_t MBEDTLS_PRIVATE(p_collateral); - /** Function that performs a final key derivation step */ - psa_drv_se_key_derivation_derive_t MBEDTLS_PRIVATE(p_derive); - /** Function that performs a final key derivation or agreement and - * exports the key */ - psa_drv_se_key_derivation_export_t MBEDTLS_PRIVATE(p_export); -} psa_drv_se_key_derivation_t; - -/**@}*/ - -/** \defgroup se_registration Secure element driver registration - */ -/**@{*/ - -/** A structure containing pointers to all the entry points of a - * secure element driver. - * - * Future versions of this specification may add extra substructures at - * the end of this structure. - */ -typedef struct { - /** The version of the driver HAL that this driver implements. - * This is a protection against loading driver binaries built against - * a different version of this specification. - * Use #PSA_DRV_SE_HAL_VERSION. - */ - uint32_t MBEDTLS_PRIVATE(hal_version); - - /** The size of the driver's persistent data in bytes. - * - * This can be 0 if the driver does not need persistent data. - * - * See the documentation of psa_drv_se_context_t::persistent_data - * for more information about why and how a driver can use - * persistent data. - */ - size_t MBEDTLS_PRIVATE(persistent_data_size); - - /** The driver initialization function. - * - * This function is called once during the initialization of the - * PSA Cryptography subsystem, before any other function of the - * driver is called. If this function returns a failure status, - * the driver will be unusable, at least until the next system reset. - * - * If this field is \c NULL, it is equivalent to a function that does - * nothing and returns #PSA_SUCCESS. - */ - psa_drv_se_init_t MBEDTLS_PRIVATE(p_init); - - const psa_drv_se_key_management_t *MBEDTLS_PRIVATE(key_management); - const psa_drv_se_mac_t *MBEDTLS_PRIVATE(mac); - const psa_drv_se_cipher_t *MBEDTLS_PRIVATE(cipher); - const psa_drv_se_aead_t *MBEDTLS_PRIVATE(aead); - const psa_drv_se_asymmetric_t *MBEDTLS_PRIVATE(asymmetric); - const psa_drv_se_key_derivation_t *MBEDTLS_PRIVATE(derivation); -} psa_drv_se_t; - -/** The current version of the secure element driver HAL. - */ -/* 0.0.0 patchlevel 5 */ -#define PSA_DRV_SE_HAL_VERSION 0x00000005 - -/** Register an external cryptoprocessor (secure element) driver. - * - * This function is only intended to be used by driver code, not by - * application code. In implementations with separation between the - * PSA cryptography module and applications, this function should - * only be available to callers that run in the same memory space as - * the cryptography module, and should not be exposed to applications - * running in a different memory space. - * - * This function may be called before psa_crypto_init(). It is - * implementation-defined whether this function may be called - * after psa_crypto_init(). - * - * \note Implementations store metadata about keys including the lifetime - * value, which contains the driver's location indicator. Therefore, - * from one instantiation of the PSA Cryptography - * library to the next one, if there is a key in storage with a certain - * lifetime value, you must always register the same driver (or an - * updated version that communicates with the same secure element) - * with the same location value. - * - * \param location The location value through which this driver will - * be exposed to applications. - * This driver will be used for all keys such that - * `location == #PSA_KEY_LIFETIME_GET_LOCATION( lifetime )`. - * The value #PSA_KEY_LOCATION_LOCAL_STORAGE is reserved - * and may not be used for drivers. Implementations - * may reserve other values. - * \param[in] methods The method table of the driver. This structure must - * remain valid for as long as the cryptography - * module keeps running. It is typically a global - * constant. - * - * \return #PSA_SUCCESS - * The driver was successfully registered. Applications can now - * use \p location to access keys through the methods passed to - * this function. - * \return #PSA_ERROR_BAD_STATE - * This function was called after the initialization of the - * cryptography module, and this implementation does not support - * driver registration at this stage. - * \return #PSA_ERROR_ALREADY_EXISTS - * There is already a registered driver for this value of \p location. - * \return #PSA_ERROR_INVALID_ARGUMENT - * \p location is a reserved value. - * \return #PSA_ERROR_NOT_SUPPORTED - * `methods->hal_version` is not supported by this implementation. - * \return #PSA_ERROR_INSUFFICIENT_MEMORY - * \return #PSA_ERROR_NOT_PERMITTED - * \return #PSA_ERROR_STORAGE_FAILURE - * \return #PSA_ERROR_DATA_CORRUPT - */ -psa_status_t psa_register_se_driver( - psa_key_location_t location, - const psa_drv_se_t *methods); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_SE_DRIVER_H */ diff --git a/interface/include/psa/crypto_sizes.h b/interface/include/psa/crypto_sizes.h deleted file mode 100644 index 635ee98f8..000000000 --- a/interface/include/psa/crypto_sizes.h +++ /dev/null @@ -1,1292 +0,0 @@ -/** - * \file psa/crypto_sizes.h - * - * \brief PSA cryptography module: Mbed TLS buffer size macros - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains the definitions of macros that are useful to - * compute buffer sizes. The signatures and semantics of these macros - * are standardized, but the definitions are not, because they depend on - * the available algorithms and, in some cases, on permitted tolerances - * on buffer sizes. - * - * In implementations with isolation between the application and the - * cryptography module, implementers should take care to ensure that - * the definitions that are exposed to applications match what the - * module implements. - * - * Macros that compute sizes whose values do not depend on the - * implementation are in crypto.h. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_SIZES_H -#define PSA_CRYPTO_SIZES_H - -/* - * Include the build-time configuration information header. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * TF-PSA-Crypto repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -#define PSA_BITS_TO_BYTES(bits) (((bits) + 7u) / 8u) -#define PSA_BYTES_TO_BITS(bytes) ((bytes) * 8u) -#define PSA_MAX_OF_THREE(a, b, c) ((a) <= (b) ? (b) <= (c) ? \ - (c) : (b) : (a) <= (c) ? (c) : (a)) - -#define PSA_ROUND_UP_TO_MULTIPLE(block_size, length) \ - (((length) + (block_size) - 1) / (block_size) * (block_size)) - -/** The size of the output of psa_hash_finish(), in bytes. - * - * This is also the hash size that psa_hash_verify() expects. - * - * \param alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p alg) is true), or an HMAC algorithm - * (#PSA_ALG_HMAC(\c hash_alg) where \c hash_alg is a - * hash algorithm). - * - * \return The hash size for the specified hash algorithm. - * If the hash algorithm is not recognized, return 0. - */ -#define PSA_HASH_LENGTH(alg) \ - ( \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 16u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 20u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 20u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 48u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 48u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 64u : \ - 0u) - -/** The input block size of a hash algorithm, in bytes. - * - * Hash algorithms process their input data in blocks. Hash operations will - * retain any partial blocks until they have enough input to fill the block or - * until the operation is finished. - * This affects the output from psa_hash_suspend(). - * - * \param alg A hash algorithm (\c PSA_ALG_XXX value such that - * PSA_ALG_IS_HASH(\p alg) is true). - * - * \return The block size in bytes for the specified hash algorithm. - * If the hash algorithm is not recognized, return 0. - * An implementation can return either 0 or the correct size for a - * hash algorithm that it recognizes, but does not support. - */ -#define PSA_HASH_BLOCK_LENGTH(alg) \ - ( \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 144u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 136u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 104u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 72u : \ - 0u) - -/** \def PSA_HASH_MAX_SIZE - * - * Maximum size of a hash. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a hash in bytes. - */ -/* Note: for HMAC-SHA-3, the block size is 144 bytes for HMAC-SHA3-224, - * 136 bytes for HMAC-SHA3-256, 104 bytes for SHA3-384, 72 bytes for - * HMAC-SHA3-512. */ -/* Note: PSA_HASH_MAX_SIZE should be kept in sync with MBEDTLS_MD_MAX_SIZE, - * see the note on MBEDTLS_MD_MAX_SIZE for details. */ -#if defined(PSA_WANT_ALG_SHA3_224) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 144u -#elif defined(PSA_WANT_ALG_SHA3_256) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 136u -#elif defined(PSA_WANT_ALG_SHA_512) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u -#elif defined(PSA_WANT_ALG_SHA_384) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u -#elif defined(PSA_WANT_ALG_SHA3_384) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 104u -#elif defined(PSA_WANT_ALG_SHA3_512) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 72u -#elif defined(PSA_WANT_ALG_SHA_256) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#elif defined(PSA_WANT_ALG_SHA_224) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#else /* SHA-1 or smaller */ -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#endif - -#if defined(PSA_WANT_ALG_SHA_512) || defined(PSA_WANT_ALG_SHA3_512) -#define PSA_HASH_MAX_SIZE 64u -#elif defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA3_384) -#define PSA_HASH_MAX_SIZE 48u -#elif defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA3_256) -#define PSA_HASH_MAX_SIZE 32u -#elif defined(PSA_WANT_ALG_SHA_224) || defined(PSA_WANT_ALG_SHA3_224) -#define PSA_HASH_MAX_SIZE 28u -#else /* SHA-1 or smaller */ -#define PSA_HASH_MAX_SIZE 20u -#endif - -/** \def PSA_MAC_MAX_SIZE - * - * Maximum size of a MAC. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a MAC in bytes. - */ -/* All non-HMAC MACs have a maximum size that's smaller than the - * minimum possible value of PSA_HASH_MAX_SIZE in this implementation. */ -/* Note that the encoding of truncated MAC algorithms limits this value - * to 64 bytes. - */ -#define PSA_MAC_MAX_SIZE PSA_HASH_MAX_SIZE - -/** The length of a tag for an AEAD algorithm, in bytes. - * - * This macro can be used to allocate a buffer of sufficient size to store the - * tag output from psa_aead_finish(). - * - * See also #PSA_AEAD_TAG_MAX_SIZE. - * - * \param key_type The type of the AEAD key. - * \param key_bits The size of the AEAD key in bits. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return The tag length for the specified algorithm and key. - * If the AEAD algorithm does not have an identified - * tag that can be distinguished from the rest of - * the ciphertext, return 0. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_TAG_LENGTH(key_type, key_bits, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - ((void) (key_bits), 0u)) - -/** The maximum tag size for all supported AEAD algorithms, in bytes. - * - * See also #PSA_AEAD_TAG_LENGTH(\p key_type, \p key_bits, \p alg). - */ -#define PSA_AEAD_TAG_MAX_SIZE 16u - -/* The maximum size of an RSA key on this implementation, in bits. - * This is a vendor-specific macro. - * - * Mbed TLS does not set a hard limit on the size of RSA keys: any key - * whose parameters fit in a bignum is accepted. However large keys can - * induce a large memory usage and long computation times. Unlike other - * auxiliary macros in this file and in crypto.h, which reflect how the - * library is configured, this macro defines how the library is - * configured. This implementation refuses to import or generate an - * RSA key whose size is larger than the value defined here. - * - * Note that an implementation may set different size limits for different - * operations, and does not need to accept all key sizes up to the limit. */ -#define PSA_VENDOR_RSA_MAX_KEY_BITS 4096u - -/* The minimum size of an RSA key on this implementation, in bits. - * This is a vendor-specific macro. - * - * Limits RSA key generation to a minimum due to avoid accidental misuse. - * This value cannot be less than 128 bits. - */ -#if defined(MBEDTLS_RSA_GEN_KEY_MIN_BITS) -#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS MBEDTLS_RSA_GEN_KEY_MIN_BITS -#else -#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS 1024 -#endif - -/* The maximum size of an DH key on this implementation, in bits. - * This is a vendor-specific macro.*/ -#if defined(PSA_WANT_DH_RFC7919_8192) -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 8192u -#elif defined(PSA_WANT_DH_RFC7919_6144) -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 6144u -#elif defined(PSA_WANT_DH_RFC7919_4096) -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 4096u -#elif defined(PSA_WANT_DH_RFC7919_3072) -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 3072u -#elif defined(PSA_WANT_DH_RFC7919_2048) -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 2048u -#else -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 0u -#endif - -/* The maximum size of an ECC key on this implementation, in bits. - * This is a vendor-specific macro. */ -#if defined(PSA_WANT_ECC_SECP_R1_521) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 521u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 512u -#elif defined(PSA_WANT_ECC_MONTGOMERY_448) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 448u -#elif defined(PSA_WANT_ECC_SECP_R1_384) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u -#elif defined(PSA_WANT_ECC_SECP_R1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_SECP_K1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_MONTGOMERY_255) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 255u -#elif defined(PSA_WANT_ECC_SECP_R1_224) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u -#elif defined(PSA_WANT_ECC_SECP_K1_224) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u -#elif defined(PSA_WANT_ECC_SECP_R1_192) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u -#elif defined(PSA_WANT_ECC_SECP_K1_192) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u -#else -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 0u -#endif - -/** This macro returns the maximum supported length of the PSK for the - * TLS-1.2 PSK-to-MS key derivation - * (#PSA_ALG_TLS12_PSK_TO_MS(\c hash_alg)). - * - * The maximum supported length does not depend on the chosen hash algorithm. - * - * Quoting RFC 4279, Sect 5.3: - * TLS implementations supporting these ciphersuites MUST support - * arbitrary PSK identities up to 128 octets in length, and arbitrary - * PSKs up to 64 octets in length. Supporting longer identities and - * keys is RECOMMENDED. - * - * Therefore, no implementation should define a value smaller than 64 - * for #PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE. - */ -#define PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE 128u - -/* The expected size of input passed to psa_tls12_ecjpake_to_pms_input, - * which is expected to work with P-256 curve only. */ -#define PSA_TLS12_ECJPAKE_TO_PMS_INPUT_SIZE 65u - -/* The size of a serialized K.X coordinate to be used in - * psa_tls12_ecjpake_to_pms_input. This function only accepts the P-256 - * curve. */ -#define PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE 32u - -/* The maximum number of iterations for PBKDF2 on this implementation, in bits. - * This is a vendor-specific macro. This can be configured if necessary */ -#define PSA_VENDOR_PBKDF2_MAX_ITERATIONS 0xffffffffU - -/** The maximum size of a block cipher. */ -#define PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE 16u - -/** The size of the output of psa_mac_sign_finish(), in bytes. - * - * This is also the MAC size that psa_mac_verify_finish() expects. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type The type of the MAC key. - * \param key_bits The size of the MAC key in bits. - * \param alg A MAC algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_MAC(\p alg) is true). - * - * \return The MAC size for the specified algorithm with - * the specified key parameters. - * \return 0 if the MAC algorithm is not recognized. - * \return Either 0 or the correct size for a MAC algorithm that - * the implementation recognizes, but does not support. - * \return Unspecified if the key parameters are not consistent - * with the algorithm. - */ -#define PSA_MAC_LENGTH(key_type, key_bits, alg) \ - ((alg) & PSA_ALG_MAC_TRUNCATION_MASK ? PSA_MAC_TRUNCATED_LENGTH(alg) : \ - PSA_ALG_IS_HMAC(alg) ? PSA_HASH_LENGTH(PSA_ALG_HMAC_GET_HASH(alg)) : \ - PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - ((void) (key_type), (void) (key_bits), 0u)) - -/** The maximum size of the output of psa_aead_encrypt(), in bytes. - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_aead_encrypt() will not fail due to an - * insufficient buffer size. Depending on the algorithm, the actual size of - * the ciphertext may be smaller. - * - * See also #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param plaintext_length Size of the plaintext in bytes. - * - * \return The AEAD ciphertext size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_ENCRYPT_OUTPUT_SIZE(key_type, alg, plaintext_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - (plaintext_length) + PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_encrypt(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the ciphertext buffer is at least this large, it is guaranteed - * that psa_aead_encrypt() will not fail due to an insufficient buffer size. - * - * \note This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * See also #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, - * \p plaintext_length). - * - * \param plaintext_length Size of the plaintext in bytes. - * - * \return A sufficient output buffer size for any of the - * supported key types and AEAD algorithms. - * - */ -#define PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(plaintext_length) \ - ((plaintext_length) + PSA_AEAD_TAG_MAX_SIZE) - - -/** The maximum size of the output of psa_aead_decrypt(), in bytes. - * - * If the size of the plaintext buffer is at least this large, it is - * guaranteed that psa_aead_decrypt() will not fail due to an - * insufficient buffer size. Depending on the algorithm, the actual size of - * the plaintext may be smaller. - * - * See also #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param ciphertext_length Size of the plaintext in bytes. - * - * \return The AEAD ciphertext size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_DECRYPT_OUTPUT_SIZE(key_type, alg, ciphertext_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - (ciphertext_length) > PSA_ALG_AEAD_GET_TAG_LENGTH(alg) ? \ - (ciphertext_length) - PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_decrypt(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the plaintext buffer is at least this large, it is guaranteed - * that psa_aead_decrypt() will not fail due to an insufficient buffer size. - * - * \note This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * See also #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, - * \p ciphertext_length). - * - * \param ciphertext_length Size of the ciphertext in bytes. - * - * \return A sufficient output buffer size for any of the - * supported key types and AEAD algorithms. - * - */ -#define PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(ciphertext_length) \ - (ciphertext_length) - -/** The default nonce size for an AEAD algorithm, in bytes. - * - * This macro can be used to allocate a buffer of sufficient size to - * store the nonce output from #psa_aead_generate_nonce(). - * - * See also #PSA_AEAD_NONCE_MAX_SIZE. - * - * \note This is not the maximum size of nonce supported as input to - * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), - * just the default size that is generated by #psa_aead_generate_nonce(). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with - * algorithm \p alg. - * - * \param alg An AEAD algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return The default nonce size for the specified key type and algorithm. - * If the key type or AEAD algorithm is not recognized, - * or the parameters are incompatible, return 0. - */ -#define PSA_AEAD_NONCE_LENGTH(key_type, alg) \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) == 16 ? \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CCM) ? 13u : \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_GCM) ? 12u : \ - 0u : \ - (key_type) == PSA_KEY_TYPE_CHACHA20 && \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CHACHA20_POLY1305) ? 12u : \ - 0u) - -/** The maximum default nonce size among all supported pairs of key types and - * AEAD algorithms, in bytes. - * - * This is equal to or greater than any value that #PSA_AEAD_NONCE_LENGTH() - * may return. - * - * \note This is not the maximum size of nonce supported as input to - * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), - * just the largest size that may be generated by - * #psa_aead_generate_nonce(). - */ -#define PSA_AEAD_NONCE_MAX_SIZE 13u - -/** A sufficient output buffer size for psa_aead_update(). - * - * If the size of the output buffer is at least this large, it is - * guaranteed that psa_aead_update() will not fail due to an - * insufficient buffer size. The actual size of the output may be smaller - * in any given call. - * - * See also #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output buffer size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -/* For all the AEAD modes defined in this specification, it is possible - * to emit output without delay. However, hardware may not always be - * capable of this. So for modes based on a block cipher, allow the - * implementation to delay the output until it has a full block. */ -#define PSA_AEAD_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), (input_length)) : \ - (input_length) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_update(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_aead_update() will not fail due to an insufficient buffer size. - * - * See also #PSA_AEAD_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, (input_length))) - -/** A sufficient ciphertext buffer size for psa_aead_finish(). - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_aead_finish() will not fail due to an - * insufficient ciphertext buffer size. The actual size of the output may - * be smaller in any given call. - * - * See also #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE. - * - * \param key_type A symmetric key type that is - compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return A sufficient ciphertext buffer size for the - * specified algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_FINISH_OUTPUT_SIZE(key_type, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) - -/** A sufficient ciphertext buffer size for psa_aead_finish(), for any of the - * supported key types and AEAD algorithms. - * - * See also #PSA_AEAD_FINISH_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_AEAD_FINISH_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -/** A sufficient plaintext buffer size for psa_aead_verify(). - * - * If the size of the plaintext buffer is at least this large, it is - * guaranteed that psa_aead_verify() will not fail due to an - * insufficient plaintext buffer size. The actual size of the output may - * be smaller in any given call. - * - * See also #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return A sufficient plaintext buffer size for the - * specified algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_VERIFY_OUTPUT_SIZE(key_type, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) - -/** A sufficient plaintext buffer size for psa_aead_verify(), for any of the - * supported key types and AEAD algorithms. - * - * See also #PSA_AEAD_VERIFY_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -#define PSA_RSA_MINIMUM_PADDING_SIZE(alg) \ - (PSA_ALG_IS_RSA_OAEP(alg) ? \ - 2u * PSA_HASH_LENGTH(PSA_ALG_RSA_OAEP_GET_HASH(alg)) + 1u : \ - 11u /*PKCS#1v1.5*/) - -/** - * \brief ECDSA signature size for a given curve bit size - * - * \param curve_bits Curve size in bits. - * \return Signature size in bytes. - * - * \note This macro returns a compile-time constant if its argument is one. - */ -#define PSA_ECDSA_SIGNATURE_SIZE(curve_bits) \ - (PSA_BITS_TO_BYTES(curve_bits) * 2u) - -/** Sufficient signature buffer size for psa_sign_hash(). - * - * This macro returns a sufficient buffer size for a signature using a key - * of the specified type and size, with the specified algorithm. - * Note that the actual size of the signature may be smaller - * (some algorithms produce a variable-size signature). - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The signature algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_sign_hash() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_SIGN_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ - PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_ECDSA_SIGNATURE_SIZE(key_bits) : \ - ((void) alg, 0u)) - -#define PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE \ - PSA_ECDSA_SIGNATURE_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) - -/** \def PSA_SIGNATURE_MAX_SIZE - * - * Maximum size of an asymmetric signature. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a signature in bytes. - */ -#define PSA_SIGNATURE_MAX_SIZE 1 - -#if (defined(PSA_WANT_ALG_ECDSA) || defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA)) && \ - (PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE > PSA_SIGNATURE_MAX_SIZE) -#undef PSA_SIGNATURE_MAX_SIZE -#define PSA_SIGNATURE_MAX_SIZE PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE -#endif -#if (defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) || defined(PSA_WANT_ALG_RSA_PSS)) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) > PSA_SIGNATURE_MAX_SIZE) -#undef PSA_SIGNATURE_MAX_SIZE -#define PSA_SIGNATURE_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif - -/** Sufficient output buffer size for psa_asymmetric_encrypt(). - * - * This macro returns a sufficient buffer size for a ciphertext produced using - * a key of the specified type and size, with the specified algorithm. - * Note that the actual size of the ciphertext may be smaller, depending - * on the algorithm. - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The asymmetric encryption algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_asymmetric_encrypt() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? \ - ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ - 0u) - -/** A sufficient output buffer size for psa_asymmetric_encrypt(), for any - * supported asymmetric encryption. - * - * See also #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). - */ -/* This macro assumes that RSA is the only supported asymmetric encryption. */ -#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_MAX_SIZE \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) - -/** Sufficient output buffer size for psa_asymmetric_decrypt(). - * - * This macro returns a sufficient buffer size for a plaintext produced using - * a key of the specified type and size, with the specified algorithm. - * Note that the actual size of the plaintext may be smaller, depending - * on the algorithm. - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The asymmetric encryption algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_asymmetric_decrypt() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? \ - PSA_BITS_TO_BYTES(key_bits) - PSA_RSA_MINIMUM_PADDING_SIZE(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_asymmetric_decrypt(), for any - * supported asymmetric decryption. - * - * This macro assumes that RSA is the only supported asymmetric encryption. - * - * See also #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). - */ -#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_MAX_SIZE \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) - -/* Maximum size of the ASN.1 encoding of an INTEGER with the specified - * number of bits. - * - * This definition assumes that bits <= 2^19 - 9 so that the length field - * is at most 3 bytes. The length of the encoding is the length of the - * bit string padded to a whole number of bytes plus: - * - 1 type byte; - * - 1 to 3 length bytes; - * - 0 to 1 bytes of leading 0 due to the sign bit. - */ -#define PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(bits) \ - ((bits) / 8u + 5u) - -/* Maximum size of the export encoding of an RSA public key. - * Assumes that the public exponent is less than 2^32. - * - * RSAPublicKey ::= SEQUENCE { - * modulus INTEGER, -- n - * publicExponent INTEGER } -- e - * - * - 4 bytes of SEQUENCE overhead; - * - n : INTEGER; - * - 7 bytes for the public exponent. - */ -#define PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) + 11u) - -/* Maximum size of the export encoding of an RSA key pair. - * Assumes that the public exponent is less than 2^32 and that the size - * difference between the two primes is at most 1 bit. - * - * RSAPrivateKey ::= SEQUENCE { - * version Version, -- 0 - * modulus INTEGER, -- N-bit - * publicExponent INTEGER, -- 32-bit - * privateExponent INTEGER, -- N-bit - * prime1 INTEGER, -- N/2-bit - * prime2 INTEGER, -- N/2-bit - * exponent1 INTEGER, -- N/2-bit - * exponent2 INTEGER, -- N/2-bit - * coefficient INTEGER, -- N/2-bit - * } - * - * - 4 bytes of SEQUENCE overhead; - * - 3 bytes of version; - * - 7 half-size INTEGERs plus 2 full-size INTEGERs, - * overapproximated as 9 half-size INTEGERS; - * - 7 bytes for the public exponent. - */ -#define PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) \ - (9u * PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE((key_bits) / 2u + 1u) + 14u) - -/* Maximum size of the export encoding of a DSA public key. - * - * SubjectPublicKeyInfo ::= SEQUENCE { - * algorithm AlgorithmIdentifier, - * subjectPublicKey BIT STRING } -- contains DSAPublicKey - * AlgorithmIdentifier ::= SEQUENCE { - * algorithm OBJECT IDENTIFIER, - * parameters Dss-Params } -- SEQUENCE of 3 INTEGERs - * DSAPublicKey ::= INTEGER -- public key, Y - * - * - 3 * 4 bytes of SEQUENCE overhead; - * - 1 + 1 + 7 bytes of algorithm (DSA OID); - * - 4 bytes of BIT STRING overhead; - * - 3 full-size INTEGERs (p, g, y); - * - 1 + 1 + 32 bytes for 1 sub-size INTEGER (q <= 256 bits). - */ -#define PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 59u) - -/* Maximum size of the export encoding of a DSA key pair. - * - * DSAPrivateKey ::= SEQUENCE { - * version Version, -- 0 - * prime INTEGER, -- p - * subprime INTEGER, -- q - * generator INTEGER, -- g - * public INTEGER, -- y - * private INTEGER, -- x - * } - * - * - 4 bytes of SEQUENCE overhead; - * - 3 bytes of version; - * - 3 full-size INTEGERs (p, g, y); - * - 2 * (1 + 1 + 32) bytes for 2 sub-size INTEGERs (q, x <= 256 bits). - */ -#define PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 75u) - -/* Maximum size of the export encoding of an ECC public key. - * - * The representation of an ECC public key is: - * - The byte 0x04; - * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; - * - `y_P` as a `ceiling(m/8)`-byte string, big-endian; - * - where m is the bit size associated with the curve. - * - * - 1 byte + 2 * point size. - */ -#define PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (2u * PSA_BITS_TO_BYTES(key_bits) + 1u) - -/* Maximum size of the export encoding of an ECC key pair. - * - * An ECC key pair is represented by the secret value. - */ -#define PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/* Maximum size of the export encoding of an DH key pair. - * - * An DH key pair is represented by the secret value. - */ -#define PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/* Maximum size of the export encoding of an DH public key. - */ -#define PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/** Sufficient output buffer size for psa_export_key() or - * psa_export_public_key(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * The following code illustrates how to allocate enough memory to export - * a key by querying the key type and size at runtime. - * \code{c} - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * psa_status_t status; - * status = psa_get_key_attributes(key, &attributes); - * if (status != PSA_SUCCESS) handle_error(...); - * psa_key_type_t key_type = psa_get_key_type(&attributes); - * size_t key_bits = psa_get_key_bits(&attributes); - * size_t buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits); - * psa_reset_key_attributes(&attributes); - * uint8_t *buffer = malloc(buffer_size); - * if (buffer == NULL) handle_error(...); - * size_t buffer_length; - * status = psa_export_key(key, buffer, buffer_size, &buffer_length); - * if (status != PSA_SUCCESS) handle_error(...); - * \endcode - * - * \param key_type A supported key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_export_key() or psa_export_public_key() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the return value is unspecified. - */ -#define PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits) \ - (PSA_KEY_TYPE_IS_UNSTRUCTURED(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - (key_type) == PSA_KEY_TYPE_RSA_KEY_PAIR ? PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_DSA_KEY_PAIR ? PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY ? PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) ? PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - 0u) - -/** Sufficient output buffer size for psa_export_public_key(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * The following code illustrates how to allocate enough memory to export - * a public key by querying the key type and size at runtime. - * \code{c} - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * psa_status_t status; - * status = psa_get_key_attributes(key, &attributes); - * if (status != PSA_SUCCESS) handle_error(...); - * psa_key_type_t key_type = psa_get_key_type(&attributes); - * size_t key_bits = psa_get_key_bits(&attributes); - * size_t buffer_size = PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits); - * psa_reset_key_attributes(&attributes); - * uint8_t *buffer = malloc(buffer_size); - * if (buffer == NULL) handle_error(...); - * size_t buffer_length; - * status = psa_export_public_key(key, buffer, buffer_size, &buffer_length); - * if (status != PSA_SUCCESS) handle_error(...); - * \endcode - * - * \param key_type A public key or key pair key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_export_public_key() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not - * supported, return either a sensible size or 0. - * If the parameters are not valid, - * the return value is unspecified. - * - * If the parameters are valid and supported, - * return the same result as - * #PSA_EXPORT_KEY_OUTPUT_SIZE( - * \p #PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\p key_type), - * \p key_bits). - */ -#define PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - 0u) - -/** Sufficient buffer size for exporting any asymmetric key pair. - * - * This macro expands to a compile-time constant integer. This value is - * a sufficient buffer size when calling psa_export_key() to export any - * asymmetric key pair, regardless of the exact key type and key size. - * - * See also #PSA_EXPORT_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE 1 - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** Sufficient buffer size for exporting any asymmetric public key. - * - * This macro expands to a compile-time constant integer. This value is - * a sufficient buffer size when calling psa_export_key() or - * psa_export_public_key() to export any asymmetric public key, - * regardless of the exact key type and key size. - * - * See also #PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE 1 - -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** Sufficient output buffer size for psa_raw_key_agreement(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE. - * - * \param key_type A supported key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_raw_key_agreement() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that - * is not supported, return either a sensible size or 0. - * If the parameters are not valid, - * the return value is unspecified. - */ -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(key_type, key_bits) \ - ((PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) || \ - PSA_KEY_TYPE_IS_DH_KEY_PAIR(key_type)) ? PSA_BITS_TO_BYTES(key_bits) : 0u) - -/** Maximum size of the output from psa_raw_key_agreement(). - * - * This macro expands to a compile-time constant integer. This value is the - * maximum size of the output any raw key agreement algorithm, in bytes. - * - * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE 1 - -#if defined(PSA_WANT_ALG_ECDH) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) -#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_ALG_FFDH) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) -#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** The default IV size for a cipher algorithm, in bytes. - * - * The IV that is generated as part of a call to #psa_cipher_encrypt() is always - * the default IV length for the algorithm. - * - * This macro can be used to allocate a buffer of sufficient size to - * store the IV output from #psa_cipher_generate_iv() when using - * a multi-part cipher operation. - * - * See also #PSA_CIPHER_IV_MAX_SIZE. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with algorithm \p alg. - * - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \return The default IV size for the specified key type and algorithm. - * If the algorithm does not use an IV, return 0. - * If the key type or cipher algorithm is not recognized, - * or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_IV_LENGTH(key_type, alg) \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) > 1 && \ - ((alg) == PSA_ALG_CTR || \ - (alg) == PSA_ALG_CFB || \ - (alg) == PSA_ALG_OFB || \ - (alg) == PSA_ALG_XTS || \ - (alg) == PSA_ALG_CBC_NO_PADDING || \ - (alg) == PSA_ALG_CBC_PKCS7) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - (key_type) == PSA_KEY_TYPE_CHACHA20 && \ - (alg) == PSA_ALG_STREAM_CIPHER ? 12u : \ - (alg) == PSA_ALG_CCM_STAR_NO_TAG ? 13u : \ - 0u) - -/** The maximum IV size for all supported cipher algorithms, in bytes. - * - * See also #PSA_CIPHER_IV_LENGTH(). - */ -#define PSA_CIPHER_IV_MAX_SIZE 16u - -/** The maximum size of the output of psa_cipher_encrypt(), in bytes. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. - * Depending on the algorithm, the actual size of the output might be smaller. - * - * See also #PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(\p input_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ - (alg == PSA_ALG_CBC_PKCS7 ? \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ - (input_length) + 1u) + \ - PSA_CIPHER_IV_LENGTH((key_type), (alg)) : 0u) : \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (input_length) + PSA_CIPHER_IV_LENGTH((key_type), (alg)) : \ - 0u)) - -/** A sufficient output buffer size for psa_cipher_encrypt(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - * - */ -#define PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, \ - (input_length) + 1u) + \ - PSA_CIPHER_IV_MAX_SIZE) - -/** The maximum size of the output of psa_cipher_decrypt(), in bytes. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. - * Depending on the algorithm, the actual size of the output might be smaller. - * - * See also #PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(\p input_length). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_CIPHER_DECRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_ALG_IS_CIPHER(alg) && \ - ((key_type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ - (input_length) : \ - 0u) - -/** A sufficient output buffer size for psa_cipher_decrypt(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(input_length) \ - (input_length) - -/** A sufficient output buffer size for psa_cipher_update(). - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_update() will not fail due to an insufficient buffer size. - * The actual size of the output might be smaller in any given call. - * - * See also #PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(\p input_length). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ - (((alg) == PSA_ALG_CBC_PKCS7 || \ - (alg) == PSA_ALG_CBC_NO_PADDING || \ - (alg) == PSA_ALG_ECB_NO_PADDING) ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ - input_length) : \ - (input_length)) : 0u) : \ - 0u) - -/** A sufficient output buffer size for psa_cipher_update(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_update() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, input_length)) - -/** A sufficient ciphertext buffer size for psa_cipher_finish(). - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_cipher_finish() will not fail due to an insufficient - * ciphertext buffer size. The actual size of the output might be smaller in - * any given call. - * - * See also #PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE(). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_FINISH_OUTPUT_SIZE(key_type, alg) \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (alg == PSA_ALG_CBC_PKCS7 ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) : \ - 0u) - -/** A sufficient ciphertext buffer size for psa_cipher_finish(), for any of the - * supported key types and cipher algorithms. - * - * See also #PSA_CIPHER_FINISH_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE \ - (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -#endif /* PSA_CRYPTO_SIZES_H */ diff --git a/interface/include/psa/crypto_struct.h b/interface/include/psa/crypto_struct.h deleted file mode 100644 index 3913551aa..000000000 --- a/interface/include/psa/crypto_struct.h +++ /dev/null @@ -1,501 +0,0 @@ -/** - * \file psa/crypto_struct.h - * - * \brief PSA cryptography module: Mbed TLS structured type implementations - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains the definitions of some data structures with - * implementation-specific definitions. - * - * In implementations with isolation between the application and the - * cryptography module, it is expected that the front-end and the back-end - * would have different versions of this file. - * - *

Design notes about multipart operation structures

- * - * For multipart operations without driver delegation support, each multipart - * operation structure contains a `psa_algorithm_t alg` field which indicates - * which specific algorithm the structure is for. When the structure is not in - * use, `alg` is 0. Most of the structure consists of a union which is - * discriminated by `alg`. - * - * For multipart operations with driver delegation support, each multipart - * operation structure contains an `unsigned int id` field indicating which - * driver got assigned to do the operation. When the structure is not in use, - * 'id' is 0. The structure contains also a driver context which is the union - * of the contexts of all drivers able to handle the type of multipart - * operation. - * - * Note that when `alg` or `id` is 0, the content of other fields is undefined. - * In particular, it is not guaranteed that a freshly-initialized structure - * is all-zero: we initialize structures to something like `{0, 0}`, which - * is only guaranteed to initializes the first member of the union; - * GCC and Clang initialize the whole structure to 0 (at the time of writing), - * but MSVC and CompCert don't. - * - * In Mbed TLS, multipart operation structures live independently from - * the key. This allows Mbed TLS to free the key objects when destroying - * a key slot. If a multipart operation needs to remember the key after - * the setup function returns, the operation structure needs to contain a - * copy of the key. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_STRUCT_H -#define PSA_CRYPTO_STRUCT_H -#include "mbedtls/private_access.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Include the build-time configuration information header. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * TF-PSA-Crypto repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -/* Include the context definition for the compiled-in drivers for the primitive - * algorithms. */ -#include "psa/crypto_driver_contexts_primitives.h" - -struct psa_hash_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_driver_wrappers.h. - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. the driver context is not active, in use). */ - unsigned int MBEDTLS_PRIVATE(id); - psa_driver_hash_context_t MBEDTLS_PRIVATE(ctx); -#endif -}; -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_HASH_OPERATION_INIT { 0 } -#else -#define PSA_HASH_OPERATION_INIT { 0, { 0 } } -#endif -static inline struct psa_hash_operation_s psa_hash_operation_init(void) -{ - const struct psa_hash_operation_s v = PSA_HASH_OPERATION_INIT; - return v; -} - -struct psa_cipher_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - unsigned int MBEDTLS_PRIVATE(iv_required) : 1; - unsigned int MBEDTLS_PRIVATE(iv_set) : 1; - - uint8_t MBEDTLS_PRIVATE(default_iv_length); - - psa_driver_cipher_context_t MBEDTLS_PRIVATE(ctx); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_CIPHER_OPERATION_INIT { 0 } -#else -#define PSA_CIPHER_OPERATION_INIT { 0, 0, 0, 0, { 0 } } -#endif -static inline struct psa_cipher_operation_s psa_cipher_operation_init(void) -{ - const struct psa_cipher_operation_s v = PSA_CIPHER_OPERATION_INIT; - return v; -} - -/* Include the context definition for the compiled-in drivers for the composite - * algorithms. */ -#include "psa/crypto_driver_contexts_composites.h" - -struct psa_mac_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - uint8_t MBEDTLS_PRIVATE(mac_size); - unsigned int MBEDTLS_PRIVATE(is_sign) : 1; - psa_driver_mac_context_t MBEDTLS_PRIVATE(ctx); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_MAC_OPERATION_INIT { 0 } -#else -#define PSA_MAC_OPERATION_INIT { 0, 0, 0, { 0 } } -#endif -static inline struct psa_mac_operation_s psa_mac_operation_init(void) -{ - const struct psa_mac_operation_s v = PSA_MAC_OPERATION_INIT; - return v; -} - -struct psa_aead_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_algorithm_t MBEDTLS_PRIVATE(alg); - psa_key_type_t MBEDTLS_PRIVATE(key_type); - - size_t MBEDTLS_PRIVATE(ad_remaining); - size_t MBEDTLS_PRIVATE(body_remaining); - - unsigned int MBEDTLS_PRIVATE(nonce_set) : 1; - unsigned int MBEDTLS_PRIVATE(lengths_set) : 1; - unsigned int MBEDTLS_PRIVATE(ad_started) : 1; - unsigned int MBEDTLS_PRIVATE(body_started) : 1; - unsigned int MBEDTLS_PRIVATE(is_encrypt) : 1; - - psa_driver_aead_context_t MBEDTLS_PRIVATE(ctx); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_AEAD_OPERATION_INIT { 0 } -#else -#define PSA_AEAD_OPERATION_INIT { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 } } -#endif -static inline struct psa_aead_operation_s psa_aead_operation_init(void) -{ - const struct psa_aead_operation_s v = PSA_AEAD_OPERATION_INIT; - return v; -} - -/* Include the context definition for the compiled-in drivers for the key - * derivation algorithms. */ -#include "psa/crypto_driver_contexts_key_derivation.h" - -struct psa_key_derivation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - psa_algorithm_t MBEDTLS_PRIVATE(alg); - unsigned int MBEDTLS_PRIVATE(can_output_key) : 1; - size_t MBEDTLS_PRIVATE(capacity); - psa_driver_key_derivation_context_t MBEDTLS_PRIVATE(ctx); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_KEY_DERIVATION_OPERATION_INIT { 0 } -#else -/* This only zeroes out the first byte in the union, the rest is unspecified. */ -#define PSA_KEY_DERIVATION_OPERATION_INIT { 0, 0, 0, { 0 } } -#endif -static inline struct psa_key_derivation_s psa_key_derivation_operation_init( - void) -{ - const struct psa_key_derivation_s v = PSA_KEY_DERIVATION_OPERATION_INIT; - return v; -} - -struct psa_key_production_parameters_s { - /* Future versions may add other fields in this structure. */ - uint32_t flags; - uint8_t data[]; -}; - -/** The default production parameters for key generation or key derivation. - * - * Calling psa_generate_key_ext() or psa_key_derivation_output_key_ext() - * with `params=PSA_KEY_PRODUCTION_PARAMETERS_INIT` and - * `params_data_length == 0` is equivalent to - * calling psa_generate_key() or psa_key_derivation_output_key() - * respectively. - */ -#define PSA_KEY_PRODUCTION_PARAMETERS_INIT { 0 } - -struct psa_key_policy_s { - psa_key_usage_t MBEDTLS_PRIVATE(usage); - psa_algorithm_t MBEDTLS_PRIVATE(alg); - psa_algorithm_t MBEDTLS_PRIVATE(alg2); -}; -typedef struct psa_key_policy_s psa_key_policy_t; - -#define PSA_KEY_POLICY_INIT { 0, 0, 0 } -static inline struct psa_key_policy_s psa_key_policy_init(void) -{ - const struct psa_key_policy_s v = PSA_KEY_POLICY_INIT; - return v; -} - -/* The type used internally for key sizes. - * Public interfaces use size_t, but internally we use a smaller type. */ -typedef uint16_t psa_key_bits_t; -/* The maximum value of the type used to represent bit-sizes. - * This is used to mark an invalid key size. */ -#define PSA_KEY_BITS_TOO_LARGE ((psa_key_bits_t) -1) -/* The maximum size of a key in bits. - * Currently defined as the maximum that can be represented, rounded down - * to a whole number of bytes. - * This is an uncast value so that it can be used in preprocessor - * conditionals. */ -#define PSA_MAX_KEY_BITS 0xfff8 - -struct psa_key_attributes_s { -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - psa_key_slot_number_t MBEDTLS_PRIVATE(slot_number); - int MBEDTLS_PRIVATE(has_slot_number); -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - psa_key_type_t MBEDTLS_PRIVATE(type); - psa_key_bits_t MBEDTLS_PRIVATE(bits); - psa_key_lifetime_t MBEDTLS_PRIVATE(lifetime); - psa_key_policy_t MBEDTLS_PRIVATE(policy); - /* This type has a different layout in the client view wrt the - * service view of the key id, i.e. in service view usually is - * expected to have MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER defined - * thus adding an owner field to the standard psa_key_id_t. For - * implementations with client/service separation, this means the - * object will be marshalled through a transport channel and - * interpreted differently at each side of the transport. Placing - * it at the end of structures allows to interpret the structure - * at the client without reorganizing the memory layout of the - * struct - */ - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(id); -}; - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -#define PSA_KEY_ATTRIBUTES_MAYBE_SLOT_NUMBER 0, 0, -#else -#define PSA_KEY_ATTRIBUTES_MAYBE_SLOT_NUMBER -#endif -#define PSA_KEY_ATTRIBUTES_INIT { PSA_KEY_ATTRIBUTES_MAYBE_SLOT_NUMBER \ - PSA_KEY_TYPE_NONE, 0, \ - PSA_KEY_LIFETIME_VOLATILE, \ - PSA_KEY_POLICY_INIT, \ - MBEDTLS_SVC_KEY_ID_INIT } - -static inline struct psa_key_attributes_s psa_key_attributes_init(void) -{ - const struct psa_key_attributes_s v = PSA_KEY_ATTRIBUTES_INIT; - return v; -} - -static inline void psa_set_key_id(psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t key) -{ - psa_key_lifetime_t lifetime = attributes->MBEDTLS_PRIVATE(lifetime); - - attributes->MBEDTLS_PRIVATE(id) = key; - - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { - attributes->MBEDTLS_PRIVATE(lifetime) = - PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( - PSA_KEY_LIFETIME_PERSISTENT, - PSA_KEY_LIFETIME_GET_LOCATION(lifetime)); - } -} - -static inline mbedtls_svc_key_id_t psa_get_key_id( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(id); -} - -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER -static inline void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, - mbedtls_key_owner_id_t owner) -{ - attributes->MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = owner; -} -#endif - -static inline void psa_set_key_lifetime(psa_key_attributes_t *attributes, - psa_key_lifetime_t lifetime) -{ - attributes->MBEDTLS_PRIVATE(lifetime) = lifetime; - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER - attributes->MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = 0; -#else - attributes->MBEDTLS_PRIVATE(id) = 0; -#endif - } -} - -static inline psa_key_lifetime_t psa_get_key_lifetime( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(lifetime); -} - -static inline void psa_extend_key_usage_flags(psa_key_usage_t *usage_flags) -{ - if (*usage_flags & PSA_KEY_USAGE_SIGN_HASH) { - *usage_flags |= PSA_KEY_USAGE_SIGN_MESSAGE; - } - - if (*usage_flags & PSA_KEY_USAGE_VERIFY_HASH) { - *usage_flags |= PSA_KEY_USAGE_VERIFY_MESSAGE; - } -} - -static inline void psa_set_key_usage_flags(psa_key_attributes_t *attributes, - psa_key_usage_t usage_flags) -{ - psa_extend_key_usage_flags(&usage_flags); - attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage) = usage_flags; -} - -static inline psa_key_usage_t psa_get_key_usage_flags( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage); -} - -static inline void psa_set_key_algorithm(psa_key_attributes_t *attributes, - psa_algorithm_t alg) -{ - attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg) = alg; -} - -static inline psa_algorithm_t psa_get_key_algorithm( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg); -} - -static inline void psa_set_key_type(psa_key_attributes_t *attributes, - psa_key_type_t type) -{ - attributes->MBEDTLS_PRIVATE(type) = type; -} - -static inline psa_key_type_t psa_get_key_type( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(type); -} - -static inline void psa_set_key_bits(psa_key_attributes_t *attributes, - size_t bits) -{ - if (bits > PSA_MAX_KEY_BITS) { - attributes->MBEDTLS_PRIVATE(bits) = PSA_KEY_BITS_TOO_LARGE; - } else { - attributes->MBEDTLS_PRIVATE(bits) = (psa_key_bits_t) bits; - } -} - -static inline size_t psa_get_key_bits( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(bits); -} - -/** - * \brief The context for PSA interruptible hash signing. - */ -struct psa_sign_hash_interruptible_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_driver_sign_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); - - unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; - - uint32_t MBEDTLS_PRIVATE(num_ops); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } -#else -#define PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } -#endif - -static inline struct psa_sign_hash_interruptible_operation_s -psa_sign_hash_interruptible_operation_init(void) -{ - const struct psa_sign_hash_interruptible_operation_s v = - PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; - - return v; -} - -/** - * \brief The context for PSA interruptible hash verification. - */ -struct psa_verify_hash_interruptible_operation_s { -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_psa_client_handle_t handle; -#else - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_driver_verify_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); - - unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; - - uint32_t MBEDTLS_PRIVATE(num_ops); -#endif -}; - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) && !defined(MBEDTLS_PSA_CRYPTO_C) -#define PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } -#else -#define PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } -#endif - -static inline struct psa_verify_hash_interruptible_operation_s -psa_verify_hash_interruptible_operation_init(void) -{ - const struct psa_verify_hash_interruptible_operation_s v = - PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; - - return v; -} - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_STRUCT_H */ diff --git a/interface/include/psa/crypto_types.h b/interface/include/psa/crypto_types.h deleted file mode 100644 index c21bad86c..000000000 --- a/interface/include/psa/crypto_types.h +++ /dev/null @@ -1,484 +0,0 @@ -/** - * \file psa/crypto_types.h - * - * \brief PSA cryptography module: type aliases. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. Drivers must include the appropriate driver - * header file. - * - * This file contains portable definitions of integral types for properties - * of cryptographic keys, designations of cryptographic algorithms, and - * error codes returned by the library. - * - * This header file does not declare any function. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_TYPES_H -#define PSA_CRYPTO_TYPES_H - -/* - * Include the build-time configuration information header. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * TF-PSA-Crypto repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -/* Define the MBEDTLS_PRIVATE macro. */ -#include "mbedtls/private_access.h" - -#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) -#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE -#else -#include "crypto_platform.h" -#endif - -#include - -/** \defgroup error Error codes - * @{ - */ - -/** - * \brief Function return status. - * - * This is either #PSA_SUCCESS (which is zero), indicating success, - * or a small negative value indicating that an error occurred. Errors are - * encoded as one of the \c PSA_ERROR_xxx values defined here. */ -/* If #PSA_SUCCESS is already defined, it means that #psa_status_t - * is also defined in an external header, so prevent its multiple - * definition. - */ -#ifndef PSA_SUCCESS -typedef int32_t psa_status_t; -#endif - -/**@}*/ - -/** \defgroup crypto_types Key and algorithm types - * @{ - */ - -/** \brief Encoding of a key type. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_TYPE_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint16_t psa_key_type_t; - -/** The type of PSA elliptic curve family identifiers. - * - * Values of this type are generally constructed by macros called - * `PSA_ECC_FAMILY_xxx`. - * - * The curve identifier is required to create an ECC key using the - * PSA_KEY_TYPE_ECC_KEY_PAIR() or PSA_KEY_TYPE_ECC_PUBLIC_KEY() - * macros. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional families must use an encoding in this range. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_ecc_family_t; - -/** The type of PSA Diffie-Hellman group family identifiers. - * - * Values of this type are generally constructed by macros called - * `PSA_DH_FAMILY_xxx`. - * - * The group identifier is required to create a Diffie-Hellman key using the - * PSA_KEY_TYPE_DH_KEY_PAIR() or PSA_KEY_TYPE_DH_PUBLIC_KEY() - * macros. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional families must use an encoding in this range. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_dh_family_t; - -/** \brief Encoding of a cryptographic algorithm. - * - * Values of this type are generally constructed by macros called - * `PSA_ALG_xxx`. - * - * For algorithms that can be applied to multiple key types, this type - * does not encode the key type. For example, for symmetric ciphers - * based on a block cipher, #psa_algorithm_t encodes the block cipher - * mode and the padding mode while the block cipher itself is encoded - * via #psa_key_type_t. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_algorithm_t; - -/**@}*/ - -/** \defgroup key_lifetimes Key lifetimes - * @{ - */ - -/** Encoding of key lifetimes. - * - * The lifetime of a key indicates where it is stored and what system actions - * may create and destroy it. - * - * Lifetime values have the following structure: - * - Bits 0-7 (#PSA_KEY_LIFETIME_GET_PERSISTENCE(\c lifetime)): - * persistence level. This value indicates what device management - * actions can cause it to be destroyed. In particular, it indicates - * whether the key is _volatile_ or _persistent_. - * See ::psa_key_persistence_t for more information. - * - Bits 8-31 (#PSA_KEY_LIFETIME_GET_LOCATION(\c lifetime)): - * location indicator. This value indicates which part of the system - * has access to the key material and can perform operations using the key. - * See ::psa_key_location_t for more information. - * - * Volatile keys are automatically destroyed when the application instance - * terminates or on a power reset of the device. Persistent keys are - * preserved until the application explicitly destroys them or until an - * integration-specific device management event occurs (for example, - * a factory reset). - * - * Persistent keys have a key identifier of type #mbedtls_svc_key_id_t. - * This identifier remains valid throughout the lifetime of the key, - * even if the application instance that created the key terminates. - * The application can call psa_open_key() to open a persistent key that - * it created previously. - * - * The default lifetime of a key is #PSA_KEY_LIFETIME_VOLATILE. The lifetime - * #PSA_KEY_LIFETIME_PERSISTENT is supported if persistent storage is - * available. Other lifetime values may be supported depending on the - * library configuration. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_LIFETIME_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_lifetime_t; - -/** Encoding of key persistence levels. - * - * What distinguishes different persistence levels is what device management - * events may cause keys to be destroyed. _Volatile_ keys are destroyed - * by a power reset. Persistent keys may be destroyed by events such as - * a transfer of ownership or a factory reset. What management events - * actually affect persistent keys at different levels is outside the - * scope of the PSA Cryptography specification. - * - * The PSA Cryptography specification defines the following values of - * persistence levels: - * - \c 0 = #PSA_KEY_PERSISTENCE_VOLATILE: volatile key. - * A volatile key is automatically destroyed by the implementation when - * the application instance terminates. In particular, a volatile key - * is automatically destroyed on a power reset of the device. - * - \c 1 = #PSA_KEY_PERSISTENCE_DEFAULT: - * persistent key with a default lifetime. - * - \c 2-254: currently not supported by Mbed TLS. - * - \c 255 = #PSA_KEY_PERSISTENCE_READ_ONLY: - * read-only or write-once key. - * A key with this persistence level cannot be destroyed. - * Mbed TLS does not currently offer a way to create such keys, but - * integrations of Mbed TLS can use it for built-in keys that the - * application cannot modify (for example, a hardware unique key (HUK)). - * - * \note Key persistence levels are 8-bit values. Key management - * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which - * encode the persistence as the lower 8 bits of a 32-bit value. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_key_persistence_t; - -/** Encoding of key location indicators. - * - * If an integration of Mbed TLS can make calls to external - * cryptoprocessors such as secure elements, the location of a key - * indicates which secure element performs the operations on the key. - * Depending on the design of the secure element, the key - * material may be stored either in the secure element, or - * in wrapped (encrypted) form alongside the key metadata in the - * primary local storage. - * - * The PSA Cryptography API specification defines the following values of - * location indicators: - * - \c 0: primary local storage. - * This location is always available. - * The primary local storage is typically the same storage area that - * contains the key metadata. - * - \c 1: primary secure element. - * Integrations of Mbed TLS should support this value if there is a secure - * element attached to the operating environment. - * As a guideline, secure elements may provide higher resistance against - * side channel and physical attacks than the primary local storage, but may - * have restrictions on supported key types, sizes, policies and operations - * and may have different performance characteristics. - * - \c 2-0x7fffff: other locations defined by a PSA specification. - * The PSA Cryptography API does not currently assign any meaning to these - * locations, but future versions of that specification or other PSA - * specifications may do so. - * - \c 0x800000-0xffffff: vendor-defined locations. - * No PSA specification will assign a meaning to locations in this range. - * - * \note Key location indicators are 24-bit values. Key management - * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which - * encode the location as the upper 24 bits of a 32-bit value. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_location_t; - -/** Encoding of identifiers of persistent keys. - * - * - Applications may freely choose key identifiers in the range - * #PSA_KEY_ID_USER_MIN to #PSA_KEY_ID_USER_MAX. - * - The implementation may define additional key identifiers in the range - * #PSA_KEY_ID_VENDOR_MIN to #PSA_KEY_ID_VENDOR_MAX. - * - 0 is reserved as an invalid key identifier. - * - Key identifiers outside these ranges are reserved for future use. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to how values are allocated must require careful - * consideration to allow backward compatibility. - */ -typedef uint32_t psa_key_id_t; - -/** Encoding of key identifiers as seen inside the PSA Crypto implementation. - * - * When PSA Crypto is built as a library inside an application, this type - * is identical to #psa_key_id_t. When PSA Crypto is built as a service - * that can store keys on behalf of multiple clients, this type - * encodes the #psa_key_id_t value seen by each client application as - * well as extra information that identifies the client that owns - * the key. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) -typedef psa_key_id_t mbedtls_svc_key_id_t; - -#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ -/* Implementation-specific: The Mbed TLS library can be built as - * part of a multi-client service that exposes the PSA Cryptography API in each - * client and encodes the client identity in the key identifier argument of - * functions such as psa_open_key(). - */ -typedef struct { - psa_key_id_t MBEDTLS_PRIVATE(key_id); - mbedtls_key_owner_id_t MBEDTLS_PRIVATE(owner); -} mbedtls_svc_key_id_t; - -#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/**@}*/ - -/** \defgroup policy Key policies - * @{ - */ - -/** \brief Encoding of permitted usage on a key. - * - * Values of this type are generally constructed as bitwise-ors of macros - * called `PSA_KEY_USAGE_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_usage_t; - -/**@}*/ - -/** \defgroup attributes Key attributes - * @{ - */ - -/** The type of a structure containing key attributes. - * - * This is an opaque structure that can represent the metadata of a key - * object. Metadata that can be stored in attributes includes: - * - The location of the key in storage, indicated by its key identifier - * and its lifetime. - * - The key's policy, comprising usage flags and a specification of - * the permitted algorithm(s). - * - Information about the key itself: the key type and its size. - * - Additional implementation-defined attributes. - * - * The actual key material is not considered an attribute of a key. - * Key attributes do not contain information that is generally considered - * highly confidential. - * - * An attribute structure works like a simple data structure where each function - * `psa_set_key_xxx` sets a field and the corresponding function - * `psa_get_key_xxx` retrieves the value of the corresponding field. - * However, a future version of the library may report values that are - * equivalent to the original one, but have a different encoding. Invalid - * values may be mapped to different, also invalid values. - * - * An attribute structure may contain references to auxiliary resources, - * for example pointers to allocated memory or indirect references to - * pre-calculated values. In order to free such resources, the application - * must call psa_reset_key_attributes(). As an exception, calling - * psa_reset_key_attributes() on an attribute structure is optional if - * the structure has only been modified by the following functions - * since it was initialized or last reset with psa_reset_key_attributes(): - * - psa_set_key_id() - * - psa_set_key_lifetime() - * - psa_set_key_type() - * - psa_set_key_bits() - * - psa_set_key_usage_flags() - * - psa_set_key_algorithm() - * - * Before calling any function on a key attribute structure, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_key_attributes_t attributes; - * memset(&attributes, 0, sizeof(attributes)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_key_attributes_t attributes = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_KEY_ATTRIBUTES_INIT, - * for example: - * \code - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * \endcode - * - Assign the result of the function psa_key_attributes_init() - * to the structure, for example: - * \code - * psa_key_attributes_t attributes; - * attributes = psa_key_attributes_init(); - * \endcode - * - * A freshly initialized attribute structure contains the following - * values: - * - * - lifetime: #PSA_KEY_LIFETIME_VOLATILE. - * - key identifier: 0 (which is not a valid key identifier). - * - type: \c 0 (meaning that the type is unspecified). - * - key size: \c 0 (meaning that the size is unspecified). - * - usage flags: \c 0 (which allows no usage except exporting a public key). - * - algorithm: \c 0 (which allows no cryptographic usage, but allows - * exporting). - * - * A typical sequence to create a key is as follows: - * -# Create and initialize an attribute structure. - * -# If the key is persistent, call psa_set_key_id(). - * Also call psa_set_key_lifetime() to place the key in a non-default - * location. - * -# Set the key policy with psa_set_key_usage_flags() and - * psa_set_key_algorithm(). - * -# Set the key type with psa_set_key_type(). - * Skip this step if copying an existing key with psa_copy_key(). - * -# When generating a random key with psa_generate_key() or deriving a key - * with psa_key_derivation_output_key(), set the desired key size with - * psa_set_key_bits(). - * -# Call a key creation function: psa_import_key(), psa_generate_key(), - * psa_key_derivation_output_key() or psa_copy_key(). This function reads - * the attribute structure, creates a key with these attributes, and - * outputs a key identifier to the newly created key. - * -# The attribute structure is now no longer necessary. - * You may call psa_reset_key_attributes(), although this is optional - * with the workflow presented here because the attributes currently - * defined in this specification do not require any additional resources - * beyond the structure itself. - * - * A typical sequence to query a key's attributes is as follows: - * -# Call psa_get_key_attributes(). - * -# Call `psa_get_key_xxx` functions to retrieve the attribute(s) that - * you are interested in. - * -# Call psa_reset_key_attributes() to free any resources that may be - * used by the attribute structure. - * - * Once a key has been created, it is impossible to change its attributes. - */ -typedef struct psa_key_attributes_s psa_key_attributes_t; - - -#ifndef __DOXYGEN_ONLY__ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* Mbed TLS defines this type in crypto_types.h because it is also - * visible to applications through an implementation-specific extension. - * For the PSA Cryptography specification, this type is only visible - * via crypto_se_driver.h. */ -typedef uint64_t psa_key_slot_number_t; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ -#endif /* !__DOXYGEN_ONLY__ */ - -/**@}*/ - -/** \defgroup derivation Key derivation - * @{ - */ - -/** \brief Encoding of the step of a key derivation. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_DERIVATION_INPUT_xxx`. - */ -typedef uint16_t psa_key_derivation_step_t; - -/** \brief Custom parameters for key generation or key derivation. - * - * This is a structure type with at least the following fields: - * - * - \c flags: an unsigned integer type. 0 for the default production parameters. - * - \c data: a flexible array of bytes. - * - * The interpretation of this structure depend on the type of the - * created key. - * - * - #PSA_KEY_TYPE_RSA_KEY_PAIR: - * - \c flags: must be 0. - * - \c data: the public exponent, in little-endian order. - * This must be an odd integer and must not be 1. - * Implementations must support 65537, should support 3 and may - * support other values. - * When not using a driver, Mbed TLS supports values up to \c INT_MAX. - * If this is empty or if the custom production parameters are omitted - * altogether, the default value 65537 is used. - * - Other key types: reserved for future use. \c flags must be 0. - * - */ -typedef struct psa_key_production_parameters_s psa_key_production_parameters_t; - -/**@}*/ - -#endif /* PSA_CRYPTO_TYPES_H */ diff --git a/interface/include/psa/crypto_values.h b/interface/include/psa/crypto_values.h deleted file mode 100644 index 1d678dbfc..000000000 --- a/interface/include/psa/crypto_values.h +++ /dev/null @@ -1,2783 +0,0 @@ -/** - * \file psa/crypto_values.h - * - * \brief PSA cryptography module: macros to build and analyze integer values. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. Drivers must include the appropriate driver - * header file. - * - * This file contains portable definitions of macros to build and analyze - * values of integral types that encode properties of cryptographic keys, - * designations of cryptographic algorithms, and error codes returned by - * the library. - * - * Note that many of the constants defined in this file are embedded in - * the persistent key store, as part of key metadata (including usage - * policies). As a consequence, they must not be changed (unless the storage - * format version changes). - * - * This header file only defines preprocessor macros. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later - */ - -#ifndef PSA_CRYPTO_VALUES_H -#define PSA_CRYPTO_VALUES_H -#include "mbedtls/private_access.h" - -/** \defgroup error Error codes - * @{ - */ - -/* PSA error codes */ - -/* Error codes are standardized across PSA domains (framework, crypto, storage, - * etc.). Do not change the values in this section or even the expansions - * of each macro: it must be possible to `#include` both this header - * and some other PSA component's headers in the same C source, - * which will lead to duplicate definitions of the `PSA_SUCCESS` and - * `PSA_ERROR_xxx` macros, which is ok if and only if the macros expand - * to the same sequence of tokens. - * - * If you must add a new - * value, check with the Arm PSA framework group to pick one that other - * domains aren't already using. */ - -/* Tell uncrustify not to touch the constant definitions, otherwise - * it might change the spacing to something that is not PSA-compliant - * (e.g. adding a space after casts). - * - * *INDENT-OFF* - */ - -/** The action was completed successfully. */ -#define PSA_SUCCESS ((psa_status_t)0) - -/** An error occurred that does not correspond to any defined - * failure cause. - * - * Implementations may use this error code if none of the other standard - * error codes are applicable. */ -#define PSA_ERROR_GENERIC_ERROR ((psa_status_t)-132) - -/** The requested operation or a parameter is not supported - * by this implementation. - * - * Implementations should return this error code when an enumeration - * parameter such as a key type, algorithm, etc. is not recognized. - * If a combination of parameters is recognized and identified as - * not valid, return #PSA_ERROR_INVALID_ARGUMENT instead. */ -#define PSA_ERROR_NOT_SUPPORTED ((psa_status_t)-134) - -/** The requested action is denied by a policy. - * - * Implementations should return this error code when the parameters - * are recognized as valid and supported, and a policy explicitly - * denies the requested operation. - * - * If a subset of the parameters of a function call identify a - * forbidden operation, and another subset of the parameters are - * not valid or not supported, it is unspecified whether the function - * returns #PSA_ERROR_NOT_PERMITTED, #PSA_ERROR_NOT_SUPPORTED or - * #PSA_ERROR_INVALID_ARGUMENT. */ -#define PSA_ERROR_NOT_PERMITTED ((psa_status_t)-133) - -/** An output buffer is too small. - * - * Applications can call the \c PSA_xxx_SIZE macro listed in the function - * description to determine a sufficient buffer size. - * - * Implementations should preferably return this error code only - * in cases when performing the operation with a larger output - * buffer would succeed. However implementations may return this - * error if a function has invalid or unsupported parameters in addition - * to the parameters that determine the necessary output buffer size. */ -#define PSA_ERROR_BUFFER_TOO_SMALL ((psa_status_t)-138) - -/** Asking for an item that already exists - * - * Implementations should return this error, when attempting - * to write an item (like a key) that already exists. */ -#define PSA_ERROR_ALREADY_EXISTS ((psa_status_t)-139) - -/** Asking for an item that doesn't exist - * - * Implementations should return this error, if a requested item (like - * a key) does not exist. */ -#define PSA_ERROR_DOES_NOT_EXIST ((psa_status_t)-140) - -/** The requested action cannot be performed in the current state. - * - * Multipart operations return this error when one of the - * functions is called out of sequence. Refer to the function - * descriptions for permitted sequencing of functions. - * - * Implementations shall not return this error code to indicate - * that a key either exists or not, - * but shall instead return #PSA_ERROR_ALREADY_EXISTS or #PSA_ERROR_DOES_NOT_EXIST - * as applicable. - * - * Implementations shall not return this error code to indicate that a - * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE - * instead. */ -#define PSA_ERROR_BAD_STATE ((psa_status_t)-137) - -/** The parameters passed to the function are invalid. - * - * Implementations may return this error any time a parameter or - * combination of parameters are recognized as invalid. - * - * Implementations shall not return this error code to indicate that a - * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE - * instead. - */ -#define PSA_ERROR_INVALID_ARGUMENT ((psa_status_t)-135) - -/** There is not enough runtime memory. - * - * If the action is carried out across multiple security realms, this - * error can refer to available memory in any of the security realms. */ -#define PSA_ERROR_INSUFFICIENT_MEMORY ((psa_status_t)-141) - -/** There is not enough persistent storage. - * - * Functions that modify the key storage return this error code if - * there is insufficient storage space on the host media. In addition, - * many functions that do not otherwise access storage may return this - * error code if the implementation requires a mandatory log entry for - * the requested action and the log storage space is full. */ -#define PSA_ERROR_INSUFFICIENT_STORAGE ((psa_status_t)-142) - -/** There was a communication failure inside the implementation. - * - * This can indicate a communication failure between the application - * and an external cryptoprocessor or between the cryptoprocessor and - * an external volatile or persistent memory. A communication failure - * may be transient or permanent depending on the cause. - * - * \warning If a function returns this error, it is undetermined - * whether the requested action has completed or not. Implementations - * should return #PSA_SUCCESS on successful completion whenever - * possible, however functions may return #PSA_ERROR_COMMUNICATION_FAILURE - * if the requested action was completed successfully in an external - * cryptoprocessor but there was a breakdown of communication before - * the cryptoprocessor could report the status to the application. - */ -#define PSA_ERROR_COMMUNICATION_FAILURE ((psa_status_t)-145) - -/** There was a storage failure that may have led to data loss. - * - * This error indicates that some persistent storage is corrupted. - * It should not be used for a corruption of volatile memory - * (use #PSA_ERROR_CORRUPTION_DETECTED), for a communication error - * between the cryptoprocessor and its external storage (use - * #PSA_ERROR_COMMUNICATION_FAILURE), or when the storage is - * in a valid state but is full (use #PSA_ERROR_INSUFFICIENT_STORAGE). - * - * Note that a storage failure does not indicate that any data that was - * previously read is invalid. However this previously read data may no - * longer be readable from storage. - * - * When a storage failure occurs, it is no longer possible to ensure - * the global integrity of the keystore. Depending on the global - * integrity guarantees offered by the implementation, access to other - * data may or may not fail even if the data is still readable but - * its integrity cannot be guaranteed. - * - * Implementations should only use this error code to report a - * permanent storage corruption. However application writers should - * keep in mind that transient errors while reading the storage may be - * reported using this error code. */ -#define PSA_ERROR_STORAGE_FAILURE ((psa_status_t)-146) - -/** A hardware failure was detected. - * - * A hardware failure may be transient or permanent depending on the - * cause. */ -#define PSA_ERROR_HARDWARE_FAILURE ((psa_status_t)-147) - -/** A tampering attempt was detected. - * - * If an application receives this error code, there is no guarantee - * that previously accessed or computed data was correct and remains - * confidential. Applications should not perform any security function - * and should enter a safe failure state. - * - * Implementations may return this error code if they detect an invalid - * state that cannot happen during normal operation and that indicates - * that the implementation's security guarantees no longer hold. Depending - * on the implementation architecture and on its security and safety goals, - * the implementation may forcibly terminate the application. - * - * This error code is intended as a last resort when a security breach - * is detected and it is unsure whether the keystore data is still - * protected. Implementations shall only return this error code - * to report an alarm from a tampering detector, to indicate that - * the confidentiality of stored data can no longer be guaranteed, - * or to indicate that the integrity of previously returned data is now - * considered compromised. Implementations shall not use this error code - * to indicate a hardware failure that merely makes it impossible to - * perform the requested operation (use #PSA_ERROR_COMMUNICATION_FAILURE, - * #PSA_ERROR_STORAGE_FAILURE, #PSA_ERROR_HARDWARE_FAILURE, - * #PSA_ERROR_INSUFFICIENT_ENTROPY or other applicable error code - * instead). - * - * This error indicates an attack against the application. Implementations - * shall not return this error code as a consequence of the behavior of - * the application itself. */ -#define PSA_ERROR_CORRUPTION_DETECTED ((psa_status_t)-151) - -/** There is not enough entropy to generate random data needed - * for the requested action. - * - * This error indicates a failure of a hardware random generator. - * Application writers should note that this error can be returned not - * only by functions whose purpose is to generate random data, such - * as key, IV or nonce generation, but also by functions that execute - * an algorithm with a randomized result, as well as functions that - * use randomization of intermediate computations as a countermeasure - * to certain attacks. - * - * Implementations should avoid returning this error after psa_crypto_init() - * has succeeded. Implementations should generate sufficient - * entropy during initialization and subsequently use a cryptographically - * secure pseudorandom generator (PRNG). However implementations may return - * this error at any time if a policy requires the PRNG to be reseeded - * during normal operation. */ -#define PSA_ERROR_INSUFFICIENT_ENTROPY ((psa_status_t)-148) - -/** The signature, MAC or hash is incorrect. - * - * Verification functions return this error if the verification - * calculations completed successfully, and the value to be verified - * was determined to be incorrect. - * - * If the value to verify has an invalid size, implementations may return - * either #PSA_ERROR_INVALID_ARGUMENT or #PSA_ERROR_INVALID_SIGNATURE. */ -#define PSA_ERROR_INVALID_SIGNATURE ((psa_status_t)-149) - -/** The decrypted padding is incorrect. - * - * \warning In some protocols, when decrypting data, it is essential that - * the behavior of the application does not depend on whether the padding - * is correct, down to precise timing. Applications should prefer - * protocols that use authenticated encryption rather than plain - * encryption. If the application must perform a decryption of - * unauthenticated data, the application writer should take care not - * to reveal whether the padding is invalid. - * - * Implementations should strive to make valid and invalid padding - * as close as possible to indistinguishable to an external observer. - * In particular, the timing of a decryption operation should not - * depend on the validity of the padding. */ -#define PSA_ERROR_INVALID_PADDING ((psa_status_t)-150) - -/** Return this error when there's insufficient data when attempting - * to read from a resource. */ -#define PSA_ERROR_INSUFFICIENT_DATA ((psa_status_t)-143) - -/** This can be returned if a function can no longer operate correctly. - * For example, if an essential initialization operation failed or - * a mutex operation failed. */ -#define PSA_ERROR_SERVICE_FAILURE ((psa_status_t)-144) - -/** The key identifier is not valid. See also :ref:\`key-handles\`. - */ -#define PSA_ERROR_INVALID_HANDLE ((psa_status_t)-136) - -/** Stored data has been corrupted. - * - * This error indicates that some persistent storage has suffered corruption. - * It does not indicate the following situations, which have specific error - * codes: - * - * - A corruption of volatile memory - use #PSA_ERROR_CORRUPTION_DETECTED. - * - A communication error between the cryptoprocessor and its external - * storage - use #PSA_ERROR_COMMUNICATION_FAILURE. - * - When the storage is in a valid state but is full - use - * #PSA_ERROR_INSUFFICIENT_STORAGE. - * - When the storage fails for other reasons - use - * #PSA_ERROR_STORAGE_FAILURE. - * - When the stored data is not valid - use #PSA_ERROR_DATA_INVALID. - * - * \note A storage corruption does not indicate that any data that was - * previously read is invalid. However this previously read data might no - * longer be readable from storage. - * - * When a storage failure occurs, it is no longer possible to ensure the - * global integrity of the keystore. - */ -#define PSA_ERROR_DATA_CORRUPT ((psa_status_t)-152) - -/** Data read from storage is not valid for the implementation. - * - * This error indicates that some data read from storage does not have a valid - * format. It does not indicate the following situations, which have specific - * error codes: - * - * - When the storage or stored data is corrupted - use #PSA_ERROR_DATA_CORRUPT - * - When the storage fails for other reasons - use #PSA_ERROR_STORAGE_FAILURE - * - An invalid argument to the API - use #PSA_ERROR_INVALID_ARGUMENT - * - * This error is typically a result of either storage corruption on a - * cleartext storage backend, or an attempt to read data that was - * written by an incompatible version of the library. - */ -#define PSA_ERROR_DATA_INVALID ((psa_status_t)-153) - -/** The function that returns this status is defined as interruptible and - * still has work to do, thus the user should call the function again with the - * same operation context until it either returns #PSA_SUCCESS or any other - * error. This is not an error per se, more a notification of status. - */ -#define PSA_OPERATION_INCOMPLETE ((psa_status_t)-248) - -/* *INDENT-ON* */ - -/**@}*/ - -/** \defgroup crypto_types Key and algorithm types - * @{ - */ - -/* Note that key type values, including ECC family and DH group values, are - * embedded in the persistent key store, as part of key metadata. As a - * consequence, they must not be changed (unless the storage format version - * changes). - */ - -/** An invalid key type value. - * - * Zero is not the encoding of any key type. - */ -#define PSA_KEY_TYPE_NONE ((psa_key_type_t) 0x0000) - -/** Vendor-defined key type flag. - * - * Key types defined by this standard will never have the - * #PSA_KEY_TYPE_VENDOR_FLAG bit set. Vendors who define additional key types - * must use an encoding with the #PSA_KEY_TYPE_VENDOR_FLAG bit set and should - * respect the bitwise structure used by standard encodings whenever practical. - */ -#define PSA_KEY_TYPE_VENDOR_FLAG ((psa_key_type_t) 0x8000) - -#define PSA_KEY_TYPE_CATEGORY_MASK ((psa_key_type_t) 0x7000) -#define PSA_KEY_TYPE_CATEGORY_RAW ((psa_key_type_t) 0x1000) -#define PSA_KEY_TYPE_CATEGORY_SYMMETRIC ((psa_key_type_t) 0x2000) -#define PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY ((psa_key_type_t) 0x4000) -#define PSA_KEY_TYPE_CATEGORY_KEY_PAIR ((psa_key_type_t) 0x7000) - -#define PSA_KEY_TYPE_CATEGORY_FLAG_PAIR ((psa_key_type_t) 0x3000) - -/** Whether a key type is vendor-defined. - * - * See also #PSA_KEY_TYPE_VENDOR_FLAG. - */ -#define PSA_KEY_TYPE_IS_VENDOR_DEFINED(type) \ - (((type) & PSA_KEY_TYPE_VENDOR_FLAG) != 0) - -/** Whether a key type is an unstructured array of bytes. - * - * This encompasses both symmetric keys and non-key data. - */ -#define PSA_KEY_TYPE_IS_UNSTRUCTURED(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_RAW || \ - ((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC) - -/** Whether a key type is asymmetric: either a key pair or a public key. */ -#define PSA_KEY_TYPE_IS_ASYMMETRIC(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK \ - & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) == \ - PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) -/** Whether a key type is the public part of a key pair. */ -#define PSA_KEY_TYPE_IS_PUBLIC_KEY(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) -/** Whether a key type is a key pair containing a private part and a public - * part. */ -#define PSA_KEY_TYPE_IS_KEY_PAIR(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_KEY_PAIR) -/** The key pair type corresponding to a public key type. - * - * You may also pass a key pair type as \p type, it will be left unchanged. - * - * \param type A public key type or key pair type. - * - * \return The corresponding key pair type. - * If \p type is not a public key or a key pair, - * the return value is undefined. - */ -#define PSA_KEY_TYPE_KEY_PAIR_OF_PUBLIC_KEY(type) \ - ((type) | PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) -/** The public key type corresponding to a key pair type. - * - * You may also pass a public key type as \p type, it will be left unchanged. - * - * \param type A public key type or key pair type. - * - * \return The corresponding public key type. - * If \p type is not a public key or a key pair, - * the return value is undefined. - */ -#define PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) \ - ((type) & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) - -/** Raw data. - * - * A "key" of this type cannot be used for any cryptographic operation. - * Applications may use this type to store arbitrary data in the keystore. */ -#define PSA_KEY_TYPE_RAW_DATA ((psa_key_type_t) 0x1001) - -/** HMAC key. - * - * The key policy determines which underlying hash algorithm the key can be - * used for. - * - * HMAC keys should generally have the same size as the underlying hash. - * This size can be calculated with #PSA_HASH_LENGTH(\c alg) where - * \c alg is the HMAC algorithm or the underlying hash algorithm. */ -#define PSA_KEY_TYPE_HMAC ((psa_key_type_t) 0x1100) - -/** A secret for key derivation. - * - * This key type is for high-entropy secrets only. For low-entropy secrets, - * #PSA_KEY_TYPE_PASSWORD should be used instead. - * - * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_SECRET or - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input of key derivation algorithms. - * - * The key policy determines which key derivation algorithm the key - * can be used for. - */ -#define PSA_KEY_TYPE_DERIVE ((psa_key_type_t) 0x1200) - -/** A low-entropy secret for password hashing or key derivation. - * - * This key type is suitable for passwords and passphrases which are typically - * intended to be memorizable by humans, and have a low entropy relative to - * their size. It can be used for randomly generated or derived keys with - * maximum or near-maximum entropy, but #PSA_KEY_TYPE_DERIVE is more suitable - * for such keys. It is not suitable for passwords with extremely low entropy, - * such as numerical PINs. - * - * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_PASSWORD input of - * key derivation algorithms. Algorithms that accept such an input were - * designed to accept low-entropy secret and are known as password hashing or - * key stretching algorithms. - * - * These keys cannot be used as the #PSA_KEY_DERIVATION_INPUT_SECRET input of - * key derivation algorithms, as the algorithms that take such an input expect - * it to be high-entropy. - * - * The key policy determines which key derivation algorithm the key can be - * used for, among the permissible subset defined above. - */ -#define PSA_KEY_TYPE_PASSWORD ((psa_key_type_t) 0x1203) - -/** A secret value that can be used to verify a password hash. - * - * The key policy determines which key derivation algorithm the key - * can be used for, among the same permissible subset as for - * #PSA_KEY_TYPE_PASSWORD. - */ -#define PSA_KEY_TYPE_PASSWORD_HASH ((psa_key_type_t) 0x1205) - -/** A secret value that can be used in when computing a password hash. - * - * The key policy determines which key derivation algorithm the key - * can be used for, among the subset of algorithms that can use pepper. - */ -#define PSA_KEY_TYPE_PEPPER ((psa_key_type_t) 0x1206) - -/** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. - * - * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or - * 32 bytes (AES-256). - */ -#define PSA_KEY_TYPE_AES ((psa_key_type_t) 0x2400) - -/** Key for a cipher, AEAD or MAC algorithm based on the - * ARIA block cipher. */ -#define PSA_KEY_TYPE_ARIA ((psa_key_type_t) 0x2406) - -/** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). - * - * The size of the key can be 64 bits (single DES), 128 bits (2-key 3DES) or - * 192 bits (3-key 3DES). - * - * Note that single DES and 2-key 3DES are weak and strongly - * deprecated and should only be used to decrypt legacy data. 3-key 3DES - * is weak and deprecated and should only be used in legacy protocols. - */ -#define PSA_KEY_TYPE_DES ((psa_key_type_t) 0x2301) - -/** Key for a cipher, AEAD or MAC algorithm based on the - * Camellia block cipher. */ -#define PSA_KEY_TYPE_CAMELLIA ((psa_key_type_t) 0x2403) - -/** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. - * - * ChaCha20 and the ChaCha20_Poly1305 construction are defined in RFC 7539. - * - * \note For ChaCha20 and ChaCha20_Poly1305, Mbed TLS only supports - * 12-byte nonces. - * - * \note For ChaCha20, the initial counter value is 0. To encrypt or decrypt - * with the initial counter value 1, you can process and discard a - * 64-byte block before the real data. - */ -#define PSA_KEY_TYPE_CHACHA20 ((psa_key_type_t) 0x2004) - -/** RSA public key. - * - * The size of an RSA key is the bit size of the modulus. - */ -#define PSA_KEY_TYPE_RSA_PUBLIC_KEY ((psa_key_type_t) 0x4001) -/** RSA key pair (private and public key). - * - * The size of an RSA key is the bit size of the modulus. - */ -#define PSA_KEY_TYPE_RSA_KEY_PAIR ((psa_key_type_t) 0x7001) -/** Whether a key type is an RSA key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_RSA(type) \ - (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) - -#define PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4100) -#define PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((psa_key_type_t) 0x7100) -#define PSA_KEY_TYPE_ECC_CURVE_MASK ((psa_key_type_t) 0x00ff) -/** Elliptic curve key pair. - * - * The size of an elliptic curve key is the bit size associated with the curve, - * i.e. the bit size of *q* for a curve over a field *Fq*. - * See the documentation of `PSA_ECC_FAMILY_xxx` curve families for details. - * - * \param curve A value of type ::psa_ecc_family_t that - * identifies the ECC curve to be used. - */ -#define PSA_KEY_TYPE_ECC_KEY_PAIR(curve) \ - (PSA_KEY_TYPE_ECC_KEY_PAIR_BASE | (curve)) -/** Elliptic curve public key. - * - * The size of an elliptic curve public key is the same as the corresponding - * private key (see #PSA_KEY_TYPE_ECC_KEY_PAIR and the documentation of - * `PSA_ECC_FAMILY_xxx` curve families). - * - * \param curve A value of type ::psa_ecc_family_t that - * identifies the ECC curve to be used. - */ -#define PSA_KEY_TYPE_ECC_PUBLIC_KEY(curve) \ - (PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE | (curve)) - -/** Whether a key type is an elliptic curve key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_ECC(type) \ - ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ - ~PSA_KEY_TYPE_ECC_CURVE_MASK) == PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) -/** Whether a key type is an elliptic curve key pair. */ -#define PSA_KEY_TYPE_IS_ECC_KEY_PAIR(type) \ - (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ - PSA_KEY_TYPE_ECC_KEY_PAIR_BASE) -/** Whether a key type is an elliptic curve public key. */ -#define PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(type) \ - (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ - PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) - -/** Extract the curve from an elliptic curve key type. */ -#define PSA_KEY_TYPE_ECC_GET_FAMILY(type) \ - ((psa_ecc_family_t) (PSA_KEY_TYPE_IS_ECC(type) ? \ - ((type) & PSA_KEY_TYPE_ECC_CURVE_MASK) : \ - 0)) - -/** Check if the curve of given family is Weierstrass elliptic curve. */ -#define PSA_ECC_FAMILY_IS_WEIERSTRASS(family) ((family & 0xc0) == 0) - -/** SEC Koblitz curves over prime fields. - * - * This family comprises the following curves: - * secp192k1, secp224k1, secp256k1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - * - * \note For secp224k1, the bit-size is 225 (size of a private value). - * - * \note Mbed TLS only supports secp192k1 and secp256k1. - */ -#define PSA_ECC_FAMILY_SECP_K1 ((psa_ecc_family_t) 0x17) - -/** SEC random curves over prime fields. - * - * This family comprises the following curves: - * secp192r1, secp224r1, secp256r1, secp384r1, secp521r1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECP_R1 ((psa_ecc_family_t) 0x12) -/* SECP160R2 (SEC2 v1, obsolete, not supported in Mbed TLS) */ -#define PSA_ECC_FAMILY_SECP_R2 ((psa_ecc_family_t) 0x1b) - -/** SEC Koblitz curves over binary fields. - * - * This family comprises the following curves: - * sect163k1, sect233k1, sect239k1, sect283k1, sect409k1, sect571k1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - * - * \note Mbed TLS does not support any curve in this family. - */ -#define PSA_ECC_FAMILY_SECT_K1 ((psa_ecc_family_t) 0x27) - -/** SEC random curves over binary fields. - * - * This family comprises the following curves: - * sect163r1, sect233r1, sect283r1, sect409r1, sect571r1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - * - * \note Mbed TLS does not support any curve in this family. - */ -#define PSA_ECC_FAMILY_SECT_R1 ((psa_ecc_family_t) 0x22) - -/** SEC additional random curves over binary fields. - * - * This family comprises the following curve: - * sect163r2. - * It is defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - * - * \note Mbed TLS does not support any curve in this family. - */ -#define PSA_ECC_FAMILY_SECT_R2 ((psa_ecc_family_t) 0x2b) - -/** Brainpool P random curves. - * - * This family comprises the following curves: - * brainpoolP160r1, brainpoolP192r1, brainpoolP224r1, brainpoolP256r1, - * brainpoolP320r1, brainpoolP384r1, brainpoolP512r1. - * It is defined in RFC 5639. - * - * \note Mbed TLS only supports the 256-bit, 384-bit and 512-bit curves - * in this family. - */ -#define PSA_ECC_FAMILY_BRAINPOOL_P_R1 ((psa_ecc_family_t) 0x30) - -/** Curve25519 and Curve448. - * - * This family comprises the following Montgomery curves: - * - 255-bit: Bernstein et al., - * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. - * The algorithm #PSA_ALG_ECDH performs X25519 when used with this curve. - * - 448-bit: Hamburg, - * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. - * The algorithm #PSA_ALG_ECDH performs X448 when used with this curve. - */ -#define PSA_ECC_FAMILY_MONTGOMERY ((psa_ecc_family_t) 0x41) - -/** The twisted Edwards curves Ed25519 and Ed448. - * - * These curves are suitable for EdDSA (#PSA_ALG_PURE_EDDSA for both curves, - * #PSA_ALG_ED25519PH for the 255-bit curve, - * #PSA_ALG_ED448PH for the 448-bit curve). - * - * This family comprises the following twisted Edwards curves: - * - 255-bit: Edwards25519, the twisted Edwards curve birationally equivalent - * to Curve25519. - * Bernstein et al., _Twisted Edwards curves_, Africacrypt 2008. - * - 448-bit: Edwards448, the twisted Edwards curve birationally equivalent - * to Curve448. - * Hamburg, _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. - * - * \note Mbed TLS does not support Edwards curves yet. - */ -#define PSA_ECC_FAMILY_TWISTED_EDWARDS ((psa_ecc_family_t) 0x42) - -#define PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4200) -#define PSA_KEY_TYPE_DH_KEY_PAIR_BASE ((psa_key_type_t) 0x7200) -#define PSA_KEY_TYPE_DH_GROUP_MASK ((psa_key_type_t) 0x00ff) -/** Diffie-Hellman key pair. - * - * \param group A value of type ::psa_dh_family_t that identifies the - * Diffie-Hellman group to be used. - */ -#define PSA_KEY_TYPE_DH_KEY_PAIR(group) \ - (PSA_KEY_TYPE_DH_KEY_PAIR_BASE | (group)) -/** Diffie-Hellman public key. - * - * \param group A value of type ::psa_dh_family_t that identifies the - * Diffie-Hellman group to be used. - */ -#define PSA_KEY_TYPE_DH_PUBLIC_KEY(group) \ - (PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE | (group)) - -/** Whether a key type is a Diffie-Hellman key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_DH(type) \ - ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ - ~PSA_KEY_TYPE_DH_GROUP_MASK) == PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) -/** Whether a key type is a Diffie-Hellman key pair. */ -#define PSA_KEY_TYPE_IS_DH_KEY_PAIR(type) \ - (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ - PSA_KEY_TYPE_DH_KEY_PAIR_BASE) -/** Whether a key type is a Diffie-Hellman public key. */ -#define PSA_KEY_TYPE_IS_DH_PUBLIC_KEY(type) \ - (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ - PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) - -/** Extract the group from a Diffie-Hellman key type. */ -#define PSA_KEY_TYPE_DH_GET_FAMILY(type) \ - ((psa_dh_family_t) (PSA_KEY_TYPE_IS_DH(type) ? \ - ((type) & PSA_KEY_TYPE_DH_GROUP_MASK) : \ - 0)) - -/** Diffie-Hellman groups defined in RFC 7919 Appendix A. - * - * This family includes groups with the following key sizes (in bits): - * 2048, 3072, 4096, 6144, 8192. A given implementation may support - * all of these sizes or only a subset. - */ -#define PSA_DH_FAMILY_RFC7919 ((psa_dh_family_t) 0x03) - -#define PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) \ - (((type) >> 8) & 7) -/** The block size of a block cipher. - * - * \param type A cipher key type (value of type #psa_key_type_t). - * - * \return The block size for a block cipher, or 1 for a stream cipher. - * The return value is undefined if \p type is not a supported - * cipher key type. - * - * \note It is possible to build stream cipher algorithms on top of a block - * cipher, for example CTR mode (#PSA_ALG_CTR). - * This macro only takes the key type into account, so it cannot be - * used to determine the size of the data that #psa_cipher_update() - * might buffer for future processing in general. - * - * \note This macro returns a compile-time constant if its argument is one. - * - * \warning This macro may evaluate its argument multiple times. - */ -#define PSA_BLOCK_CIPHER_BLOCK_LENGTH(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ - 1u << PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) : \ - 0u) - -/* Note that algorithm values are embedded in the persistent key store, - * as part of key metadata. As a consequence, they must not be changed - * (unless the storage format version changes). - */ - -/** Vendor-defined algorithm flag. - * - * Algorithms defined by this standard will never have the #PSA_ALG_VENDOR_FLAG - * bit set. Vendors who define additional algorithms must use an encoding with - * the #PSA_ALG_VENDOR_FLAG bit set and should respect the bitwise structure - * used by standard encodings whenever practical. - */ -#define PSA_ALG_VENDOR_FLAG ((psa_algorithm_t) 0x80000000) - -#define PSA_ALG_CATEGORY_MASK ((psa_algorithm_t) 0x7f000000) -#define PSA_ALG_CATEGORY_HASH ((psa_algorithm_t) 0x02000000) -#define PSA_ALG_CATEGORY_MAC ((psa_algorithm_t) 0x03000000) -#define PSA_ALG_CATEGORY_CIPHER ((psa_algorithm_t) 0x04000000) -#define PSA_ALG_CATEGORY_AEAD ((psa_algorithm_t) 0x05000000) -#define PSA_ALG_CATEGORY_SIGN ((psa_algorithm_t) 0x06000000) -#define PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION ((psa_algorithm_t) 0x07000000) -#define PSA_ALG_CATEGORY_KEY_DERIVATION ((psa_algorithm_t) 0x08000000) -#define PSA_ALG_CATEGORY_KEY_AGREEMENT ((psa_algorithm_t) 0x09000000) - -/** Whether an algorithm is vendor-defined. - * - * See also #PSA_ALG_VENDOR_FLAG. - */ -#define PSA_ALG_IS_VENDOR_DEFINED(alg) \ - (((alg) & PSA_ALG_VENDOR_FLAG) != 0) - -/** Whether the specified algorithm is a hash algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a hash algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HASH(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_HASH) - -/** Whether the specified algorithm is a MAC algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a MAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_MAC(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_MAC) - -/** Whether the specified algorithm is a symmetric cipher algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a symmetric cipher algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_CIPHER(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_CIPHER) - -/** Whether the specified algorithm is an authenticated encryption - * with associated data (AEAD) algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an AEAD algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_AEAD(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_AEAD) - -/** Whether the specified algorithm is an asymmetric signature algorithm, - * also known as public-key signature algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an asymmetric signature algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_SIGN(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_SIGN) - -/** Whether the specified algorithm is an asymmetric encryption algorithm, - * also known as public-key encryption algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an asymmetric encryption algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_ASYMMETRIC_ENCRYPTION(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION) - -/** Whether the specified algorithm is a key agreement algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key agreement algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_KEY_AGREEMENT(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_AGREEMENT) - -/** Whether the specified algorithm is a key derivation algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key derivation algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_KEY_DERIVATION(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_DERIVATION) - -/** Whether the specified algorithm is a key stretching / password hashing - * algorithm. - * - * A key stretching / password hashing algorithm is a key derivation algorithm - * that is suitable for use with a low-entropy secret such as a password. - * Equivalently, it's a key derivation algorithm that uses a - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input step. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key stretching / password hashing algorithm, 0 - * otherwise. This macro may return either 0 or 1 if \p alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_KEY_DERIVATION_STRETCHING(alg) \ - (PSA_ALG_IS_KEY_DERIVATION(alg) && \ - (alg) & PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG) - -/** An invalid algorithm identifier value. */ -/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ -#define PSA_ALG_NONE ((psa_algorithm_t)0) -/* *INDENT-ON* */ - -#define PSA_ALG_HASH_MASK ((psa_algorithm_t) 0x000000ff) -/** MD5 */ -#define PSA_ALG_MD5 ((psa_algorithm_t) 0x02000003) -/** PSA_ALG_RIPEMD160 */ -#define PSA_ALG_RIPEMD160 ((psa_algorithm_t) 0x02000004) -/** SHA1 */ -#define PSA_ALG_SHA_1 ((psa_algorithm_t) 0x02000005) -/** SHA2-224 */ -#define PSA_ALG_SHA_224 ((psa_algorithm_t) 0x02000008) -/** SHA2-256 */ -#define PSA_ALG_SHA_256 ((psa_algorithm_t) 0x02000009) -/** SHA2-384 */ -#define PSA_ALG_SHA_384 ((psa_algorithm_t) 0x0200000a) -/** SHA2-512 */ -#define PSA_ALG_SHA_512 ((psa_algorithm_t) 0x0200000b) -/** SHA2-512/224 */ -#define PSA_ALG_SHA_512_224 ((psa_algorithm_t) 0x0200000c) -/** SHA2-512/256 */ -#define PSA_ALG_SHA_512_256 ((psa_algorithm_t) 0x0200000d) -/** SHA3-224 */ -#define PSA_ALG_SHA3_224 ((psa_algorithm_t) 0x02000010) -/** SHA3-256 */ -#define PSA_ALG_SHA3_256 ((psa_algorithm_t) 0x02000011) -/** SHA3-384 */ -#define PSA_ALG_SHA3_384 ((psa_algorithm_t) 0x02000012) -/** SHA3-512 */ -#define PSA_ALG_SHA3_512 ((psa_algorithm_t) 0x02000013) -/** The first 512 bits (64 bytes) of the SHAKE256 output. - * - * This is the prehashing for Ed448ph (see #PSA_ALG_ED448PH). For other - * scenarios where a hash function based on SHA3/SHAKE is desired, SHA3-512 - * has the same output size and a (theoretically) higher security strength. - */ -#define PSA_ALG_SHAKE256_512 ((psa_algorithm_t) 0x02000015) - -/** In a hash-and-sign algorithm policy, allow any hash algorithm. - * - * This value may be used to form the algorithm usage field of a policy - * for a signature algorithm that is parametrized by a hash. The key - * may then be used to perform operations using the same signature - * algorithm parametrized with any supported hash. - * - * That is, suppose that `PSA_xxx_SIGNATURE` is one of the following macros: - * - #PSA_ALG_RSA_PKCS1V15_SIGN, #PSA_ALG_RSA_PSS, #PSA_ALG_RSA_PSS_ANY_SALT, - * - #PSA_ALG_ECDSA, #PSA_ALG_DETERMINISTIC_ECDSA. - * Then you may create and use a key as follows: - * - Set the key usage field using #PSA_ALG_ANY_HASH, for example: - * ``` - * psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); // or VERIFY - * psa_set_key_algorithm(&attributes, PSA_xxx_SIGNATURE(PSA_ALG_ANY_HASH)); - * ``` - * - Import or generate key material. - * - Call psa_sign_hash() or psa_verify_hash(), passing - * an algorithm built from `PSA_xxx_SIGNATURE` and a specific hash. Each - * call to sign or verify a message may use a different hash. - * ``` - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); - * ``` - * - * This value may not be used to build other algorithms that are - * parametrized over a hash. For any valid use of this macro to build - * an algorithm \c alg, #PSA_ALG_IS_HASH_AND_SIGN(\c alg) is true. - * - * This value may not be used to build an algorithm specification to - * perform an operation. It is only valid to build policies. - */ -#define PSA_ALG_ANY_HASH ((psa_algorithm_t) 0x020000ff) - -#define PSA_ALG_MAC_SUBCATEGORY_MASK ((psa_algorithm_t) 0x00c00000) -#define PSA_ALG_HMAC_BASE ((psa_algorithm_t) 0x03800000) -/** Macro to build an HMAC algorithm. - * - * For example, #PSA_ALG_HMAC(#PSA_ALG_SHA_256) is HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HMAC algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HMAC(hash_alg) \ - (PSA_ALG_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_HMAC_GET_HASH(hmac_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hmac_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is an HMAC algorithm. - * - * HMAC is a family of MAC algorithms that are based on a hash function. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an HMAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HMAC(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ - PSA_ALG_HMAC_BASE) - -/* In the encoding of a MAC algorithm, the bits corresponding to - * PSA_ALG_MAC_TRUNCATION_MASK encode the length to which the MAC is - * truncated. As an exception, the value 0 means the untruncated algorithm, - * whatever its length is. The length is encoded in 6 bits, so it can - * reach up to 63; the largest MAC is 64 bytes so its trivial truncation - * to full length is correctly encoded as 0 and any non-trivial truncation - * is correctly encoded as a value between 1 and 63. */ -#define PSA_ALG_MAC_TRUNCATION_MASK ((psa_algorithm_t) 0x003f0000) -#define PSA_MAC_TRUNCATION_OFFSET 16 - -/* In the encoding of a MAC algorithm, the bit corresponding to - * #PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm - * is a wildcard algorithm. A key with such wildcard algorithm as permitted - * algorithm policy can be used with any algorithm corresponding to the - * same base class and having a (potentially truncated) MAC length greater or - * equal than the one encoded in #PSA_ALG_MAC_TRUNCATION_MASK. */ -#define PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) - -/** Macro to build a truncated MAC algorithm. - * - * A truncated MAC algorithm is identical to the corresponding MAC - * algorithm except that the MAC value for the truncated algorithm - * consists of only the first \p mac_length bytes of the MAC value - * for the untruncated algorithm. - * - * \note This macro may allow constructing algorithm identifiers that - * are not valid, either because the specified length is larger - * than the untruncated MAC or because the specified length is - * smaller than permitted by the implementation. - * - * \note It is implementation-defined whether a truncated MAC that - * is truncated to the same length as the MAC of the untruncated - * algorithm is considered identical to the untruncated algorithm - * for policy comparison purposes. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). This may be a truncated or untruncated - * MAC algorithm. - * \param mac_length Desired length of the truncated MAC in bytes. - * This must be at most the full length of the MAC - * and must be at least an implementation-specified - * minimum. The implementation-specified minimum - * shall not be zero. - * - * \return The corresponding MAC algorithm with the specified - * length. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm or if \p mac_length is too small or - * too large for the specified MAC algorithm. - */ -#define PSA_ALG_TRUNCATED_MAC(mac_alg, mac_length) \ - (((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) | \ - ((mac_length) << PSA_MAC_TRUNCATION_OFFSET & PSA_ALG_MAC_TRUNCATION_MASK)) - -/** Macro to build the base MAC algorithm corresponding to a truncated - * MAC algorithm. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). This may be a truncated or untruncated - * MAC algorithm. - * - * \return The corresponding base MAC algorithm. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm. - */ -#define PSA_ALG_FULL_LENGTH_MAC(mac_alg) \ - ((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) - -/** Length to which a MAC algorithm is truncated. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). - * - * \return Length of the truncated MAC in bytes. - * \return 0 if \p mac_alg is a non-truncated MAC algorithm. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm. - */ -#define PSA_MAC_TRUNCATED_LENGTH(mac_alg) \ - (((mac_alg) & PSA_ALG_MAC_TRUNCATION_MASK) >> PSA_MAC_TRUNCATION_OFFSET) - -/** Macro to build a MAC minimum-MAC-length wildcard algorithm. - * - * A minimum-MAC-length MAC wildcard algorithm permits all MAC algorithms - * sharing the same base algorithm, and where the (potentially truncated) MAC - * length of the specific algorithm is equal to or larger then the wildcard - * algorithm's minimum MAC length. - * - * \note When setting the minimum required MAC length to less than the - * smallest MAC length allowed by the base algorithm, this effectively - * becomes an 'any-MAC-length-allowed' policy for that base algorithm. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). - * \param min_mac_length Desired minimum length of the message authentication - * code in bytes. This must be at most the untruncated - * length of the MAC and must be at least 1. - * - * \return The corresponding MAC wildcard algorithm with the - * specified minimum length. - * \return Unspecified if \p mac_alg is not a supported MAC - * algorithm or if \p min_mac_length is less than 1 or - * too large for the specified MAC algorithm. - */ -#define PSA_ALG_AT_LEAST_THIS_LENGTH_MAC(mac_alg, min_mac_length) \ - (PSA_ALG_TRUNCATED_MAC(mac_alg, min_mac_length) | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) - -#define PSA_ALG_CIPHER_MAC_BASE ((psa_algorithm_t) 0x03c00000) -/** The CBC-MAC construction over a block cipher - * - * \warning CBC-MAC is insecure in many cases. - * A more secure mode, such as #PSA_ALG_CMAC, is recommended. - */ -#define PSA_ALG_CBC_MAC ((psa_algorithm_t) 0x03c00100) -/** The CMAC construction over a block cipher */ -#define PSA_ALG_CMAC ((psa_algorithm_t) 0x03c00200) - -/** Whether the specified algorithm is a MAC algorithm based on a block cipher. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a MAC algorithm based on a block cipher, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ - PSA_ALG_CIPHER_MAC_BASE) - -#define PSA_ALG_CIPHER_STREAM_FLAG ((psa_algorithm_t) 0x00800000) -#define PSA_ALG_CIPHER_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) - -/** Whether the specified algorithm is a stream cipher. - * - * A stream cipher is a symmetric cipher that encrypts or decrypts messages - * by applying a bitwise-xor with a stream of bytes that is generated - * from a key. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a stream cipher algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier or if it is not a symmetric cipher algorithm. - */ -#define PSA_ALG_IS_STREAM_CIPHER(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_CIPHER_STREAM_FLAG)) == \ - (PSA_ALG_CATEGORY_CIPHER | PSA_ALG_CIPHER_STREAM_FLAG)) - -/** The stream cipher mode of a stream cipher algorithm. - * - * The underlying stream cipher is determined by the key type. - * - To use ChaCha20, use a key type of #PSA_KEY_TYPE_CHACHA20. - */ -#define PSA_ALG_STREAM_CIPHER ((psa_algorithm_t) 0x04800100) - -/** The CTR stream cipher mode. - * - * CTR is a stream cipher which is built from a block cipher. - * The underlying block cipher is determined by the key type. - * For example, to use AES-128-CTR, use this algorithm with - * a key of type #PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). - */ -#define PSA_ALG_CTR ((psa_algorithm_t) 0x04c01000) - -/** The CFB stream cipher mode. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_CFB ((psa_algorithm_t) 0x04c01100) - -/** The OFB stream cipher mode. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_OFB ((psa_algorithm_t) 0x04c01200) - -/** The XTS cipher mode. - * - * XTS is a cipher mode which is built from a block cipher. It requires at - * least one full block of input, but beyond this minimum the input - * does not need to be a whole number of blocks. - */ -#define PSA_ALG_XTS ((psa_algorithm_t) 0x0440ff00) - -/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. - * - * \warning ECB mode does not protect the confidentiality of the encrypted data - * except in extremely narrow circumstances. It is recommended that applications - * only use ECB if they need to construct an operating mode that the - * implementation does not provide. Implementations are encouraged to provide - * the modes that applications need in preference to supporting direct access - * to ECB. - * - * The underlying block cipher is determined by the key type. - * - * This symmetric cipher mode can only be used with messages whose lengths are a - * multiple of the block size of the chosen block cipher. - * - * ECB mode does not accept an initialization vector (IV). When using a - * multi-part cipher operation with this algorithm, psa_cipher_generate_iv() - * and psa_cipher_set_iv() must not be called. - */ -#define PSA_ALG_ECB_NO_PADDING ((psa_algorithm_t) 0x04404400) - -/** The CBC block cipher chaining mode, with no padding. - * - * The underlying block cipher is determined by the key type. - * - * This symmetric cipher mode can only be used with messages whose lengths - * are whole number of blocks for the chosen block cipher. - */ -#define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t) 0x04404000) - -/** The CBC block cipher chaining mode with PKCS#7 padding. - * - * The underlying block cipher is determined by the key type. - * - * This is the padding method defined by PKCS#7 (RFC 2315) §10.3. - */ -#define PSA_ALG_CBC_PKCS7 ((psa_algorithm_t) 0x04404100) - -#define PSA_ALG_AEAD_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) - -/** Whether the specified algorithm is an AEAD mode on a block cipher. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an AEAD algorithm which is an AEAD mode based on - * a block cipher, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) == \ - (PSA_ALG_CATEGORY_AEAD | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) - -/** The CCM authenticated encryption algorithm. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_CCM ((psa_algorithm_t) 0x05500100) - -/** The CCM* cipher mode without authentication. - * - * This is CCM* as specified in IEEE 802.15.4 §7, with a tag length of 0. - * For CCM* with a nonzero tag length, use the AEAD algorithm #PSA_ALG_CCM. - * - * The underlying block cipher is determined by the key type. - * - * Currently only 13-byte long IV's are supported. - */ -#define PSA_ALG_CCM_STAR_NO_TAG ((psa_algorithm_t) 0x04c01300) - -/** The GCM authenticated encryption algorithm. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_GCM ((psa_algorithm_t) 0x05500200) - -/** The Chacha20-Poly1305 AEAD algorithm. - * - * The ChaCha20_Poly1305 construction is defined in RFC 7539. - * - * Implementations must support 12-byte nonces, may support 8-byte nonces, - * and should reject other sizes. - * - * Implementations must support 16-byte tags and should reject other sizes. - */ -#define PSA_ALG_CHACHA20_POLY1305 ((psa_algorithm_t) 0x05100500) - -/* In the encoding of an AEAD algorithm, the bits corresponding to - * PSA_ALG_AEAD_TAG_LENGTH_MASK encode the length of the AEAD tag. - * The constants for default lengths follow this encoding. - */ -#define PSA_ALG_AEAD_TAG_LENGTH_MASK ((psa_algorithm_t) 0x003f0000) -#define PSA_AEAD_TAG_LENGTH_OFFSET 16 - -/* In the encoding of an AEAD algorithm, the bit corresponding to - * #PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm - * is a wildcard algorithm. A key with such wildcard algorithm as permitted - * algorithm policy can be used with any algorithm corresponding to the - * same base class and having a tag length greater than or equal to the one - * encoded in #PSA_ALG_AEAD_TAG_LENGTH_MASK. */ -#define PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) - -/** Macro to build a shortened AEAD algorithm. - * - * A shortened AEAD algorithm is similar to the corresponding AEAD - * algorithm, but has an authentication tag that consists of fewer bytes. - * Depending on the algorithm, the tag length may affect the calculation - * of the ciphertext. - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) - * is true). - * \param tag_length Desired length of the authentication tag in bytes. - * - * \return The corresponding AEAD algorithm with the specified - * length. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm or if \p tag_length is not valid - * for the specified AEAD algorithm. - */ -#define PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, tag_length) \ - (((aead_alg) & ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | \ - PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG)) | \ - ((tag_length) << PSA_AEAD_TAG_LENGTH_OFFSET & \ - PSA_ALG_AEAD_TAG_LENGTH_MASK)) - -/** Retrieve the tag length of a specified AEAD algorithm - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) - * is true). - * - * \return The tag length specified by the input algorithm. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm. - */ -#define PSA_ALG_AEAD_GET_TAG_LENGTH(aead_alg) \ - (((aead_alg) & PSA_ALG_AEAD_TAG_LENGTH_MASK) >> \ - PSA_AEAD_TAG_LENGTH_OFFSET) - -/** Calculate the corresponding AEAD algorithm with the default tag length. - * - * \param aead_alg An AEAD algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p aead_alg) is true). - * - * \return The corresponding AEAD algorithm with the default - * tag length for that algorithm. - */ -#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(aead_alg) \ - ( \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CCM) \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_GCM) \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CHACHA20_POLY1305) \ - 0) -#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, ref) \ - PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, 0) == \ - PSA_ALG_AEAD_WITH_SHORTENED_TAG(ref, 0) ? \ - ref : - -/** Macro to build an AEAD minimum-tag-length wildcard algorithm. - * - * A minimum-tag-length AEAD wildcard algorithm permits all AEAD algorithms - * sharing the same base algorithm, and where the tag length of the specific - * algorithm is equal to or larger then the minimum tag length specified by the - * wildcard algorithm. - * - * \note When setting the minimum required tag length to less than the - * smallest tag length allowed by the base algorithm, this effectively - * becomes an 'any-tag-length-allowed' policy for that base algorithm. - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that - * #PSA_ALG_IS_AEAD(\p aead_alg) is true). - * \param min_tag_length Desired minimum length of the authentication tag in - * bytes. This must be at least 1 and at most the largest - * allowed tag length of the algorithm. - * - * \return The corresponding AEAD wildcard algorithm with the - * specified minimum length. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm or if \p min_tag_length is less than 1 - * or too large for the specified AEAD algorithm. - */ -#define PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG(aead_alg, min_tag_length) \ - (PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, min_tag_length) | \ - PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) - -#define PSA_ALG_RSA_PKCS1V15_SIGN_BASE ((psa_algorithm_t) 0x06000200) -/** RSA PKCS#1 v1.5 signature with hashing. - * - * This is the signature scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSASSA-PKCS1-v1_5. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PKCS#1 v1.5 signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PKCS1V15_SIGN(hash_alg) \ - (PSA_ALG_RSA_PKCS1V15_SIGN_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Raw PKCS#1 v1.5 signature. - * - * The input to this algorithm is the DigestInfo structure used by - * RFC 8017 (PKCS#1: RSA Cryptography Specifications), §9.2 - * steps 3–6. - */ -#define PSA_ALG_RSA_PKCS1V15_SIGN_RAW PSA_ALG_RSA_PKCS1V15_SIGN_BASE -#define PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PKCS1V15_SIGN_BASE) - -#define PSA_ALG_RSA_PSS_BASE ((psa_algorithm_t) 0x06000300) -#define PSA_ALG_RSA_PSS_ANY_SALT_BASE ((psa_algorithm_t) 0x06001300) -/** RSA PSS signature with hashing. - * - * This is the signature scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSASSA-PSS, with the message generation function MGF1, and with - * a salt length equal to the length of the hash, or the largest - * possible salt length for the algorithm and key size if that is - * smaller than the hash length. The specified hash algorithm is - * used to hash the input message, to create the salted hash, and - * for the mask generation. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PSS signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PSS(hash_alg) \ - (PSA_ALG_RSA_PSS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** RSA PSS signature with hashing with relaxed verification. - * - * This algorithm has the same behavior as #PSA_ALG_RSA_PSS when signing, - * but allows an arbitrary salt length (including \c 0) when verifying a - * signature. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PSS signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PSS_ANY_SALT(hash_alg) \ - (PSA_ALG_RSA_PSS_ANY_SALT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is RSA PSS with standard salt. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_BASE) - -/** Whether the specified algorithm is RSA PSS with any salt. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS_ANY_SALT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_ANY_SALT_BASE) - -/** Whether the specified algorithm is RSA PSS. - * - * This includes any of the RSA PSS algorithm variants, regardless of the - * constraints on salt length. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS(\c hash_alg) or - * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS(alg) \ - (PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) || \ - PSA_ALG_IS_RSA_PSS_ANY_SALT(alg)) - -#define PSA_ALG_ECDSA_BASE ((psa_algorithm_t) 0x06000600) -/** ECDSA signature with hashing. - * - * This is the ECDSA signature scheme defined by ANSI X9.62, - * with a random per-message secret number (*k*). - * - * The representation of the signature as a byte string consists of - * the concatenation of the signature values *r* and *s*. Each of - * *r* and *s* is encoded as an *N*-octet string, where *N* is the length - * of the base point of the curve in octets. Each value is represented - * in big-endian order (most significant octet first). - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding ECDSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_ECDSA(hash_alg) \ - (PSA_ALG_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** ECDSA signature without hashing. - * - * This is the same signature scheme as #PSA_ALG_ECDSA(), but - * without specifying a hash algorithm. This algorithm may only be - * used to sign or verify a sequence of bytes that should be an - * already-calculated hash. Note that the input is padded with - * zeros on the left or truncated on the left as required to fit - * the curve size. - */ -#define PSA_ALG_ECDSA_ANY PSA_ALG_ECDSA_BASE -#define PSA_ALG_DETERMINISTIC_ECDSA_BASE ((psa_algorithm_t) 0x06000700) -/** Deterministic ECDSA signature with hashing. - * - * This is the deterministic ECDSA signature scheme defined by RFC 6979. - * - * The representation of a signature is the same as with #PSA_ALG_ECDSA(). - * - * Note that when this algorithm is used for verification, signatures - * made with randomized ECDSA (#PSA_ALG_ECDSA(\p hash_alg)) with the - * same private key are accepted. In other words, - * #PSA_ALG_DETERMINISTIC_ECDSA(\p hash_alg) differs from - * #PSA_ALG_ECDSA(\p hash_alg) only for signature, not for verification. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding deterministic ECDSA signature - * algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DETERMINISTIC_ECDSA(hash_alg) \ - (PSA_ALG_DETERMINISTIC_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t) 0x00000100) -#define PSA_ALG_IS_ECDSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_ECDSA_DETERMINISTIC_FLAG) == \ - PSA_ALG_ECDSA_BASE) -#define PSA_ALG_ECDSA_IS_DETERMINISTIC(alg) \ - (((alg) & PSA_ALG_ECDSA_DETERMINISTIC_FLAG) != 0) -#define PSA_ALG_IS_DETERMINISTIC_ECDSA(alg) \ - (PSA_ALG_IS_ECDSA(alg) && PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) -#define PSA_ALG_IS_RANDOMIZED_ECDSA(alg) \ - (PSA_ALG_IS_ECDSA(alg) && !PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) - -/** Edwards-curve digital signature algorithm without prehashing (PureEdDSA), - * using standard parameters. - * - * Contexts are not supported in the current version of this specification - * because there is no suitable signature interface that can take the - * context as a parameter. A future version of this specification may add - * suitable functions and extend this algorithm to support contexts. - * - * PureEdDSA requires an elliptic curve key on a twisted Edwards curve. - * In this specification, the following curves are supported: - * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 255-bit: Ed25519 as specified - * in RFC 8032. - * The curve is Edwards25519. - * The hash function used internally is SHA-512. - * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 448-bit: Ed448 as specified - * in RFC 8032. - * The curve is Edwards448. - * The hash function used internally is the first 114 bytes of the - * SHAKE256 output. - * - * This algorithm can be used with psa_sign_message() and - * psa_verify_message(). Since there is no prehashing, it cannot be used - * with psa_sign_hash() or psa_verify_hash(). - * - * The signature format is the concatenation of R and S as defined by - * RFC 8032 §5.1.6 and §5.2.6 (a 64-byte string for Ed25519, a 114-byte - * string for Ed448). - */ -#define PSA_ALG_PURE_EDDSA ((psa_algorithm_t) 0x06000800) - -#define PSA_ALG_HASH_EDDSA_BASE ((psa_algorithm_t) 0x06000900) -#define PSA_ALG_IS_HASH_EDDSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HASH_EDDSA_BASE) - -/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), - * using SHA-512 and the Edwards25519 curve. - * - * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. - * - * This algorithm is Ed25519 as specified in RFC 8032. - * The curve is Edwards25519. - * The prehash is SHA-512. - * The hash function used internally is SHA-512. - * - * This is a hash-and-sign algorithm: to calculate a signature, - * you can either: - * - call psa_sign_message() on the message; - * - or calculate the SHA-512 hash of the message - * with psa_hash_compute() - * or with a multi-part hash operation started with psa_hash_setup(), - * using the hash algorithm #PSA_ALG_SHA_512, - * then sign the calculated hash with psa_sign_hash(). - * Verifying a signature is similar, using psa_verify_message() or - * psa_verify_hash() instead of the signature function. - */ -#define PSA_ALG_ED25519PH \ - (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHA_512 & PSA_ALG_HASH_MASK)) - -/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), - * using SHAKE256 and the Edwards448 curve. - * - * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. - * - * This algorithm is Ed448 as specified in RFC 8032. - * The curve is Edwards448. - * The prehash is the first 64 bytes of the SHAKE256 output. - * The hash function used internally is the first 114 bytes of the - * SHAKE256 output. - * - * This is a hash-and-sign algorithm: to calculate a signature, - * you can either: - * - call psa_sign_message() on the message; - * - or calculate the first 64 bytes of the SHAKE256 output of the message - * with psa_hash_compute() - * or with a multi-part hash operation started with psa_hash_setup(), - * using the hash algorithm #PSA_ALG_SHAKE256_512, - * then sign the calculated hash with psa_sign_hash(). - * Verifying a signature is similar, using psa_verify_message() or - * psa_verify_hash() instead of the signature function. - */ -#define PSA_ALG_ED448PH \ - (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHAKE256_512 & PSA_ALG_HASH_MASK)) - -/* Default definition, to be overridden if the library is extended with - * more hash-and-sign algorithms that we want to keep out of this header - * file. */ -#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) 0 - -/** Whether the specified algorithm is a signature algorithm that can be used - * with psa_sign_hash() and psa_verify_hash(). - * - * This encompasses all strict hash-and-sign algorithms categorized by - * PSA_ALG_IS_HASH_AND_SIGN(), as well as algorithms that follow the - * paradigm more loosely: - * - #PSA_ALG_RSA_PKCS1V15_SIGN_RAW (expects its input to be an encoded hash) - * - #PSA_ALG_ECDSA_ANY (doesn't specify what kind of hash the input is) - * - * \param alg An algorithm identifier (value of type psa_algorithm_t). - * - * \return 1 if alg is a signature algorithm that can be used to sign a - * hash. 0 if alg is a signature algorithm that can only be used - * to sign a message. 0 if alg is not a signature algorithm. - * This macro can return either 0 or 1 if alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_SIGN_HASH(alg) \ - (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || \ - PSA_ALG_IS_ECDSA(alg) || PSA_ALG_IS_HASH_EDDSA(alg) || \ - PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg)) - -/** Whether the specified algorithm is a signature algorithm that can be used - * with psa_sign_message() and psa_verify_message(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if alg is a signature algorithm that can be used to sign a - * message. 0 if \p alg is a signature algorithm that can only be used - * to sign an already-calculated hash. 0 if \p alg is not a signature - * algorithm. This macro can return either 0 or 1 if \p alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_SIGN_MESSAGE(alg) \ - (PSA_ALG_IS_SIGN_HASH(alg) || (alg) == PSA_ALG_PURE_EDDSA) - -/** Whether the specified algorithm is a hash-and-sign algorithm. - * - * Hash-and-sign algorithms are asymmetric (public-key) signature algorithms - * structured in two parts: first the calculation of a hash in a way that - * does not depend on the key, then the calculation of a signature from the - * hash value and the key. Hash-and-sign algorithms encode the hash - * used for the hashing step, and you can call #PSA_ALG_SIGN_GET_HASH - * to extract this algorithm. - * - * Thus, for a hash-and-sign algorithm, - * `psa_sign_message(key, alg, input, ...)` is equivalent to - * ``` - * psa_hash_compute(PSA_ALG_SIGN_GET_HASH(alg), input, ..., hash, ...); - * psa_sign_hash(key, alg, hash, ..., signature, ...); - * ``` - * Most usefully, separating the hash from the signature allows the hash - * to be calculated in multiple steps with psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(). Likewise psa_verify_message() is equivalent to - * calculating the hash and then calling psa_verify_hash(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a hash-and-sign algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HASH_AND_SIGN(alg) \ - (PSA_ALG_IS_SIGN_HASH(alg) && \ - ((alg) & PSA_ALG_HASH_MASK) != 0) - -/** Get the hash used by a hash-and-sign signature algorithm. - * - * A hash-and-sign algorithm is a signature algorithm which is - * composed of two phases: first a hashing phase which does not use - * the key and produces a hash of the input message, then a signing - * phase which only uses the hash and the key and not the message - * itself. - * - * \param alg A signature algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_SIGN(\p alg) is true). - * - * \return The underlying hash algorithm if \p alg is a hash-and-sign - * algorithm. - * \return 0 if \p alg is a signature algorithm that does not - * follow the hash-and-sign structure. - * \return Unspecified if \p alg is not a signature algorithm or - * if it is not supported by the implementation. - */ -#define PSA_ALG_SIGN_GET_HASH(alg) \ - (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ - ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ - 0) - -/** RSA PKCS#1 v1.5 encryption. - * - * \warning Calling psa_asymmetric_decrypt() with this algorithm as a - * parameter is considered an inherently dangerous function - * (CWE-242). Unless it is used in a side channel free and safe - * way (eg. implementing the TLS protocol as per 7.4.7.1 of - * RFC 5246), the calling code is vulnerable. - * - */ -#define PSA_ALG_RSA_PKCS1V15_CRYPT ((psa_algorithm_t) 0x07000200) - -#define PSA_ALG_RSA_OAEP_BASE ((psa_algorithm_t) 0x07000300) -/** RSA OAEP encryption. - * - * This is the encryption scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSAES-OAEP, with the message generation function MGF1. - * - * \param hash_alg The hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true) to use - * for MGF1. - * - * \return The corresponding RSA OAEP encryption algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_OAEP(hash_alg) \ - (PSA_ALG_RSA_OAEP_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_IS_RSA_OAEP(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_OAEP_BASE) -#define PSA_ALG_RSA_OAEP_GET_HASH(alg) \ - (PSA_ALG_IS_RSA_OAEP(alg) ? \ - ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ - 0) - -#define PSA_ALG_HKDF_BASE ((psa_algorithm_t) 0x08000100) -/** Macro to build an HKDF algorithm. - * - * For example, `PSA_ALG_HKDF(PSA_ALG_SHA_256)` is HKDF using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt used in the "extract" step. - * It is optional; if omitted, the derivation uses an empty salt. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key used in the "extract" step. - * - #PSA_KEY_DERIVATION_INPUT_INFO is the info string used in the "expand" step. - * You must pass #PSA_KEY_DERIVATION_INPUT_SALT before #PSA_KEY_DERIVATION_INPUT_SECRET. - * You may pass #PSA_KEY_DERIVATION_INPUT_INFO at any time after steup and before - * starting to generate output. - * - * \warning HKDF processes the salt as follows: first hash it with hash_alg - * if the salt is longer than the block size of the hash algorithm; then - * pad with null bytes up to the block size. As a result, it is possible - * for distinct salt inputs to result in the same outputs. To ensure - * unique outputs, it is recommended to use a fixed length for salt values. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF(hash_alg) \ - (PSA_ALG_HKDF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF algorithm. - * - * HKDF is a family of key derivation algorithms that are based on a hash - * function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE) -#define PSA_ALG_HKDF_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_HKDF_EXTRACT_BASE ((psa_algorithm_t) 0x08000400) -/** Macro to build an HKDF-Extract algorithm. - * - * For example, `PSA_ALG_HKDF_EXTRACT(PSA_ALG_SHA_256)` is - * HKDF-Extract using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - PSA_KEY_DERIVATION_INPUT_SALT is the salt. - * - PSA_KEY_DERIVATION_INPUT_SECRET is the input keying material used in the - * "extract" step. - * The inputs are mandatory and must be passed in the order above. - * Each input may only be passed once. - * - * \warning HKDF-Extract is not meant to be used on its own. PSA_ALG_HKDF - * should be used instead if possible. PSA_ALG_HKDF_EXTRACT is provided - * as a separate algorithm for the sake of protocols that use it as a - * building block. It may also be a slight performance optimization - * in applications that use HKDF with the same salt and key but many - * different info strings. - * - * \warning HKDF processes the salt as follows: first hash it with hash_alg - * if the salt is longer than the block size of the hash algorithm; then - * pad with null bytes up to the block size. As a result, it is possible - * for distinct salt inputs to result in the same outputs. To ensure - * unique outputs, it is recommended to use a fixed length for salt values. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF-Extract algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF_EXTRACT(hash_alg) \ - (PSA_ALG_HKDF_EXTRACT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF-Extract algorithm. - * - * HKDF-Extract is a family of key derivation algorithms that are based - * on a hash function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF-Extract algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF_EXTRACT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE) - -#define PSA_ALG_HKDF_EXPAND_BASE ((psa_algorithm_t) 0x08000500) -/** Macro to build an HKDF-Expand algorithm. - * - * For example, `PSA_ALG_HKDF_EXPAND(PSA_ALG_SHA_256)` is - * HKDF-Expand using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - PSA_KEY_DERIVATION_INPUT_SECRET is the pseudorandom key (PRK). - * - PSA_KEY_DERIVATION_INPUT_INFO is the info string. - * - * The inputs are mandatory and must be passed in the order above. - * Each input may only be passed once. - * - * \warning HKDF-Expand is not meant to be used on its own. `PSA_ALG_HKDF` - * should be used instead if possible. `PSA_ALG_HKDF_EXPAND` is provided as - * a separate algorithm for the sake of protocols that use it as a building - * block. It may also be a slight performance optimization in applications - * that use HKDF with the same salt and key but many different info strings. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF-Expand algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF_EXPAND(hash_alg) \ - (PSA_ALG_HKDF_EXPAND_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF-Expand algorithm. - * - * HKDF-Expand is a family of key derivation algorithms that are based - * on a hash function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF-Expand algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF_EXPAND(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) - -/** Whether the specified algorithm is an HKDF or HKDF-Extract or - * HKDF-Expand algorithm. - * - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is any HKDF type algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_ANY_HKDF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE || \ - ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE || \ - ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) - -#define PSA_ALG_TLS12_PRF_BASE ((psa_algorithm_t) 0x08000200) -/** Macro to build a TLS-1.2 PRF algorithm. - * - * TLS 1.2 uses a custom pseudorandom function (PRF) for key schedule, - * specified in Section 5 of RFC 5246. It is based on HMAC and can be - * used with either SHA-256 or SHA-384. - * - * This key derivation algorithm uses the following inputs, which must be - * passed in the order given here: - * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. - * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. - * - * For the application to TLS-1.2 key expansion, the seed is the - * concatenation of ServerHello.Random + ClientHello.Random, - * and the label is "key expansion". - * - * For example, `PSA_ALG_TLS12_PRF(PSA_ALG_SHA_256)` represents the - * TLS 1.2 PRF using HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding TLS-1.2 PRF algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_TLS12_PRF(hash_alg) \ - (PSA_ALG_TLS12_PRF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a TLS-1.2 PRF algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a TLS-1.2 PRF algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_TLS12_PRF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PRF_BASE) -#define PSA_ALG_TLS12_PRF_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_TLS12_PSK_TO_MS_BASE ((psa_algorithm_t) 0x08000300) -/** Macro to build a TLS-1.2 PSK-to-MasterSecret algorithm. - * - * In a pure-PSK handshake in TLS 1.2, the master secret is derived - * from the PreSharedKey (PSK) through the application of padding - * (RFC 4279, Section 2) and the TLS-1.2 PRF (RFC 5246, Section 5). - * The latter is based on HMAC and can be used with either SHA-256 - * or SHA-384. - * - * This key derivation algorithm uses the following inputs, which must be - * passed in the order given here: - * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. - * - #PSA_KEY_DERIVATION_INPUT_OTHER_SECRET is the other secret for the - * computation of the premaster secret. This input is optional; - * if omitted, it defaults to a string of null bytes with the same length - * as the secret (PSK) input. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. - * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. - * - * For the application to TLS-1.2, the seed (which is - * forwarded to the TLS-1.2 PRF) is the concatenation of the - * ClientHello.Random + ServerHello.Random, - * the label is "master secret" or "extended master secret" and - * the other secret depends on the key exchange specified in the cipher suite: - * - for a plain PSK cipher suite (RFC 4279, Section 2), omit - * PSA_KEY_DERIVATION_INPUT_OTHER_SECRET - * - for a DHE-PSK (RFC 4279, Section 3) or ECDHE-PSK cipher suite - * (RFC 5489, Section 2), the other secret should be the output of the - * PSA_ALG_FFDH or PSA_ALG_ECDH key agreement performed with the peer. - * The recommended way to pass this input is to use a key derivation - * algorithm constructed as - * PSA_ALG_KEY_AGREEMENT(ka_alg, PSA_ALG_TLS12_PSK_TO_MS(hash_alg)) - * and to call psa_key_derivation_key_agreement(). Alternatively, - * this input may be an output of `psa_raw_key_agreement()` passed with - * psa_key_derivation_input_bytes(), or an equivalent input passed with - * psa_key_derivation_input_bytes() or psa_key_derivation_input_key(). - * - for a RSA-PSK cipher suite (RFC 4279, Section 4), the other secret - * should be the 48-byte client challenge (the PreMasterSecret of - * (RFC 5246, Section 7.4.7.1)) concatenation of the TLS version and - * a 46-byte random string chosen by the client. On the server, this is - * typically an output of psa_asymmetric_decrypt() using - * PSA_ALG_RSA_PKCS1V15_CRYPT, passed to the key derivation operation - * with `psa_key_derivation_input_bytes()`. - * - * For example, `PSA_ALG_TLS12_PSK_TO_MS(PSA_ALG_SHA_256)` represents the - * TLS-1.2 PSK to MasterSecret derivation PRF using HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding TLS-1.2 PSK to MS algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_TLS12_PSK_TO_MS(hash_alg) \ - (PSA_ALG_TLS12_PSK_TO_MS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a TLS-1.2 PSK to MS algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a TLS-1.2 PSK to MS algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_TLS12_PSK_TO_MS(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PSK_TO_MS_BASE) -#define PSA_ALG_TLS12_PSK_TO_MS_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -/* The TLS 1.2 ECJPAKE-to-PMS KDF. It takes the shared secret K (an EC point - * in case of EC J-PAKE) and calculates SHA256(K.X) that the rest of TLS 1.2 - * will use to derive the session secret, as defined by step 2 of - * https://datatracker.ietf.org/doc/html/draft-cragie-tls-ecjpake-01#section-8.7. - * Uses PSA_ALG_SHA_256. - * This function takes a single input: - * #PSA_KEY_DERIVATION_INPUT_SECRET is the shared secret K from EC J-PAKE. - * The only supported curve is secp256r1 (the 256-bit curve in - * #PSA_ECC_FAMILY_SECP_R1), so the input must be exactly 65 bytes. - * The output has to be read as a single chunk of 32 bytes, defined as - * PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE. - */ -#define PSA_ALG_TLS12_ECJPAKE_TO_PMS ((psa_algorithm_t) 0x08000609) - -/* This flag indicates whether the key derivation algorithm is suitable for - * use on low-entropy secrets such as password - these algorithms are also - * known as key stretching or password hashing schemes. These are also the - * algorithms that accepts inputs of type #PSA_KEY_DERIVATION_INPUT_PASSWORD. - * - * Those algorithms cannot be combined with a key agreement algorithm. - */ -#define PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG ((psa_algorithm_t) 0x00800000) - -#define PSA_ALG_PBKDF2_HMAC_BASE ((psa_algorithm_t) 0x08800100) -/** Macro to build a PBKDF2-HMAC password hashing / key stretching algorithm. - * - * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). - * This macro specifies the PBKDF2 algorithm constructed using a PRF based on - * HMAC with the specified hash. - * For example, `PSA_ALG_PBKDF2_HMAC(PSA_ALG_SHA_256)` specifies PBKDF2 - * using the PRF HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs, which must be - * provided in the following order: - * - #PSA_KEY_DERIVATION_INPUT_COST is the iteration count. - * This input step must be used exactly once. - * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt. - * This input step must be used one or more times; if used several times, the - * inputs will be concatenated. This can be used to build the final salt - * from multiple sources, both public and secret (also known as pepper). - * - #PSA_KEY_DERIVATION_INPUT_PASSWORD is the password to be hashed. - * This input step must be used exactly once. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding PBKDF2-HMAC-XXX algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_PBKDF2_HMAC(hash_alg) \ - (PSA_ALG_PBKDF2_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a PBKDF2-HMAC algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a PBKDF2-HMAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_PBKDF2_HMAC(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_PBKDF2_HMAC_BASE) -#define PSA_ALG_PBKDF2_HMAC_GET_HASH(pbkdf2_alg) \ - (PSA_ALG_CATEGORY_HASH | ((pbkdf2_alg) & PSA_ALG_HASH_MASK)) -/** The PBKDF2-AES-CMAC-PRF-128 password hashing / key stretching algorithm. - * - * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). - * This macro specifies the PBKDF2 algorithm constructed using the - * AES-CMAC-PRF-128 PRF specified by RFC 4615. - * - * This key derivation algorithm uses the same inputs as - * #PSA_ALG_PBKDF2_HMAC() with the same constraints. - */ -#define PSA_ALG_PBKDF2_AES_CMAC_PRF_128 ((psa_algorithm_t) 0x08800200) - -#define PSA_ALG_IS_PBKDF2(kdf_alg) \ - (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg) || \ - ((kdf_alg) == PSA_ALG_PBKDF2_AES_CMAC_PRF_128)) - -#define PSA_ALG_KEY_DERIVATION_MASK ((psa_algorithm_t) 0xfe00ffff) -#define PSA_ALG_KEY_AGREEMENT_MASK ((psa_algorithm_t) 0xffff0000) - -/** Macro to build a combined algorithm that chains a key agreement with - * a key derivation. - * - * \param ka_alg A key agreement algorithm (\c PSA_ALG_XXX value such - * that #PSA_ALG_IS_KEY_AGREEMENT(\p ka_alg) is true). - * \param kdf_alg A key derivation algorithm (\c PSA_ALG_XXX value such - * that #PSA_ALG_IS_KEY_DERIVATION(\p kdf_alg) is true). - * - * \return The corresponding key agreement and derivation - * algorithm. - * \return Unspecified if \p ka_alg is not a supported - * key agreement algorithm or \p kdf_alg is not a - * supported key derivation algorithm. - */ -#define PSA_ALG_KEY_AGREEMENT(ka_alg, kdf_alg) \ - ((ka_alg) | (kdf_alg)) - -#define PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) \ - (((alg) & PSA_ALG_KEY_DERIVATION_MASK) | PSA_ALG_CATEGORY_KEY_DERIVATION) - -#define PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) \ - (((alg) & PSA_ALG_KEY_AGREEMENT_MASK) | PSA_ALG_CATEGORY_KEY_AGREEMENT) - -/** Whether the specified algorithm is a raw key agreement algorithm. - * - * A raw key agreement algorithm is one that does not specify - * a key derivation function. - * Usually, raw key agreement algorithms are constructed directly with - * a \c PSA_ALG_xxx macro while non-raw key agreement algorithms are - * constructed with #PSA_ALG_KEY_AGREEMENT(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a raw key agreement algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_RAW_KEY_AGREEMENT(alg) \ - (PSA_ALG_IS_KEY_AGREEMENT(alg) && \ - PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) == PSA_ALG_CATEGORY_KEY_DERIVATION) - -#define PSA_ALG_IS_KEY_DERIVATION_OR_AGREEMENT(alg) \ - ((PSA_ALG_IS_KEY_DERIVATION(alg) || PSA_ALG_IS_KEY_AGREEMENT(alg))) - -/** The finite-field Diffie-Hellman (DH) key agreement algorithm. - * - * The shared secret produced by key agreement is - * `g^{ab}` in big-endian format. - * It is `ceiling(m / 8)` bytes long where `m` is the size of the prime `p` - * in bits. - */ -#define PSA_ALG_FFDH ((psa_algorithm_t) 0x09010000) - -/** Whether the specified algorithm is a finite field Diffie-Hellman algorithm. - * - * This includes the raw finite field Diffie-Hellman algorithm as well as - * finite-field Diffie-Hellman followed by any supporter key derivation - * algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a finite field Diffie-Hellman algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key agreement algorithm identifier. - */ -#define PSA_ALG_IS_FFDH(alg) \ - (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_FFDH) - -/** The elliptic curve Diffie-Hellman (ECDH) key agreement algorithm. - * - * The shared secret produced by key agreement is the x-coordinate of - * the shared secret point. It is always `ceiling(m / 8)` bytes long where - * `m` is the bit size associated with the curve, i.e. the bit size of the - * order of the curve's coordinate field. When `m` is not a multiple of 8, - * the byte containing the most significant bit of the shared secret - * is padded with zero bits. The byte order is either little-endian - * or big-endian depending on the curve type. - * - * - For Montgomery curves (curve types `PSA_ECC_FAMILY_CURVEXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in little-endian byte order. - * The bit size is 448 for Curve448 and 255 for Curve25519. - * - For Weierstrass curves over prime fields (curve types - * `PSA_ECC_FAMILY_SECPXXX` and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in big-endian byte order. - * The bit size is `m = ceiling(log_2(p))` for the field `F_p`. - * - For Weierstrass curves over binary fields (curve types - * `PSA_ECC_FAMILY_SECTXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in big-endian byte order. - * The bit size is `m` for the field `F_{2^m}`. - */ -#define PSA_ALG_ECDH ((psa_algorithm_t) 0x09020000) - -/** Whether the specified algorithm is an elliptic curve Diffie-Hellman - * algorithm. - * - * This includes the raw elliptic curve Diffie-Hellman algorithm as well as - * elliptic curve Diffie-Hellman followed by any supporter key derivation - * algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an elliptic curve Diffie-Hellman algorithm, - * 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key agreement algorithm identifier. - */ -#define PSA_ALG_IS_ECDH(alg) \ - (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_ECDH) - -/** Whether the specified algorithm encoding is a wildcard. - * - * Wildcard values may only be used to set the usage algorithm field in - * a policy, not to perform an operation. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a wildcard algorithm encoding. - * \return 0 if \c alg is a non-wildcard algorithm encoding (suitable for - * an operation). - * \return This macro may return either 0 or 1 if \c alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_WILDCARD(alg) \ - (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ - PSA_ALG_SIGN_GET_HASH(alg) == PSA_ALG_ANY_HASH : \ - PSA_ALG_IS_MAC(alg) ? \ - (alg & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ - PSA_ALG_IS_AEAD(alg) ? \ - (alg & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ - (alg) == PSA_ALG_ANY_HASH) - -/** Get the hash used by a composite algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return The underlying hash algorithm if alg is a composite algorithm that - * uses a hash algorithm. - * - * \return \c 0 if alg is not a composite algorithm that uses a hash. - */ -#define PSA_ALG_GET_HASH(alg) \ - (((alg) & 0x000000ff) == 0 ? ((psa_algorithm_t) 0) : 0x02000000 | ((alg) & 0x000000ff)) - -/**@}*/ - -/** \defgroup key_lifetimes Key lifetimes - * @{ - */ - -/* Note that location and persistence level values are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** The default lifetime for volatile keys. - * - * A volatile key only exists as long as the identifier to it is not destroyed. - * The key material is guaranteed to be erased on a power reset. - * - * A key with this lifetime is typically stored in the RAM area of the - * PSA Crypto subsystem. However this is an implementation choice. - * If an implementation stores data about the key in a non-volatile memory, - * it must release all the resources associated with the key and erase the - * key material if the calling application terminates. - */ -#define PSA_KEY_LIFETIME_VOLATILE ((psa_key_lifetime_t) 0x00000000) - -/** The default lifetime for persistent keys. - * - * A persistent key remains in storage until it is explicitly destroyed or - * until the corresponding storage area is wiped. This specification does - * not define any mechanism to wipe a storage area, but integrations may - * provide their own mechanism (for example to perform a factory reset, - * to prepare for device refurbishment, or to uninstall an application). - * - * This lifetime value is the default storage area for the calling - * application. Integrations of Mbed TLS may support other persistent lifetimes. - * See ::psa_key_lifetime_t for more information. - */ -#define PSA_KEY_LIFETIME_PERSISTENT ((psa_key_lifetime_t) 0x00000001) - -/** The persistence level of volatile keys. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_VOLATILE ((psa_key_persistence_t) 0x00) - -/** The default persistence level for persistent keys. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_DEFAULT ((psa_key_persistence_t) 0x01) - -/** A persistence level indicating that a key is never destroyed. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_READ_ONLY ((psa_key_persistence_t) 0xff) - -#define PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) \ - ((psa_key_persistence_t) ((lifetime) & 0x000000ff)) - -#define PSA_KEY_LIFETIME_GET_LOCATION(lifetime) \ - ((psa_key_location_t) ((lifetime) >> 8)) - -/** Whether a key lifetime indicates that the key is volatile. - * - * A volatile key is automatically destroyed by the implementation when - * the application instance terminates. In particular, a volatile key - * is automatically destroyed on a power reset of the device. - * - * A key that is not volatile is persistent. Persistent keys are - * preserved until the application explicitly destroys them or until an - * implementation-specific device management event occurs (for example, - * a factory reset). - * - * \param lifetime The lifetime value to query (value of type - * ::psa_key_lifetime_t). - * - * \return \c 1 if the key is volatile, otherwise \c 0. - */ -#define PSA_KEY_LIFETIME_IS_VOLATILE(lifetime) \ - (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ - PSA_KEY_PERSISTENCE_VOLATILE) - -/** Whether a key lifetime indicates that the key is read-only. - * - * Read-only keys cannot be created or destroyed through the PSA Crypto API. - * They must be created through platform-specific means that bypass the API. - * - * Some platforms may offer ways to destroy read-only keys. For example, - * consider a platform with multiple levels of privilege, where a - * low-privilege application can use a key but is not allowed to destroy - * it, and the platform exposes the key to the application with a read-only - * lifetime. High-privilege code can destroy the key even though the - * application sees the key as read-only. - * - * \param lifetime The lifetime value to query (value of type - * ::psa_key_lifetime_t). - * - * \return \c 1 if the key is read-only, otherwise \c 0. - */ -#define PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime) \ - (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ - PSA_KEY_PERSISTENCE_READ_ONLY) - -/** Construct a lifetime from a persistence level and a location. - * - * \param persistence The persistence level - * (value of type ::psa_key_persistence_t). - * \param location The location indicator - * (value of type ::psa_key_location_t). - * - * \return The constructed lifetime value. - */ -#define PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location) \ - ((location) << 8 | (persistence)) - -/** The local storage area for persistent keys. - * - * This storage area is available on all systems that can store persistent - * keys without delegating the storage to a third-party cryptoprocessor. - * - * See ::psa_key_location_t for more information. - */ -#define PSA_KEY_LOCATION_LOCAL_STORAGE ((psa_key_location_t) 0x000000) - -#define PSA_KEY_LOCATION_VENDOR_FLAG ((psa_key_location_t) 0x800000) - -/* Note that key identifier values are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** The null key identifier. - */ -/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ -#define PSA_KEY_ID_NULL ((psa_key_id_t)0) -/* *INDENT-ON* */ -/** The minimum value for a key identifier chosen by the application. - */ -#define PSA_KEY_ID_USER_MIN ((psa_key_id_t) 0x00000001) -/** The maximum value for a key identifier chosen by the application. - */ -#define PSA_KEY_ID_USER_MAX ((psa_key_id_t) 0x3fffffff) -/** The minimum value for a key identifier chosen by the implementation. - */ -#define PSA_KEY_ID_VENDOR_MIN ((psa_key_id_t) 0x40000000) -/** The maximum value for a key identifier chosen by the implementation. - */ -#define PSA_KEY_ID_VENDOR_MAX ((psa_key_id_t) 0x7fffffff) - - -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - -#define MBEDTLS_SVC_KEY_ID_INIT ((psa_key_id_t) 0) -#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) (id) -#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) (0) - -/** Utility to initialize a key identifier at runtime. - * - * \param unused Unused parameter. - * \param key_id Identifier of the key. - */ -static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( - unsigned int unused, psa_key_id_t key_id) -{ - (void) unused; - - return key_id; -} - -/** Compare two key identifiers. - * - * \param id1 First key identifier. - * \param id2 Second key identifier. - * - * \return Non-zero if the two key identifier are equal, zero otherwise. - */ -static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, - mbedtls_svc_key_id_t id2) -{ - return id1 == id2; -} - -/** Check whether a key identifier is null. - * - * \param key Key identifier. - * - * \return Non-zero if the key identifier is null, zero otherwise. - */ -static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) -{ - return key == 0; -} - -#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -#define MBEDTLS_SVC_KEY_ID_INIT ((mbedtls_svc_key_id_t){ 0, 0 }) -#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) ((id).MBEDTLS_PRIVATE(key_id)) -#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) ((id).MBEDTLS_PRIVATE(owner)) - -/** Utility to initialize a key identifier at runtime. - * - * \param owner_id Identifier of the key owner. - * \param key_id Identifier of the key. - */ -static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( - mbedtls_key_owner_id_t owner_id, psa_key_id_t key_id) -{ - return (mbedtls_svc_key_id_t){ .MBEDTLS_PRIVATE(key_id) = key_id, - .MBEDTLS_PRIVATE(owner) = owner_id }; -} - -/** Compare two key identifiers. - * - * \param id1 First key identifier. - * \param id2 Second key identifier. - * - * \return Non-zero if the two key identifier are equal, zero otherwise. - */ -static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, - mbedtls_svc_key_id_t id2) -{ - return (id1.MBEDTLS_PRIVATE(key_id) == id2.MBEDTLS_PRIVATE(key_id)) && - mbedtls_key_owner_id_equal(id1.MBEDTLS_PRIVATE(owner), id2.MBEDTLS_PRIVATE(owner)); -} - -/** Check whether a key identifier is null. - * - * \param key Key identifier. - * - * \return Non-zero if the key identifier is null, zero otherwise. - */ -static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) -{ - return key.MBEDTLS_PRIVATE(key_id) == 0; -} - -#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/**@}*/ - -/** \defgroup policy Key policies - * @{ - */ - -/* Note that key usage flags are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** Whether the key may be exported. - * - * A public key or the public part of a key pair may always be exported - * regardless of the value of this permission flag. - * - * If a key does not have export permission, implementations shall not - * allow the key to be exported in plain form from the cryptoprocessor, - * whether through psa_export_key() or through a proprietary interface. - * The key may however be exportable in a wrapped form, i.e. in a form - * where it is encrypted by another key. - */ -#define PSA_KEY_USAGE_EXPORT ((psa_key_usage_t) 0x00000001) - -/** Whether the key may be copied. - * - * This flag allows the use of psa_copy_key() to make a copy of the key - * with the same policy or a more restrictive policy. - * - * For lifetimes for which the key is located in a secure element which - * enforce the non-exportability of keys, copying a key outside the secure - * element also requires the usage flag #PSA_KEY_USAGE_EXPORT. - * Copying the key inside the secure element is permitted with just - * #PSA_KEY_USAGE_COPY if the secure element supports it. - * For keys with the lifetime #PSA_KEY_LIFETIME_VOLATILE or - * #PSA_KEY_LIFETIME_PERSISTENT, the usage flag #PSA_KEY_USAGE_COPY - * is sufficient to permit the copy. - */ -#define PSA_KEY_USAGE_COPY ((psa_key_usage_t) 0x00000002) - -/** Whether the key may be used to encrypt a message. - * - * This flag allows the key to be used for a symmetric encryption operation, - * for an AEAD encryption-and-authentication operation, - * or for an asymmetric encryption operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_ENCRYPT ((psa_key_usage_t) 0x00000100) - -/** Whether the key may be used to decrypt a message. - * - * This flag allows the key to be used for a symmetric decryption operation, - * for an AEAD decryption-and-verification operation, - * or for an asymmetric decryption operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_DECRYPT ((psa_key_usage_t) 0x00000200) - -/** Whether the key may be used to sign a message. - * - * This flag allows the key to be used for a MAC calculation operation or for - * an asymmetric message signature operation, if otherwise permitted by the - * key’s type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_SIGN_MESSAGE ((psa_key_usage_t) 0x00000400) - -/** Whether the key may be used to verify a message. - * - * This flag allows the key to be used for a MAC verification operation or for - * an asymmetric message signature verification operation, if otherwise - * permitted by the key’s type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_VERIFY_MESSAGE ((psa_key_usage_t) 0x00000800) - -/** Whether the key may be used to sign a message. - * - * This flag allows the key to be used for a MAC calculation operation - * or for an asymmetric signature operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t) 0x00001000) - -/** Whether the key may be used to verify a message signature. - * - * This flag allows the key to be used for a MAC verification operation - * or for an asymmetric signature verification operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t) 0x00002000) - -/** Whether the key may be used to derive other keys or produce a password - * hash. - * - * This flag allows the key to be used for a key derivation operation or for - * a key agreement operation, if otherwise permitted by the key's type and - * policy. - * - * If this flag is present on all keys used in calls to - * psa_key_derivation_input_key() for a key derivation operation, then it - * permits calling psa_key_derivation_output_bytes() or - * psa_key_derivation_output_key() at the end of the operation. - */ -#define PSA_KEY_USAGE_DERIVE ((psa_key_usage_t) 0x00004000) - -/** Whether the key may be used to verify the result of a key derivation, - * including password hashing. - * - * This flag allows the key to be used: - * - * This flag allows the key to be used in a key derivation operation, if - * otherwise permitted by the key's type and policy. - * - * If this flag is present on all keys used in calls to - * psa_key_derivation_input_key() for a key derivation operation, then it - * permits calling psa_key_derivation_verify_bytes() or - * psa_key_derivation_verify_key() at the end of the operation. - */ -#define PSA_KEY_USAGE_VERIFY_DERIVATION ((psa_key_usage_t) 0x00008000) - -/**@}*/ - -/** \defgroup derivation Key derivation - * @{ - */ - -/* Key input steps are not embedded in the persistent storage, so you can - * change them if needed: it's only an ABI change. */ - -/** A secret input for key derivation. - * - * This should be a key of type #PSA_KEY_TYPE_DERIVE - * (passed to psa_key_derivation_input_key()) - * or the shared secret resulting from a key agreement - * (obtained via psa_key_derivation_key_agreement()). - * - * The secret can also be a direct input (passed to - * key_derivation_input_bytes()). In this case, the derivation operation - * may not be used to derive keys: the operation will only allow - * psa_key_derivation_output_bytes(), - * psa_key_derivation_verify_bytes(), or - * psa_key_derivation_verify_key(), but not - * psa_key_derivation_output_key(). - */ -#define PSA_KEY_DERIVATION_INPUT_SECRET ((psa_key_derivation_step_t) 0x0101) - -/** A low-entropy secret input for password hashing / key stretching. - * - * This is usually a key of type #PSA_KEY_TYPE_PASSWORD (passed to - * psa_key_derivation_input_key()) or a direct input (passed to - * psa_key_derivation_input_bytes()) that is a password or passphrase. It can - * also be high-entropy secret such as a key of type #PSA_KEY_TYPE_DERIVE or - * the shared secret resulting from a key agreement. - * - * The secret can also be a direct input (passed to - * key_derivation_input_bytes()). In this case, the derivation operation - * may not be used to derive keys: the operation will only allow - * psa_key_derivation_output_bytes(), - * psa_key_derivation_verify_bytes(), or - * psa_key_derivation_verify_key(), but not - * psa_key_derivation_output_key(). - */ -#define PSA_KEY_DERIVATION_INPUT_PASSWORD ((psa_key_derivation_step_t) 0x0102) - -/** A high-entropy additional secret input for key derivation. - * - * This is typically the shared secret resulting from a key agreement obtained - * via `psa_key_derivation_key_agreement()`. It may alternatively be a key of - * type `PSA_KEY_TYPE_DERIVE` passed to `psa_key_derivation_input_key()`, or - * a direct input passed to `psa_key_derivation_input_bytes()`. - */ -#define PSA_KEY_DERIVATION_INPUT_OTHER_SECRET \ - ((psa_key_derivation_step_t) 0x0103) - -/** A label for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_LABEL ((psa_key_derivation_step_t) 0x0201) - -/** A salt for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA or - * #PSA_KEY_TYPE_PEPPER. - */ -#define PSA_KEY_DERIVATION_INPUT_SALT ((psa_key_derivation_step_t) 0x0202) - -/** An information string for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_INFO ((psa_key_derivation_step_t) 0x0203) - -/** A seed for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_SEED ((psa_key_derivation_step_t) 0x0204) - -/** A cost parameter for password hashing / key stretching. - * - * This must be a direct input, passed to psa_key_derivation_input_integer(). - */ -#define PSA_KEY_DERIVATION_INPUT_COST ((psa_key_derivation_step_t) 0x0205) - -/**@}*/ - -/** \defgroup helper_macros Helper macros - * @{ - */ - -/* Helper macros */ - -/** Check if two AEAD algorithm identifiers refer to the same AEAD algorithm - * regardless of the tag length they encode. - * - * \param aead_alg_1 An AEAD algorithm identifier. - * \param aead_alg_2 An AEAD algorithm identifier. - * - * \return 1 if both identifiers refer to the same AEAD algorithm, - * 0 otherwise. - * Unspecified if neither \p aead_alg_1 nor \p aead_alg_2 are - * a supported AEAD algorithm. - */ -#define MBEDTLS_PSA_ALG_AEAD_EQUAL(aead_alg_1, aead_alg_2) \ - (!(((aead_alg_1) ^ (aead_alg_2)) & \ - ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG))) - -/**@}*/ - -/**@}*/ - -/** \defgroup interruptible Interruptible operations - * @{ - */ - -/** Maximum value for use with \c psa_interruptible_set_max_ops() to determine - * the maximum number of ops allowed to be executed by an interruptible - * function in a single call. - */ -#define PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED UINT32_MAX - -/**@}*/ - -#endif /* PSA_CRYPTO_VALUES_H */ diff --git a/interface/include/psa/service.h b/interface/include/psa/service.h index 39fde10ab..5c0c07837 100644 --- a/interface/include/psa/service.h +++ b/interface/include/psa/service.h @@ -140,10 +140,9 @@ psa_status_t psa_get(psa_signal_t signal, psa_msg_t *msg); * \param[in] msg_handle Handle for the client's message. * \param[in] rhandle Reverse handle allocated by the RoT Service. * - * \retval void Success, rhandle will be provided with all - * subsequent messages delivered on this - * connection. - * \retval "PROGRAMMER ERROR" msg_handle is invalid. + * \note When successful,rhandle will be provided with all subsequent messages + * delivered on this connection. + * \note The call is a "PROGRAMMER ERROR" if msg_handle is invalid. */ void psa_set_rhandle(psa_handle_t msg_handle, void *rhandle); @@ -207,17 +206,13 @@ size_t psa_skip(psa_handle_t msg_handle, uint32_t invec_idx, size_t num_bytes); * \param[in] num_bytes Number of bytes to write to the client output * vector. * - * \retval void Success - * \retval "PROGRAMMER ERROR" The call is invalid, one or more of the - * following are true: - * \arg msg_handle is invalid. - * \arg msg_handle does not refer to a request - * message. - * \arg outvec_idx is equal to or greater than - * \ref PSA_MAX_IOVEC. - * \arg The memory reference for buffer is invalid. - * \arg The call attempts to write data past the end - * of the client output vector. + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - msg_handle is invalid. + * - msg_handle does not refer to a request message. + * - outvec_idx is equal to or greater than \ref PSA_MAX_IOVEC. + * - the memory reference for buffer is invalid. + * - the call attempts to write data past the end of the client output + * vector. */ void psa_write(psa_handle_t msg_handle, uint32_t outvec_idx, const void *buffer, size_t num_bytes); @@ -229,12 +224,9 @@ void psa_write(psa_handle_t msg_handle, uint32_t outvec_idx, * \param[in] status Message result value to be reported to the * client. * - * \retval void Success. - * \retval "PROGRAMMER ERROR" The call is invalid, one or more of the - * following are true: - * \arg msg_handle is invalid. - * \arg An invalid status code is specified for the - * type of message. + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - msg_handle is invalid. + * - An invalid status code is specified for the type of message. */ void psa_reply(psa_handle_t msg_handle, psa_status_t status); @@ -243,18 +235,16 @@ void psa_reply(psa_handle_t msg_handle, psa_status_t status); * * \param[in] partition_id Secure Partition ID of the target partition. * - * \retval void Success. - * \retval "PROGRAMMER ERROR" partition_id does not correspond to a Secure - * Partition. + * \note The call is a "PROGRAMMER ERROR" if partition_id does not correspond to + * a Secure Partition. */ void psa_notify(int32_t partition_id); /** * \brief Clear the PSA_DOORBELL signal. * - * \retval void Success. - * \retval "PROGRAMMER ERROR" The Secure Partition's doorbell signal is not - * currently asserted. + * \note The call is a "PROGRAMMER ERROR" if the Secure Partition's doorbell + * signal is not currently asserted. */ void psa_clear(void); @@ -263,21 +253,17 @@ void psa_clear(void); * * \param[in] irq_signal The interrupt signal that has been processed. * - * \retval void Success. - * \retval "PROGRAMMER ERROR" The call is invalid, one or more of the - * following are true: - * \arg irq_signal is not an interrupt signal. - * \arg irq_signal indicates more than one signal. - * \arg irq_signal is not currently asserted. - * \arg The interrupt is not using SLIH. + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - irq_signal is not an interrupt signal. + * - irq_signal indicates more than one signal. + * - irq_signal is not currently asserted. + * - The interrupt is not using SLIH. */ void psa_eoi(psa_signal_t irq_signal); /** * \brief Terminate execution within the calling Secure Partition and will not * return. - * - * \retval "Does not return" */ void psa_panic(void); @@ -289,10 +275,9 @@ void psa_panic(void); * signal value for an interrupt in the calling Secure * Partition. * - * \retval void - * \retval "PROGRAMMER ERROR" If one or more of the following are true: - * \arg \a irq_signal is not an interrupt signal. - * \arg \a irq_signal indicates more than one signal. + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - \a irq_signal is not an interrupt signal. + * - \a irq_signal indicates more than one signal. */ void psa_irq_enable(psa_signal_t irq_signal); @@ -323,13 +308,11 @@ psa_irq_status_t psa_irq_disable(psa_signal_t irq_signal); * currently asserted signal for an interrupt that is * defined to use FLIH handling. * - * \retval void - * \retval "Programmer Error" if one or more of the following are true: - * \arg \a irq_signal is not a signal for an interrupt - * that is specified with FLIH handling in the Secure - * Partition manifest. - * \arg \a irq_signal indicates more than one signal. - * \arg \a irq_signal is not currently asserted. + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - \a irq_signal is not a signal for an interrupt that is specified + * with FLIH handling in the Secure Partition manifest. + * - \a irq_signal indicates more than one signal. + * - \a irq_signal is not currently asserted. */ void psa_reset_signal(psa_signal_t irq_signal); @@ -369,18 +352,13 @@ const void *psa_map_invec(psa_handle_t msg_handle, uint32_t invec_idx); * \param[in] invec_idx Index of input vector to map. Must be * less than \ref PSA_MAX_IOVEC. * - * \retval void - * \retval "PROGRAMMER ERROR" The call is invalid, one or more of the - * following are true: - * \arg msg_handle is invalid. - * \arg msg_handle does not refer to a request - * message. - * \arg invec_idx is equal to or greater than - * \ref PSA_MAX_IOVEC. - * \arg The input vector has not been mapped by a call - * to psa_map_invec(). - * \arg The input vector has already been unmapped by - * a call to psa_unmap_invec(). + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - msg_handle is invalid. + * - msg_handle does not refer to a request message. + * - invec_idx is equal to or greater than \ref PSA_MAX_IOVEC. + * - The input vector has not been mapped by a call to psa_map_invec(). + * - The input vector has already been unmapped by a call to + * psa_unmap_invec(). */ void psa_unmap_invec(psa_handle_t msg_handle, uint32_t invec_idx); @@ -421,18 +399,13 @@ void *psa_map_outvec(psa_handle_t msg_handle, uint32_t outvec_idx); * vector. This must be less than or equal to the * size of the output vector. * - * \retval void - * \retval "PROGRAMMER ERROR" The call is invalid, one or more of the - * following are true: - * \arg msg_handle is invalid. - * \arg msg_handle does not refer to a request - * message. - * \arg outvec_idx is equal to or greater than - * \ref PSA_MAX_IOVEC. - * \arg The output vector has not been mapped by a - * call to psa_map_outvec(). - * \arg The output vector has already been unmapped by - * a call to psa_unmap_outvec(). + * \note The call is a "PROGRAMMER ERROR" if one or more of the following occur: + * - msg_handle is invalid. + * - msg_handle does not refer to a request message. + * - outvec_idx is equal to or greater than \ref PSA_MAX_IOVEC. + * - The output vector has not been mapped by a call to psa_map_outvec(). + * - The output vector has already been unmapped by a call to + * psa_unmap_outvec(). */ void psa_unmap_outvec(psa_handle_t msg_handle, uint32_t outvec_idx, size_t len); diff --git a/interface/include/tfm_crypto_defs.h b/interface/include/tfm_crypto_defs.h index ad34edeb0..52357cb6a 100644 --- a/interface/include/tfm_crypto_defs.h +++ b/interface/include/tfm_crypto_defs.h @@ -60,6 +60,7 @@ struct tfm_crypto_pack_iovec { size_t capacity; /*!< Key derivation capacity */ uint64_t value; /*!< Key derivation integer for update*/ }; + psa_pake_role_t role; /*!< PAKE role */ }; /** @@ -76,7 +77,8 @@ enum tfm_crypto_group_id_t { TFM_CRYPTO_GROUP_ID_AEAD = UINT8_C(6), TFM_CRYPTO_GROUP_ID_ASYM_SIGN = UINT8_C(7), TFM_CRYPTO_GROUP_ID_ASYM_ENCRYPT = UINT8_C(8), - TFM_CRYPTO_GROUP_ID_KEY_DERIVATION = UINT8_C(9) + TFM_CRYPTO_GROUP_ID_KEY_DERIVATION = UINT8_C(9), + TFM_CRYPTO_GROUP_ID_PAKE = UINT8_C(10) }; /* Set of X macros describing each of the available PSA Crypto APIs */ @@ -165,6 +167,17 @@ enum tfm_crypto_group_id_t { #define BASE__VALUE(x) ((uint16_t)((((uint16_t)(x)) << 8) & 0xFF00)) +#define PAKE_FUNCS \ + X(TFM_CRYPTO_PAKE_SETUP) \ + X(TFM_CRYPTO_PAKE_SET_ROLE) \ + X(TFM_CRYPTO_PAKE_SET_USER) \ + X(TFM_CRYPTO_PAKE_SET_PEER) \ + X(TFM_CRYPTO_PAKE_SET_CONTEXT) \ + X(TFM_CRYPTO_PAKE_OUTPUT) \ + X(TFM_CRYPTO_PAKE_INPUT) \ + X(TFM_CRYPTO_PAKE_GET_SHARED_KEY) \ + X(TFM_CRYPTO_PAKE_ABORT) + /** * \brief This type defines numerical progressive values identifying a function API * exposed through the interfaces (S or NS). It's used to dispatch the requests @@ -197,6 +210,8 @@ enum tfm_crypto_func_sid_t { ASYM_ENCRYPT_FUNCS BASE__KEY_DERIVATION = BASE__VALUE(TFM_CRYPTO_GROUP_ID_KEY_DERIVATION) - 1, KEY_DERIVATION_FUNCS + BASE__PAKE = BASE__VALUE(TFM_CRYPTO_GROUP_ID_PAKE) - 1, + PAKE_FUNCS #undef X }; diff --git a/interface/src/tfm_crypto_api.c b/interface/src/tfm_crypto_api.c index 65eae4682..febd86d3b 100644 --- a/interface/src/tfm_crypto_api.c +++ b/interface/src/tfm_crypto_api.c @@ -1,10 +1,11 @@ /* - * Copyright (c) 2018-2023, Arm Limited. All rights reserved. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors * * SPDX-License-Identifier: BSD-3-Clause * */ +#include #include #include @@ -63,6 +64,27 @@ TFM_CRYPTO_API(psa_status_t, psa_crypto_init)(void) return PSA_SUCCESS; } +TFM_CRYPTO_API(int, psa_can_do_hash)(psa_algorithm_t hash_alg) +{ + (void)hash_alg; + /* There isn't any hashing algorithm that would not be ready + * to be used after TF-M has booted up, hence this function + * just returns success all the time + */ + return (int)true; +} + +TFM_CRYPTO_API(int, psa_can_do_cipher)(psa_key_type_t key_type, psa_algorithm_t cipher_alg) +{ + (void)cipher_alg; + (void)key_type; + /* There isn't any cipher algorithm that would not be ready + * to be used after TF-M has booted up, hence this function + * just returns success all the time + */ + return (int)true; +} + TFM_CRYPTO_API(psa_status_t, psa_open_key)(psa_key_id_t id, psa_key_id_t *key) { @@ -1690,3 +1712,158 @@ TFM_CRYPTO_API(void, psa_reset_key_attributes)( { memset(attributes, 0, sizeof(*attributes)); } + +TFM_CRYPTO_API(psa_status_t, psa_pake_setup) +(psa_pake_operation_t *operation, psa_key_id_t password_key, + const psa_pake_cipher_suite_t *cipher_suite) { + struct tfm_crypto_pack_iovec iov = {.function_id = TFM_CRYPTO_PAKE_SETUP_SID, + .op_handle = operation->handle, + .key_id = password_key}; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = cipher_suite, .len = sizeof(psa_pake_cipher_suite_t)}, + }; + + psa_outvec out_vec[] = { + {.base = &(operation->handle), .len = sizeof(uint32_t)}, + }; + + return API_DISPATCH(in_vec, out_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_set_role) +(psa_pake_operation_t *operation, psa_pake_role_t role) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_SET_ROLE_SID, + .op_handle = operation->handle, + .role = role, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + }; + + return API_DISPATCH_NO_OUTVEC(in_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_set_user) +(psa_pake_operation_t *operation, const uint8_t *user_id, size_t user_id_len) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_SET_USER_SID, + .op_handle = operation->handle, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = user_id, .len = user_id_len}, + }; + + return API_DISPATCH_NO_OUTVEC(in_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_set_peer) +(psa_pake_operation_t *operation, const uint8_t *peer_id, size_t peer_id_len) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_SET_PEER_SID, + .op_handle = operation->handle, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = peer_id, .len = peer_id_len}, + }; + + return API_DISPATCH_NO_OUTVEC(in_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_set_context) +(psa_pake_operation_t *operation, const uint8_t *context, size_t context_len) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_SET_CONTEXT_SID, + .op_handle = operation->handle, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = context, .len = context_len}, + }; + + return API_DISPATCH_NO_OUTVEC(in_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_output) +(psa_pake_operation_t *operation, psa_pake_step_t step, uint8_t *output, + size_t output_size, size_t *output_length) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_OUTPUT_SID, + .op_handle = operation->handle, + .step = step, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + }; + + psa_outvec out_vec[] = {{.base = output, .len = output_size}}; + + status = API_DISPATCH(in_vec, out_vec); + + *output_length = out_vec[0].len; + + return status; +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_input) +(psa_pake_operation_t *operation, psa_pake_step_t step, const uint8_t *input, + size_t input_length) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_INPUT_SID, + .op_handle = operation->handle, + .step = step, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = input, .len = input_length}, + }; + + return API_DISPATCH_NO_OUTVEC(in_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_get_shared_key) +(psa_pake_operation_t *operation, const psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t *key) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_GET_SHARED_KEY_SID, + .op_handle = operation->handle, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + {.base = attributes, .len = sizeof(psa_key_attributes_t)}, + }; + + psa_outvec out_vec[] = { + {.base = &(operation->handle), .len = sizeof(uint32_t)}, + {.base = key, .len = sizeof(mbedtls_svc_key_id_t)}}; + + return API_DISPATCH(in_vec, out_vec); +} + +TFM_CRYPTO_API(psa_status_t, psa_pake_abort)(psa_pake_operation_t *operation) { + struct tfm_crypto_pack_iovec iov = { + .function_id = TFM_CRYPTO_PAKE_ABORT_SID, + .op_handle = operation->handle, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct tfm_crypto_pack_iovec)}, + }; + psa_outvec out_vec[] = { + {.base = &(operation->handle), .len = sizeof(uint32_t)}, + }; + + return API_DISPATCH(in_vec, out_vec); +} diff --git a/lib/ext/CMakeLists.txt b/lib/ext/CMakeLists.txt index 05f6b8f14..aa5525bb7 100644 --- a/lib/ext/CMakeLists.txt +++ b/lib/ext/CMakeLists.txt @@ -6,8 +6,10 @@ #------------------------------------------------------------------------------- set(FETCHCONTENT_BASE_DIR ${CMAKE_BINARY_DIR}/lib/ext CACHE STRING "" FORCE) -add_subdirectory(qcbor) -add_subdirectory(t_cose) +if(TFM_PARTITION_INITIAL_ATTESTATION) + add_subdirectory(qcbor) + add_subdirectory(t_cose) +endif() add_subdirectory(mbedcrypto) add_subdirectory(cmsis) if(BL2) diff --git a/lib/ext/cmsis/0001-iar-Add-missing-v8.1m-check.patch b/lib/ext/cmsis/0001-iar-Add-missing-v8.1m-check.patch index 5b69e319b..a391b28e0 100644 --- a/lib/ext/cmsis/0001-iar-Add-missing-v8.1m-check.patch +++ b/lib/ext/cmsis/0001-iar-Add-missing-v8.1m-check.patch @@ -16,7 +16,7 @@ index 4fe09f20..c726cecf 100644 --- a/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h +++ b/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h @@ -77,7 +77,7 @@ - + /* Alternativ core deduction for older ICCARM's */ #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) diff --git a/lib/ext/ethos_u_core_driver/001-Remove-malloc-usage.patch b/lib/ext/ethos_u_core_driver/001-Remove-malloc-usage.patch deleted file mode 100644 index 3f5fb6b89..000000000 --- a/lib/ext/ethos_u_core_driver/001-Remove-malloc-usage.patch +++ /dev/null @@ -1,65 +0,0 @@ -diff --git a/src/ethosu_device.h b/src/ethosu_device.h -index 02942b1..28506b8 100644 ---- a/src/ethosu_device.h -+++ b/src/ethosu_device.h -@@ -59,12 +59,12 @@ struct ethosu_device - /** - * Initialize the device. - */ --struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable); -+enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev); - - /** - * Deinitialize the device. - */ --void ethosu_dev_deinit(struct ethosu_device *dev); -+enum ethosu_error_codes ethosu_dev_deinit(struct ethosu_device *dev); - - /** - * Initialize AXI settings for device. -diff --git a/src/ethosu_device_u55_u65.c b/src/ethosu_device_u55_u65.c -index 50b78af..22ea067 100644 ---- a/src/ethosu_device_u55_u65.c -+++ b/src/ethosu_device_u55_u65.c -@@ -67,19 +67,8 @@ uint64_t __attribute__((weak)) ethosu_address_remap(uint64_t address, int index) - return address; - } - --struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_enable, uint32_t privilege_enable) -+enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev) - { -- struct ethosu_device *dev = malloc(sizeof(struct ethosu_device)); -- if (!dev) -- { -- LOG_ERR("Failed to allocate memory for Ethos-U device"); -- return NULL; -- } -- -- dev->reg = (volatile struct NPU_REG *)base_address; -- dev->secure = secure_enable; -- dev->privileged = privilege_enable; -- - #ifdef ETHOSU55 - if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U55) - #else -@@ -96,16 +85,15 @@ struct ethosu_device *ethosu_dev_init(void *const base_address, uint32_t secure_ - goto err; - } - -- return dev; -+ return ETHOSU_SUCCESS; - - err: -- free(dev); -- return NULL; -+ return ETHOSU_GENERIC_FAILURE; - } - --void ethosu_dev_deinit(struct ethosu_device *dev) -+enum ethosu_error_codes ethosu_dev_deinit(struct ethosu_device *dev) - { -- free(dev); -+ return ETHOSU_SUCCESS; - } - - enum ethosu_error_codes ethosu_dev_axi_init(struct ethosu_device *dev) diff --git a/lib/ext/ethos_u_core_driver/002-Remove-product-check.patch b/lib/ext/ethos_u_core_driver/002-Remove-product-check.patch deleted file mode 100644 index 4580bf7fe..000000000 --- a/lib/ext/ethos_u_core_driver/002-Remove-product-check.patch +++ /dev/null @@ -1,21 +0,0 @@ -diff --git a/src/ethosu_device_u55_u65.c b/src/ethosu_device_u55_u65.c -index 22ea067..09dfc9e 100644 ---- a/src/ethosu_device_u55_u65.c -+++ b/src/ethosu_device_u55_u65.c -@@ -69,16 +69,6 @@ uint64_t __attribute__((weak)) ethosu_address_remap(uint64_t address, int index) - - enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev) - { --#ifdef ETHOSU55 -- if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U55) --#else -- if (dev->reg->CONFIG.product != ETHOSU_PRODUCT_U65) --#endif -- { -- LOG_ERR("Failed to initialize device. Driver has not been compiled for this product"); -- goto err; -- } -- - // Make sure the NPU is in a known state - if (ethosu_dev_soft_reset(dev) != ETHOSU_SUCCESS) - { diff --git a/lib/ext/ethos_u_core_driver/CMakeLists.txt b/lib/ext/ethos_u_core_driver/CMakeLists.txt index 32b10271a..7de2574d8 100644 --- a/lib/ext/ethos_u_core_driver/CMakeLists.txt +++ b/lib/ext/ethos_u_core_driver/CMakeLists.txt @@ -11,6 +11,7 @@ fetch_remote_library( LIB_PATCH_DIR ${CMAKE_CURRENT_LIST_DIR} FETCH_CONTENT_ARGS GIT_REPOSITORY "https://review.mlplatform.org/ml/ethos-u/ethos-u-core-driver" - GIT_TAG "23.05" + GIT_TAG "24.08" + GIT_SHALLOW TRUE GIT_PROGRESS TRUE ) diff --git a/lib/ext/mbedcrypto/0001-Add-TF-M-Builtin-Key-Loader-driver-entry-points.patch b/lib/ext/mbedcrypto/0001-Add-TF-M-Builtin-Key-Loader-driver-entry-points.patch index 7eb724578..7b9cd4802 100644 --- a/lib/ext/mbedcrypto/0001-Add-TF-M-Builtin-Key-Loader-driver-entry-points.patch +++ b/lib/ext/mbedcrypto/0001-Add-TF-M-Builtin-Key-Loader-driver-entry-points.patch @@ -1,4 +1,4 @@ -From f4355fd5675936015f1b822cc30b39c369ea9bfb Mon Sep 17 00:00:00 2001 +From 91ebcce1e2a1cc5f84fc378e22f625e519951f76 Mon Sep 17 00:00:00 2001 From: Antonio de Angelis Date: Thu, 21 Mar 2024 11:44:56 +0000 Subject: [PATCH 1/7] Add TF-M Builtin Key Loader driver entry points @@ -18,7 +18,7 @@ Co-authored-by: Antonio de Angelis 3 files changed, 143 insertions(+), 9 deletions(-) diff --git a/library/psa_crypto.c b/library/psa_crypto.c -index 969c695ac..867b4019b 100644 +index 348c79cf4..78fa0205a 100644 --- a/library/psa_crypto.c +++ b/library/psa_crypto.c @@ -73,6 +73,10 @@ @@ -32,7 +32,7 @@ index 969c695ac..867b4019b 100644 #if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) -@@ -1166,7 +1170,11 @@ static psa_status_t psa_get_and_lock_transparent_key_slot_with_policy( +@@ -1172,7 +1176,11 @@ static psa_status_t psa_get_and_lock_transparent_key_slot_with_policy( return status; } @@ -46,7 +46,7 @@ index 969c695ac..867b4019b 100644 *p_slot = NULL; return PSA_ERROR_NOT_SUPPORTED; diff --git a/library/psa_crypto_driver_wrappers.h b/library/psa_crypto_driver_wrappers.h -index ea6aee32e..2ea6358f9 100644 +index 0ed221b50..17b129a02 100644 --- a/library/psa_crypto_driver_wrappers.h +++ b/library/psa_crypto_driver_wrappers.h @@ -42,16 +42,32 @@ @@ -129,7 +129,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -391,6 +422,9 @@ static inline psa_status_t psa_driver_wrapper_verify_hash( +@@ -390,6 +421,9 @@ static inline psa_status_t psa_driver_wrapper_verify_hash( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -139,7 +139,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -521,6 +555,9 @@ static inline psa_status_t psa_driver_wrapper_sign_hash_start( +@@ -519,6 +553,9 @@ static inline psa_status_t psa_driver_wrapper_sign_hash_start( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -149,7 +149,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -613,6 +650,9 @@ static inline psa_status_t psa_driver_wrapper_verify_hash_start( +@@ -611,6 +648,9 @@ static inline psa_status_t psa_driver_wrapper_verify_hash_start( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -159,7 +159,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -775,6 +815,9 @@ static inline psa_status_t psa_driver_wrapper_generate_key( +@@ -774,6 +814,9 @@ static inline psa_status_t psa_driver_wrapper_generate_key( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -169,7 +169,7 @@ index ea6aee32e..2ea6358f9 100644 #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) /* Transparent drivers are limited to generating asymmetric keys. */ /* We don't support passing custom production parameters -@@ -879,6 +922,9 @@ static inline psa_status_t psa_driver_wrapper_import_key( +@@ -878,6 +921,9 @@ static inline psa_status_t psa_driver_wrapper_import_key( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -179,7 +179,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -980,6 +1026,9 @@ static inline psa_status_t psa_driver_wrapper_export_key( +@@ -979,6 +1025,9 @@ static inline psa_status_t psa_driver_wrapper_export_key( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -189,7 +189,7 @@ index ea6aee32e..2ea6358f9 100644 return( psa_export_key_internal( attributes, key_buffer, key_buffer_size, -@@ -1086,6 +1135,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( +@@ -1085,6 +1134,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -199,7 +199,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -1176,6 +1228,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( +@@ -1175,6 +1227,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -209,7 +209,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -1253,6 +1308,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( +@@ -1252,6 +1307,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -219,7 +219,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -1326,6 +1384,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( +@@ -1325,6 +1383,9 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -229,7 +229,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -1726,6 +1787,9 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( +@@ -1725,6 +1786,9 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -239,7 +239,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -1778,6 +1842,9 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( +@@ -1777,6 +1841,9 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -249,7 +249,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -1827,6 +1894,9 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( +@@ -1826,6 +1893,9 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -259,7 +259,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -1875,6 +1945,9 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( +@@ -1874,6 +1944,9 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -269,7 +269,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ -@@ -2211,6 +2284,9 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( +@@ -2210,6 +2283,9 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -279,7 +279,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2275,6 +2351,9 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( +@@ -2274,6 +2350,9 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -289,7 +289,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2347,6 +2426,9 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( +@@ -2346,6 +2425,9 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -299,7 +299,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2547,6 +2629,9 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( +@@ -2546,6 +2628,9 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -309,7 +309,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2605,6 +2690,9 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( +@@ -2604,6 +2689,9 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -319,7 +319,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2669,6 +2757,9 @@ static inline psa_status_t psa_driver_wrapper_key_agreement( +@@ -2668,6 +2756,9 @@ static inline psa_status_t psa_driver_wrapper_key_agreement( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: @@ -329,7 +329,7 @@ index ea6aee32e..2ea6358f9 100644 /* Key is stored in the slot in export representation, so * cycle through all known transparent accelerators */ #if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -@@ -2749,6 +2840,9 @@ static inline psa_status_t psa_driver_wrapper_pake_setup( +@@ -2748,6 +2839,9 @@ static inline psa_status_t psa_driver_wrapper_pake_setup( switch( location ) { case PSA_KEY_LOCATION_LOCAL_STORAGE: diff --git a/lib/ext/mbedcrypto/0002-Enable-crypto-code-sharing-between-independent-binar.patch b/lib/ext/mbedcrypto/0002-Enable-crypto-code-sharing-between-independent-binar.patch index 01531f264..2283d0b42 100644 --- a/lib/ext/mbedcrypto/0002-Enable-crypto-code-sharing-between-independent-binar.patch +++ b/lib/ext/mbedcrypto/0002-Enable-crypto-code-sharing-between-independent-binar.patch @@ -1,4 +1,4 @@ -From 897915891d0af5947b9391f13b75bf338fabbe94 Mon Sep 17 00:00:00 2001 +From 8df3803e2ab01bb5955e3a52fbd5e7ec3a601fc3 Mon Sep 17 00:00:00 2001 From: Tamas Ban Date: Tue, 27 Oct 2020 08:55:37 +0000 Subject: [PATCH 2/7] Enable crypto code sharing between independent binaries @@ -36,7 +36,7 @@ index 890c4cbab..f8109c73f 100644 void *mbedtls_calloc(size_t nmemb, size_t size) { diff --git a/library/platform_util.c b/library/platform_util.c -index 0741bf575..b867c6da1 100644 +index 19ef07aea..2d9c731d9 100644 --- a/library/platform_util.c +++ b/library/platform_util.c @@ -88,7 +88,7 @@ diff --git a/lib/ext/mbedcrypto/0003-Allow-SE-key-to-use-key-vendor-id-within-PSA-crypto.patch b/lib/ext/mbedcrypto/0003-Allow-SE-key-to-use-key-vendor-id-within-PSA-crypto.patch index 1b989b88c..04dd5ea1b 100644 --- a/lib/ext/mbedcrypto/0003-Allow-SE-key-to-use-key-vendor-id-within-PSA-crypto.patch +++ b/lib/ext/mbedcrypto/0003-Allow-SE-key-to-use-key-vendor-id-within-PSA-crypto.patch @@ -1,4 +1,4 @@ -From f3d7c2b7000b98a5191007cbdf0b8910642fb685 Mon Sep 17 00:00:00 2001 +From 4c730658542be6eb6a3e571f95aa1398e1f990de Mon Sep 17 00:00:00 2001 From: Benjamin Baratte Date: Thu, 9 Feb 2023 10:35:01 +0100 Subject: [PATCH 3/7] Allow SE key to use key vendor id within PSA crypto @@ -9,10 +9,10 @@ Signed-off-by: Benjamin Baratte 1 file changed, 4 insertions(+) diff --git a/library/psa_crypto.c b/library/psa_crypto.c -index 867b4019b..fd1d28fc6 100644 +index 78fa0205a..95f37fe2c 100644 --- a/library/psa_crypto.c +++ b/library/psa_crypto.c -@@ -1703,7 +1703,11 @@ static psa_status_t psa_validate_key_attributes( +@@ -1732,7 +1732,11 @@ static psa_status_t psa_validate_key_attributes( return PSA_ERROR_INVALID_ARGUMENT; } } else { diff --git a/lib/ext/mbedcrypto/0004-Initialise-driver-wrappers-as-first-step-in-psa_cryp.patch b/lib/ext/mbedcrypto/0004-Initialise-driver-wrappers-as-first-step-in-psa_cryp.patch index 0a830f321..11c778dff 100644 --- a/lib/ext/mbedcrypto/0004-Initialise-driver-wrappers-as-first-step-in-psa_cryp.patch +++ b/lib/ext/mbedcrypto/0004-Initialise-driver-wrappers-as-first-step-in-psa_cryp.patch @@ -1,4 +1,4 @@ -From ba6536c5140df75a669fc92cdef2729a6913f6af Mon Sep 17 00:00:00 2001 +From 0803fb5aea0768c37cb027af0af9223c2f0f47a9 Mon Sep 17 00:00:00 2001 From: Antonio de Angelis Date: Thu, 21 Mar 2024 11:58:19 +0000 Subject: [PATCH 4/7] Initialise driver wrappers as first step in @@ -16,10 +16,10 @@ Signed-off-by: Antonio de Angelis 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/psa_crypto.c b/library/psa_crypto.c -index fd1d28fc6..1d91739da 100644 +index 95f37fe2c..451e95492 100644 --- a/library/psa_crypto.c +++ b/library/psa_crypto.c -@@ -8274,12 +8274,12 @@ psa_status_t psa_crypto_init(void) +@@ -8483,12 +8483,12 @@ psa_status_t psa_crypto_init(void) return PSA_SUCCESS; } diff --git a/lib/ext/mbedcrypto/0005-Hardcode-CC3XX-entry-points.patch b/lib/ext/mbedcrypto/0005-Hardcode-CC3XX-entry-points.patch index baf2e4e77..d423bdaa3 100644 --- a/lib/ext/mbedcrypto/0005-Hardcode-CC3XX-entry-points.patch +++ b/lib/ext/mbedcrypto/0005-Hardcode-CC3XX-entry-points.patch @@ -1,4 +1,4 @@ -From bb55d3718baa1c2d787cf996da8f01d85c99b00b Mon Sep 17 00:00:00 2001 +From cf0fc2373fce8d7110a5afb5f6c7bf4d48235ad9 Mon Sep 17 00:00:00 2001 From: Antonio de Angelis Date: Thu, 21 Mar 2024 12:58:37 +0000 Subject: [PATCH 5/7] Hardcode CC3XX entry points @@ -12,9 +12,9 @@ Signed-off-by: Antonio de Angelis --- .../psa/crypto_driver_contexts_composites.h | 10 + .../psa/crypto_driver_contexts_primitives.h | 10 + - library/psa_crypto_driver_wrappers.h | 421 ++++++++++++++++-- + library/psa_crypto_driver_wrappers.h | 431 ++++++++++++++++-- .../psa_crypto_driver_wrappers_no_static.c | 24 + - 4 files changed, 436 insertions(+), 29 deletions(-) + 4 files changed, 446 insertions(+), 29 deletions(-) diff --git a/include/psa/crypto_driver_contexts_composites.h b/include/psa/crypto_driver_contexts_composites.h index d717c5190..f6a54aefd 100644 @@ -87,7 +87,7 @@ index c90a5fbe7..3f00006f8 100644 #endif /* PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H */ diff --git a/library/psa_crypto_driver_wrappers.h b/library/psa_crypto_driver_wrappers.h -index 2ea6358f9..3fa4583b7 100644 +index 17b129a02..5c581ff72 100644 --- a/library/psa_crypto_driver_wrappers.h +++ b/library/psa_crypto_driver_wrappers.h @@ -53,6 +53,16 @@ @@ -258,8 +258,8 @@ index 2ea6358f9..3fa4583b7 100644 +#endif /* PSA_CRYPTO_DRIVER_CC3XX */ #if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) if( PSA_KEY_TYPE_IS_ECC( psa_get_key_type(attributes) ) && - PSA_ALG_IS_ECDSA(alg) && -@@ -442,6 +499,17 @@ static inline psa_status_t psa_driver_wrapper_verify_hash( + PSA_ALG_IS_RANDOMIZED_ECDSA(alg) && +@@ -441,6 +498,17 @@ static inline psa_status_t psa_driver_wrapper_verify_hash( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -277,7 +277,7 @@ index 2ea6358f9..3fa4583b7 100644 #if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) if( PSA_KEY_TYPE_IS_ECC( psa_get_key_type(attributes) ) && PSA_ALG_IS_ECDSA(alg) && -@@ -834,6 +902,12 @@ static inline psa_status_t psa_driver_wrapper_generate_key( +@@ -833,6 +901,12 @@ static inline psa_status_t psa_driver_wrapper_generate_key( if( status != PSA_ERROR_NOT_SUPPORTED ) break; #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -290,7 +290,7 @@ index 2ea6358f9..3fa4583b7 100644 #if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) if( PSA_KEY_TYPE_IS_ECC( psa_get_key_type(attributes) ) && psa_get_key_type(attributes) == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1) && -@@ -1157,6 +1231,20 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( +@@ -1156,6 +1230,20 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -311,7 +311,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) -@@ -1248,6 +1336,18 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( +@@ -1247,6 +1335,18 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -330,7 +330,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) -@@ -1328,6 +1428,16 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( +@@ -1327,6 +1427,16 @@ static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -347,7 +347,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) /* Fell through, meaning no accelerator supports this operation */ -@@ -1404,6 +1514,16 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( +@@ -1403,6 +1513,16 @@ static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -364,7 +364,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_CIPHER) /* Fell through, meaning no accelerator supports this operation */ -@@ -1473,6 +1593,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_set_iv( +@@ -1472,6 +1592,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_set_iv( &operation->ctx.opaque_test_driver_ctx, iv, iv_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -377,7 +377,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -1516,6 +1642,13 @@ static inline psa_status_t psa_driver_wrapper_cipher_update( +@@ -1515,6 +1641,13 @@ static inline psa_status_t psa_driver_wrapper_cipher_update( input, input_length, output, output_size, output_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -391,7 +391,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -1556,6 +1689,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_finish( +@@ -1555,6 +1688,12 @@ static inline psa_status_t psa_driver_wrapper_cipher_finish( &operation->ctx.opaque_test_driver_ctx, output, output_size, output_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -404,7 +404,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -1596,6 +1735,15 @@ static inline psa_status_t psa_driver_wrapper_cipher_abort( +@@ -1595,6 +1734,15 @@ static inline psa_status_t psa_driver_wrapper_cipher_abort( sizeof( operation->ctx.opaque_test_driver_ctx ) ); return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -420,7 +420,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -1617,12 +1765,19 @@ static inline psa_status_t psa_driver_wrapper_hash_compute( +@@ -1616,12 +1764,24 @@ static inline psa_status_t psa_driver_wrapper_hash_compute( psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; /* Try accelerators first */ @@ -435,13 +435,18 @@ index 2ea6358f9..3fa4583b7 100644 +#if defined(PSA_CRYPTO_DRIVER_CC3XX) + status = cc3xx_hash_compute(alg, input, input_length, hash, hash_size, + hash_length); -+ return status; ++#if defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA_512) ++ if( status != PSA_ERROR_NOT_SUPPORTED ) ++ return( status ); ++#else ++ return( status ); ++#endif /* defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA_512) */ +#endif /* PSA_CRYPTO_DRIVER_CC3XX */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* If software fallback is compiled in, try fallback */ #if defined(MBEDTLS_PSA_BUILTIN_HASH) -@@ -1649,6 +1804,7 @@ static inline psa_status_t psa_driver_wrapper_hash_setup( +@@ -1648,6 +1808,7 @@ static inline psa_status_t psa_driver_wrapper_hash_setup( psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; /* Try setup on accelerators first */ @@ -449,7 +454,7 @@ index 2ea6358f9..3fa4583b7 100644 #if defined(PSA_CRYPTO_DRIVER_TEST) status = mbedtls_test_transparent_hash_setup( &operation->ctx.test_driver_ctx, alg ); -@@ -1657,7 +1813,13 @@ static inline psa_status_t psa_driver_wrapper_hash_setup( +@@ -1656,7 +1817,18 @@ static inline psa_status_t psa_driver_wrapper_hash_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); @@ -458,13 +463,18 @@ index 2ea6358f9..3fa4583b7 100644 +#if defined(PSA_CRYPTO_DRIVER_CC3XX) + status = cc3xx_hash_setup(&operation->ctx.cc3xx_driver_ctx, alg); + operation->id = PSA_CRYPTO_CC3XX_DRIVER_ID; ++#if defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA_512) ++ if( status != PSA_ERROR_NOT_SUPPORTED ) ++ return( status ); ++#else + return( status ); ++#endif /* defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA_512) */ +#endif /* PSA_CRYPTO_DRIVER_CC3XX */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* If software fallback is compiled in, try fallback */ #if defined(MBEDTLS_PSA_BUILTIN_HASH) -@@ -1687,13 +1849,23 @@ static inline psa_status_t psa_driver_wrapper_hash_clone( +@@ -1686,13 +1858,23 @@ static inline psa_status_t psa_driver_wrapper_hash_clone( return( mbedtls_psa_hash_clone( &source_operation->ctx.mbedtls_ctx, &target_operation->ctx.mbedtls_ctx ) ); #endif @@ -489,7 +499,7 @@ index 2ea6358f9..3fa4583b7 100644 default: (void) target_operation; return( PSA_ERROR_BAD_STATE ); -@@ -1712,12 +1884,20 @@ static inline psa_status_t psa_driver_wrapper_hash_update( +@@ -1711,12 +1893,20 @@ static inline psa_status_t psa_driver_wrapper_hash_update( return( mbedtls_psa_hash_update( &operation->ctx.mbedtls_ctx, input, input_length ) ); #endif @@ -511,7 +521,7 @@ index 2ea6358f9..3fa4583b7 100644 default: (void) input; (void) input_length; -@@ -1738,12 +1918,20 @@ static inline psa_status_t psa_driver_wrapper_hash_finish( +@@ -1737,12 +1927,20 @@ static inline psa_status_t psa_driver_wrapper_hash_finish( return( mbedtls_psa_hash_finish( &operation->ctx.mbedtls_ctx, hash, hash_size, hash_length ) ); #endif @@ -533,7 +543,7 @@ index 2ea6358f9..3fa4583b7 100644 default: (void) hash; (void) hash_size; -@@ -1761,11 +1949,18 @@ static inline psa_status_t psa_driver_wrapper_hash_abort( +@@ -1760,11 +1958,18 @@ static inline psa_status_t psa_driver_wrapper_hash_abort( case PSA_CRYPTO_MBED_TLS_DRIVER_ID: return( mbedtls_psa_hash_abort( &operation->ctx.mbedtls_ctx ) ); #endif @@ -553,7 +563,7 @@ index 2ea6358f9..3fa4583b7 100644 default: return( PSA_ERROR_BAD_STATE ); } -@@ -1806,6 +2001,17 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( +@@ -1805,6 +2010,17 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -571,7 +581,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Fell through, meaning no accelerator supports this operation */ -@@ -1861,6 +2067,17 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( +@@ -1860,6 +2076,17 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -589,7 +599,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Fell through, meaning no accelerator supports this operation */ -@@ -1912,6 +2129,15 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( +@@ -1911,6 +2138,15 @@ static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -605,7 +615,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Fell through, meaning no accelerator supports this operation */ -@@ -1964,6 +2190,16 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( +@@ -1963,6 +2199,16 @@ static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -622,7 +632,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ /* Fell through, meaning no accelerator supports this operation */ -@@ -2010,6 +2246,12 @@ static inline psa_status_t psa_driver_wrapper_aead_set_nonce( +@@ -2009,6 +2255,12 @@ static inline psa_status_t psa_driver_wrapper_aead_set_nonce( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -635,7 +645,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2044,6 +2286,12 @@ static inline psa_status_t psa_driver_wrapper_aead_set_lengths( +@@ -2043,6 +2295,12 @@ static inline psa_status_t psa_driver_wrapper_aead_set_lengths( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -648,7 +658,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2078,6 +2326,12 @@ static inline psa_status_t psa_driver_wrapper_aead_update_ad( +@@ -2077,6 +2335,12 @@ static inline psa_status_t psa_driver_wrapper_aead_update_ad( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -661,7 +671,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2117,6 +2371,13 @@ static inline psa_status_t psa_driver_wrapper_aead_update( +@@ -2116,6 +2380,13 @@ static inline psa_status_t psa_driver_wrapper_aead_update( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -675,7 +685,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2161,6 +2422,13 @@ static inline psa_status_t psa_driver_wrapper_aead_finish( +@@ -2160,6 +2431,13 @@ static inline psa_status_t psa_driver_wrapper_aead_finish( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -689,7 +699,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2225,6 +2493,13 @@ static inline psa_status_t psa_driver_wrapper_aead_verify( +@@ -2224,6 +2502,13 @@ static inline psa_status_t psa_driver_wrapper_aead_verify( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -703,7 +713,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2257,6 +2532,11 @@ static inline psa_status_t psa_driver_wrapper_aead_abort( +@@ -2256,6 +2541,11 @@ static inline psa_status_t psa_driver_wrapper_aead_abort( /* Add cases for opaque driver here */ #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -715,7 +725,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ } -@@ -2299,6 +2579,12 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( +@@ -2298,6 +2588,12 @@ static inline psa_status_t psa_driver_wrapper_mac_compute( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -728,7 +738,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_MAC) /* Fell through, meaning no accelerator supports this operation */ -@@ -2370,6 +2656,15 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( +@@ -2369,6 +2665,15 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -744,7 +754,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_MAC) /* Fell through, meaning no accelerator supports this operation */ -@@ -2445,6 +2740,15 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( +@@ -2444,6 +2749,15 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_setup( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -760,7 +770,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ #if defined(MBEDTLS_PSA_BUILTIN_MAC) /* Fell through, meaning no accelerator supports this operation */ -@@ -2512,6 +2816,10 @@ static inline psa_status_t psa_driver_wrapper_mac_update( +@@ -2511,6 +2825,10 @@ static inline psa_status_t psa_driver_wrapper_mac_update( &operation->ctx.opaque_test_driver_ctx, input, input_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -771,7 +781,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ default: (void) input; -@@ -2546,6 +2854,11 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_finish( +@@ -2545,6 +2863,11 @@ static inline psa_status_t psa_driver_wrapper_mac_sign_finish( &operation->ctx.opaque_test_driver_ctx, mac, mac_size, mac_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -783,7 +793,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ default: (void) mac; -@@ -2580,6 +2893,12 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_finish( +@@ -2579,6 +2902,12 @@ static inline psa_status_t psa_driver_wrapper_mac_verify_finish( &operation->ctx.opaque_test_driver_ctx, mac, mac_length ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -796,7 +806,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ default: (void) mac; -@@ -2607,6 +2926,10 @@ static inline psa_status_t psa_driver_wrapper_mac_abort( +@@ -2606,6 +2935,10 @@ static inline psa_status_t psa_driver_wrapper_mac_abort( return( mbedtls_test_opaque_mac_abort( &operation->ctx.opaque_test_driver_ctx ) ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -807,7 +817,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ default: return( PSA_ERROR_INVALID_ARGUMENT ); -@@ -2644,6 +2967,20 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( +@@ -2643,6 +2976,20 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -828,7 +838,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ return( mbedtls_psa_asymmetric_encrypt( attributes, key_buffer, key_buffer_size, alg, input, input_length, -@@ -2705,6 +3042,20 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( +@@ -2704,6 +3051,20 @@ static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ @@ -849,7 +859,7 @@ index 2ea6358f9..3fa4583b7 100644 #endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ return( mbedtls_psa_asymmetric_decrypt( attributes, key_buffer, key_buffer_size, alg,input, input_length, -@@ -2772,6 +3123,18 @@ static inline psa_status_t psa_driver_wrapper_key_agreement( +@@ -2771,6 +3132,18 @@ static inline psa_status_t psa_driver_wrapper_key_agreement( if( status != PSA_ERROR_NOT_SUPPORTED ) return( status ); #endif /* PSA_CRYPTO_DRIVER_TEST */ diff --git a/lib/ext/mbedcrypto/0006-Enable-psa_can_do_hash.patch b/lib/ext/mbedcrypto/0006-Enable-psa_can_do_hash.patch index 38d9fd766..501c85722 100644 --- a/lib/ext/mbedcrypto/0006-Enable-psa_can_do_hash.patch +++ b/lib/ext/mbedcrypto/0006-Enable-psa_can_do_hash.patch @@ -1,4 +1,4 @@ -From a1dae597483b1f64327902adbaa1d6b20e661081 Mon Sep 17 00:00:00 2001 +From 29fa390e489ace016b9d1dcb2843c81d1e4067f3 Mon Sep 17 00:00:00 2001 From: Antonio de Angelis Date: Thu, 21 Mar 2024 13:02:44 +0000 Subject: [PATCH 6/7] Enable psa_can_do_hash @@ -14,7 +14,7 @@ Signed-off-by: Summer Qin 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/library/psa_crypto.c b/library/psa_crypto.c -index 1d91739da..6219f8169 100644 +index 451e95492..af630d590 100644 --- a/library/psa_crypto.c +++ b/library/psa_crypto.c @@ -288,7 +288,8 @@ static uint8_t psa_get_drivers_initialized(void) diff --git a/lib/ext/mbedcrypto/0007-Enable-sources-when-MCUBOOT_USE_PSA_CRYPTO-and-not-M.patch b/lib/ext/mbedcrypto/0007-Enable-sources-when-MCUBOOT_USE_PSA_CRYPTO-and-not-M.patch deleted file mode 100644 index c9198e1fa..000000000 --- a/lib/ext/mbedcrypto/0007-Enable-sources-when-MCUBOOT_USE_PSA_CRYPTO-and-not-M.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 5f1f13a6607a145ab6169810207ca1be8b844468 Mon Sep 17 00:00:00 2001 -From: Antonio de Angelis -Date: Tue, 9 Apr 2024 15:26:59 +0100 -Subject: [PATCH 7/7] Enable sources when MCUBOOT_USE_PSA_CRYPTO and not - MBEDTLS_PSA_CRYPTO_C - -Gate relevant files for the thin PSA crypto core on MCUBOOT_USE_PSA_CRYPTO -during BL2 build instead of MBEDTLS_PSA_CRYPTO_C which is not defined in -such case. A full solution might require a change in config strategy of -Mbed TLS with the definition - -Signed-off-by: Antonio de Angelis ---- - include/mbedtls/psa_util.h | 2 +- - library/psa_crypto_driver_wrappers.h | 2 +- - library/psa_crypto_ecp.c | 2 +- - library/psa_crypto_hash.c | 2 +- - library/psa_crypto_rsa.c | 2 +- - 5 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/include/mbedtls/psa_util.h b/include/mbedtls/psa_util.h -index c78cc2333..7350eafcb 100644 ---- a/include/mbedtls/psa_util.h -+++ b/include/mbedtls/psa_util.h -@@ -21,7 +21,7 @@ - * otherwise error codes would be unknown in test_suite_psa_crypto_util.data.*/ - #include - --#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) -+#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) || defined(MCUBOOT_USE_PSA_CRYPTO) - - /** The random generator function for the PSA subsystem. - * -diff --git a/library/psa_crypto_driver_wrappers.h b/library/psa_crypto_driver_wrappers.h -index 3fa4583b7..1769ad405 100644 ---- a/library/psa_crypto_driver_wrappers.h -+++ b/library/psa_crypto_driver_wrappers.h -@@ -23,7 +23,7 @@ - #include "mbedtls/constant_time.h" - /* END-common headers */ - --#if defined(MBEDTLS_PSA_CRYPTO_C) -+#if defined(MBEDTLS_PSA_CRYPTO_C) || defined(MCUBOOT_USE_PSA_CRYPTO) - - /* BEGIN-driver headers */ - /* Headers for mbedtls_test opaque driver */ -diff --git a/library/psa_crypto_ecp.c b/library/psa_crypto_ecp.c -index 95baff6a0..317554bfb 100644 ---- a/library/psa_crypto_ecp.c -+++ b/library/psa_crypto_ecp.c -@@ -8,7 +8,7 @@ - - #include "common.h" - --#if defined(MBEDTLS_PSA_CRYPTO_C) -+#if defined(MBEDTLS_PSA_CRYPTO_C) || defined(MCUBOOT_USE_PSA_CRYPTO) - - #include - #include "psa_crypto_core.h" -diff --git a/library/psa_crypto_hash.c b/library/psa_crypto_hash.c -index eeb7666c1..5c025b335 100644 ---- a/library/psa_crypto_hash.c -+++ b/library/psa_crypto_hash.c -@@ -8,7 +8,7 @@ - - #include "common.h" - --#if defined(MBEDTLS_PSA_CRYPTO_C) -+#if defined(MBEDTLS_PSA_CRYPTO_C) || defined(MCUBOOT_USE_PSA_CRYPTO) - - #include - #include "psa_crypto_core.h" -diff --git a/library/psa_crypto_rsa.c b/library/psa_crypto_rsa.c -index 2f613b32d..2594b110f 100644 ---- a/library/psa_crypto_rsa.c -+++ b/library/psa_crypto_rsa.c -@@ -8,7 +8,7 @@ - - #include "common.h" - --#if defined(MBEDTLS_PSA_CRYPTO_C) -+#if defined(MBEDTLS_PSA_CRYPTO_C) || defined(MCUBOOT_USE_PSA_CRYPTO) - - #include - #include "psa/crypto_values.h" --- -2.34.1 - diff --git a/lib/ext/mbedcrypto/0007-P256M-Add-option-to-force-not-use-of-asm.patch b/lib/ext/mbedcrypto/0007-P256M-Add-option-to-force-not-use-of-asm.patch new file mode 100644 index 000000000..9561b2685 --- /dev/null +++ b/lib/ext/mbedcrypto/0007-P256M-Add-option-to-force-not-use-of-asm.patch @@ -0,0 +1,30 @@ +From c47b819cefb69a9c7e9f5cdd2dbd3d9a91b16f66 Mon Sep 17 00:00:00 2001 +From: Antonio de Angelis +Date: Wed, 9 Oct 2024 13:36:42 +0100 +Subject: [PATCH 7/7] P256M: Add option to force not use of asm + +Add an option to let the compiler generate the assembly +code for u32_muladd64(), especially for MinSizeRel and +Release builds. + +Signed-off-by: Antonio de Angelis +--- + 3rdparty/p256-m/p256-m/p256-m.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/3rdparty/p256-m/p256-m/p256-m.c b/3rdparty/p256-m/p256-m/p256-m.c +index 42c35b5bf..558a8bc95 100644 +--- a/3rdparty/p256-m/p256-m/p256-m.c ++++ b/3rdparty/p256-m/p256-m/p256-m.c +@@ -197,7 +197,7 @@ static uint64_t u32_muladd64(uint32_t x, uint32_t y, uint32_t z, uint32_t t); + * v7-M architectures. __ARM_ARCH_PROFILE is not defined for v6 and earlier. + * Thumb and 32-bit assembly is supported; aarch64 is not supported. + */ +-#if defined(__GNUC__) &&\ ++#if !defined(MULADD64_IGNORE_ASM) && defined(__GNUC__) &&\ + defined(__ARM_ARCH) && __ARM_ARCH >= 6 && defined(__ARM_ARCH_PROFILE) && \ + ( __ARM_ARCH_PROFILE == 77 || __ARM_ARCH_PROFILE == 65 ) /* 'M' or 'A' */ && \ + !defined(__aarch64__) +-- +2.34.1 + diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h index 85c94032b..d64f8dc6d 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h @@ -198,6 +198,26 @@ */ #define MBEDTLS_PK_RSA_ALT_SUPPORT +/** + * \def MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + * + * Assume all buffers passed to PSA functions are owned exclusively by the + * PSA function and are not stored in shared memory. + * + * This option may be enabled if all buffers passed to any PSA function reside + * in memory that is accessible only to the PSA function during its execution. + * + * This option MUST be disabled whenever buffer arguments are in memory shared + * with an untrusted party, for example where arguments to PSA calls are passed + * across a trust boundary. + * + * \note Enabling this option reduces memory usage and code size. + * + * \note Enabling this option causes overlap of input and output buffers + * not to be supported by PSA functions. + */ +#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + /** * \def MBEDTLS_PSA_CRYPTO_CONFIG * diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default_client.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default_client.h index c90cb8803..b13f9fc71 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default_client.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default_client.h @@ -136,20 +136,6 @@ */ #define MBEDTLS_ECP_NIST_OPTIM -/** - * \def MBEDTLS_PK_PARSE_EC_EXTENDED - * - * Enhance support for reading EC keys using variants of SEC1 not allowed by - * RFC 5915 and RFC 5480. - * - * Currently this means parsing the SpecifiedECDomain choice of EC - * parameters (only known groups are supported, not arbitrary domains, to - * avoid validation issues). - * - * Disable if you only need to support RFC 5915 + 5480 key formats. - */ -#define MBEDTLS_PK_PARSE_EC_EXTENDED - /** * \def MBEDTLS_NO_PLATFORM_ENTROPY * diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large.h index 10ffeaa3d..9722269f6 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large.h @@ -199,6 +199,26 @@ */ #define MBEDTLS_PK_RSA_ALT_SUPPORT +/** + * \def MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + * + * Assume all buffers passed to PSA functions are owned exclusively by the + * PSA function and are not stored in shared memory. + * + * This option may be enabled if all buffers passed to any PSA function reside + * in memory that is accessible only to the PSA function during its execution. + * + * This option MUST be disabled whenever buffer arguments are in memory shared + * with an untrusted party, for example where arguments to PSA calls are passed + * across a trust boundary. + * + * \note Enabling this option reduces memory usage and code size. + * + * \note Enabling this option causes overlap of input and output buffers + * not to be supported by PSA functions. + */ +#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + /** * \def MBEDTLS_PSA_CRYPTO_CONFIG * diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large_client.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large_client.h index 39df0cc7b..41f7cc4d9 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large_client.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_large_client.h @@ -137,20 +137,6 @@ */ #define MBEDTLS_ECP_NIST_OPTIM -/** - * \def MBEDTLS_PK_PARSE_EC_EXTENDED - * - * Enhance support for reading EC keys using variants of SEC1 not allowed by - * RFC 5915 and RFC 5480. - * - * Currently this means parsing the SpecifiedECDomain choice of EC - * parameters (only known groups are supported, not arbitrary domains, to - * avoid validation issues). - * - * Disable if you only need to support RFC 5915 + 5480 key formats. - */ -#define MBEDTLS_PK_PARSE_EC_EXTENDED - /** * \def MBEDTLS_NO_PLATFORM_ENTROPY * diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_medium.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_medium.h index 61ed556c9..8c517a2af 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_medium.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_medium.h @@ -192,6 +192,26 @@ */ #define MBEDTLS_SHA256_SMALLER +/** + * \def MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + * + * Assume all buffers passed to PSA functions are owned exclusively by the + * PSA function and are not stored in shared memory. + * + * This option may be enabled if all buffers passed to any PSA function reside + * in memory that is accessible only to the PSA function during its execution. + * + * This option MUST be disabled whenever buffer arguments are in memory shared + * with an untrusted party, for example where arguments to PSA calls are passed + * across a trust boundary. + * + * \note Enabling this option reduces memory usage and code size. + * + * \note Enabling this option causes overlap of input and output buffers + * not to be supported by PSA functions. + */ +#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + /** * \def MBEDTLS_PSA_CRYPTO_CONFIG * diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small.h index 81e7af24f..848600816 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small.h @@ -181,6 +181,26 @@ */ #define MBEDTLS_SHA256_SMALLER +/** + * \def MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + * + * Assume all buffers passed to PSA functions are owned exclusively by the + * PSA function and are not stored in shared memory. + * + * This option may be enabled if all buffers passed to any PSA function reside + * in memory that is accessible only to the PSA function during its execution. + * + * This option MUST be disabled whenever buffer arguments are in memory shared + * with an untrusted party, for example where arguments to PSA calls are passed + * across a trust boundary. + * + * \note Enabling this option reduces memory usage and code size. + * + * \note Enabling this option causes overlap of input and output buffers + * not to be supported by PSA functions. + */ +#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS + /** * \def MBEDTLS_PSA_CRYPTO_CONFIG * @@ -315,7 +335,7 @@ * * Uncomment to enable generic message digest wrappers. */ -#define MBEDTLS_MD_C +//#define MBEDTLS_MD_C /** * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C diff --git a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small_client.h b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small_client.h index dcab54c5c..139b81462 100644 --- a/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small_client.h +++ b/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_profile_small_client.h @@ -331,7 +331,7 @@ * * Uncomment to enable generic message digest wrappers. */ -#define MBEDTLS_MD_C +//#define MBEDTLS_MD_C /** * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C diff --git a/lib/ext/tf-m-tests/version.txt b/lib/ext/tf-m-tests/version.txt index edd79c4fc..fde44504f 100644 --- a/lib/ext/tf-m-tests/version.txt +++ b/lib/ext/tf-m-tests/version.txt @@ -1,11 +1,12 @@ -#------------------------------------------------------- -# Copyright (c) 2023, Arm Limited. All rights reserved. +#------------------------------------------------------------------------------- +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors # # SPDX-License-Identifier: BSD-3-Clause -#------------------------------------------------------- +#------------------------------------------------------------------------------- # This file tracks the recommended tf-m-tests version to verify TF-M. -# Developers should keep the version value up to date to make sure it fits current TF-M version. +# Developers should keep the version value up to date to make sure it fits +# current TF-M version. # TF-M does not rely on this file to build. -version=TF-Mv2.1.0 +version=TF-Mv2.1.2 diff --git a/platform/CMakeLists.txt b/platform/CMakeLists.txt index 4555caf1e..7f404ef64 100644 --- a/platform/CMakeLists.txt +++ b/platform/CMakeLists.txt @@ -28,9 +28,6 @@ endif() set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR} CACHE PATH "Path to platform directory") -# Skip "up-to-date" prints to avoid flooding the build output. Just print "installing" -set(CMAKE_INSTALL_MESSAGE LAZY) - add_subdirectory(ext/target/${TFM_PLATFORM} target) #====================== CMSIS stack override interface ========================# @@ -63,6 +60,7 @@ target_include_directories(platform_common_interface target_include_directories(platform_s PUBLIC $<$:${CMAKE_CURRENT_SOURCE_DIR}/ext/accelerator/interface> + ../secure_fw/spm/include/private ) target_sources(platform_s @@ -385,6 +383,7 @@ target_compile_definitions(platform_region_defs BL1_TRAILER_SIZE=${BL1_TRAILER_SIZE} $<$:PLATFORM_DEFAULT_BL1> $<$:SECURE_UART1> + $<$:CONFIG_TFM_LOG_SHARE_UART> DAUTH_${DEBUG_AUTHENTICATION} $<$:MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}> $<$:MCUBOOT_BUILTIN_KEY> diff --git a/platform/ext/accelerator/CMakeLists.txt b/platform/ext/accelerator/CMakeLists.txt index f300f7d47..2f7b5406d 100644 --- a/platform/ext/accelerator/CMakeLists.txt +++ b/platform/ext/accelerator/CMakeLists.txt @@ -5,6 +5,18 @@ # #------------------------------------------------------------------------------- +cmake_policy(SET CMP0079 NEW) + +# TODO: Verify that this works for both minimal and normal configuration +target_compile_definitions(tfm_config + INTERFACE + CRYPTO_HW_ACCELERATOR + CRYPTO_EXT_RNG +) + +# When using nrf_security we don't need these build scripts +return() + if(BL2) add_library(bl2_crypto_hw STATIC) endif() diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c index 832c95885..66e91836c 100644 --- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c +++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_hash.c @@ -198,6 +198,9 @@ void cc3xx_lowlevel_hash_finish(uint32_t *res, size_t length) P_CC3XX->hash.hash_pad_cfg = 0x4U; } + /* Wait until HASH engine is idle */ + while (P_CC3XX->cc_ctl.hash_busy != 0) {} + get_hash_h(res, length); cc3xx_lowlevel_hash_uninit(); diff --git a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_pka.c b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_pka.c index bfbc7e97f..99b4a6202 100644 --- a/platform/ext/accelerator/cc312/cc312-rom/cc3xx_pka.c +++ b/platform/ext/accelerator/cc312/cc312-rom/cc3xx_pka.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, The TrustedFirmware-M Contributors. All rights reserved. + * Copyright (c) 2023-2024, The TrustedFirmware-M Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -19,7 +19,12 @@ #define PKA_WORD_SIZE 8 #define PKA_WORD_BIT_SIZE (PKA_WORD_SIZE * 8) + +#ifdef CC3XX_CONFIG_HW_VERSION_CC310 +#define PKA_SRAM_SIZE 0x1000 /* 4KiB */ +#else #define PKA_SRAM_SIZE 0x1800 /* 6KiB */ +#endif /* The hardware requires and extra word and byte to deal with carries etc * (which would then later be removed by a reduction operation). The TRM @@ -162,6 +167,9 @@ static void pka_init_from_state(void) P_CC3XX->misc.pka_clk_enable = 1; P_CC3XX->pka.pka_sw_reset = 1; + /* Wait for SW reset to complete before proceeding */ + while(!P_CC3XX->pka.pka_done) {} + /* The TRM says that this register is a byte-size, but it is in fact a * bit-size. */ @@ -1275,4 +1283,3 @@ void cc3xx_lowlevel_pka_reduce(cc3xx_pka_reg_id_t r0) */ cc3xx_lowlevel_pka_and(r0, CC3XX_PKA_REG_N_MASK, r0); } - diff --git a/platform/ext/accelerator/cc312/cc312-rom/psa_driver_api/src/cc3xx_psa_aead.c b/platform/ext/accelerator/cc312/cc312-rom/psa_driver_api/src/cc3xx_psa_aead.c index 29423a89d..c07058853 100644 --- a/platform/ext/accelerator/cc312/cc312-rom/psa_driver_api/src/cc3xx_psa_aead.c +++ b/platform/ext/accelerator/cc312/cc312-rom/psa_driver_api/src/cc3xx_psa_aead.c @@ -70,7 +70,9 @@ static psa_status_t aead_crypt( CC3XX_ASSERT(key_buffer != NULL); CC3XX_ASSERT(nonce != NULL); CC3XX_ASSERT(!additional_data_length ^ (additional_data != NULL)); - CC3XX_ASSERT(input != NULL); + if (input_length != 0) { + CC3XX_ASSERT(input != NULL); + } CC3XX_ASSERT(!output_size ^ (output != NULL)); CC3XX_ASSERT(output_length != NULL); diff --git a/platform/ext/accelerator/cc312/crypto_accelerator_config.h b/platform/ext/accelerator/cc312/crypto_accelerator_config.h index 6cf595554..419c27941 100644 --- a/platform/ext/accelerator/cc312/crypto_accelerator_config.h +++ b/platform/ext/accelerator/cc312/crypto_accelerator_config.h @@ -114,6 +114,7 @@ extern "C" { #define MBEDTLS_PSA_ACCEL_ALG_DETERMINISTIC_ECDSA #define MBEDTLS_HMAC_DRBG_C #define MBEDTLS_MD_C +#define MBEDTLS_MD_CAN_SHA256 #endif #ifdef PSA_WANT_ALG_CBC_NO_PADDING diff --git a/platform/ext/common/boot_hal_bl1_1.c b/platform/ext/common/boot_hal_bl1_1.c index 8bc52732a..04d125ac6 100644 --- a/platform/ext/common/boot_hal_bl1_1.c +++ b/platform/ext/common/boot_hal_bl1_1.c @@ -104,7 +104,7 @@ __WEAK int32_t boot_platform_init(void) #endif /* TFM_BL1_2_IN_FLASH */ /* Clear boot data area */ - memset((void*)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void*)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); return 0; } @@ -175,20 +175,20 @@ static int boot_add_data_to_shared_area(uint8_t major_type, return -1; } - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; /* Check whether the shared area needs to be initialized. */ if ((boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) || - (boot_data->header.tlv_tot_len > BOOT_TFM_SHARED_DATA_SIZE)) { + (boot_data->header.tlv_tot_len > SHARED_BOOT_MEASUREMENT_SIZE)) { - memset((void *)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void *)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); boot_data->header.tlv_magic = SHARED_DATA_TLV_INFO_MAGIC; boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE; } /* Get the boundaries of TLV section. */ - tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len; - offset = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE; + tlv_end = SHARED_BOOT_MEASUREMENT_BASE + boot_data->header.tlv_tot_len; + offset = SHARED_BOOT_MEASUREMENT_BASE + SHARED_DATA_HEADER_SIZE; /* Check whether TLV entry is already added. Iterates over the TLV section * looks for the same entry if found then returns with error. @@ -213,7 +213,7 @@ static int boot_add_data_to_shared_area(uint8_t major_type, (UINT16_MAX - boot_data->header.tlv_tot_len)) { return -1; } else if ((SHARED_DATA_ENTRY_SIZE(size) + boot_data->header.tlv_tot_len) > - BOOT_TFM_SHARED_DATA_SIZE) { + SHARED_BOOT_MEASUREMENT_SIZE) { return -1; } diff --git a/platform/ext/common/boot_hal_bl1_2.c b/platform/ext/common/boot_hal_bl1_2.c index f237cd231..0942a412f 100644 --- a/platform/ext/common/boot_hal_bl1_2.c +++ b/platform/ext/common/boot_hal_bl1_2.c @@ -230,20 +230,20 @@ static int boot_add_data_to_shared_area(uint8_t major_type, return -1; } - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; /* Check whether the shared area needs to be initialized. */ if ((boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) || - (boot_data->header.tlv_tot_len > BOOT_TFM_SHARED_DATA_SIZE)) { + (boot_data->header.tlv_tot_len > SHARED_BOOT_MEASUREMENT_SIZE)) { - memset((void *)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void *)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); boot_data->header.tlv_magic = SHARED_DATA_TLV_INFO_MAGIC; boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE; } /* Get the boundaries of TLV section. */ - tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len; - offset = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE; + tlv_end = SHARED_BOOT_MEASUREMENT_BASE + boot_data->header.tlv_tot_len; + offset = SHARED_BOOT_MEASUREMENT_BASE + SHARED_DATA_HEADER_SIZE; /* Check whether TLV entry is already added. Iterates over the TLV section * looks for the same entry if found then returns with error. @@ -268,7 +268,7 @@ static int boot_add_data_to_shared_area(uint8_t major_type, (UINT16_MAX - boot_data->header.tlv_tot_len)) { return -1; } else if ((SHARED_DATA_ENTRY_SIZE(size) + boot_data->header.tlv_tot_len) > - BOOT_TFM_SHARED_DATA_SIZE) { + SHARED_BOOT_MEASUREMENT_SIZE) { return -1; } diff --git a/platform/ext/common/boot_hal_bl2.c b/platform/ext/common/boot_hal_bl2.c index 103e183ef..0d0b9cb15 100644 --- a/platform/ext/common/boot_hal_bl2.c +++ b/platform/ext/common/boot_hal_bl2.c @@ -264,20 +264,20 @@ static int boot_add_data_to_shared_area(uint8_t major_type, return -1; } - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; /* Check whether the shared area needs to be initialized. */ if ((boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) || - (boot_data->header.tlv_tot_len > BOOT_TFM_SHARED_DATA_SIZE)) { + (boot_data->header.tlv_tot_len > SHARED_BOOT_MEASUREMENT_SIZE)) { - memset((void *)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void *)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); boot_data->header.tlv_magic = SHARED_DATA_TLV_INFO_MAGIC; boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE; } /* Get the boundaries of TLV section. */ - tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len; - offset = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE; + tlv_end = SHARED_BOOT_MEASUREMENT_BASE + boot_data->header.tlv_tot_len; + offset = SHARED_BOOT_MEASUREMENT_BASE + SHARED_DATA_HEADER_SIZE; /* Check whether TLV entry is already added. Iterates over the TLV section * looks for the same entry if found then returns with error. @@ -302,7 +302,7 @@ static int boot_add_data_to_shared_area(uint8_t major_type, (UINT16_MAX - boot_data->header.tlv_tot_len)) { return -1; } else if ((SHARED_DATA_ENTRY_SIZE(size) + boot_data->header.tlv_tot_len) > - BOOT_TFM_SHARED_DATA_SIZE) { + SHARED_BOOT_MEASUREMENT_SIZE) { return -1; } diff --git a/platform/ext/common/exception_info.c b/platform/ext/common/exception_info.c index 03264ba32..5a765f565 100644 --- a/platform/ext/common/exception_info.c +++ b/platform/ext/common/exception_info.c @@ -9,6 +9,7 @@ #include "tfm_spm_log.h" /* "exception_info.h" must be the last include because of the IAR pragma */ #include "exception_info.h" +#include "uart_stdout.h" static struct exception_info_t exception_info; @@ -168,6 +169,10 @@ static void dump_error(const struct exception_info_t *ctx) { bool stack_error = false; +#if defined(CONFIG_TFM_LOG_SHARE_UART) + stdio_init(); +#endif + SPMLOG_ERRMSG("FATAL ERROR: "); switch (ctx->VECTACTIVE) { case EXCEPTION_TYPE_HARDFAULT: diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld index 67c96a9a7..71aac990c 100644 --- a/platform/ext/common/gcc/tfm_common_s.ld +++ b/platform/ext/common/gcc/tfm_common_s.ld @@ -152,6 +152,9 @@ SECTIONS *libflash_drivers*:(SORT_BY_ALIGNMENT(.text*)) *libflash_drivers*:(SORT_BY_ALIGNMENT(.rodata*)) KEEP(*(.ramfunc)) +#if defined(S_RAM_CODE_EXTRA_SECTION_NAME) + KEEP(*(S_RAM_CODE_EXTRA_SECTION_NAME)) +#endif . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */ } > CODE_RAM AT > FLASH @@ -286,6 +289,15 @@ SECTIONS . = ALIGN(TFM_LINKER_PT_RO_ALIGNMENT); Image$$PT_RO_END$$Base = .; +#if defined(CONFIG_PSA_NEED_CRACEN_KMU_DRIVER) + .nrf_kmu_reserved_push_area S_DATA_START (NOLOAD): + { + __nrf_kmu_reserved_push_area = .; + *(.nrf_kmu_reserved_push_area) + __nrf_kmu_reserved_push_area_end = .; + } > RAM +#endif /* CONFIG_PSA_NEED_CRACEN_KMU_DRIVER */ + /**** Base address of secure data area */ .tfm_secure_data_start : { diff --git a/platform/ext/target/arm/mps3/common/provisioning/CMakeLists.txt b/platform/ext/common/provisioning_bundle/CMakeLists.txt similarity index 83% rename from platform/ext/target/arm/mps3/common/provisioning/CMakeLists.txt rename to platform/ext/common/provisioning_bundle/CMakeLists.txt index 5ce424b36..26f6bd93f 100644 --- a/platform/ext/target/arm/mps3/common/provisioning/CMakeLists.txt +++ b/platform/ext/common/provisioning_bundle/CMakeLists.txt @@ -11,14 +11,14 @@ find_package(Python3) add_executable(provisioning_bundle) if(${TFM_DUMMY_PROVISIONING}) - include(${CMAKE_SOURCE_DIR}/platform/ext/target/arm/mps3/common/provisioning/provisioning_config.cmake) + include(${CMAKE_SOURCE_DIR}/platform/ext/common/provisioning_bundle/provisioning_config.cmake) else() include("${PROVISIONING_KEYS_CONFIG}" OPTIONAL RESULT_VARIABLE PROVISIONING_KEYS_CONFIG_PATH) if(NOT PROVISIONING_KEYS_CONFIG_PATH) message(WARNING "The PROVISIONING_KEYS_CONFIG is not set. If the keys are not passed via the command line then \ random numbers will be used for HUK/IAK etc. \ To create and use a PROVISIONING_KEYS_CONFIG file, \ - see the example in: tf-m/platform/ext/target/arm/mps3/common/provisioning/provisioning_config.cmake") + see the example in: tf-m/platform/ext/common/provisioning_bundle/provisioning_config.cmake") endif() endif() @@ -28,11 +28,13 @@ set_target_properties(provisioning_bundle RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin" ) -target_add_scatter_file(provisioning_bundle - $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.sct> - $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.ld> - $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.icf> -) +if(${PLATFORM_DEFAULT_PROV_LINKER_SCRIPT}) + target_add_scatter_file(provisioning_bundle + $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.sct> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.ld> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/provisioning_bundle.icf> + ) +endif() target_link_options(provisioning_bundle PRIVATE @@ -75,23 +77,23 @@ target_compile_definitions(provisioning_bundle MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h" ) -add_custom_target(encrypted_provisioning_bundle +add_custom_target(provisioning_bundle_bin ALL - SOURCES encrypted_provisioning_bundle.bin + SOURCES provisioning_bundle.bin ) -add_custom_command(OUTPUT encrypted_provisioning_bundle.bin +add_custom_command(OUTPUT provisioning_bundle.bin DEPENDS $/provisioning_bundle.axf DEPENDS provisioning_bundle DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/create_provisioning_bundle.py COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/create_provisioning_bundle.py --provisioning_bundle_axf ${CMAKE_BINARY_DIR}/bin/provisioning_bundle.axf - --bundle_output_file encrypted_provisioning_bundle.bin + --bundle_output_file provisioning_bundle.bin --code_pad_size ${PROVISIONING_CODE_PADDED_SIZE} --data_pad_size ${PROVISIONING_DATA_PADDED_SIZE} --values_pad_size ${PROVISIONING_VALUES_PADDED_SIZE} --magic "0xC0DEFEED" - COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_CURRENT_BINARY_DIR}/encrypted_provisioning_bundle.bin ${CMAKE_BINARY_DIR}/bin/encrypted_provisioning_bundle.bin + COMMAND ${CMAKE_COMMAND} -E copy ${CMAKE_CURRENT_BINARY_DIR}/provisioning_bundle.bin ${CMAKE_BINARY_DIR}/bin/provisioning_bundle.bin ) target_sources(platform_s @@ -124,6 +126,7 @@ add_custom_command(OUTPUT provisioning_data.c ${CMAKE_CURRENT_BINARY_DIR}/provisioning_data.c --bl2_rot_priv_key_0=${MCUBOOT_KEY_S} --bl2_rot_priv_key_1=${MCUBOOT_KEY_NS} + --bl2_mcuboot_hw_key=${MCUBOOT_HW_KEY} --template_path=${CMAKE_CURRENT_SOURCE_DIR} --secure_debug_pk=${SECURE_DEBUG_PK} --huk=${HUK} diff --git a/platform/ext/target/arm/mps3/common/provisioning/bl2_provisioning.c b/platform/ext/common/provisioning_bundle/bl2_provisioning.c similarity index 88% rename from platform/ext/target/arm/mps3/common/provisioning/bl2_provisioning.c rename to platform/ext/common/provisioning_bundle/bl2_provisioning.c index f95638557..761a6a444 100644 --- a/platform/ext/target/arm/mps3/common/provisioning/bl2_provisioning.c +++ b/platform/ext/common/provisioning_bundle/bl2_provisioning.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,7 @@ #include "string.h" #include "provisioning_bundle.h" -static const volatile struct provisioning_bundle *encrypted_bundle = +static const volatile struct provisioning_bundle *bundle = (const struct provisioning_bundle *)PROVISIONING_BUNDLE_START; static enum tfm_plat_err_t provision_assembly_and_test(void); @@ -72,8 +72,8 @@ enum tfm_plat_err_t tfm_plat_provisioning_perform(void) if (lcs == PLAT_OTP_LCS_ASSEMBLY_AND_TEST) { BOOT_LOG_INF("Waiting for provisioning bundle"); - while (encrypted_bundle->magic != BUNDLE_MAGIC || - encrypted_bundle->magic2 != BUNDLE_MAGIC) { + while (bundle->magic != BUNDLE_MAGIC || + bundle->magic2 != BUNDLE_MAGIC) { } err = provision_assembly_and_test(); @@ -91,13 +91,13 @@ static enum tfm_plat_err_t provision_assembly_and_test(void) /* TODO replace this with decrypt and auth */ memcpy((void*)PROVISIONING_BUNDLE_CODE_START, - (void *)encrypted_bundle->code, + (void *)bundle->code, PROVISIONING_BUNDLE_CODE_SIZE); memcpy((void*)PROVISIONING_BUNDLE_DATA_START, - (void *)&encrypted_bundle->data, + (void *)&bundle->data, PROVISIONING_BUNDLE_DATA_SIZE); memcpy((void*)PROVISIONING_BUNDLE_VALUES_START, - (void *)&encrypted_bundle->values, + (void *)&bundle->values, PROVISIONING_BUNDLE_VALUES_SIZE); BOOT_LOG_INF("Running provisioning bundle"); diff --git a/platform/ext/target/arm/mps3/common/provisioning/create_provisioning_bundle.py b/platform/ext/common/provisioning_bundle/create_provisioning_bundle.py similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/create_provisioning_bundle.py rename to platform/ext/common/provisioning_bundle/create_provisioning_bundle.py diff --git a/platform/ext/target/arm/mps3/common/provisioning/create_provisioning_data.py b/platform/ext/common/provisioning_bundle/create_provisioning_data.py similarity index 81% rename from platform/ext/target/arm/mps3/common/provisioning/create_provisioning_data.py rename to platform/ext/common/provisioning_bundle/create_provisioning_data.py index 8ec7f4483..a4f629f04 100644 --- a/platform/ext/target/arm/mps3/common/provisioning/create_provisioning_data.py +++ b/platform/ext/common/provisioning_bundle/create_provisioning_data.py @@ -31,11 +31,20 @@ os.environ['LANG'] = 'C.UTF-8' -def get_key_hash_c_array(key_file): +def get_key_hash_c_array(key_file, mcuboot_hw_key): key = imgtool.main.load_key(key_file) - digest = Hash(SHA256()) - digest.update(key.get_public_bytes()) - return hex_to_c_array(digest.finalize()) + key_bytes = [] + if mcuboot_hw_key == "ON": + digest = Hash(SHA256()) + digest.update(key.get_public_bytes()) + key_bytes = digest.finalize() + else: + # If the full key is used then use only the raw key + # bit string (subjectPublicKey). The offset of the + # bit string is 26, so drop the first 26 bytes. + key_bytes = key.get_public_bytes()[26:] + + return hex_to_c_array(key_bytes) @click.argument('outfile') @@ -43,6 +52,7 @@ def get_key_hash_c_array(key_file): @click.option('--bl2_rot_priv_key_1', metavar='filename', required=False) @click.option('--bl2_rot_priv_key_2', metavar='filename', required=False) @click.option('--bl2_rot_priv_key_3', metavar='filename', required=False) +@click.option('--bl2_mcuboot_hw_key', metavar='string', required=True) @click.option('--template_path', metavar='filename', required=True) @click.option('--secure_debug_pk', metavar='key', required=False) @click.option('--huk', metavar='key', required=False) @@ -58,7 +68,7 @@ def get_key_hash_c_array(key_file): provisioning_data_template.jinja2 template which is located in "template_path" and outputs it to "outfile"''') def generate_provisioning_data_c(outfile, bl2_rot_priv_key_0, - bl2_rot_priv_key_1, + bl2_rot_priv_key_1, bl2_mcuboot_hw_key, template_path, bl2_rot_priv_key_2, bl2_rot_priv_key_3, secure_debug_pk, huk, iak, boot_seed, @@ -72,19 +82,23 @@ def generate_provisioning_data_c(outfile, bl2_rot_priv_key_0, bl2_rot_pub_key_0_hash = "" if bool(bl2_rot_priv_key_0) is True: - bl2_rot_pub_key_0_hash = get_key_hash_c_array(bl2_rot_priv_key_0) + bl2_rot_pub_key_0_hash = get_key_hash_c_array( + bl2_rot_priv_key_0, bl2_mcuboot_hw_key) bl2_rot_pub_key_1_hash = "" if bool(bl2_rot_priv_key_1) is True: - bl2_rot_pub_key_1_hash = get_key_hash_c_array(bl2_rot_priv_key_1) + bl2_rot_pub_key_1_hash = get_key_hash_c_array( + bl2_rot_priv_key_1, bl2_mcuboot_hw_key) bl2_rot_pub_key_2_hash = "" if bool(bl2_rot_priv_key_2) is True: - bl2_rot_pub_key_2_hash = get_key_hash_c_array(bl2_rot_priv_key_2) + bl2_rot_pub_key_2_hash = get_key_hash_c_array( + bl2_rot_priv_key_2, bl2_mcuboot_hw_key) bl2_rot_pub_key_3_hash = "" if bool(bl2_rot_priv_key_3) is True: - bl2_rot_pub_key_3_hash = get_key_hash_c_array(bl2_rot_priv_key_3) + bl2_rot_pub_key_3_hash = get_key_hash_c_array( + bl2_rot_priv_key_3, bl2_mcuboot_hw_key) if bool(huk) is False: huk = hex_to_c_array(os.urandom(32)) diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.h b/platform/ext/common/provisioning_bundle/provisioning_bundle.h similarity index 72% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.h rename to platform/ext/common/provisioning_bundle/provisioning_bundle.h index 4a7edb13d..c6e55c1f5 100644 --- a/platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.h +++ b/platform/ext/common/provisioning_bundle/provisioning_bundle.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -18,6 +18,20 @@ extern "C" { #define BUNDLE_MAGIC 0xC0DEFEED +#ifdef MCUBOOT_SIGN_EC384 +#define PUB_KEY_HASH_SIZE (48) +#define PUB_KEY_SIZE (100) /* Size must be aligned to 4 Bytes */ +#else +#define PUB_KEY_HASH_SIZE (32) +#define PUB_KEY_SIZE (68) /* Size must be aligned to 4 Bytes */ +#endif /* MCUBOOT_SIGN_EC384 */ + +#ifdef MCUBOOT_BUILTIN_KEY +#define PROV_ROTPK_DATA_SIZE PUB_KEY_SIZE +#else +#define PROV_ROTPK_DATA_SIZE PUB_KEY_HASH_SIZE +#endif /* MCUBOOT_BUILTIN_KEY */ + __PACKED_STRUCT tfm_assembly_and_test_provisioning_data_t { uint8_t huk[32]; }; @@ -40,13 +54,13 @@ __PACKED_STRUCT tfm_psa_rot_provisioning_data_t { }; __PACKED_STRUCT bl2_assembly_and_test_provisioning_data_t { - uint8_t bl2_rotpk_0[32]; - uint8_t bl2_rotpk_1[32]; + uint8_t bl2_rotpk_0[PROV_ROTPK_DATA_SIZE]; + uint8_t bl2_rotpk_1[PROV_ROTPK_DATA_SIZE]; #if (MCUBOOT_IMAGE_NUMBER > 2) - uint8_t bl2_rotpk_2[32]; + uint8_t bl2_rotpk_2[PROV_ROTPK_DATA_SIZE]; #endif #if (MCUBOOT_IMAGE_NUMBER > 3) - uint8_t bl2_rotpk_3[32]; + uint8_t bl2_rotpk_3[PROV_ROTPK_DATA_SIZE]; #endif #ifdef PLATFORM_PSA_ADAC_SECURE_DEBUG @@ -63,7 +77,7 @@ __PACKED_STRUCT provisioning_data_t { struct __attribute__((__packed__)) provisioning_bundle { /* This section is authenticated */ uint32_t magic; - /* This section is encrypted */ + uint8_t code[PROVISIONING_BUNDLE_CODE_SIZE]; union __attribute__((__packed__)) { const struct provisioning_data_t values; diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.icf b/platform/ext/common/provisioning_bundle/provisioning_bundle.icf similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.icf rename to platform/ext/common/provisioning_bundle/provisioning_bundle.icf diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.ld b/platform/ext/common/provisioning_bundle/provisioning_bundle.ld similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.ld rename to platform/ext/common/provisioning_bundle/provisioning_bundle.ld diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.sct b/platform/ext/common/provisioning_bundle/provisioning_bundle.sct similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_bundle.sct rename to platform/ext/common/provisioning_bundle/provisioning_bundle.sct diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_code.c b/platform/ext/common/provisioning_bundle/provisioning_code.c similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_code.c rename to platform/ext/common/provisioning_bundle/provisioning_code.c diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_config.cmake b/platform/ext/common/provisioning_bundle/provisioning_config.cmake similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_config.cmake rename to platform/ext/common/provisioning_bundle/provisioning_config.cmake diff --git a/platform/ext/target/arm/mps3/common/provisioning/provisioning_data_template.jinja2 b/platform/ext/common/provisioning_bundle/provisioning_data_template.jinja2 similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/provisioning_data_template.jinja2 rename to platform/ext/common/provisioning_bundle/provisioning_data_template.jinja2 diff --git a/platform/ext/target/arm/mps3/common/provisioning/runtime_stub_provisioning.c b/platform/ext/common/provisioning_bundle/runtime_stub_provisioning.c similarity index 100% rename from platform/ext/target/arm/mps3/common/provisioning/runtime_stub_provisioning.c rename to platform/ext/common/provisioning_bundle/runtime_stub_provisioning.c diff --git a/platform/ext/common/template/nv_counters.c b/platform/ext/common/template/nv_counters.c index 44fb8f366..8e5b085e5 100644 --- a/platform/ext/common/template/nv_counters.c +++ b/platform/ext/common/template/nv_counters.c @@ -135,10 +135,10 @@ enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id, return read_nv_counter_otp(PLAT_OTP_ID_NV_COUNTER_BL2_3, size, val); #endif /* BL2 */ -#ifdef BL1 +#if defined(BL1) && defined(PLATFORM_DEFAULT_BL1) case (PLAT_NV_COUNTER_BL1_0): return read_nv_counter_otp(PLAT_OTP_ID_NV_COUNTER_BL1_0, size, val); -#endif /* BL1 */ +#endif /* BL1 && PLATFORM_DEFAULT_BL1 */ #if (PLATFORM_NS_NV_COUNTERS > 0) case (PLAT_NV_COUNTER_NS_0): @@ -264,11 +264,11 @@ enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, break; #endif /* BL2 */ -#ifdef BL1 +#if defined(BL1) && defined(PLATFORM_DEFAULT_BL1) case (PLAT_NV_COUNTER_BL1_0): err = set_nv_counter_otp(PLAT_OTP_ID_NV_COUNTER_BL1_0, value); break; -#endif /* BL1 */ +#endif /* BL1 && PLATFORM_DEFAULT_BL1 */ #if (PLATFORM_NS_NV_COUNTERS > 0) case (PLAT_NV_COUNTER_NS_0): diff --git a/platform/ext/common/template/tfm_hal_its_encryption.c b/platform/ext/common/template/tfm_hal_its_encryption.c new file mode 100644 index 000000000..a7a8f68a9 --- /dev/null +++ b/platform/ext/common/template/tfm_hal_its_encryption.c @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA. + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Derived from platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption.c + */ + +#include +#include + + +#include "config_tfm.h" +#include "platform/include/tfm_hal_its_encryption.h" +#include "platform/include/tfm_hal_its.h" +#include "platform/include/tfm_platform_system.h" + +#include "tfm_plat_crypto_keys.h" +#include "crypto_keys/tfm_builtin_key_ids.h" +#include "tfm_plat_otp.h" +#include "psa_manifest/pid.h" +#include "tfm_builtin_key_loader.h" + + +#ifndef ITS_CRYPTO_AEAD_ALG +#define ITS_CRYPTO_AEAD_ALG PSA_ALG_GCM +#endif + +/* The PSA key type used by this implementation */ +#define ITS_KEY_TYPE PSA_KEY_TYPE_AES +/* The PSA key usage required by this implementation */ +#define ITS_KEY_USAGE (PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT) + +/* The PSA algorithm used by this implementation */ +#define ITS_CRYPTO_ALG \ + PSA_ALG_AEAD_WITH_SHORTENED_TAG(ITS_CRYPTO_AEAD_ALG, TFM_ITS_AUTH_TAG_LENGTH) + +static uint32_t g_enc_counter; +static uint8_t g_enc_nonce_seed[TFM_ITS_ENC_NONCE_LENGTH - + sizeof(g_enc_counter)]; + +#if TFM_ITS_ENC_NONCE_LENGTH != 12 +#error "This implementation only supports a ITS nonce of size 12" +#endif + +/* Copy PS solution */ +static psa_status_t its_crypto_setkey(psa_key_handle_t *its_key, + const uint8_t *key_label, + size_t key_label_len) +{ + psa_status_t status; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_key_derivation_operation_t op = PSA_KEY_DERIVATION_OPERATION_INIT; + psa_key_handle_t seed_key = mbedtls_svc_key_id_make(TFM_SP_ITS, TFM_BUILTIN_KEY_ID_HUK); + + if (key_label_len == 0 || key_label == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Set the key attributes for the storage key */ + psa_set_key_usage_flags(&attributes, ITS_KEY_USAGE); + psa_set_key_algorithm(&attributes, ITS_CRYPTO_ALG); + psa_set_key_type(&attributes, ITS_KEY_TYPE); + psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(TFM_ITS_KEY_LENGTH)); + + status = psa_key_derivation_setup(&op, PSA_ALG_HKDF(PSA_ALG_SHA_256)); + if (status != PSA_SUCCESS) { + return status; + } + + /* Set up a key derivation operation with HUK */ + status = psa_key_derivation_input_key(&op, PSA_KEY_DERIVATION_INPUT_SECRET, + seed_key); + if (status != PSA_SUCCESS) { + goto err_release_op; + } + + /* Supply the ITS key label as an input to the key derivation */ + status = psa_key_derivation_input_bytes(&op, PSA_KEY_DERIVATION_INPUT_INFO, + key_label, + key_label_len); + if (status != PSA_SUCCESS) { + goto err_release_op; + } + + /* Create the storage key from the key derivation operation */ + status = psa_key_derivation_output_key(&attributes, &op, its_key); + if (status != PSA_SUCCESS) { + goto err_release_op; + } + + /* Free resources associated with the key derivation operation */ + status = psa_key_derivation_abort(&op); + if (status != PSA_SUCCESS) { + goto err_release_key; + } + + return PSA_SUCCESS; + +err_release_key: + (void)psa_destroy_key(*its_key); + +err_release_op: + (void)psa_key_derivation_abort(&op); + + return PSA_ERROR_GENERIC_ERROR; +} + +enum tfm_hal_status_t tfm_hal_its_aead_generate_nonce(uint8_t *nonce, + const size_t nonce_size) +{ + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + size_t output_length; + + if (nonce == NULL){ + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (g_enc_counter == UINT32_MAX) { + return TFM_HAL_ERROR_GENERIC; + } + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + if (g_enc_counter == 0) { + status = mbedtls_psa_external_get_random(NULL, &g_enc_nonce_seed[0], + sizeof(g_enc_nonce_seed), + &output_length); + if ((status != PSA_SUCCESS) || (sizeof(g_enc_nonce_seed) != output_length)) { + return TFM_HAL_ERROR_GENERIC; + } + } +#else + return TFM_HAL_ERROR_NOT_SUPPORTED; +#endif + + memcpy(nonce, g_enc_nonce_seed, sizeof(g_enc_nonce_seed)); + memcpy(nonce + sizeof(g_enc_nonce_seed), + &g_enc_counter, + sizeof(g_enc_counter)); + + g_enc_counter++; + + return TFM_HAL_SUCCESS; +} + +static bool ctx_is_valid(struct tfm_hal_its_auth_crypt_ctx *ctx) +{ + bool ret; + + if (ctx == NULL) { + return false; + } + + ret = (ctx->deriv_label == NULL && ctx->deriv_label_size != 0) || + (ctx->aad == NULL && ctx->aad_size != 0) || + (ctx->nonce == NULL && ctx->nonce_size != 0); + + return !ret; +} + +enum tfm_hal_status_t tfm_hal_its_aead_encrypt( + struct tfm_hal_its_auth_crypt_ctx *ctx, + const uint8_t *plaintext, + const size_t plaintext_size, + uint8_t *ciphertext, + const size_t ciphertext_size, + uint8_t *tag, + const size_t tag_size) +{ + + psa_status_t status; + psa_key_handle_t its_key = PSA_KEY_HANDLE_INIT; + size_t ciphertext_length; + + if (!ctx_is_valid(ctx) || tag == NULL) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (plaintext_size > ciphertext_size) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + status = its_crypto_setkey(&its_key, ctx->deriv_label, ctx->deriv_label_size); + if (status != PSA_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + status = psa_aead_encrypt(its_key, ITS_CRYPTO_ALG, + ctx->nonce, ctx->nonce_size, + ctx->aad, ctx->aad_size, + plaintext, plaintext_size, + ciphertext, ciphertext_size, + &ciphertext_length); + if (status != PSA_SUCCESS) { + (void)psa_destroy_key(its_key); + return TFM_HAL_ERROR_GENERIC; + } + + /* Copy the tag out of the output buffer */ + ciphertext_length -= TFM_ITS_AUTH_TAG_LENGTH; + (void)memcpy(tag, (ciphertext + ciphertext_length), tag_size); + + /* Destroy the transient key */ + status = psa_destroy_key(its_key); + if (status != PSA_SUCCESS) { + return PSA_ERROR_GENERIC_ERROR; + } + + return TFM_HAL_SUCCESS; +} + +enum tfm_hal_status_t tfm_hal_its_aead_decrypt( + struct tfm_hal_its_auth_crypt_ctx *ctx, + const uint8_t *ciphertext, + const size_t ciphertext_size, + uint8_t *tag, + const size_t tag_size, + uint8_t *plaintext, + const size_t plaintext_size) +{ + psa_status_t status; + psa_key_handle_t its_key = PSA_KEY_HANDLE_INIT; + size_t ciphertext_and_tag_size, out_len; + + if (!ctx_is_valid(ctx) || tag == NULL) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (plaintext_size < ciphertext_size) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + /* Copy the tag into the input buffer */ + (void)memcpy((ciphertext + ciphertext_size), tag, TFM_ITS_AUTH_TAG_LENGTH); + ciphertext_and_tag_size = ciphertext_size + TFM_ITS_AUTH_TAG_LENGTH; + + status = its_crypto_setkey(&its_key, ctx->deriv_label, ctx->deriv_label_size); + if (status != PSA_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + status = psa_aead_decrypt(its_key, ITS_CRYPTO_ALG, + ctx->nonce, ctx->nonce_size, + ctx->aad, ctx->aad_size, + ciphertext, ciphertext_and_tag_size, + plaintext, plaintext_size, + &out_len); + if (status != PSA_SUCCESS) { + (void)psa_destroy_key(its_key); + return TFM_HAL_ERROR_GENERIC; + } + + /* Destroy the transient key */ + status = psa_destroy_key(its_key); + if (status != PSA_SUCCESS) { + return PSA_ERROR_GENERIC_ERROR; + } + + return TFM_HAL_SUCCESS; +} + diff --git a/platform/ext/target/adi/max32657/CMakeLists.txt b/platform/ext/target/adi/max32657/CMakeLists.txt new file mode 100644 index 000000000..9b310c531 --- /dev/null +++ b/platform/ext/target/adi/max32657/CMakeLists.txt @@ -0,0 +1,254 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +################################################################################ + +# Get S - NS peripheral and memory access +include(s_ns_access.cmake) + +# Add hal_adi in build system +include(hal_adi.cmake) + +########################## Platform region defs ################################ +target_include_directories(platform_region_defs + INTERFACE + ./ + partition +) + +###### BL2 Related Cmake Configurations ######################################## +if(BL2) + # Add scatter files for BL2 + target_add_scatter_file(bl2 + $<$:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/gcc/${TARGET_LC}_sla.ld> + ) + + # Add startup file for BL2 + target_sources(bl2 + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/startup_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/sla_header_${TARGET_LC}.c + ) + + # Add includes for BL2 + target_include_directories(platform_bl2 + PUBLIC + partition + PRIVATE + . + ${PLATFORM_DIR}/.. + ) + + target_compile_options(platform_bl2 + PUBLIC + -mno-unaligned-access # Added to mitigate the unaligned access problem + ) + + target_sources(platform_bl2 + PRIVATE + cmsis_drivers/Driver_Flash.c + cmsis_drivers/Driver_USART.c + $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> + ) + + target_compile_definitions(platform_bl2 + PUBLIC + CMSIS_device_header="${TARGET_LC}.h" + ) + + # + # Process Trusted Edge Security Arhictecture (TESA) extention + # + include(tesa-toolkit.cmake) + +endif() + +###### TF-M Related Cmake Configurations ####################################### + +target_compile_definitions(tfm_s + PRIVATE + IS_SECURE_ENVIRONMENT + TFM_DATA_INITIALIZE # Enables copying of TF-M specific Data sections from Flash to RAM during startup +) + +target_add_scatter_file(tfm_s + $<$:${PLATFORM_DIR}/ext/common/gcc/tfm_common_s.ld> +) + +target_sources(tfm_s + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/startup_${TARGET_LC}.c + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c +) + +if(EXISTS "${CMAKE_BINARY_DIR}/../../adi_soc_peripheral_init.c") + target_sources(tfm_s + PRIVATE + ${CMAKE_BINARY_DIR}/../../adi_soc_peripheral_init.c + ) +endif() + +target_compile_definitions(tfm_s + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 +) + +target_sources(tfm_spm + PRIVATE + target_cfg.c + tfm_hal_isolation.c + tfm_hal_platform.c +) + +target_compile_definitions(platform_s + PUBLIC + CMSIS_device_header="${TARGET_LC}.h" + + $<$:TFM_S_REG_TEST> + $<$:TFM_NS_REG_TEST> +) + +target_compile_options(platform_s + PUBLIC + ${COMPILER_CMSE_FLAG} + -mno-unaligned-access # Added to mitigate the unaligned access problem +) + +target_sources(platform_s + PRIVATE + cmsis_drivers/Driver_Flash.c + cmsis_drivers/Driver_USART.c + cmsis_drivers/Driver_PPC.c + cmsis_drivers/Driver_MPC.c + device/src/mpc_sie200_drv.c + $<$>:${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/otp_max32657.c> + + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_hal_ioctl.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common + partition + device/inc + services/include + ${PLATFORM_DIR}/.. +) + +if(NOT PLATFORM_DEFAULT_PROVISIONING) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) + + target_compile_definitions(platform_region_defs + INTERFACE + PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} + PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} + PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} + ) +endif() + +#========================= Files for building NS platform =====================# + +install(FILES ${TARGET_PLATFORM_PATH}/cmsis_drivers/Driver_USART.c + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(FILES ${TARGET_PLATFORM_PATH}/partition/region_defs.h + ${TARGET_PLATFORM_PATH}/partition/flash_layout.h + ${TARGET_PLATFORM_PATH}/device/inc/mpc_sie200_drv.h + ${TARGET_PLATFORM_PATH}/platform_retarget.h + ${TARGET_PLATFORM_PATH}/target_cfg.h + ${TARGET_PLATFORM_PATH}/device_cfg.h + ${TARGET_PLATFORM_PATH}/tfm_peripherals_def.h + ${TARGET_PLATFORM_PATH}/RTE_Device.h + ${TARGET_PLATFORM_PATH}/cmsis.h + ${PLATFORM_DIR}/ext/common/test_interrupt.h + ${PLATFORM_DIR}/ext/driver/Driver_USART.h + ${PLATFORM_DIR}/ext/driver/Driver_Common.h + ${PLATFORM_DIR}/include/tfm_plat_defs.h + ${CMAKE_SOURCE_DIR}/lib/fih/inc/fih.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) + +install(DIRECTORY ${HAL_ADI_PERIPH_INC_DIR} + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) + +install(DIRECTORY ${HAL_ADI_CMSIS_INC_DIR} + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include/cmsis) + +install(FILES ${TARGET_PLATFORM_PATH}/device/src/startup_${TARGET_LC}.c + ${TARGET_PLATFORM_PATH}/device/src/system_${TARGET_LC}.c + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/device/src) + +install(FILES ${HAL_ADI_CMSIS_INC_DIR}/max32657.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/device/inc) + +install(FILES ${PLATFORM_DIR}/ext/common/gcc/tfm_common_ns.ld + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/linker_scripts) + +# copy all files from active platform directory +install(DIRECTORY ${TARGET_PLATFORM_PATH}/ns/ + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(FILES ${TARGET_PLATFORM_PATH}/cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Copy the platform specific config +install(FILES ${TARGET_PLATFORM_PATH}/config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Install test configs +install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Copy the S-NS peripheral & memory configuration +install(FILES ${TARGET_PLATFORM_PATH}/s_ns_access.cmake + DESTINATION ${CMAKE_BINARY_DIR}/../) + +# Export configuration flags +target_compile_definitions(tfm_spm + PUBLIC + $<$:ADI_NS_PRPH_GCR> + $<$:ADI_NS_PRPH_SIR> + $<$:ADI_NS_PRPH_FCR> + $<$:ADI_NS_PRPH_WDT> + $<$:ADI_NS_PRPH_AES> + $<$:ADI_NS_PRPH_AESKEY> + $<$:ADI_NS_PRPH_CRC> + $<$:ADI_NS_PRPH_GPIO0> + $<$:ADI_NS_PRPH_TIMER0> + $<$:ADI_NS_PRPH_TIMER1> + $<$:ADI_NS_PRPH_TIMER2> + $<$:ADI_NS_PRPH_TIMER3> + $<$:ADI_NS_PRPH_TIMER4> + $<$:ADI_NS_PRPH_TIMER5> + $<$:ADI_NS_PRPH_I3C> + $<$:ADI_NS_PRPH_UART> + $<$:ADI_NS_PRPH_SPI> + $<$:ADI_NS_PRPH_TRNG> + $<$:ADI_NS_PRPH_BTLE_DBB> + $<$:ADI_NS_PRPH_BTLE_RFFE> + $<$:ADI_NS_PRPH_RSTZ> + $<$:ADI_NS_PRPH_BOOST> + $<$:ADI_NS_PRPH_BBSIR> + $<$:ADI_NS_PRPH_BBFCR> + $<$:ADI_NS_PRPH_RTC> + $<$:ADI_NS_PRPH_WUT0> + $<$:ADI_NS_PRPH_WUT1> + $<$:ADI_NS_PRPH_PWR> + $<$:ADI_NS_PRPH_MCR> +) diff --git a/platform/ext/target/adi/max32657/RTE_Device.h b/platform/ext/target/adi/max32657/RTE_Device.h new file mode 100644 index 000000000..cc84193fa --- /dev/null +++ b/platform/ext/target/adi/max32657/RTE_Device.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2016-2018 ARM Limited + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] + +// PPC (Peripheral Protection Controller) [Driver_PPC] +// Configuration settings for Driver_PPC in component ::Drivers:PPC +#define RTE_PPC 1 +// PPC (Peripheral Protection Controller) [Driver_PPC] + +// FLASH (Flash Memory) [Driver_FLASH0] +// Configuration settings for Driver_FLASH0 in component ::Drivers:FLASH +#define RTE_FLASH0 1 +// FLASH (Flash Memory) [Driver_FLASH0] + +// MPC (Memory Protection Controller) [Driver_SRAM0_MPC] +// Configuration settings for Driver_SRAM0_MPC in component ::Drivers:MPC +#define RTE_SRAM0_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM0_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM1_MPC] +// Configuration settings for Driver_SRAM1_MPC in component ::Drivers:MPC +#define RTE_SRAM1_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM1_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM2_MPC] +// Configuration settings for Driver_SRAM2_MPC in component ::Drivers:MPC +#define RTE_SRAM2_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM2_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM3_MPC] +// Configuration settings for Driver_SRAM3_MPC in component ::Drivers:MPC +#define RTE_SRAM3_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM3_MPC] + +// MPC (Memory Protection Controller) [Driver_SRAM4_MPC] +// Configuration settings for Driver_SRAM4_MPC in component ::Drivers:MPC +#define RTE_SRAM4_MPC 1 +// MPC (Memory Protection Controller) [Driver_SRAM4_MPC] + +// MPC (Memory Protection Controller) [Driver_FLASH_MPC] +// Configuration settings for Driver_FLASH_MPC in component ::Drivers:MPC +#define RTE_FLASH_MPC 1 +// MPC (Memory Protection Controller) [Driver_FLASH_MPC] + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/adi/max32657/cmsis.h b/platform/ext/target/adi/max32657/cmsis.h new file mode 100644 index 000000000..1a7efc690 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MAX32657_CMSIS_H__ +#define __MAX32657_CMSIS_H__ + +#include "max32657.h" + +#endif /* __MAX32657_CMSIS_H__ */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c new file mode 100644 index 000000000..4fd67258e --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_Flash.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "Driver_Flash.h" +#include "platform_retarget.h" +#include "RTE_Device.h" +#include "mxc_errors.h" +#include "flc.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) ((void)arg) +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 1) + +/** + * Data width values for ARM_FLASH_CAPABILITIES::data_width + * \ref ARM_FLASH_CAPABILITIES + */ + enum { + DATA_WIDTH_8BIT = 0u, + DATA_WIDTH_16BIT, + DATA_WIDTH_32BIT, + DATA_WIDTH_ENUM_SIZE +}; + +static const uint32_t data_width_byte[DATA_WIDTH_ENUM_SIZE] = { + sizeof(uint8_t), + sizeof(uint16_t), + sizeof(uint32_t), +}; + +struct arm_flash_dev_t { + const uint32_t memory_base; /*!< FLASH memory base address */ + ARM_FLASH_INFO *data; /*!< FLASH data */ +}; + +/* Flash Status */ +static ARM_FLASH_STATUS FlashStatus = {0, 0, 0}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_FLASH_API_VERSION, + ARM_FLASH_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + 0, /* event_ready */ + 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ + 1 /* erase_chip */ +}; + +#if (RTE_FLASH0) +static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE, + .sector_size = FLASH0_SECTOR_SIZE, + .page_size = FLASH0_PAGE_SIZE, + .program_unit = FLASH0_PROGRAM_UNIT, + .erased_value = 0xFF +}; + +static struct arm_flash_dev_t ARM_FLASH0_DEV = { +#if (__DOMAIN_NS == 1) + .memory_base = FLASH0_BASE_NS, +#else + .memory_base = FLASH0_BASE_S, +#endif /* __DOMAIN_NS == 1 */ + .data = &(ARM_FLASH0_DEV_DATA)}; + +struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV; + +/* + * Functions + */ + +static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) +{ + ARG_UNUSED(cb_event); + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static int32_t ARM_Flash_ReadData(uint32_t offset, void *data, uint32_t cnt) +{ + /* Check flash memory boundaries */ + if ((offset + cnt) >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* CMSIS ARM_FLASH_ReadData API requires the offset data type size aligned. + * Data type size is specified by the data_width in ARM_FLASH_CAPABILITIES. + */ + if (offset % data_width_byte[DriverCapabilities.data_width] != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Conversion between data items and bytes */ + uint32_t addr = FLASH0_DEV->memory_base + offset; + int num_of_bytes = cnt * data_width_byte[DriverCapabilities.data_width]; + + MXC_FLC_Read(addr, data, num_of_bytes); + + return cnt; +} + +static int32_t ARM_Flash_ProgramData(uint32_t offset, const void *data, uint32_t cnt) +{ + /* Check flash memory boundaries */ + if ((offset + cnt) >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + uint32_t addr = FLASH0_DEV->memory_base + offset; + + if(MXC_FLC_Write(addr, cnt, (uint32_t *)data) != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + return cnt; +} + +static int32_t ARM_Flash_EraseSector(uint32_t offset) +{ + /* Check flash memory boundaries */ + if (offset >= FLASH0_SIZE) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + /* Sector shall be aligned, check it */ + if ((offset % FLASH0_DEV->data->sector_size) != 0) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + uint32_t addr = FLASH0_DEV->memory_base + offset; + + if (MXC_FLC_PageErase(addr) != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_Flash_EraseChip(void) +{ + if (DriverCapabilities.erase_chip == 1) { + if(MXC_FLC_MassErase() != E_NO_ERROR) { + return ARM_DRIVER_ERROR_PARAMETER; + } + } else { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static ARM_FLASH_STATUS ARM_Flash_GetStatus(void) +{ + return FlashStatus; +} + +static ARM_FLASH_INFO* ARM_Flash_GetInfo(void) +{ + return FLASH0_DEV->data; +} + +ARM_DRIVER_FLASH Driver_FLASH0 = { + ARM_Flash_GetVersion, + ARM_Flash_GetCapabilities, + ARM_Flash_Initialize, + ARM_Flash_Uninitialize, + ARM_Flash_PowerControl, + ARM_Flash_ReadData, + ARM_Flash_ProgramData, + ARM_Flash_EraseSector, + ARM_Flash_EraseChip, + ARM_Flash_GetStatus, + ARM_Flash_GetInfo +}; +#endif /* RTE_FLASH0 */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c new file mode 100644 index 000000000..2f357fb68 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_MPC.c @@ -0,0 +1,944 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "Driver_MPC.h" + +#include "mxc_device.h" +#include "platform_retarget.h" +#include "RTE_Device.h" +#include "mpc_sie200_drv.h" + +/* ARM MPC SSE 200 driver structures */ +#ifdef RTE_SRAM0_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM0_DEV_CFG_S = { + .base = MPC_SRAM0_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM0_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM0_DEV_S = { + &(MPC_SRAM0_DEV_CFG_S), + &(MPC_SRAM0_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM1_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM1_DEV_CFG_S = { + .base = MPC_SRAM1_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM1_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM1_DEV_S = { + &(MPC_SRAM1_DEV_CFG_S), + &(MPC_SRAM1_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM2_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM2_DEV_CFG_S = { + .base = MPC_SRAM2_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM2_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM2_DEV_S = { + &(MPC_SRAM2_DEV_CFG_S), + &(MPC_SRAM2_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM3_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM3_DEV_CFG_S = { + .base = MPC_SRAM3_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM3_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM3_DEV_S = { + &(MPC_SRAM3_DEV_CFG_S), + &(MPC_SRAM3_DEV_DATA_S)}; +#endif + +#ifdef RTE_SRAM4_MPC +static const struct mpc_sie200_dev_cfg_t MPC_SRAM4_DEV_CFG_S = { + .base = MPC_SRAM4_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_SRAM4_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_SRAM4_DEV_S = { + &(MPC_SRAM4_DEV_CFG_S), + &(MPC_SRAM4_DEV_DATA_S)}; +#endif + +#ifdef RTE_FLASH_MPC +static const struct mpc_sie200_dev_cfg_t MPC_FLASH_DEV_CFG_S = { + .base = MPC_FLASH_BASE_S}; +static struct mpc_sie200_dev_data_t MPC_FLASH_DEV_DATA_S = { + .range_list = 0, + .nbr_of_ranges = 0, + .state = 0, + .reserved = 0}; +struct mpc_sie200_dev_t MPC_FLASH_DEV_S = { + &(MPC_FLASH_DEV_CFG_S), + &(MPC_FLASH_DEV_DATA_S)}; +#endif + +/* driver version */ +#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_MPC_API_VERSION, + ARM_MPC_DRV_VERSION}; + +static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void) +{ + return DriverVersion; +} + +/* + * \brief Translates error codes from native API to CMSIS API. + * + * \param[in] err Error code to translate (\ref mpc_sie200_error_t). + * + * \return Returns CMSIS error code. + */ +static int32_t error_trans(enum mpc_sie200_error_t err) +{ + switch (err) + { + case MPC_SIE200_ERR_NONE: + return ARM_DRIVER_OK; + case MPC_SIE200_INVALID_ARG: + return ARM_DRIVER_ERROR_PARAMETER; + case MPC_SIE200_NOT_INIT: + return ARM_MPC_ERR_NOT_INIT; + case MPC_SIE200_ERR_NOT_IN_RANGE: + return ARM_MPC_ERR_NOT_IN_RANGE; + case MPC_SIE200_ERR_NOT_ALIGNED: + return ARM_MPC_ERR_NOT_ALIGNED; + case MPC_SIE200_ERR_INVALID_RANGE: + return ARM_MPC_ERR_INVALID_RANGE; + case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE: + return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + /* default: The default is not defined intentionally to force the + * compiler to check that all the enumeration values are + * covered in the switch. + */ + } +} + +#if (RTE_SRAM0_MPC) +/* Ranges controlled by this SRAM0_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM0_RANGE_S = { + .base = MPC_SRAM0_RANGE_BASE_S, + .limit = MPC_SRAM0_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM0_RANGE_NS = { + .base = MPC_SRAM0_RANGE_BASE_NS, + .limit = MPC_SRAM0_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM0_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM0_RANGE_LIST[MPC_SRAM0_RANGE_LIST_LEN] = + {&MPC_SRAM0_RANGE_S, &MPC_SRAM0_RANGE_NS}; + +/* SRAM0_MPC Driver wrapper functions */ +static int32_t SRAM0_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM0_DEV_S, + MPC_SRAM0_RANGE_LIST, + MPC_SRAM0_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM0_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM0_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM0_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM0_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM0_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM0_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM0_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM0_DEV_S); + + return error_trans(ret); +} + +static void SRAM0_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM0_DEV_S); +} + +static void SRAM0_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM0_DEV_S); +} + +static uint32_t SRAM0_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM0_DEV_S); +} + +static int32_t SRAM0_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM0_DEV_S); +} + +/* SRAM0_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM0_MPC; +ARM_DRIVER_MPC Driver_SRAM0_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM0_MPC_Initialize, + .Uninitialize = SRAM0_MPC_Uninitialize, + .GetBlockSize = SRAM0_MPC_GetBlockSize, + .GetCtrlConfig = SRAM0_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM0_MPC_SetCtrlConfig, + .ConfigRegion = SRAM0_MPC_ConfigRegion, + .GetRegionConfig = SRAM0_MPC_GetRegionConfig, + .EnableInterrupt = SRAM0_MPC_EnableInterrupt, + .DisableInterrupt = SRAM0_MPC_DisableInterrupt, + .ClearInterrupt = SRAM0_MPC_ClearInterrupt, + .InterruptState = SRAM0_MPC_InterruptState, + .LockDown = SRAM0_MPC_LockDown, +}; +#endif /* RTE_SRAM0_MPC */ + +#if (RTE_SRAM1_MPC) +/* Ranges controlled by this SRAM1_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM1_RANGE_S = { + .base = MPC_SRAM1_RANGE_BASE_S, + .limit = MPC_SRAM1_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM1_RANGE_NS = { + .base = MPC_SRAM1_RANGE_BASE_NS, + .limit = MPC_SRAM1_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM1_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM1_RANGE_LIST[MPC_SRAM1_RANGE_LIST_LEN] = + {&MPC_SRAM1_RANGE_S, &MPC_SRAM1_RANGE_NS}; + +/* SRAM1_MPC Driver wrapper functions */ +static int32_t SRAM1_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM1_DEV_S, + MPC_SRAM1_RANGE_LIST, + MPC_SRAM1_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM1_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM1_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM1_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM1_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM1_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM1_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM1_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM1_DEV_S); + + return error_trans(ret); +} + +static void SRAM1_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM1_DEV_S); +} + +static void SRAM1_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM1_DEV_S); +} + +static uint32_t SRAM1_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM1_DEV_S); +} + +static int32_t SRAM1_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM1_DEV_S); +} + +/* SRAM1_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM1_MPC; +ARM_DRIVER_MPC Driver_SRAM1_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM1_MPC_Initialize, + .Uninitialize = SRAM1_MPC_Uninitialize, + .GetBlockSize = SRAM1_MPC_GetBlockSize, + .GetCtrlConfig = SRAM1_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM1_MPC_SetCtrlConfig, + .ConfigRegion = SRAM1_MPC_ConfigRegion, + .GetRegionConfig = SRAM1_MPC_GetRegionConfig, + .EnableInterrupt = SRAM1_MPC_EnableInterrupt, + .DisableInterrupt = SRAM1_MPC_DisableInterrupt, + .ClearInterrupt = SRAM1_MPC_ClearInterrupt, + .InterruptState = SRAM1_MPC_InterruptState, + .LockDown = SRAM1_MPC_LockDown, +}; +#endif /* RTE_SRAM1_MPC */ + +#if (RTE_SRAM2_MPC) +/* Ranges controlled by this SRAM2_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM2_RANGE_S = { + .base = MPC_SRAM2_RANGE_BASE_S, + .limit = MPC_SRAM2_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM2_RANGE_NS = { + .base = MPC_SRAM2_RANGE_BASE_NS, + .limit = MPC_SRAM2_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM2_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM2_RANGE_LIST[MPC_SRAM2_RANGE_LIST_LEN] = + {&MPC_SRAM2_RANGE_S, &MPC_SRAM2_RANGE_NS}; + +/* SRAM2_MPC Driver wrapper functions */ +static int32_t SRAM2_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM2_DEV_S, + MPC_SRAM2_RANGE_LIST, + MPC_SRAM2_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM2_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM2_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM2_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM2_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM2_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM2_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM2_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM2_DEV_S); + + return error_trans(ret); +} + +static void SRAM2_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM2_DEV_S); +} + +static void SRAM2_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM2_DEV_S); +} + +static uint32_t SRAM2_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM2_DEV_S); +} + +static int32_t SRAM2_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM2_DEV_S); +} + +/* SRAM2_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM2_MPC; +ARM_DRIVER_MPC Driver_SRAM2_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM2_MPC_Initialize, + .Uninitialize = SRAM2_MPC_Uninitialize, + .GetBlockSize = SRAM2_MPC_GetBlockSize, + .GetCtrlConfig = SRAM2_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM2_MPC_SetCtrlConfig, + .ConfigRegion = SRAM2_MPC_ConfigRegion, + .GetRegionConfig = SRAM2_MPC_GetRegionConfig, + .EnableInterrupt = SRAM2_MPC_EnableInterrupt, + .DisableInterrupt = SRAM2_MPC_DisableInterrupt, + .ClearInterrupt = SRAM2_MPC_ClearInterrupt, + .InterruptState = SRAM2_MPC_InterruptState, + .LockDown = SRAM2_MPC_LockDown, +}; +#endif /* RTE_SRAM2_MPC */ + +#if (RTE_SRAM3_MPC) +/* Ranges controlled by this SRAM3_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM3_RANGE_S = { + .base = MPC_SRAM3_RANGE_BASE_S, + .limit = MPC_SRAM3_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM3_RANGE_NS = { + .base = MPC_SRAM3_RANGE_BASE_NS, + .limit = MPC_SRAM3_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM3_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM3_RANGE_LIST[MPC_SRAM3_RANGE_LIST_LEN] = + {&MPC_SRAM3_RANGE_S, &MPC_SRAM3_RANGE_NS}; + +/* SRAM3_MPC Driver wrapper functions */ +static int32_t SRAM3_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM3_DEV_S, + MPC_SRAM3_RANGE_LIST, + MPC_SRAM3_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM3_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM3_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM3_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM3_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM3_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM3_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM3_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM3_DEV_S); + + return error_trans(ret); +} + +static void SRAM3_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM3_DEV_S); +} + +static void SRAM3_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM3_DEV_S); +} + +static uint32_t SRAM3_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM3_DEV_S); +} + +static int32_t SRAM3_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM3_DEV_S); +} + +/* SRAM3_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM3_MPC; +ARM_DRIVER_MPC Driver_SRAM3_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM3_MPC_Initialize, + .Uninitialize = SRAM3_MPC_Uninitialize, + .GetBlockSize = SRAM3_MPC_GetBlockSize, + .GetCtrlConfig = SRAM3_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM3_MPC_SetCtrlConfig, + .ConfigRegion = SRAM3_MPC_ConfigRegion, + .GetRegionConfig = SRAM3_MPC_GetRegionConfig, + .EnableInterrupt = SRAM3_MPC_EnableInterrupt, + .DisableInterrupt = SRAM3_MPC_DisableInterrupt, + .ClearInterrupt = SRAM3_MPC_ClearInterrupt, + .InterruptState = SRAM3_MPC_InterruptState, + .LockDown = SRAM3_MPC_LockDown, +}; +#endif /* RTE_SRAM3_MPC */ + +#if (RTE_SRAM4_MPC) +/* Ranges controlled by this SRAM4_MPC */ +static struct mpc_sie200_memory_range_t MPC_SRAM4_RANGE_S = { + .base = MPC_SRAM4_RANGE_BASE_S, + .limit = MPC_SRAM4_RANGE_LIMIT_S, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_SRAM4_RANGE_NS = { + .base = MPC_SRAM4_RANGE_BASE_NS, + .limit = MPC_SRAM4_RANGE_LIMIT_NS, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_SRAM4_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_SRAM4_RANGE_LIST[MPC_SRAM4_RANGE_LIST_LEN] = + {&MPC_SRAM4_RANGE_S, &MPC_SRAM4_RANGE_NS}; + +/* SRAM4_MPC Driver wrapper functions */ +static int32_t SRAM4_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_SRAM4_DEV_S, + MPC_SRAM4_RANGE_LIST, + MPC_SRAM4_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t SRAM4_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_SRAM4_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_SRAM4_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_SRAM4_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_SRAM4_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_SRAM4_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t SRAM4_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_SRAM4_DEV_S); + + return error_trans(ret); +} + +static void SRAM4_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_SRAM4_DEV_S); +} + +static void SRAM4_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_SRAM4_DEV_S); +} + +static uint32_t SRAM4_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_SRAM4_DEV_S); +} + +static int32_t SRAM4_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_SRAM4_DEV_S); +} + +/* SRAM4_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_SRAM4_MPC; +ARM_DRIVER_MPC Driver_SRAM4_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = SRAM4_MPC_Initialize, + .Uninitialize = SRAM4_MPC_Uninitialize, + .GetBlockSize = SRAM4_MPC_GetBlockSize, + .GetCtrlConfig = SRAM4_MPC_GetCtrlConfig, + .SetCtrlConfig = SRAM4_MPC_SetCtrlConfig, + .ConfigRegion = SRAM4_MPC_ConfigRegion, + .GetRegionConfig = SRAM4_MPC_GetRegionConfig, + .EnableInterrupt = SRAM4_MPC_EnableInterrupt, + .DisableInterrupt = SRAM4_MPC_DisableInterrupt, + .ClearInterrupt = SRAM4_MPC_ClearInterrupt, + .InterruptState = SRAM4_MPC_InterruptState, + .LockDown = SRAM4_MPC_LockDown, +}; +#endif /* RTE_SRAM4_MPC */ + +#if (RTE_FLASH_MPC) +/* Ranges controlled by this FLASH_MPC */ +static struct mpc_sie200_memory_range_t MPC_FLASH_RANGE_S = { + .base = FLASH0_BASE_S, + .limit = FLASH0_BASE_S + FLASH0_SIZE - 1, + .attr = MPC_SIE200_SEC_ATTR_SECURE}; + +static struct mpc_sie200_memory_range_t MPC_FLASH_RANGE_NS = { + .base = FLASH0_BASE_NS, + .limit = FLASH0_BASE_NS + FLASH0_SIZE - 1, + .attr = MPC_SIE200_SEC_ATTR_NONSECURE}; + +#define MPC_FLASH_RANGE_LIST_LEN 2u +static const struct mpc_sie200_memory_range_t *MPC_FLASH_RANGE_LIST[MPC_FLASH_RANGE_LIST_LEN] = + {&MPC_FLASH_RANGE_S, &MPC_FLASH_RANGE_NS}; + +/* FLASH_MPC Driver wrapper functions */ +static int32_t FLASH_MPC_Initialize(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_init(&MPC_FLASH_DEV_S, + MPC_FLASH_RANGE_LIST, + MPC_FLASH_RANGE_LIST_LEN); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t FLASH_MPC_GetBlockSize(uint32_t *blk_size) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_block_size(&MPC_FLASH_DEV_S, blk_size); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_GetCtrlConfig(uint32_t *ctrl_val) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_ctrl(&MPC_FLASH_DEV_S, ctrl_val); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_SetCtrlConfig(uint32_t ctrl) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_set_ctrl(&MPC_FLASH_DEV_S, ctrl); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_GetRegionConfig(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR *attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_get_region_config(&MPC_FLASH_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t *)attr); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_ConfigRegion(uintptr_t base, + uintptr_t limit, + ARM_MPC_SEC_ATTR attr) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_config_region(&MPC_FLASH_DEV_S, base, limit, + (enum mpc_sie200_sec_attr_t)attr); + + return error_trans(ret); +} + +static int32_t FLASH_MPC_EnableInterrupt(void) +{ + enum mpc_sie200_error_t ret; + + ret = mpc_sie200_irq_enable(&MPC_FLASH_DEV_S); + + return error_trans(ret); +} + +static void FLASH_MPC_DisableInterrupt(void) +{ + mpc_sie200_irq_disable(&MPC_FLASH_DEV_S); +} + +static void FLASH_MPC_ClearInterrupt(void) +{ + mpc_sie200_clear_irq(&MPC_FLASH_DEV_S); +} + +static uint32_t FLASH_MPC_InterruptState(void) +{ + return mpc_sie200_irq_state(&MPC_FLASH_DEV_S); +} + +static int32_t FLASH_MPC_LockDown(void) +{ + return mpc_sie200_lock_down(&MPC_FLASH_DEV_S); +} + +/* FLASH_MPC Driver CMSIS access structure */ +extern ARM_DRIVER_MPC Driver_FLASH_MPC; +ARM_DRIVER_MPC Driver_FLASH_MPC = { + .GetVersion = ARM_MPC_GetVersion, + .Initialize = FLASH_MPC_Initialize, + .Uninitialize = FLASH_MPC_Uninitialize, + .GetBlockSize = FLASH_MPC_GetBlockSize, + .GetCtrlConfig = FLASH_MPC_GetCtrlConfig, + .SetCtrlConfig = FLASH_MPC_SetCtrlConfig, + .ConfigRegion = FLASH_MPC_ConfigRegion, + .GetRegionConfig = FLASH_MPC_GetRegionConfig, + .EnableInterrupt = FLASH_MPC_EnableInterrupt, + .DisableInterrupt = FLASH_MPC_DisableInterrupt, + .ClearInterrupt = FLASH_MPC_ClearInterrupt, + .InterruptState = FLASH_MPC_InterruptState, + .LockDown = FLASH_MPC_LockDown, +}; +#endif /* RTE_FLASH_MPC */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c new file mode 100644 index 000000000..eb3432581 --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_PPC.c @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "Driver_PPC.h" + +#include "mxc_device.h" +#include "RTE_Device.h" +#include "spc.h" + +/* Driver version */ +#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) + +#ifdef RTE_PPC + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_PPC_API_VERSION, + ARM_PPC_DRV_VERSION +}; + +static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void) +{ + return DriverVersion; +} + +static int32_t PPC_Initialize(void) +{ + return ARM_DRIVER_OK; +} + +static int32_t PPC_Uninitialize(void) +{ + return ARM_DRIVER_OK; +} + +static int32_t PPC_ConfigPeriph(uint8_t periph, + ARM_PPC_SecAttr sec_attr, + ARM_PPC_PrivAttr priv_attr) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + mxc_spc_priv_t mxc_priv; + + if (priv_attr == ARM_PPC_PRIV_ONLY) { + mxc_priv = MXC_SPC_PRIVILEGED; + } else { + mxc_priv = MXC_SPC_UNPRIVILEGED; + } + + if(sec_attr == ARM_PPC_SECURE_ONLY) { + MXC_SPC_SetSecure(mxc_periph); + } else { + MXC_SPC_SetNonSecure(mxc_periph); + } + MXC_SPC_SetPrivAccess(mxc_periph, mxc_priv); + + return ARM_DRIVER_OK; +} + +static uint32_t PPC_IsPeriphSecure(uint8_t periph) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + + if (MXC_SPC->apbsec & mxc_periph) { + return 0; // Non-Secure + } else { + return 1; // Secure + } +} + +static uint32_t PPC_IsPeriphPrivOnly(uint8_t periph) +{ + mxc_spc_periph_t mxc_periph = (1U << periph); + + if (MXC_SPC->apbpriv & mxc_periph) { + return 0; // unprivileged + } else { + return 1; // privileged + } +} + +static int32_t PPC_EnableInterrupt(void) +{ + MXC_SPC_PPC_EnableInt(MXC_F_SPC_PPC_INTEN_APBPPC); + + return ARM_DRIVER_OK; +} + +static void PPC_DisableInterrupt(void) +{ + MXC_SPC_PPC_DisableInt(MXC_F_SPC_PPC_INTEN_APBPPC); +} + +static void PPC_ClearInterrupt(void) +{ + MXC_SPC_PPC_ClearFlags(MXC_F_SPC_PPC_INTCLR_APBPPC); +} + +static uint32_t PPC_InterruptState(void) +{ + if (MXC_SPC_PPC_GetFlags() & MXC_F_SPC_PPC_STATUS_APBPPC) { + return 1; // pending interrupt + } else { + return 0; // no interrupt + } +} + +ARM_DRIVER_PPC Driver_PPC = { + .GetVersion = ARM_PPC_GetVersion, + .Initialize = PPC_Initialize, + .Uninitialize = PPC_Uninitialize, + .ConfigPeriph = PPC_ConfigPeriph, + .IsPeriphSecure = PPC_IsPeriphSecure, + .IsPeriphPrivOnly = PPC_IsPeriphPrivOnly, + .EnableInterrupt = PPC_EnableInterrupt, + .DisableInterrupt = PPC_DisableInterrupt, + .ClearInterrupt = PPC_ClearInterrupt, + .InterruptState = PPC_InterruptState +}; +#endif /* RTE_PPC */ diff --git a/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c new file mode 100644 index 000000000..225ee56ad --- /dev/null +++ b/platform/ext/target/adi/max32657/cmsis_drivers/Driver_USART.c @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "Driver_USART.h" + +#include "mxc_device.h" +#include "uart.h" +#include "RTE_Device.h" +#include "device_cfg.h" + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +/* Driver version */ +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */ + 0 /* Reserved */ +}; + +static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +typedef struct { + mxc_uart_regs_t* dev; /* UART regs */ + uint32_t tx_nbr_bytes; /* Number of bytes transfered */ + uint32_t rx_nbr_bytes; /* Number of bytes recevied */ + ARM_USART_SignalEvent_t cb_event; /* Callback function for events */ +} UARTx_Resources; + +static int32_t ARM_USARTx_Initialize(UARTx_Resources* uart_dev) +{ + /* Initializes generic UART driver */ + MXC_UART_Init(uart_dev->dev, DEFAULT_UART_BAUDRATE, MXC_UART_APB_CLK); + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Send(UARTx_Resources* uart_dev, const void *src, uint32_t len) +{ + if (src == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + int retVal; + uint8_t *data = (uint8_t *)src; + uint32_t i = 0; + + while (i < len) { + retVal = MXC_UART_WriteCharacter(uart_dev->dev, data[i]); + if (retVal == E_NO_ERROR) { + i++; + } + } + uart_dev->tx_nbr_bytes = i; + + if (uart_dev->cb_event) { + uart_dev->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_Receive(UARTx_Resources* uart_dev, void *dst, uint32_t len) +{ + if (dst == NULL) { + return ARM_DRIVER_ERROR_PARAMETER; + } + + int retVal; + uint8_t *data = (uint8_t *)dst; + uint32_t i = 0; + + while (i < len) { + retVal = MXC_UART_ReadCharacter(uart_dev->dev); + if (retVal >= 0) { + data[i] = retVal; + i++; + } + } + uart_dev->rx_nbr_bytes = i; + + if (uart_dev->cb_event) { + uart_dev->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } + + return ARM_DRIVER_OK; +} + +static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources* uart_dev) +{ + return uart_dev->tx_nbr_bytes; +} + +static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources* uart_dev) +{ + return uart_dev->rx_nbr_bytes; +} + +static int32_t ARM_USARTx_Control(UARTx_Resources* uart_dev, uint32_t control, + uint32_t arg) +{ + if ((control & ARM_USART_CONTROL_Msk) != ARM_USART_MODE_ASYNCHRONOUS) { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + if(MXC_UART_SetFrequency(uart_dev->dev, arg, MXC_UART_APB_CLK) < 0) { + return ARM_USART_ERROR_BAUDRATE; + } + + /* UART Data bits */ + switch (control & ARM_USART_DATA_BITS_Msk) { + case ARM_USART_DATA_BITS_5: + MXC_UART_SetDataSize(uart_dev->dev, 5); + break; + case ARM_USART_DATA_BITS_6: + MXC_UART_SetDataSize(uart_dev->dev, 6); + break; + case ARM_USART_DATA_BITS_7: + MXC_UART_SetDataSize(uart_dev->dev, 7); + break; + case ARM_USART_DATA_BITS_8: + MXC_UART_SetDataSize(uart_dev->dev, 8); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Parity */ + switch (control & ARM_USART_PARITY_Msk) { + case ARM_USART_PARITY_NONE: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_DISABLE); + break; + case ARM_USART_PARITY_EVEN: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_EVEN_1); + break; + case ARM_USART_PARITY_ODD: + MXC_UART_SetParity(uart_dev->dev, MXC_UART_PARITY_ODD_1); + break; + } + + /* USART Stop bits */ + switch (control & ARM_USART_STOP_BITS_Msk) { + case ARM_USART_STOP_BITS_1: + MXC_UART_SetStopBits(uart_dev->dev, MXC_UART_STOP_1); + break; + case ARM_USART_STOP_BITS_2: + MXC_UART_SetStopBits(uart_dev->dev, MXC_UART_STOP_2); + break; + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_PowerControl(UARTx_Resources* uart_dev, + ARM_POWER_STATE state) +{ + ARG_UNUSED(uart_dev); + + switch (state) { + case ARM_POWER_OFF: + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + default: + return ARM_DRIVER_ERROR_PARAMETER; + } +} + +#if (RTE_USART0) + +/* USART0 Driver wrapper functions */ +static UARTx_Resources USART0_DEV = { + .dev = MXC_UART, + .tx_nbr_bytes = 0, + .rx_nbr_bytes = 0, + .cb_event = NULL, +}; + +static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event) +{ + USART0_DEV.cb_event = cb_event; + + return ARM_USARTx_Initialize(&USART0_DEV); +} + +static int32_t ARM_USART0_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state) +{ + return ARM_USARTx_PowerControl(&USART0_DEV, state); +} + +static int32_t ARM_USART0_Send(const void *data, uint32_t num) +{ + return ARM_USARTx_Send(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Receive(void *data, uint32_t num) +{ + return ARM_USARTx_Receive(&USART0_DEV, data, num); +} + +static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in, + uint32_t num) +{ + ARG_UNUSED(data_out); + ARG_UNUSED(data_in); + ARG_UNUSED(num); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static uint32_t ARM_USART0_GetTxCount(void) +{ + return ARM_USARTx_GetTxCount(&USART0_DEV); +} + +static uint32_t ARM_USART0_GetRxCount(void) +{ + return ARM_USARTx_GetRxCount(&USART0_DEV); +} + +static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg) +{ + return ARM_USARTx_Control(&USART0_DEV, control, arg); +} + +static ARM_USART_STATUS ARM_USART0_GetStatus(void) +{ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; + return status; +} + +static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + ARG_UNUSED(control); + + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; + + return modem_status; +} + +extern ARM_DRIVER_USART Driver_USART0; +ARM_DRIVER_USART Driver_USART0 = { + ARM_USART_GetVersion, + ARM_USART_GetCapabilities, + ARM_USART0_Initialize, + ARM_USART0_Uninitialize, + ARM_USART0_PowerControl, + ARM_USART0_Send, + ARM_USART0_Receive, + ARM_USART0_Transfer, + ARM_USART0_GetTxCount, + ARM_USART0_GetRxCount, + ARM_USART0_Control, + ARM_USART0_GetStatus, + ARM_USART0_SetModemControl, + ARM_USART0_GetModemStatus +}; +#endif /* RTE_USART0 */ diff --git a/platform/ext/target/adi/max32657/config.cmake b/platform/ext/target/adi/max32657/config.cmake new file mode 100644 index 000000000..4be71e55b --- /dev/null +++ b/platform/ext/target/adi/max32657/config.cmake @@ -0,0 +1,46 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(BL1 OFF CACHE BOOL "Enable/disable ADI Secure Boot ROM, BL2 image will be signed") +set(PLATFORM_DEFAULT_BL1 OFF CACHE STRING "ADI provides Secure Boot ROM so that disable default BL1") +set(TFM_BL2_SIGNING_KEY_PATH "" CACHE FILEPATH "") + +set(BL2 ON CACHE BOOL "Whether to build BL2") +set(CONFIG_TFM_USE_TRUSTZONE ON) +set(TFM_PARTITION_PROTECTED_STORAGE ON CACHE BOOL "Enable Protected Stroage partition") +set(TFM_PARTITION_PLATFORM OFF CACHE BOOL "Enable Platform partition") +set(TFM_PARTITION_CRYPTO ON CACHE BOOL "Enable Crypto partition") +set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON CACHE BOOL "Enable Internal Trusted Storage partition") +set(TFM_PARTITION_NS_AGENT_TZ ON CACHE BOOL "Enable Non-Secure Agent in Secure partition") +set(CONFIG_TFM_BOOT_STORE_MEASUREMENTS ON CACHE BOOL "Store measurement values from all the boot stages. Used for initial attestation token.") +set(CONFIG_TFM_BOOT_STORE_ENCODED_MEASUREMENTS ON CACHE BOOL "Enable storing of encoded measurements in boot.") +set(TFM_PARTITION_INITIAL_ATTESTATION ON CACHE BOOL "Enable Initial Attestation partition") +set(CONFIG_TFM_HALT_ON_CORE_PANIC ON CACHE BOOL "On fatal errors in the secure firmware, halt instead of rebooting.") +set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use trusted on-chip flash to implement OTP memory") + +set(PLATFORM_DEFAULT_PROVISIONING ON CACHE BOOL "Use default provisioning implementation") +set(PROVISIONING_DATA_PADDED_SIZE "0x400" CACHE STRING "") +set(PROVISIONING_KEYS_CONFIG "" CACHE FILEPATH "The config file which has the keys and seeds for provisioning") +set(PROVISIONING_CODE_PADDED_SIZE "0x2000" CACHE STRING "") +set(PROVISIONING_VALUES_PADDED_SIZE "0x400" CACHE STRING "") + +set(HAL_ADI_PATH "DOWNLOAD" CACHE PATH "Path to hal_adi (or DOWNLOAD to fetch automatically") +set(HAL_ADI_VERSION "dd1c525" CACHE STRING "The version of hal_adi to use") + +set(MCUBOOT_USE_PSA_CRYPTO ON CACHE BOOL "Use PSA Crypto for MCUBOOT") +set(CRYPTO_HW_ACCELERATOR OFF) + +if (CONFIG_TFM_PROFILE_SMALL) + # Static Buffer size for MBEDTLS allocations - Has been increased from the default value of small profile + # to ensure that initial attestation testcases in regression build passes + add_compile_definitions(CRYPTO_ENGINE_BUF_SIZE=0x500) +endif() + +if(TFM_PARTITION_PROTECTED_STORAGE) + # Enable single part functions in crypto library needed for PS Encryption + set(CRYPTO_SINGLE_PART_FUNCS_DISABLED OFF CACHE BOOL "Disable single part functions in crypto library") +endif() diff --git a/platform/ext/target/adi/max32657/cpuarch.cmake b/platform/ext/target/adi/max32657/cpuarch.cmake new file mode 100644 index 000000000..f693263b8 --- /dev/null +++ b/platform/ext/target/adi/max32657/cpuarch.cmake @@ -0,0 +1,16 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# Copyright (C) 2024 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# In the new split build this file defines a platform specific parameters +# like mcpu core, arch etc and to be included by toolchain files. + +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") +set(CONFIG_TFM_ENABLE_FP OFF) +set(CONFIG_TFM_ENABLE_CP10CP11 ON) diff --git a/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld new file mode 100644 index 000000000..10a91a559 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/gcc/max32657_sla.ld @@ -0,0 +1,219 @@ +;/* +; * Copyright (c) 2022-2024 Arm Limited. All rights reserved. +; * Copyright (C) 2024-2025 Analog Devices, Inc. +; * +; * Licensed under the Apache License, Version 2.0 (the "License"); +; * you may not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an "AS IS" BASIS, +; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * +; * This file is derivative of CMSIS V5.00 gcc_arm.ld +; */ + +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ + +#include "region_defs.h" + +MEMORY +{ + FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE + RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE +} + +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .text (READONLY) : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + . = ALIGN(1024); /* Authentication header is 1024 byte aligned. */ + KEEP(*(.sla_header)) /* authentication header */ + + *(.text*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .copy.table */ + . = ALIGN(4); + __copy_table_start__ = .; +#ifdef CODE_SHARING + LONG (LOADADDR(.tfm_shared_symbols)) + LONG (ADDR(.tfm_shared_symbols)) + LONG (SIZEOF(.tfm_shared_symbols) / 4) +#endif + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + __copy_table_end__ = .; + + /* .zero.table */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) + __zero_table_end__ = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + +#ifdef CODE_SHARING + /* The code sharing between bootloader and runtime firmware requires to + * share the global variables. Section size must be equal with + * SHARED_SYMBOL_AREA_SIZE defined in region_defs.h + */ + .tfm_shared_symbols : ALIGN(4) + { + *(.data.mbedtls_calloc_func) + *(.data.mbedtls_free_func) + *(.data.mbedtls_exit) + *(.data.memset_func) + . = ALIGN(SHARED_SYMBOL_AREA_SIZE); + } > RAM AT > FLASH + + ASSERT(SHARED_SYMBOL_AREA_SIZE % 4 == 0, "SHARED_SYMBOL_AREA_SIZE must be divisible by 4") +#endif + + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + + .data : ALIGN(4) + { + *(vtable) + *(.data*) + + KEEP(*(.jcr*)) + . = ALIGN(4); + + } > RAM AT > FLASH + Image$$ER_DATA$$Base = ADDR(.data); + + .bss : ALIGN(4) + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .msp_stack (NOLOAD) : ALIGN(32) + { + . += __msp_stack_size__ - 0x8; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .msp_stack_seal_res : + { + . += 0x8; + } > RAM + __StackSeal = ADDR(.msp_stack_seal_res); + +#else + .msp_stack (NOLOAD) : ALIGN(32) + { + . += __msp_stack_size__; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + .heap (NOLOAD): ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + + /* End of flash image. */ + /* This segment is required during the signing operation to + * enforce any padding in previous FLASH segments. + */ + .end_of_flash_image : + { + FILL(0xFF) + KEEP(*(.end_of_flash_image)) + /* End marker. */ + LONG(0x55AA55AA); + _application_end = .; + } > FLASH +} diff --git a/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h b/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h new file mode 100644 index 000000000..9f9bd9587 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/inc/mpc_sie200_drv.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file mpc_sie200_drv.h + * \brief Generic driver for ARM SIE 200 Memory Protection + * Controllers (MPC). + */ + +#ifndef __MPC_SIE_200_DRV_H__ +#define __MPC_SIE_200_DRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Error code returned by the driver functions */ +enum mpc_sie200_error_t { + MPC_SIE200_ERR_NONE, /*!< No error */ + MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */ + MPC_SIE200_NOT_INIT, /*!< MPC not initialized */ + MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range + * controlled by the MPC */ + MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size + * of this MPC */ + MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure + * is invalid. This could be because: + * - The base and limit swapped + * - The base and limit addresses + * are in different ranges */ + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be + * accessed with the wanted + * security attributes */ +}; + +/* Security attribute used in various place of the API */ +enum mpc_sie200_sec_attr_t { + MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */ + MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */ + /*!< Used when getting the configuration of a memory range and some blocks + * are secure whereas some other are non secure */ + MPC_SIE200_SEC_ATTR_MIXED, +}; + +/* What can happen when trying to do an illegal memory access */ +enum mpc_sie200_sec_resp_t { + MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */ + MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */ +}; + +/* Description of a memory range controlled by the MPC */ +struct mpc_sie200_memory_range_t { + const uint32_t base; /*!< Base address (included in the range) */ + const uint32_t limit; /*!< Limit address (excluded in the range) */ + const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute + needed to be matched when + accessing this range. + For example, the non-secure + alias of a memory region can not + be accessed using secure access, + and configuring the MPC to + secure using that range will not + be permitted by the driver. */ +}; + +/* ARM MPC SIE 200 device configuration structure */ +struct mpc_sie200_dev_cfg_t { + const uint32_t base; /*!< MPC base address */ +}; + +/* ARM MPC SIE 200 device data structure */ +struct mpc_sie200_dev_data_t { + const struct mpc_sie200_memory_range_t** range_list; /*!< Array of pointers + to memory ranges + controlled by + the MPC */ + uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */ + uint8_t state; /*!< Indicates if the MPC driver + is initialized and enabled */ + uint16_t reserved; /*!< 32 bits alignment */ +}; + +/* ARM MPC SIE 200 device structure */ +struct mpc_sie200_dev_t { + const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */ + struct mpc_sie200_dev_data_t* const data; /*!< MPC data */ +}; + +/** + * \brief Initializes a MPC device. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] range_list List of memory ranges controller by the MPC + * (\ref mpc_sie200_memory_range_t). This list can not + * freed after the initializations. + * \param[in] nbr_of_ranges Number of memory ranges + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges); + +/** + * \brief Gets MPC block size. All regions must be aligned on this block + * size (base address and limit+1 address). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] blk_size MPC block size + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size); + +/** + * \brief Configures a memory region (base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to poll. This bound is + * included. It does not need to be aligned in any way. + * + * \param[in] limit Limit address of the region to poll. This bound is + * included. (limit+1) does not need to be aligned + * in any way. + * \param[in] attr Security attribute of the region. If the region has mixed + * secure/non-secure, a special value is returned + * (\ref mpc_sie200_sec_attr_t). + * + * In case base and limit+1 addresses are not aligned on + * the block size, the enclosing region with base and + * limit+1 aligned on block size will be queried. + * In case of early termination of the function (error), the + * security attribute will be set to MPC_SIE200_ATTR_MIXED. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr); + +/** + * \brief Gets a memory region configuration(base and limit included). + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] base Base address of the region to get the configuration. + * \param[in] limit Limit address of the region to get the configuration. + * \param[out] attr Security attribute of the region + * \ref mpc_sie200_sec_attr_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, + uint32_t limit, + enum mpc_sie200_sec_attr_t* attr); + +/** + * \brief Gets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] ctrl_val Current MPC control value. + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val); + +/** + * \brief Sets the MPC control value. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[in] mpc_ctrl New MPC control value + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl); + +/** + * \brief Gets the configured secure response. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t). + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep); + +/** + * \brief Enables MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Disables MPC interrupt + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev); + +/** + * \brief Clears MPC interrupt. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \note This function doesn't check if dev is NULL. + */ +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev); + +/** + * \brief Returns the MPC interrupt state. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns 1 if the interrupt is active, 0 otherwise. + * + * \note This function doesn't check if dev is NULL. + */ +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev); + +/** + * \brief Locks down the MPC configuration. + * + * \param[in] dev MPC device \ref mpc_sie200_dev_t + * + * \return Returns error code as specified in \ref mpc_sie200_error_t + * + * \note This function doesn't check if dev is NULL. + */ +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev); + +#ifdef __cplusplus +} +#endif +#endif /* __MPC_SIE_200_DRV_H__ */ diff --git a/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c b/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c new file mode 100644 index 000000000..31c5b84a9 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/mpc_sie200_drv.c @@ -0,0 +1,657 @@ +/* + * Copyright (c) 2016-2017 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mpc_sie200_drv.h" + +#include + +#include "mxc_device.h" + +#define MPC_SIE200_BLK_CFG_OFFSET 5U + +#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a + * bus error */ +#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */ +#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */ + +/* ARM MPC interrupt */ +#define MPC_SIE200_INT_EN 1UL +#define MPC_SIE200_INT_STAT 1UL + +/* ARM MPC state definitions */ +#define MPC_SIE200_INITIALIZED (1 << 0) + +/* Error code returned by the internal driver functions */ +enum mpc_sie200_intern_error_t{ + MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE, + MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE, + MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED, + MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE, + MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE = + MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, + /* Calculated block index + is higher than the maximum allowed by the MPC. It should never + happen unless the controlled ranges of the MPC are misconfigured + in the driver or if the IP has not enough LUTs to cover the + range, due to wrong reported block size for example. + */ + MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1, + +}; + +/* ARM MPC memory mapped register access structure */ +struct mpc_sie200_reg_map_t { + volatile uint32_t ctrl; /* (R/W) MPC Control */ + volatile uint32_t reserved[3];/* Reserved */ + volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */ + volatile uint32_t blk_cfg; /* (R/ ) Block configuration */ + volatile uint32_t blk_idx; /* (R/W) Index value for accessing block + * based look up table */ + volatile uint32_t blk_lutn; /* (R/W) Block based gating + * Look Up Table (LUT) */ + volatile uint32_t int_stat; /* (R/ ) Interrupt state */ + volatile uint32_t int_clear; /* ( /W) Interrupt clear */ + volatile uint32_t int_en; /* (R/W) Interrupt enable */ + volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */ + volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */ + volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */ + volatile uint32_t reserved2[997]; /* Reserved */ + volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */ + volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */ + volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */ + volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */ + volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */ + volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */ + volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */ + volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */ + volatile uint32_t cidr0; /* (R/ ) Component ID 0 */ + volatile uint32_t cidr1; /* (R/ ) Component ID 1 */ + volatile uint32_t cidr2; /* (R/ ) Component ID 2 */ + volatile uint32_t cidr3; /* (R/ ) Component ID 3 */ +}; + +/* + * Checks if the address is controlled by the MPC and returns + * the range index in which it is contained. + * + * \param[in] dev MPC device to initalize \ref mpc_sie200_dev_t + * \param[in] addr Address to check if it is controlled by MPC. + * \param[out] addr_range Range index in which it is contained. + * + * \return True if the base is controller by the range list, false otherwise. + */ +static uint32_t is_ctrl_by_range_list(struct mpc_sie200_dev_t* dev, uint32_t addr, + const struct mpc_sie200_memory_range_t** addr_range) +{ + uint32_t i; + const struct mpc_sie200_memory_range_t* range; + + for(i = 0; i < dev->data->nbr_of_ranges; i++) { + range = dev->data->range_list[i]; + if(addr >= range->base && addr <= range->limit) { + *addr_range = range; + return 1; + } + } + return 0; +} + +/* + * Gets the masks selecting the bits in the LUT of the MPC corresponding + * to the base address (included) up to the limit address (included) + * + * \param[in] mpc_dev The MPC device. + * \param[in] base Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[in] limit Address in a range controlled by this MPC + * (included), aligned on block size. + * \param[out] range Memory range in which the base address and + * limit are. + * \param[out] first_word_idx Index of the first touched word in the LUT. + * \param[out] nr_words Number of words used in the LUT. If 1, only + * first_word_mask is valid and limit_word_mask + * must not be used. + * \param[out] first_word_mask First word mask in the LUT will be stored here. + * \param[out] limit_word_mask Limit word mask in the LUT will be stored here. + * + * \return Returns error code as specified in \ref mpc_sie200_intern_error_t + */ +static enum mpc_sie200_intern_error_t get_lut_masks( + struct mpc_sie200_dev_t* dev, + const uint32_t base, const uint32_t limit, + const struct mpc_sie200_memory_range_t** range, + uint32_t *first_word_idx, + uint32_t *nr_words, + uint32_t *first_word_mask, + uint32_t *limit_word_mask) +{ + const struct mpc_sie200_memory_range_t* base_range; + uint32_t block_size; + uint32_t base_block_idx; + uint32_t base_word_idx; + uint32_t blk_max; + const struct mpc_sie200_memory_range_t* limit_range; + uint32_t limit_block_idx; + uint32_t limit_word_idx; + uint32_t mask; + uint32_t norm_base; + uint32_t norm_limit; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + /* + * Check that the addresses are within the controlled regions + * of this MPC + */ + if(!is_ctrl_by_range_list(dev, base, &base_range) || + !is_ctrl_by_range_list(dev, limit, &limit_range)) { + return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE; + } + + /* Base and limit should be part of the same range */ + if(base_range != limit_range) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + *range = base_range; + + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + /* Base and limit+1 addresses must be aligned on the MPC block size */ + if(base % block_size || (limit+1) % block_size) { + return MPC_SIE200_INTERN_ERR_NOT_ALIGNED; + } + + /* + * Get a normalized address that is an offset from the beginning + * of the lowest range controlled by the MPC + */ + norm_base = (base - base_range->base); + norm_limit = (limit - base_range->base); + + /* + * Calculate block index and to which 32 bits word it belongs + */ + limit_block_idx = norm_limit/block_size; + limit_word_idx = limit_block_idx/32; + + base_block_idx = norm_base/block_size; + base_word_idx = base_block_idx/32; + + if(base_block_idx > limit_block_idx) { + return MPC_SIE200_INTERN_ERR_INVALID_RANGE; + } + + /* Transmit the information to the caller */ + *nr_words = limit_word_idx - base_word_idx + 1; + *first_word_idx = base_word_idx; + + /* Limit to the highest block that can be configured */ + blk_max = p_mpc->blk_max; + + if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) { + return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH; + } + + /* + * Create the mask for the first word to only select the limit N bits + */ + *first_word_mask = ~((1 << (base_block_idx % 32)) - 1); + + /* + * Create the mask for the limit word to select only the first M bits. + */ + *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1; + /* + * If limit_word_mask is 0, it means that the limit touched block index is + * the limit in its word, so the limit word mask has all its bits selected + */ + if(*limit_word_mask == 0) { + *limit_word_mask = 0xFFFFFFFF; + } + + /* + * If the blocks to configure are all packed in one word, only + * touch this word. + * Code using the computed masks should test if this mask + * is non-zero, and if so, only use this one instead of the limit_word_mask + * and first_word_mask. + * As the only bits that are the same in both masks are the 1 that we want + * to select, just use XOR to extract them. + */ + if(base_word_idx == limit_word_idx) { + mask = ~(*first_word_mask ^ *limit_word_mask); + *first_word_mask = mask; + *limit_word_mask = mask; + } + + return MPC_SIE200_INTERN_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev, + const struct mpc_sie200_memory_range_t** range_list, + uint8_t nbr_of_ranges) +{ + if((range_list == NULL) || (nbr_of_ranges == 0)) { + return MPC_SIE200_INVALID_ARG; + } + + dev->data->range_list = range_list; + dev->data->nbr_of_ranges = nbr_of_ranges; + dev->data->state = MPC_SIE200_INITIALIZED; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev, + uint32_t* blk_size) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(blk_size == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* Calculate the block size in byte according to the manual */ + *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev, + const uint32_t base, + const uint32_t limit, + enum mpc_sie200_sec_attr_t attr) +{ + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_mask; + uint32_t limit_word_idx; + uint32_t nr_words; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + /* Sanity check to make sure the given range is within this MPCs range */ + if ((dev->data->range_list[attr]->base > base) || + (dev->data->range_list[attr]->limit < limit) ) { + return MPC_SIE200_ERR_NOT_IN_RANGE; + } + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx + nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to a generic errpr */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* + * The memory range should allow accesses in with the wanted security + * attribute if it requires special attribute for successfull accesses + */ + if(range->attr != attr) { + return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE; + } + + /* + * Starts changing actual configuration so issue DMB to ensure every + * transaction has completed by now + */ + __DMB(); + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; + } + + /* First word */ + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= first_word_mask; + } else { + word_value &= ~first_word_mask; + } + /* + * Set the index again because full word read or write could have + * incremented it + */ + p_mpc->blk_idx = first_word_idx; + /* Partially configure the first word */ + p_mpc->blk_lutn = word_value; + + /* Fully configure the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + p_mpc->blk_lutn = 0xFFFFFFFF; + } else { + p_mpc->blk_lutn = 0x00000000; + } + } + + /* Partially configure the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn; + if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) { + word_value |= limit_word_mask; + } else { + word_value &= ~limit_word_mask; + } + p_mpc->blk_idx = limit_word_idx; + p_mpc->blk_lutn = word_value; + + /* Commit the configuration change */ + __DSB(); + __ISB(); + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_region_config( + struct mpc_sie200_dev_t* dev, + uint32_t base, uint32_t limit, + enum mpc_sie200_sec_attr_t* attr) +{ + enum mpc_sie200_sec_attr_t attr_prev; + uint32_t block_size; + uint32_t block_size_mask; + enum mpc_sie200_intern_error_t error; + uint32_t first_word_idx; + uint32_t first_word_mask; + uint32_t i; + uint32_t limit_word_idx; + uint32_t limit_word_mask; + uint32_t nr_words; + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + const struct mpc_sie200_memory_range_t* range; + uint32_t word_value; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(attr == 0) { + return MPC_SIE200_INVALID_ARG; + } + + /* + * Initialize the security attribute to mixed in case of early + * termination of this function. A caller that does not check the + * returned error will act as if it does not know anything about the + * region queried, which is the safest bet + */ + *attr = MPC_SIE200_SEC_ATTR_MIXED; + + /* + * If the base and limit are not aligned, align them and make sure + * that the resulting region fully includes the original region + */ + block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET)); + + block_size_mask = block_size - 1; + base &= ~(block_size_mask); + limit &= ~(block_size_mask); + limit += block_size - 1; /* Round to the upper block address, + * and then remove one to get the preceding + * address. + */ + + /* Get the bitmasks used to select the bits in the LUT */ + error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words, + &first_word_mask, &limit_word_mask); + + limit_word_idx = first_word_idx+nr_words - 1; + + if(error != MPC_SIE200_INTERN_ERR_NONE) { + /* Map internal error code lower than 0 to generic error */ + if(error < 0) { + return MPC_SIE200_ERR_INVALID_RANGE; + } + return (enum mpc_sie200_error_t)error; + } + + /* Set the block index to the first word that will be updated */ + p_mpc->blk_idx = first_word_idx; + + /* If only one word needs to be touched in the LUT */ + if(nr_words == 1) { + word_value = p_mpc->blk_lutn; + word_value &= first_word_mask; + if(word_value == 0) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + /* + * If there are differences between the mask and the word value, + * it means that the security attributes of blocks are mixed + */ + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + return MPC_SIE200_ERR_NONE; + } + + /* Get the partial configuration of the first word */ + word_value = p_mpc->blk_lutn & first_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + /* + * Bail out as the security attribute will be the same regardless + * of the configuration of other blocks + */ + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + /* + * Store the current found attribute, to check that all the blocks indeed + * have the same security attribute. + */ + attr_prev = *attr; + + /* Get the configuration of the intermediate words if there are any */ + for(i=first_word_idx+1; iblk_idx = i; + word_value = p_mpc->blk_lutn; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value == 0xFFFFFFFF) { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } else { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + /* If the attribute is different than the one found before, bail out */ + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + attr_prev = *attr; + } + + /* Get the partial configuration of the limit word */ + p_mpc->blk_idx = limit_word_idx; + word_value = p_mpc->blk_lutn & limit_word_mask; + if(word_value == 0x00000000) { + *attr = MPC_SIE200_SEC_ATTR_SECURE; + } else if(word_value ^ first_word_mask) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } else { + *attr = MPC_SIE200_SEC_ATTR_NONSECURE; + } + + if(*attr != attr_prev) { + *attr = MPC_SIE200_SEC_ATTR_MIXED; + return MPC_SIE200_ERR_NONE; + } + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t* ctrl_val) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(ctrl_val == 0) { + return MPC_SIE200_INVALID_ARG; + } + + *ctrl_val = p_mpc->ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev, + uint32_t mpc_ctrl) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl = mpc_ctrl; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev, + enum mpc_sie200_sec_resp_t* sec_rep) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + if(sec_rep == 0) { + return MPC_SIE200_INVALID_ARG; + } + + if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) { + *sec_rep = MPC_SIE200_RESP_BUS_ERROR; + return MPC_SIE200_ERR_NONE; + } + + *sec_rep = MPC_SIE200_RESP_RAZ_WI; + + return MPC_SIE200_ERR_NONE; +} + +enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->int_en |= MPC_SIE200_INT_EN; + + return MPC_SIE200_ERR_NONE; +} + +void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_en &= ~MPC_SIE200_INT_EN; +} + +void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + p_mpc->int_clear = MPC_SIE200_INT_EN; +} + +uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + return (p_mpc->int_stat & MPC_SIE200_INT_STAT); +} + +enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev) +{ + struct mpc_sie200_reg_map_t* p_mpc = + (struct mpc_sie200_reg_map_t*)dev->cfg->base; + + if(!(dev->data->state & MPC_SIE200_INITIALIZED)) { + return MPC_SIE200_NOT_INIT; + } + + p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT + | MPC_SIE200_CTRL_SEC_LOCK_DOWN); + + return MPC_SIE200_ERR_NONE; +} diff --git a/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c b/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c new file mode 100644 index 000000000..a9a14b8a4 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/sla_header_max32657.c @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/***** Includes *****/ +#include +#include + +extern uint32_t _application_end; + +#define SLA_HEADER_MAGIC0 0xBF1421E4 +#define SLA_HEADER_MAGIC1 0x461A8CF5 +#define SLA_HEADER_VERSION 0x00000001 +#define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001 +#define SLA_HEADER_RESERVED 0x00000000 + +typedef struct { + uint32_t magic0; + uint32_t magic1; + uint32_t version; + uint32_t verifytype; + uint32_t sigaddress; + uint32_t reserved5; + uint32_t reserved6; + uint32_t reserved7; +} flash_app_header_t; + +__attribute__((section(".sla_header"))) __attribute__((__used__)) +const flash_app_header_t sla_header = { .magic0 = SLA_HEADER_MAGIC0, + .magic1 = SLA_HEADER_MAGIC1, + .version = SLA_HEADER_VERSION, + .verifytype = SLA_HEADER_ALGORITHM_ECDSA, + .sigaddress = (uint32_t)&_application_end, + .reserved5 = SLA_HEADER_RESERVED, + .reserved6 = SLA_HEADER_RESERVED, + .reserved7 = SLA_HEADER_RESERVED }; diff --git a/platform/ext/target/adi/max32657/device/src/startup_max32657.c b/platform/ext/target/adi/max32657/device/src/startup_max32657.c new file mode 100644 index 000000000..f95240c82 --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/startup_max32657.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ +//FIXME: check if following includes are needed +#include "tfm_hal_device_header.h" +#if defined(TEST_NS_FPU) || defined(TEST_S_FPU) +#include "test_interrupt.h" +#endif + +#include "system_max32657.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ + __NO_RETURN void __WEAK handler_name(void); \ + void handler_name(void) \ + { \ + while (1) \ + ; \ + } + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) +DEFAULT_IRQ_HANDLER(Default_Handler) + +/* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + +DEFAULT_IRQ_HANDLER(ICE_IRQHandler) /* 0x10 0x0040 16: ICE Unlock */ +DEFAULT_IRQ_HANDLER(WDT_IRQHandler) /* 0x11 0x0044 17: Watchdog Timer */ +DEFAULT_IRQ_HANDLER(RTC_IRQHandler) /* 0x12 0x0048 18: RTC */ +DEFAULT_IRQ_HANDLER(TRNG_IRQHandler) /* 0x13 0x004C 19: True Random Number Generator */ +DEFAULT_IRQ_HANDLER(TMR0_IRQHandler) /* 0x14 0x0050 20: Timer 0 */ +DEFAULT_IRQ_HANDLER(TMR1_IRQHandler) /* 0x15 0x0054 21: Timer 1 */ +DEFAULT_IRQ_HANDLER(TMR2_IRQHandler) /* 0x16 0x0058 22: Timer 2 */ +DEFAULT_IRQ_HANDLER(TMR3_IRQHandler) /* 0x17 0x005C 23: Timer 3 */ +DEFAULT_IRQ_HANDLER(TMR4_IRQHandler) /* 0x18 0x0060 24: Timer 4 */ +DEFAULT_IRQ_HANDLER(TMR5_IRQHandler) /* 0x19 0x0064 25: Timer 5 */ +DEFAULT_IRQ_HANDLER(I3C_IRQHandler) /* 0x1A 0x0068 26: I3C */ +DEFAULT_IRQ_HANDLER(UART_IRQHandler) /* 0x1B 0x006C 27: UART */ +DEFAULT_IRQ_HANDLER(SPI_IRQHandler) /* 0x1C 0x0070 28: SPI */ +DEFAULT_IRQ_HANDLER(FLC_IRQHandler) /* 0x1D 0x0074 29: FLC */ +DEFAULT_IRQ_HANDLER(GPIO0_IRQHandler) /* 0x1E 0x0078 30: GPIO0 */ +DEFAULT_IRQ_HANDLER(RSV15_IRQHandler) /* 0x1F 0x007C 31: Reserved */ +DEFAULT_IRQ_HANDLER(DMA0_CH0_IRQHandler) /* 0x20 0x0080 32: DMA0 Channel 0 */ +DEFAULT_IRQ_HANDLER(DMA0_CH1_IRQHandler) /* 0x21 0x0084 33: DMA0 Channel 1 */ +DEFAULT_IRQ_HANDLER(DMA0_CH2_IRQHandler) /* 0x22 0x0088 34: DMA0 Channel 2 */ +DEFAULT_IRQ_HANDLER(DMA0_CH3_IRQHandler) /* 0x23 0x008C 35: DMA0 Channel 3 */ +DEFAULT_IRQ_HANDLER(DMA1_CH0_IRQHandler) /* 0x24 0x0090 36: DMA1 Channel 0 */ +DEFAULT_IRQ_HANDLER(DMA1_CH1_IRQHandler) /* 0x25 0x0094 37: DMA1 Channel 1 */ +DEFAULT_IRQ_HANDLER(DMA1_CH2_IRQHandler) /* 0x26 0x0098 38: DMA1 Channel 2 */ +DEFAULT_IRQ_HANDLER(DMA1_CH3_IRQHandler) /* 0x27 0x009C 39: DMA1 Channel 3 */ +DEFAULT_IRQ_HANDLER(WUT0_IRQHandler) /* 0x28 0x00A0 40: Wakeup Timer 0 */ +DEFAULT_IRQ_HANDLER(WUT1_IRQHandler) /* 0x29 0x00A4 41: Wakeup Timer 1 */ +DEFAULT_IRQ_HANDLER(GPIOWAKE_IRQHandler) /* 0x2A 0x00A8 42: GPIO Wakeup */ +DEFAULT_IRQ_HANDLER(CRC_IRQHandler) /* 0x2B 0x00AC 43: CRC */ +DEFAULT_IRQ_HANDLER(AES_IRQHandler) /* 0x2C 0x00B0 44: AES */ +DEFAULT_IRQ_HANDLER(ERFO_IRQHandler) /* 0x2D 0x00B4 45: ERFO Ready */ +DEFAULT_IRQ_HANDLER(BOOST_IRQHandler) /* 0x2E 0x00B8 46: Boost Controller */ +DEFAULT_IRQ_HANDLER(ECC_IRQHandler) /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX0_IRQHandler) /* 0x30 0x00C0 48: BTLE XXXX0 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX1_IRQHandler) /* 0x31 0x00C4 49: BTLE XXXX1 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX2_IRQHandler) /* 0x32 0x00C8 50: BTLE XXXX2 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX3_IRQHandler) /* 0x33 0x00CC 51: BTLE XXXX3 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX4_IRQHandler) /* 0x34 0x00D0 52: BTLE XXXX4 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX5_IRQHandler) /* 0x35 0x00D4 53: BTLE XXXX5 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX6_IRQHandler) /* 0x36 0x00D8 54: BTLE XXXX6 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX7_IRQHandler) /* 0x37 0x00DC 55: BTLE XXXX7 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX8_IRQHandler) /* 0x38 0x00E0 56: BTLE XXXX8 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXX9_IRQHandler) /* 0x39 0x00E4 57: BTLE XXXX9 */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXA_IRQHandler) /* 0x3A 0x00E8 58: BTLE XXXXA */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXB_IRQHandler) /* 0x3B 0x00EC 59: BTLE XXXXB */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXC_IRQHandler) /* 0x3C 0x00F0 60: BTLE XXXXC */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXD_IRQHandler) /* 0x3D 0x00F4 61: BTLE XXXXD */ +DEFAULT_IRQ_HANDLER(BTLE_XXXXE_IRQHandler) /* 0x3E 0x00F8 62: BTLE XXXXE */ +DEFAULT_IRQ_HANDLER(RSV47_IRQHandler) /* 0x3F 0x00FC 63: Reserved */ +DEFAULT_IRQ_HANDLER(MPC_IRQHandler) /* 0x40 0x0100 64: MPC Combined (Secure) */ +DEFAULT_IRQ_HANDLER(PPC_IRQHandler) /* 0x44 0x0104 65: PPC Combined (Secure) */ +DEFAULT_IRQ_HANDLER(RSV50_IRQHandler) /* 0x48 0x0108 66: Reserved */ +DEFAULT_IRQ_HANDLER(RSV51_IRQHandler) /* 0x49 0x010C 67: Reserved */ +DEFAULT_IRQ_HANDLER(RSV52_IRQHandler) /* 0x4A 0x0110 68: Reserved */ +DEFAULT_IRQ_HANDLER(RSV53_IRQHandler) /* 0x4B 0x0114 69: Reserved */ + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void (*VECTOR_TABLE_Type)(void); + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + SecureFault_Handler, /* Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + ICE_IRQHandler, /* 0x10 0x0040 16: ICE Unlock */ + WDT_IRQHandler, /* 0x11 0x0044 17: Watchdog Timer */ + RTC_IRQHandler, /* 0x12 0x0048 18: RTC */ + TRNG_IRQHandler, /* 0x13 0x004C 19: True Random Number Generator */ + TMR0_IRQHandler, /* 0x14 0x0050 20: Timer 0 */ + TMR1_IRQHandler, /* 0x15 0x0054 21: Timer 1 */ + TMR2_IRQHandler, /* 0x16 0x0058 22: Timer 2 */ + TMR3_IRQHandler, /* 0x17 0x005C 23: Timer 3 */ + TMR4_IRQHandler, /* 0x18 0x0060 24: Timer 4 */ + TMR5_IRQHandler, /* 0x19 0x0064 25: Timer 5 */ + I3C_IRQHandler, /* 0x1A 0x0068 26: I3C */ + UART_IRQHandler, /* 0x1B 0x006C 27: UART */ + SPI_IRQHandler, /* 0x1C 0x0070 28: SPI */ + FLC_IRQHandler, /* 0x1D 0x0074 29: FLC */ + GPIO0_IRQHandler, /* 0x1E 0x0078 30: GPIO0 */ + RSV15_IRQHandler, /* 0x1F 0x007C 31: Reserved */ + DMA0_CH0_IRQHandler, /* 0x20 0x0080 32: DMA0 Channel 0 */ + DMA0_CH1_IRQHandler, /* 0x21 0x0084 33: DMA0 Channel 1 */ + DMA0_CH2_IRQHandler, /* 0x22 0x0088 34: DMA0 Channel 2 */ + DMA0_CH3_IRQHandler, /* 0x23 0x008C 35: DMA0 Channel 3 */ + DMA1_CH0_IRQHandler, /* 0x24 0x0090 36: DMA1 Channel 0 */ + DMA1_CH1_IRQHandler, /* 0x25 0x0094 37: DMA1 Channel 1 */ + DMA1_CH2_IRQHandler, /* 0x26 0x0098 38: DMA1 Channel 2 */ + DMA1_CH3_IRQHandler, /* 0x27 0x009C 39: DMA1 Channel 3 */ + WUT0_IRQHandler, /* 0x28 0x00A0 40: Wakeup Timer 0 */ + WUT1_IRQHandler, /* 0x29 0x00A4 41: Wakeup Timer 1 */ + GPIOWAKE_IRQHandler, /* 0x2A 0x00A8 42: GPIO Wakeup */ + CRC_IRQHandler, /* 0x2B 0x00AC 43: CRC */ + AES_IRQHandler, /* 0x2C 0x00B0 44: AES */ + ERFO_IRQHandler, /* 0x2D 0x00B4 45: ERFO Ready */ + BOOST_IRQHandler, /* 0x2E 0x00B8 46: Boost Controller */ + ECC_IRQHandler, /* 0x2F 0x00BC 47: ECC */ + /* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + BTLE_XXXX0_IRQHandler, /* 0x30 0x00C0 48: BTLE XXXX0 */ + BTLE_XXXX1_IRQHandler, /* 0x31 0x00C4 49: BTLE XXXX1 */ + BTLE_XXXX2_IRQHandler, /* 0x32 0x00C8 50: BTLE XXXX2 */ + BTLE_XXXX3_IRQHandler, /* 0x33 0x00CC 51: BTLE XXXX3 */ + BTLE_XXXX4_IRQHandler, /* 0x34 0x00D0 52: BTLE XXXX4 */ + BTLE_XXXX5_IRQHandler, /* 0x35 0x00D4 53: BTLE XXXX5 */ + BTLE_XXXX6_IRQHandler, /* 0x36 0x00D8 54: BTLE XXXX6 */ + BTLE_XXXX7_IRQHandler, /* 0x37 0x00DC 55: BTLE XXXX7 */ + BTLE_XXXX8_IRQHandler, /* 0x38 0x00E0 56: BTLE XXXX8 */ + BTLE_XXXX9_IRQHandler, /* 0x39 0x00E4 57: BTLE XXXX9 */ + BTLE_XXXXA_IRQHandler, /* 0x3A 0x00E8 58: BTLE XXXXA */ + BTLE_XXXXB_IRQHandler, /* 0x3B 0x00EC 59: BTLE XXXXB */ + BTLE_XXXXC_IRQHandler, /* 0x3C 0x00F0 60: BTLE XXXXC */ + BTLE_XXXXD_IRQHandler, /* 0x3D 0x00F4 61: BTLE XXXXD */ + BTLE_XXXXE_IRQHandler, /* 0x3E 0x00F8 62: BTLE XXXXE */ + RSV47_IRQHandler, /* 0x3F 0x00FC 63: Reserved */ + MPC_IRQHandler, /* 0x40 0x0100 64: MPC Combined (Secure) */ + PPC_IRQHandler, /* 0x44 0x0104 65: PPC Combined (Secure) */ + RSV50_IRQHandler, /* 0x48 0x0108 66: Reserved */ + RSV51_IRQHandler, /* 0x49 0x010C 67: Reserved */ + RSV52_IRQHandler, /* 0x4A 0x0110 68: Reserved */ + RSV53_IRQHandler, /* 0x4B 0x0114 69: Reserved */ +}; + +// FIXME: if we want to have __isr_vector in system_max32657.c, uncomment below line +// extern const VECTOR_TABLE_Type __VECTOR_TABLE __attribute__((alias("__isr_vector"))); + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __disable_irq(); +#endif + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/platform/ext/target/adi/max32657/device/src/system_max32657.c b/platform/ext/target/adi/max32657/device/src/system_max32657.c new file mode 100644 index 000000000..be04a63ba --- /dev/null +++ b/platform/ext/target/adi/max32657/device/src/system_max32657.c @@ -0,0 +1,146 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include +#include "mxc_sys.h" +#include "mxc_errors.h" +#include "max32657.h" +#include "system_max32657.h" +#include "gcr_regs.h" +#include "mpc.h" +#include "icc.h" + + +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +/* + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. +*/ +__weak int _getpid(void) +{ + return E_NOT_SUPPORTED; +} + +__weak int _kill(void) +{ + return E_NOT_SUPPORTED; +} + +__weak int PeripheralInit(void) +{ + return E_NO_ERROR; +} + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + base_freq = IPO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + base_freq = IBRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; + } + + // Get the clock divider + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; + + SystemCoreClock = base_freq >> div; +} + +/** + * This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern void *__VECTOR_TABLE[]; + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif /* __VTOR_PRESENT check */ + +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + /** + * Enable Unaligned Access Trapping to throw an exception when there is an + * unaligned memory access while unaligned access support is disabled. + * + * Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + __DSB(); + __ISB(); + + /* Enable interrupts */ + __enable_irq(); + +#if CONFIG_TRUSTED_EXECUTION_SECURE + MXC_ICC_Enable(); +#endif + + /* Change system clock source to the main high-speed clock */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); + MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); + SystemCoreClockUpdate(); + +#if CONFIG_TRUSTED_EXECUTION_SECURE + /* Init peripherals */ + PeripheralInit(); +#endif + + /* + * FPCA bit of CONTROL register can be enabled while + * performing floating point operation in Secure domain. + * It will trigger fault if it is not cleared before + * switching to Non-secure domain. + * Hence, clearing FPCA bit during initialization firmware + */ + __set_CONTROL(__get_CONTROL() & ~0x4); +} diff --git a/platform/ext/target/adi/max32657/device_cfg.h b/platform/ext/target/adi/max32657/device_cfg.h new file mode 100644 index 000000000..b1f77deff --- /dev/null +++ b/platform/ext/target/adi/max32657/device_cfg.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/* ARM UART */ +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/adi/max32657/hal_adi.cmake b/platform/ext/target/adi/max32657/hal_adi.cmake new file mode 100644 index 000000000..e19dd4072 --- /dev/null +++ b/platform/ext/target/adi/max32657/hal_adi.cmake @@ -0,0 +1,210 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +################################################################################ +# Fetch hal_adi repository +set(FETCHCONTENT_QUIET TRUE) + +fetch_remote_library( + LIB_NAME hal_adi + LIB_SOURCE_PATH_VAR HAL_ADI_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi + GIT_TAG ${HAL_ADI_VERSION} + GIT_PROGRESS TRUE +) + +set(TARGET_LC "max32657" CACHE STRING "") +string(TOUPPER ${TARGET_LC} TARGET_UC) + +set(HAL_ADI_PATH ${HAL_ADI_PATH} CACHE PATH "") +set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries CACHE PATH "") + +set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC} CACHE PATH "") +set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include CACHE PATH "") +set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source CACHE PATH "") + +set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers CACHE PATH "") +set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC} CACHE PATH "") +set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source CACHE PATH "") + + +###### BL2 Related Cmake Configurations ######################################## +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + ) + + target_sources(platform_bl2 + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_reva.c + ) + + target_compile_definitions(platform_bl2 + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 + ) +endif() # BL2 + + +###### TFM Related Cmake Configurations ######################################## +target_compile_definitions(platform_s + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CONFIG_TRUSTED_EXECUTION_SECURE + IS_SECURE_ENVIRONMENT + + __MXC_FLASH_MEM_BASE=0x11000000 + __MXC_FLASH_MEM_SIZE=0x00100000 +) + +target_include_directories(platform_s + PUBLIC + ${HAL_ADI_PERIPH_INC_DIR} + ${HAL_ADI_CMSIS_INC_DIR} + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS + ${HAL_ADI_PERIPH_SRC_DIR}/AES + ${HAL_ADI_PERIPH_SRC_DIR}/CRC + ${HAL_ADI_PERIPH_SRC_DIR}/DMA + ${HAL_ADI_PERIPH_SRC_DIR}/FLC + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO + ${HAL_ADI_PERIPH_SRC_DIR}/I3C + ${HAL_ADI_PERIPH_SRC_DIR}/ICC + ${HAL_ADI_PERIPH_SRC_DIR}/LP + ${HAL_ADI_PERIPH_SRC_DIR}/RTC + ${HAL_ADI_PERIPH_SRC_DIR}/SPI + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG + ${HAL_ADI_PERIPH_SRC_DIR}/TMR + ${HAL_ADI_PERIPH_SRC_DIR}/UART + ${HAL_ADI_PERIPH_SRC_DIR}/WDT + ${HAL_ADI_PERIPH_SRC_DIR}/WUT +) + +target_sources(platform_s + PRIVATE + ${PLATFORM_DIR}/ext/target/adi/${TARGET_LC}/device/src/system_${TARGET_LC}.c + + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/FLC/flc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c + + ${HAL_ADI_PERIPH_SRC_DIR}/TZ/spc_me30.c + + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/DMA/dma_reva.c + + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TRNG/trng_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/AES/aes_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/AES/aes_revb.c + + ${HAL_ADI_PERIPH_SRC_DIR}/CRC/crc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/CRC/crc_reva.c +) + +if(NOT ADI_NS_PRPH_I3C) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/I3C/i3c_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/I3C/i3c_reva.c + ) +endif() + +if(NOT ADI_NS_PRPH_SPI) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/SPI/spi_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SPI/spi_reva1.c + ) +endif() + +if(NOT ADI_NS_PRPH_WDT) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/WDT/wdt_revb.c + ) +endif() + +if(NOT ADI_NS_PRPH_RTC) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/RTC/rtc_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/RTC/rtc_reva.c + ) +endif() + +if(NOT (ADI_NS_PRPH_WUT0 AND ADI_NS_PRPH_WUT1)) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/WUT/wut_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/WUT/wut_reva.c + ) +endif() + +if(NOT ( ADI_NS_PRPH_TIMER0 + AND ADI_NS_PRPH_TIMER1 + AND ADI_NS_PRPH_TIMER2 + AND ADI_NS_PRPH_TIMER3 + AND ADI_NS_PRPH_TIMER4 + AND ADI_NS_PRPH_TIMER5 + ) + ) + target_sources(platform_s + PRIVATE + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/TMR/tmr_revb.c + ) +endif() diff --git a/platform/ext/target/adi/max32657/mmio_defs.h b/platform/ext/target/adi/max32657/mmio_defs.h new file mode 100644 index 000000000..1033c4e8a --- /dev/null +++ b/platform/ext/target/adi/max32657/mmio_defs.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __MMIO_DEFS_H__ +#define __MMIO_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "tfm_peripherals_def.h" + +/* Boundary handle binding macros. */ +#define HANDLE_ATTR_PRIV_POS 1U +#define HANDLE_ATTR_PRIV_MASK (0x1UL << HANDLE_ATTR_PRIV_POS) +#define HANDLE_ATTR_NS_POS 0U +#define HANDLE_ATTR_NS_MASK (0x1UL << HANDLE_ATTR_NS_POS) + +/* Allowed named MMIO of this platform */ +const uintptr_t partition_named_mmio_list[] = { + (uintptr_t)TFM_PERIPHERAL_STD_UART, +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* __MMIO_DEFS_H__ */ diff --git a/platform/ext/target/adi/max32657/ns/CMakeLists.txt b/platform/ext/target/adi/max32657/ns/CMakeLists.txt new file mode 100644 index 000000000..ed25b8df6 --- /dev/null +++ b/platform/ext/target/adi/max32657/ns/CMakeLists.txt @@ -0,0 +1,89 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# This file is exported to NS side during CMake installation phase and renamed +# to CMakeLists.txt. It instructs how to build a platform on non-secture side. +# The structure and sources list are fully platform specific. +list(APPEND CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/../../trusted-firmware-m/cmake) +include(remote_library) + +add_library(platform_ns) + +# Fetch hal_adi repository +fetch_remote_library( + LIB_NAME hal_adi + LIB_SOURCE_PATH_VAR HAL_ADI_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/hal_adi + GIT_TAG ${HAL_ADI_VERSION} + GIT_PROGRESS TRUE +) + +set(TARGET_LC "max32657") +string(TOUPPER ${TARGET_LC} TARGET_UC) + +set(HAL_ADI_LIBRARY_DIR ${HAL_ADI_PATH}/MAX/Libraries) + +set(HAL_ADI_CMSIS_DIR ${HAL_ADI_LIBRARY_DIR}/CMSIS/Device/Maxim/${TARGET_UC}) +set(HAL_ADI_CMSIS_INC_DIR ${HAL_ADI_CMSIS_DIR}/Include) +set(HAL_ADI_CMSIS_SRC_DIR ${HAL_ADI_CMSIS_DIR}/Source) + +set(HAL_ADI_PERIPH_DIR ${HAL_ADI_LIBRARY_DIR}/PeriphDrivers) +set(HAL_ADI_PERIPH_INC_DIR ${HAL_ADI_PERIPH_DIR}/Include/${TARGET_UC}) +set(HAL_ADI_PERIPH_SRC_DIR ${HAL_ADI_PERIPH_DIR}/Source) + +target_compile_definitions(platform_ns + PUBLIC + TARGET=${TARGET_UC} + TARGET_REV=0x4131 + CMSIS_device_header="${TARGET_LC}.h" +) + +target_compile_options(platform_ns + PUBLIC + -mno-unaligned-access +) + +target_sources(platform_ns + PRIVATE + Driver_USART.c + device/src/startup_${TARGET_LC}.c + device/src/system_${TARGET_LC}.c + + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/UART/uart_revb.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/sys_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_reva.c + ${HAL_ADI_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${HAL_ADI_PERIPH_SRC_DIR}/SYS/pins_me30.c +) + +target_include_directories(platform_ns + PRIVATE + retarget + PUBLIC + include + include/${TARGET_UC} + ${HAL_ADI_CMSIS_INC_DIR} + ${HAL_ADI_PERIPH_INC_DIR} + ext/cmsis/Include + ext/cmsis/Include/m-profile + device/inc + ext/common +) + +# Include region_defs.h and flash_layout.h +target_include_directories(platform_region_defs + INTERFACE + include +) + +# Get S - NS peripheral and memory access +include(${CMAKE_BINARY_DIR}/../s_ns_access.cmake) diff --git a/platform/ext/target/adi/max32657/otp_max32657.c b/platform/ext/target/adi/max32657/otp_max32657.c new file mode 100644 index 000000000..756f55164 --- /dev/null +++ b/platform/ext/target/adi/max32657/otp_max32657.c @@ -0,0 +1,216 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#include "config_tfm.h" +#include "tfm_plat_otp.h" + +#include "region_defs.h" +#include "tfm_hal_device_header.h" +#include "platform_retarget.h" +#include "flc.h" + +#include "cmsis_compiler.h" + +#define INFOBLOCK_LINE_SIZE 8 +#define OTP_KEY_OFFSET (FLASH_INFO_BASE + 0x3000) + + +#ifdef BL2 +#if defined(MCUBOOT_SIGN_EC384) +#define BL2_ROTPK_HASH_SIZE (48) +#define BL2_ROTPK_KEY_SIZE (100) /* Aligned to 4 bytes */ +#else +#define BL2_ROTPK_HASH_SIZE (32) +#endif /* MCUBOOT_SIGN_EC384 */ +#if defined(MCUBOOT_SIGN_EC256) +#define BL2_ROTPK_KEY_SIZE (68) /* Aligned to 4 bytes */ +#endif /* MCUBOOT_SIGN_EC256 */ + +#ifdef MCUBOOT_BUILTIN_KEY +#define BL2_ROTPK_SIZE BL2_ROTPK_KEY_SIZE +#else +#define BL2_ROTPK_SIZE BL2_ROTPK_HASH_SIZE +#endif /* MCUBOOT_BUILTIN_KEY */ +#endif /* BL2 */ + + +__PACKED_STRUCT max32657_otp_nv_counters_region_t { + uint8_t huk[32]; + uint8_t iak[32]; + uint8_t iak_len[4]; + uint8_t iak_type[4]; + uint8_t iak_id[32]; + + uint8_t boot_seed[32]; + uint8_t lcs[4]; + uint8_t implementation_id[32]; + uint8_t cert_ref[32]; + uint8_t verification_service_url[32]; + uint8_t profile_definition[32]; + + uint8_t bl2_rotpk_0[100]; + uint8_t bl2_rotpk_1[100]; + uint8_t bl2_rotpk_2[100]; + uint8_t bl2_rotpk_3[100]; + + uint8_t bl2_nv_counter_0[64]; + uint8_t bl2_nv_counter_1[64]; + uint8_t bl2_nv_counter_2[64]; + uint8_t bl2_nv_counter_3[64]; + + uint8_t ns_nv_counter_0[64]; + uint8_t ns_nv_counter_1[64]; + uint8_t ns_nv_counter_2[64]; + + uint8_t entropy_seed[64]; + uint8_t secure_debug_pk[32]; +}; + +#define GET_OFFSET(item) (OTP_KEY_OFFSET + offsetof(struct max32657_otp_nv_counters_region_t, item)) +#define GET_SIZE(item) sizeof(((struct max32657_otp_nv_counters_region_t*)0)->item) + +struct max32657_otp_element_t { + uint32_t offset; + uint8_t len; +}; + +static const struct max32657_otp_element_t otp_map[] = { + [PLAT_OTP_ID_HUK] = {.offset = GET_OFFSET(huk) , .len = GET_SIZE(huk) }, + [PLAT_OTP_ID_IAK] = {.offset = GET_OFFSET(iak) , .len = GET_SIZE(iak) }, + [PLAT_OTP_ID_IAK_LEN] = {.offset = GET_OFFSET(iak_len) , .len = GET_SIZE(iak_len) }, + [PLAT_OTP_ID_IAK_TYPE] = {.offset = GET_OFFSET(iak_type) , .len = GET_SIZE(iak_type) }, + [PLAT_OTP_ID_IAK_ID] = {.offset = GET_OFFSET(iak_id) , .len = GET_SIZE(iak_id) }, + [PLAT_OTP_ID_BOOT_SEED] = {.offset = GET_OFFSET(boot_seed) , .len = GET_SIZE(boot_seed) }, + [PLAT_OTP_ID_LCS] = {.offset = GET_OFFSET(lcs) , .len = GET_SIZE(lcs) }, + [PLAT_OTP_ID_IMPLEMENTATION_ID] = {.offset = GET_OFFSET(implementation_id) , .len = GET_SIZE(implementation_id) }, + [PLAT_OTP_ID_CERT_REF] = {.offset = GET_OFFSET(cert_ref) , .len = GET_SIZE(cert_ref) }, + [PLAT_OTP_ID_VERIFICATION_SERVICE_URL] = {.offset = GET_OFFSET(verification_service_url) , .len = GET_SIZE(verification_service_url) }, + [PLAT_OTP_ID_PROFILE_DEFINITION] = {.offset = GET_OFFSET(profile_definition) , .len = GET_SIZE(profile_definition) }, + [PLAT_OTP_ID_BL2_ROTPK_0] = {.offset = GET_OFFSET(bl2_rotpk_0) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_1] = {.offset = GET_OFFSET(bl2_rotpk_1) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_2] = {.offset = GET_OFFSET(bl2_rotpk_2) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_BL2_ROTPK_3] = {.offset = GET_OFFSET(bl2_rotpk_3) , .len = BL2_ROTPK_SIZE }, + [PLAT_OTP_ID_NV_COUNTER_BL2_0] = {.offset = GET_OFFSET(bl2_nv_counter_0) , .len = GET_SIZE(bl2_nv_counter_0) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_1] = {.offset = GET_OFFSET(bl2_nv_counter_1) , .len = GET_SIZE(bl2_nv_counter_1) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_2] = {.offset = GET_OFFSET(bl2_nv_counter_2) , .len = GET_SIZE(bl2_nv_counter_2) }, + [PLAT_OTP_ID_NV_COUNTER_BL2_3] = {.offset = GET_OFFSET(bl2_nv_counter_3) , .len = GET_SIZE(bl2_nv_counter_3) }, + + [PLAT_OTP_ID_NV_COUNTER_NS_0] = {.offset = GET_OFFSET(ns_nv_counter_0) , .len = GET_SIZE(ns_nv_counter_0) }, + [PLAT_OTP_ID_NV_COUNTER_NS_1] = {.offset = GET_OFFSET(ns_nv_counter_1) , .len = GET_SIZE(ns_nv_counter_1) }, + [PLAT_OTP_ID_NV_COUNTER_NS_2] = {.offset = GET_OFFSET(ns_nv_counter_2) , .len = GET_SIZE(ns_nv_counter_2) }, + + [PLAT_OTP_ID_ENTROPY_SEED] = {.offset = GET_OFFSET(entropy_seed) , .len = GET_SIZE(entropy_seed) }, + [PLAT_OTP_ID_SECURE_DEBUG_PK] = {.offset = GET_OFFSET(secure_debug_pk) , .len = GET_SIZE(secure_debug_pk) }, +}; + + +enum tfm_plat_err_t tfm_plat_otp_init(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_read(enum tfm_otp_element_id_t id, + size_t out_len, uint8_t *out) +{ + int i; + size_t copy_len; + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + copy_len = (out_len < otp_map[id].len) ? out_len : otp_map[id].len; + + MXC_FLC_Read(otp_map[id].offset, out, copy_len); + /* + * TF-M project expect default OTP value be 0x00 and + * OTP bits able to be transceive from 0 to 1. + * But MAX32657 OTP default value is 0xff and it transceive from 1 to 0. + * So that after reading OTP, the bits are reversed. + */ + for(i = 0; i < copy_len; i++) { + /* Reverse bits, 1 to 0, 0 to 1 */ + out[i] ^= 0xff; + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_write(enum tfm_otp_element_id_t id, + size_t in_len, const uint8_t *in) +{ + enum tfm_plat_err_t ret = TFM_PLAT_ERR_SUCCESS; + unsigned char buf[INFOBLOCK_LINE_SIZE]; + size_t copy_len; + int addr; + int i; + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + if (in_len > otp_map[id].len) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + MXC_FLC_UnlockInfoBlock(MXC_INFO_MEM_BASE); + + addr = otp_map[id].offset; + while( in_len ) { + copy_len = (in_len < INFOBLOCK_LINE_SIZE) ? in_len: INFOBLOCK_LINE_SIZE; + + /* + * TF-M project expect default OTP value be 0x00 and + * OTP bits able to be transceive from 0 to 1. + * But MAX32657 OTP default value is 0xff and it transceive from 1 to 0. + * So that Before writing bits are reversed. + */ + for (i = 0; i < copy_len; i++) { + /* Reverse bits, 1 to 0, 0 to 1 */ + buf[i] = *in ^ 0xff; + in++; + } + + if (MXC_FLC_Write(addr, copy_len, (uint32_t *)buf) != E_NO_ERROR) { + ret = TFM_PLAT_ERR_SYSTEM_ERR; + break; + } + + in_len -= copy_len; + addr += copy_len; + } + + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + + return ret; +} + +enum tfm_plat_err_t tfm_plat_otp_get_size(enum tfm_otp_element_id_t id, + size_t *size) +{ + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + *size = otp_map[id].len; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_start(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_finish(void) +{ + /* Do nothing */ + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/adi/max32657/partition/flash_layout.h b/platform/ext/target/adi/max32657/partition/flash_layout.h new file mode 100644 index 000000000..bd6833db8 --- /dev/null +++ b/platform/ext/target/adi/max32657/partition/flash_layout.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * Copyright 2019-2023 NXP. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +/* Flash layout on MAX32657 with BL2 (multiple image boot): + * + * Secure flash address which 28th bit 1 is logical address + * + * 0X0100_0000 BL2 - MCUBoot (64KB) + * 0x0101_0000 Secure image primary slot (320KB) + * 0x0106_0000 Non-secure image primary slot (576KB) + * 0x010F_0000 Secure image secondary slot (0KB) + * 0x010F_0000 Non-secure image secondary slot (0KB) + * 0x010F_0000 Scratch area (0) + * 0x010F_0000 Protected Storage Area (0) + * 0x010F_0000 Internal Trusted Storage Area (16 KB) + * 0x010F_4000 OTP / NV counters area (16 KB) + * 0x010F_8000 Unused (32KB) + * + * Flash layout on MAX32657 with BL2 (single image boot): + * + * 0X0100_0000 BL2 - MCUBoot (64KB) + * 0x0101_0000 Primary image area (896KB): + * 0x0101_0000 Secure image primary + * 0x0106_0000 Non-secure image primary + * 0x010F_0000 Secondary image area (0KB): + * 0x010F_0000 Secure image secondary + * 0x010F_0000 Non-secure image secondary + * 0x010F_0000 Scratch area (0) + * 0x010F_0000 Protected Storage Area (0) + * 0x010F_0000 Internal Trusted Storage Area (16 KB) + * 0x010F_4000 OTP / NV counters area (16 KB) + * 0x010F_8000 Unused + * + * Flash layout on MAX32657, if BL2 not defined: + * + * 0X0100_0000 Secure image (512KB) + * 0X0108_0000 Non-secure image (512KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +#ifndef KB +#define KB(x) ((x) * 1024) +#endif + +/* Size of a Secure and of a Non-secure image */ +#define FLASH_S_PARTITION_SIZE ADI_FLASH_S_PARTITION_SIZE +#define FLASH_NS_PARTITION_SIZE ADI_FLASH_NS_PARTITION_SIZE + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif +/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE KB(8) +/* Same as FLASH0_SIZE */ +#define FLASH_TOTAL_SIZE KB(1024) + +/* Flash layout info for BL2 bootloader */ +/* Same as FLASH0_BASE_S */ +#define FLASH_BASE_ADDRESS (0x11000000) + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0) +#define FLASH_AREA_BL2_SIZE ADI_FLASH_AREA_BL2_SIZE + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE) +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_2_SIZE (0) +/* Not used (scratch area), the 'Swap' firmware upgrade operation is not + * supported on MAX32657 */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) +#elif (MCUBOOT_IMAGE_NUMBER == 2) +/* Secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE) +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE) +/* Non-secure image primary slot */ +#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) +#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE) +/* Secure image secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1) +#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE) +#define FLASH_AREA_2_SIZE (0) +/* Non-secure image secondary slot */ +#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) +#define FLASH_AREA_3_SIZE (0) +/* Scratch area */ +/* FIXME: remove scartch area. Currently removing them yields BL2 error*/ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) +#define FLASH_AREA_SCRATCH_SIZE (0) +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES (0) +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) +#else /* MCUBOOT_IMAGE_NUMBER > 2 */ +#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE) +#define FLASH_PS_AREA_SIZE ADI_FLASH_PS_AREA_SIZE + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE ADI_FLASH_ITS_AREA_SIZE + +/* Placing OTP backup area in Flash because of limited availability of Secure Flash Info area */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE*2) +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Flash device name used by BL2 */ +#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes - MAX32657: 128 bits */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x00000010) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x00000010) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x00000010) // Supports 128 bit writes + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + TFM_OTP_NV_COUNTERS_AREA_SIZE) + +/* Flash and RAM configurations for secure and non-secure image partitions*/ + +#define S_ROM_ALIAS_BASE (0x11000000) +#define NS_ROM_ALIAS_BASE (0X01000000) + +#define S_RAM_ALIAS_BASE (0x30000000) +#define NS_RAM_ALIAS_BASE (0x20000000) + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE KB(256) + +// SRAM_0 +#define MAX32657_SRAM0_OFFSET 0 +#define MAX32657_SRAM0_SIZE KB(32) +// SRAM_1 +#define MAX32657_SRAM1_OFFSET 0x00008000UL +#define MAX32657_SRAM1_SIZE KB(32) +// SRAM_2 +#define MAX32657_SRAM2_OFFSET 0x00010000UL +#define MAX32657_SRAM2_SIZE KB(64) +// SRAM_3 +#define MAX32657_SRAM3_OFFSET 0x00020000UL +#define MAX32657_SRAM3_SIZE KB(64) +// SRAM_4 +#define MAX32657_SRAM4_OFFSET 0x00030000UL +#define MAX32657_SRAM4_SIZE KB(64) + + +#if defined(ADI_NS_SRAM_0) + #define MAX32657_S_SRAM0_SIZE 0 +#else + #define MAX32657_S_SRAM0_SIZE MAX32657_SRAM0_SIZE +#endif + +#if defined(ADI_NS_SRAM_1) + #define MAX32657_S_SRAM1_SIZE 0 +#else + #define MAX32657_S_SRAM1_SIZE MAX32657_SRAM1_SIZE +#endif + +#if defined(ADI_NS_SRAM_2) + #define MAX32657_S_SRAM2_SIZE 0 +#else + #define MAX32657_S_SRAM2_SIZE MAX32657_SRAM2_SIZE +#endif + +#if defined(ADI_NS_SRAM_3) + #define MAX32657_S_SRAM3_SIZE 0 +#else + #define MAX32657_S_SRAM3_SIZE MAX32657_SRAM3_SIZE +#endif + +#if defined(ADI_NS_SRAM_4) + #define MAX32657_S_SRAM4_SIZE 0 +#else + #define MAX32657_S_SRAM4_SIZE MAX32657_SRAM4_SIZE +#endif + +/* RAM shall be defined sequential */ +#if !defined(ADI_NS_SRAM_0) + // SRAM0 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM0_OFFSET +#elif !defined(ADI_NS_SRAM_1) + // SRAM1 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM1_OFFSET +#elif !defined(ADI_NS_SRAM_2) + // SRAM2 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM2_OFFSET +#elif !defined(ADI_NS_SRAM_3) + // SRAM3 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM3_OFFSET +#elif !defined(ADI_NS_SRAM_4) + // SRAM4 on secure world + #define MAX32657_S_DATA_OFFSET MAX32657_SRAM4_OFFSET +#else + #error "SRAM Not Defined for TF-M" +#endif + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/adi/max32657/partition/region_defs.h b/platform/ext/target/adi/max32657/partition/region_defs.h new file mode 100644 index 000000000..722011cc9 --- /dev/null +++ b/platform/ext/target/adi/max32657/partition/region_defs.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2017-2023 Arm Limited. All rights reserved. + * Copyright 2019-2023 NXP. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#define BL2_HEAP_SIZE KB(4) +#define BL2_MSP_STACK_SIZE KB(6) + +#ifdef ENABLE_HEAP +#define S_HEAP_SIZE (512) +#endif + +#ifdef TFM_FIH_PROFILE_ON +#define S_MSP_STACK_SIZE (0x00000A40) +#else +#define S_MSP_STACK_SIZE KB(4) +#endif +#define S_PSP_STACK_SIZE KB(2) + +#define NS_HEAP_SIZE KB(4) +#define NS_STACK_SIZE (0x000001E0) + + +#ifdef BL2 +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0) +#endif /* BL2 */ + +#ifndef LINK_TO_SECONDARY_PARTITION + +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ +#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) +/* If secure image and nonsecure image are concatenated, and nonsecure image + * locates at the higher memory range, then the secure image does not need + * the trailer area. + */ +#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) +#else +#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#endif + +#define IMAGE_NS_CODE_SIZE FLASH_NS_PARTITION_SIZE + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +/* Size of vector table: 69 interrupt handlers + 16 bytes of reserved space */ +#define S_CODE_VECTOR_TABLE_SIZE (0x00000124) + +/* Set Secure FW SRAM Size */ +#define S_TOTAL_DATA_SIZE ( MAX32657_S_SRAM0_SIZE + \ + MAX32657_S_SRAM1_SIZE + \ + MAX32657_S_SRAM2_SIZE + \ + MAX32657_S_SRAM3_SIZE + \ + MAX32657_S_SRAM4_SIZE ) + +#define S_RAM_CODE_SIZE ADI_S_RAM_CODE_SIZE /* ramfuncs section size*/ + +#define S_DATA_START (S_RAM_ALIAS(MAX32657_S_DATA_OFFSET)) +#define S_DATA_SIZE (S_TOTAL_DATA_SIZE - S_RAM_CODE_SIZE) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +#define S_RAM_CODE_START (S_DATA_START + S_DATA_SIZE) /* ramfuncs section start */ +#define S_RAM_CODE_EXTRA_SECTION_NAME ".flashprog" /* ramfuncs section name */ + +/* Non-secure regions + * MPC block aligned 32KB, NS binary need to aling that + */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS( S_TOTAL_DATA_SIZE )) +#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC) +#define DEV_APIS_TEST_NVMEM_REGION_SIZE KB(1) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_TOTAL_DATA_SIZE - DEV_APIS_TEST_NVMEM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_TOTAL_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for MPC and SAU configuration */ + +#define MPC_CONFIG_BLOCK_SIZE KB(32) //Configurable block size by MPC is 32kb + +#define NS_PARTITION_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_PARTITION_END (NS_PARTITION_START + NS_PARTITION_SIZE - 1) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE) + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared symbol area between bootloader and runtime firmware. Global variables + * in the shared code can be placed here. + */ +#ifdef CODE_SHARING +#define SHARED_SYMBOL_AREA_BASE (S_RAM_ALIAS_BASE) +#define SHARED_SYMBOL_AREA_SIZE (0x00000020) +#else +#define SHARED_SYMBOL_AREA_BASE (S_RAM_ALIAS_BASE) +#define SHARED_SYMBOL_AREA_SIZE (0x00000000) +#endif /* CODE_SHARING */ + +/* Shared data area between bootloader and runtime firmware. + * These areas are allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE (SHARED_SYMBOL_AREA_BASE + SHARED_SYMBOL_AREA_SIZE) +#define BOOT_TFM_SHARED_DATA_SIZE KB(1) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) + +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT + +#define PROVISIONING_BUNDLE_CODE_START (BL2_DATA_START + BL2_DATA_SIZE - KB(32)) +#define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) +/* The max size of the values(keys, seeds) that are going to be provisioned into the OTP. */ +#define PROVISIONING_BUNDLE_VALUES_START (PROVISIONING_BUNDLE_CODE_START + PROVISIONING_BUNDLE_CODE_SIZE) +#define PROVISIONING_BUNDLE_VALUES_SIZE (PROVISIONING_VALUES_PADDED_SIZE) +#define PROVISIONING_BUNDLE_DATA_START (PROVISIONING_BUNDLE_VALUES_START + PROVISIONING_BUNDLE_VALUES_SIZE) +#define PROVISIONING_BUNDLE_DATA_SIZE (PROVISIONING_DATA_PADDED_SIZE) +#define PROVISIONING_BUNDLE_START (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/adi/max32657/platform_otp_ids.h b/platform/ext/target/adi/max32657/platform_otp_ids.h new file mode 100644 index 000000000..6524ba8de --- /dev/null +++ b/platform/ext/target/adi/max32657/platform_otp_ids.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __PLATFORM_OTP_IDS_H__ +#define __PLATFORM_OTP_IDS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum tfm_otp_element_id_t { + PLAT_OTP_ID_HUK = 0, + PLAT_OTP_ID_IAK, + PLAT_OTP_ID_IAK_LEN, + PLAT_OTP_ID_IAK_TYPE, + PLAT_OTP_ID_IAK_ID, + + PLAT_OTP_ID_BOOT_SEED, + PLAT_OTP_ID_LCS, + PLAT_OTP_ID_IMPLEMENTATION_ID, + PLAT_OTP_ID_CERT_REF, + PLAT_OTP_ID_VERIFICATION_SERVICE_URL, + PLAT_OTP_ID_PROFILE_DEFINITION, + + /* BL2 ROTPK must be contiguous */ + PLAT_OTP_ID_BL2_ROTPK_0, + PLAT_OTP_ID_BL2_ROTPK_1, + PLAT_OTP_ID_BL2_ROTPK_2, + PLAT_OTP_ID_BL2_ROTPK_3, + + /* BL2 NV counters must be contiguous */ + PLAT_OTP_ID_NV_COUNTER_BL2_0, + PLAT_OTP_ID_NV_COUNTER_BL2_1, + PLAT_OTP_ID_NV_COUNTER_BL2_2, + PLAT_OTP_ID_NV_COUNTER_BL2_3, + + PLAT_OTP_ID_NV_COUNTER_NS_0, + PLAT_OTP_ID_NV_COUNTER_NS_1, + PLAT_OTP_ID_NV_COUNTER_NS_2, + + PLAT_OTP_ID_ENTROPY_SEED, + PLAT_OTP_ID_SECURE_DEBUG_PK, + + PLAT_OTP_ID_MAX, +}; + +#ifdef __cplusplus +} +#endif +#endif /* __PLATFORM_OTP_IDS_H__ */ diff --git a/platform/ext/target/adi/max32657/platform_retarget.h b/platform/ext/target/adi/max32657/platform_retarget.h new file mode 100644 index 000000000..16fee969d --- /dev/null +++ b/platform/ext/target/adi/max32657/platform_retarget.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __ADI_MAX32657_RETARGET_H__ +#define __ADI_MAX32657_RETARGET_H__ + +#include "max32657.h" + +/* ======= Defines peripherals memory map addresses ======= */ +/* Define Peripherals NS address range for the platform */ +#define PERIPHERALS_BASE_NS_START (0x40000000) +#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF) + +/* Non-secure memory map addresses */ +#define UART0_BASE_NS MXC_BASE_UART_NS +#define TRNG_BASE_NS MXC_BASE_TRNG_NS + +/* Secure memory map addresses */ +#define UART0_BASE_S MXC_BASE_UART_S +#define TRNG_BASE_S MXC_BASE_TRNG_S +#define MPC_SRAM0_BASE_S MXC_BASE_MPC_SRAM0_S +#define MPC_SRAM1_BASE_S MXC_BASE_MPC_SRAM1_S +#define MPC_SRAM2_BASE_S MXC_BASE_MPC_SRAM2_S +#define MPC_SRAM3_BASE_S MXC_BASE_MPC_SRAM3_S +#define MPC_SRAM4_BASE_S MXC_BASE_MPC_SRAM4_S +#define MPC_FLASH_BASE_S MXC_BASE_MPC_FLASH_S + + +/* SRAM MPC ranges and limits */ +/* Internal memory */ +#define MPC_SRAM0_RANGE_BASE_NS 0x20000000 +#define MPC_SRAM0_RANGE_LIMIT_NS 0x20007FFF +#define MPC_SRAM0_RANGE_BASE_S 0x30000000 +#define MPC_SRAM0_RANGE_LIMIT_S 0x30007FFF + +#define MPC_SRAM1_RANGE_BASE_NS 0x20008000 +#define MPC_SRAM1_RANGE_LIMIT_NS 0x2000FFFF +#define MPC_SRAM1_RANGE_BASE_S 0x30008000 +#define MPC_SRAM1_RANGE_LIMIT_S 0x3000FFFF + +#define MPC_SRAM2_RANGE_BASE_NS 0x20010000 +#define MPC_SRAM2_RANGE_LIMIT_NS 0x2001FFFF +#define MPC_SRAM2_RANGE_BASE_S 0x30010000 +#define MPC_SRAM2_RANGE_LIMIT_S 0x3001FFFF + +#define MPC_SRAM3_RANGE_BASE_NS 0x20020000 +#define MPC_SRAM3_RANGE_LIMIT_NS 0x2002FFFF +#define MPC_SRAM3_RANGE_BASE_S 0x30020000 +#define MPC_SRAM3_RANGE_LIMIT_S 0x3002FFFF + +#define MPC_SRAM4_RANGE_BASE_NS 0x20030000 +#define MPC_SRAM4_RANGE_LIMIT_NS 0x2003FFFF +#define MPC_SRAM4_RANGE_BASE_S 0x30030000 +#define MPC_SRAM4_RANGE_LIMIT_S 0x3003FFFF + +/* Flash memory */ +#define FLASH0_BASE_S 0x11000000 +#define FLASH0_BASE_NS MXC_PHY_FLASH_MEM_BASE +#define FLASH0_SIZE MXC_PHY_FLASH_MEM_SIZE /* 1 MB */ +#define FLASH0_SECTOR_SIZE MXC_PHY_FLASH_PAGE_SIZE /* 8 kB */ +#define FLASH0_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE /* 8 kB */ +#define FLASH0_PROGRAM_UNIT 0x10 /* Minimum write size */ + +/* Flash memory Info Block */ +#define FLASH_INFO_BASE MXC_INFO_MEM_BASE +#define FLASH_INFO_SIZE MXC_INFO_MEM_SIZE /* 16 KB */ +#define FLASH_INFO_SECTOR_SIZE 0x00002000 /* 8 kB */ +#define FLASH_INFO_PAGE_SIZE 0x00002000 /* 8 kB */ +#define FLASH_INFO_PROGRAM_UNIT 0x10 /* Minimum write size */ + +#endif /* __ADI_MAX32657_RETARGET_H__ */ diff --git a/platform/ext/target/adi/max32657/s_ns_access.cmake b/platform/ext/target/adi/max32657/s_ns_access.cmake new file mode 100644 index 000000000..39939751e --- /dev/null +++ b/platform/ext/target/adi/max32657/s_ns_access.cmake @@ -0,0 +1,81 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(ADI_NS_PRPH_GCR ON CACHE BOOL "") +set(ADI_NS_PRPH_SIR ON CACHE BOOL "") +set(ADI_NS_PRPH_FCR ON CACHE BOOL "") +set(ADI_NS_PRPH_WDT ON CACHE BOOL "") +set(ADI_NS_PRPH_AES ON CACHE BOOL "") +set(ADI_NS_PRPH_AESKEY ON CACHE BOOL "") +set(ADI_NS_PRPH_CRC ON CACHE BOOL "") +set(ADI_NS_PRPH_GPIO0 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER0 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER1 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER2 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER3 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER4 ON CACHE BOOL "") +set(ADI_NS_PRPH_TIMER5 ON CACHE BOOL "") +set(ADI_NS_PRPH_I3C ON CACHE BOOL "") +set(ADI_NS_PRPH_UART ON CACHE BOOL "") +set(ADI_NS_PRPH_SPI ON CACHE BOOL "") +set(ADI_NS_PRPH_TRNG ON CACHE BOOL "") +set(ADI_NS_PRPH_BTLE_DBB ON CACHE BOOL "") +set(ADI_NS_PRPH_BTLE_RFFE ON CACHE BOOL "") +set(ADI_NS_PRPH_RSTZ ON CACHE BOOL "") +set(ADI_NS_PRPH_BOOST ON CACHE BOOL "") +set(ADI_NS_PRPH_BBSIR ON CACHE BOOL "") +set(ADI_NS_PRPH_BBFCR ON CACHE BOOL "") +set(ADI_NS_PRPH_RTC ON CACHE BOOL "") +set(ADI_NS_PRPH_WUT0 ON CACHE BOOL "") +set(ADI_NS_PRPH_WUT1 ON CACHE BOOL "") +set(ADI_NS_PRPH_PWR ON CACHE BOOL "") +set(ADI_NS_PRPH_MCR ON CACHE BOOL "") + +# SRAMs +set(ADI_NS_SRAM_0 OFF CACHE BOOL "Size: 32KB") +set(ADI_NS_SRAM_1 OFF CACHE BOOL "Size: 32KB") +set(ADI_NS_SRAM_2 ON CACHE BOOL "Size: 64KB") +set(ADI_NS_SRAM_3 ON CACHE BOOL "Size: 64KB") +set(ADI_NS_SRAM_4 ON CACHE BOOL "Size: 64KB") + +# Ramfuncs section size +set(ADI_S_RAM_CODE_SIZE "0x800" CACHE STRING "Default: 2KB") + +# Flash: BL2, TFM and Zephyr are contiguous sections. +set(ADI_FLASH_AREA_BL2_SIZE "0x10000" CACHE STRING "Default: 64KB") +set(ADI_FLASH_S_PARTITION_SIZE "0x50000" CACHE STRING "Default: 320KB") +set(ADI_FLASH_NS_PARTITION_SIZE "0x90000" CACHE STRING "Default: 576KB") +set(ADI_FLASH_PS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") +set(ADI_FLASH_ITS_AREA_SIZE "0x4000" CACHE STRING "Default: 16KB") + + +# +# Allow user set S-NS resources ownership by overlay file +# +if(EXISTS "${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake") + include(${CMAKE_BINARY_DIR}/../../s_ns_access_overlay.cmake) +endif() + +target_compile_definitions(platform_region_defs + INTERFACE + # SRAMs + $<$:ADI_NS_SRAM_0> + $<$:ADI_NS_SRAM_1> + $<$:ADI_NS_SRAM_2> + $<$:ADI_NS_SRAM_3> + $<$:ADI_NS_SRAM_4> + + # ramfunc section size + ADI_S_RAM_CODE_SIZE=${ADI_S_RAM_CODE_SIZE} + + # Flash + ADI_FLASH_AREA_BL2_SIZE=${ADI_FLASH_AREA_BL2_SIZE} + ADI_FLASH_S_PARTITION_SIZE=${ADI_FLASH_S_PARTITION_SIZE} + ADI_FLASH_NS_PARTITION_SIZE=${ADI_FLASH_NS_PARTITION_SIZE} + ADI_FLASH_PS_AREA_SIZE=${ADI_FLASH_PS_AREA_SIZE} + ADI_FLASH_ITS_AREA_SIZE=${ADI_FLASH_ITS_AREA_SIZE} +) diff --git a/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h b/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h new file mode 100644 index 000000000..ccd0a036f --- /dev/null +++ b/platform/ext/target/adi/max32657/services/include/tfm_ioctl_core_api.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#ifndef TFM_IOCTL_CORE_API_H__ +#define TFM_IOCTL_CORE_API_H__ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @brief Supported request types. + */ +enum tfm_platform_ioctl_core_reqest_types_t { + TFM_PLATFORM_ADI_IOCTL_READ_OTP_SERVICE = 0, +}; + +enum tfm_platform_err_t +tfm_platform_adi_hal_otp_service(const psa_invec *in_vec, + const psa_outvec *out_vec); + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_IOCTL_CORE_API_H__ */ diff --git a/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c b/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c new file mode 100644 index 000000000..c0cb1f1a1 --- /dev/null +++ b/platform/ext/target/adi/max32657/services/src/tfm_platform_hal_ioctl.c @@ -0,0 +1,77 @@ +/****************************************************************************** + * + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + ******************************************************************************/ + +#include "tfm_platform_api.h" +#include "psa/client.h" +#include "tfm_plat_defs.h" +#include "platform_retarget.h" +#include "flc.h" + +#define IOCTL_OTP_INVEC_LEN 1 + +#define MXC_INFO_MEM_USN_ADDR FLASH_INFO_BASE +#define MXC_INFO_MEM_USN_PKG_CODE_ADDR (FLASH_INFO_BASE + 0x14) +#define MXC_INFO_MEM_LDO_TRIM_BB_ADDR (FLASH_INFO_BASE + 0x19C) +#define MXC_INFO_MEM_LDO_TRIM_RF_ADDR (FLASH_INFO_BASE + 0x1AC) +#define MXC_INFO_MEM_DBB_SETTINGS_ADDR0 (FLASH_INFO_BASE + 0x400) +#define MXC_INFO_MEM_DBB_SETTINGS_ADDR1 (FLASH_INFO_BASE + 0x440) + +enum adi_otp_types_t { + ADI_OTP_ID_USN = 0, + ADI_OTP_ID_BLE_LDO_TRIM_BB, + ADI_OTP_ID_BLE_LDO_TRIM_RF, + ADI_OTP_ID_DBB_SETTINGS0, + ADI_OTP_ID_DBB_SETTINGS1, +}; + + +enum tfm_platform_err_t +tfm_platform_adi_hal_otp_service(const psa_invec *in_vec, + const psa_outvec *out_vec) +{ + if ( (in_vec == NULL) || + (out_vec == NULL) || + (in_vec->len != IOCTL_OTP_INVEC_LEN) ) { + + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + enum adi_otp_types_t arg = *(enum adi_otp_types_t *)in_vec->base; + int src; + int len; + switch (arg) { + case ADI_OTP_ID_USN: + len = 24; + src = MXC_INFO_MEM_USN_ADDR; + break; + case ADI_OTP_ID_BLE_LDO_TRIM_BB: + len = 4; + src = MXC_INFO_MEM_LDO_TRIM_BB_ADDR; + break; + case ADI_OTP_ID_BLE_LDO_TRIM_RF: + len = 4; + src = MXC_INFO_MEM_LDO_TRIM_RF_ADDR; + break; + case ADI_OTP_ID_DBB_SETTINGS0: + len = 64; + src = MXC_INFO_MEM_DBB_SETTINGS_ADDR0; + break; + case ADI_OTP_ID_DBB_SETTINGS1: + len = 64; + src = MXC_INFO_MEM_DBB_SETTINGS_ADDR1; + break; + default: + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + MXC_FLC_UnlockInfoBlock(FLASH_INFO_BASE); + MXC_FLC_Read(src, out_vec->base, len); + MXC_FLC_LockInfoBlock(FLASH_INFO_BASE); + + return TFM_PLATFORM_ERR_SUCCESS; +} diff --git a/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c b/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c new file mode 100644 index 000000000..8e4283d35 --- /dev/null +++ b/platform/ext/target/adi/max32657/services/src/tfm_platform_system.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + switch (request) { + case TFM_PLATFORM_ADI_IOCTL_READ_OTP_SERVICE: + return tfm_platform_adi_hal_otp_service(in_vec, out_vec); + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } +} diff --git a/platform/ext/target/adi/max32657/target_cfg.c b/platform/ext/target/adi/max32657/target_cfg.c new file mode 100644 index 000000000..45e008dbe --- /dev/null +++ b/platform/ext/target/adi/max32657/target_cfg.c @@ -0,0 +1,674 @@ +/* + * Copyright (c) 2017-2024 Arm Limited + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mxc_device.h" +#include "fih.h" +#include "target_cfg.h" +#include "Driver_MPC.h" +#include "Driver_PPC.h" +#include "platform_retarget.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "region.h" +#include "spc.h" + +/* Ensure that the start and end of NS is MPC block aligned (32kb) */ +_Static_assert(NS_PARTITION_START % MPC_CONFIG_BLOCK_SIZE == 0, "Align NS Start to MPC Block size"); +_Static_assert((NS_PARTITION_END + 1) % MPC_CONFIG_BLOCK_SIZE == 0, "Align NS End to MPC Block size"); + +#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) + +#define NVIC_SECURE_CONFIG 0 +#define NVIC_NON_SECURE_CONFIG 1 + +/* The section names come from the scatter file */ +REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); +REGION_DECLARE(Image$$, ER_VENEER, $$Base); +REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); + +#ifdef BL2 +REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); +#endif /* BL2 */ + +const struct memory_region_limits memory_regions = { + .non_secure_code_start = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + BL2_HEADER_SIZE, + + .non_secure_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), + + .non_secure_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1, + + .veneer_base = (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + .veneer_limit = (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit), + +#ifdef BL2 + .secondary_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), + + .secondary_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + + SECONDARY_PARTITION_SIZE - 1, +#endif /* BL2 */ +}; + +/* Allows software, via SAU, to define the code region as a NSC */ +#define NSCCFG_CODENSC 1 + +struct platform_data_t tfm_peripheral_std_uart = { + UART0_BASE_NS, + UART0_BASE_NS + 0xFFF, + PPC_SP_DO_NOT_CONFIGURE, + SPC_UART +}; + +/* Import MPC driver */ +extern ARM_DRIVER_MPC Driver_SRAM0_MPC, Driver_SRAM1_MPC, + Driver_SRAM2_MPC, Driver_SRAM3_MPC, + Driver_FLASH_MPC, Driver_SRAM4_MPC; + +extern ARM_DRIVER_PPC Driver_PPC; + +/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field, + * otherwise the processor ignores the write. + */ +#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)) + +typedef struct { + ARM_DRIVER_MPC *Driver_MPC; + uint32_t base; + uint32_t limit; +} NS_MPC_Config; + +/** + * @brief Array of MPC ranges for NS access + * + */ +static NS_MPC_Config ns_mpc_config_arr[] = { +#if defined(ADI_NS_SRAM_0) + { + &Driver_SRAM0_MPC, + MPC_SRAM0_RANGE_BASE_NS, + MPC_SRAM0_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_1) + { + &Driver_SRAM1_MPC, + MPC_SRAM1_RANGE_BASE_NS, + MPC_SRAM1_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_2) + { + &Driver_SRAM2_MPC, + MPC_SRAM2_RANGE_BASE_NS, + MPC_SRAM2_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_3) + { + &Driver_SRAM3_MPC, + MPC_SRAM3_RANGE_BASE_NS, + MPC_SRAM3_RANGE_LIMIT_NS + }, +#endif +#if defined(ADI_NS_SRAM_4) + { + &Driver_SRAM4_MPC, + MPC_SRAM4_RANGE_BASE_NS, + MPC_SRAM4_RANGE_LIMIT_NS + }, +#endif + { + &Driver_FLASH_MPC, + memory_regions.non_secure_partition_base, + memory_regions.non_secure_partition_limit, + }, +}; + +/** + * @brief Array of peripherals partitioned to the NS domain + * + */ + +uint8_t ns_periph_arr[] = { +#if defined(ADI_NS_PRPH_GCR) + SPC_GCR, +#endif +#if defined(ADI_NS_PRPH_SIR) + SPC_SIR, +#endif +#if defined(ADI_NS_PRPH_FCR) + SPC_FCR, +#endif +#if defined(ADI_NS_PRPH_WDT) + SPC_WDT, +#endif +#if defined(ADI_NS_PRPH_AES) + SPC_AES, +#endif +#if defined(ADI_NS_PRPH_AESKEY) + SPC_AESKEY, +#endif +#if defined(ADI_NS_PRPH_CRC) + SPC_CRC, +#endif +#if defined(ADI_NS_PRPH_GPIO0) + SPC_GPIO0, +#endif +#if defined(ADI_NS_PRPH_TIMER0) + SPC_TIMER0, +#endif +#if defined(ADI_NS_PRPH_TIMER1) + SPC_TIMER1, +#endif +#if defined(ADI_NS_PRPH_TIMER2) + SPC_TIMER2, +#endif +#if defined(ADI_NS_PRPH_TIMER3) + SPC_TIMER3, +#endif +#if defined(ADI_NS_PRPH_TIMER4) + SPC_TIMER4, +#endif +#if defined(ADI_NS_PRPH_TIMER5) + SPC_TIMER5, +#endif +#if defined(ADI_NS_PRPH_I3C) + SPC_I3C, +#endif +#if defined(ADI_NS_PRPH_UART) && !defined(TFM_S_REG_TEST) + SPC_UART, +#endif +#if defined(ADI_NS_PRPH_SPI) + SPC_SPI, +#endif +#if defined(ADI_NS_PRPH_TRNG) + SPC_TRNG, +#endif +#if defined(ADI_NS_PRPH_BTLE_DBB) + SPC_BTLE_DBB, +#endif +#if defined(ADI_NS_PRPH_BTLE_RFFE) + SPC_BTLE_RFFE, +#endif +#if defined(ADI_NS_PRPH_RSTZ) + SPC_RSTZ, +#endif +#if defined(ADI_NS_PRPH_BOOST) + SPC_BOOST, +#endif +#if defined(ADI_NS_PRPH_BBSIR) + SPC_BBSIR, +#endif +#if defined(ADI_NS_PRPH_BBFCR) + SPC_BBFCR, +#endif +#if defined(ADI_NS_PRPH_RTC) + SPC_RTC, +#endif +#if defined(ADI_NS_PRPH_WUT0) + SPC_WUT0, +#endif +#if defined(ADI_NS_PRPH_WUT1) + SPC_WUT1, +#endif +#if defined(ADI_NS_PRPH_PWR) + SPC_PWR, +#endif +#if defined(ADI_NS_PRPH_MCR) + SPC_MCR, +#endif +}; + +uint8_t nvic_set_ns[] = { +#if defined(ADI_NS_PRPH_WDT) + WDT_IRQn, +#endif +#if defined(ADI_NS_PRPH_RTC) + RTC_IRQn, +#endif +#if defined(ADI_NS_PRPH_TRNG) + TRNG_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER0) + TMR0_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER1) + TMR1_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER2) + TMR2_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER3) + TMR3_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER4) + TMR4_IRQn, +#endif +#if defined(ADI_NS_PRPH_TIMER5) + TMR5_IRQn, +#endif +#if defined(ADI_NS_PRPH_I3C) + I3C_IRQn, +#endif +#if defined(ADI_NS_PRPH_UART) && !defined(TFM_S_REG_TEST) + UART_IRQn, +#endif +#if defined(ADI_NS_PRPH_SPI) + SPI_IRQn, +#endif +#if defined(ADI_NS_PRPH_GPIO0) + GPIO0_IRQn, +#endif + DMA0_CH0_IRQn, + DMA0_CH1_IRQn, + DMA0_CH2_IRQn, + DMA0_CH3_IRQn, +#if defined(ADI_NS_PRPH_WUT0) + WUT0_IRQn, +#endif +#if defined(ADI_NS_PRPH_WUT1) + WUT1_IRQn, +#endif +#if defined(ADI_NS_PRPH_GPIO0) + GPIOWAKE_IRQn, +#endif +#if defined(ADI_NS_PRPH_CRC) + CRC_IRQn, +#endif +#if defined(ADI_NS_PRPH_AES) + AES_IRQn, +#endif + ERFO_IRQn, + BOOST_IRQn, + BTLE_TX_DONE_IRQn, + BTLE_RX_RCVD_IRQn, + BTLE_RX_ENG_DET_IRQn, + BTLE_SFD_DET_IRQn, + BTLE_SFD_TO_IRQn, + BTLE_GP_EVENT_IRQn, + BTLE_CFO_IRQn, + BTLE_SIG_DET_IRQn, + BTLE_AGC_EVENT_IRQn, + BTLE_RFFE_SPIM_IRQn, + BTLE_TX_AES_IRQn, + BTLE_RX_AES_IRQn, + BTLE_INV_APB_ADDR_IRQn, + BTLE_IQ_DATA_VALID_IRQn, + BTLE_RX_CRC_IRQn, +}; + +enum tfm_plat_err_t enable_fault_handlers(void) +{ + /* Explicitly set secure fault priority to the highest */ + NVIC_SetPriority(SecureFault_IRQn, 0); + + /* Enables BUS, MEM, USG and Secure faults */ + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk + | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk + | SCB_SHCSR_SECUREFAULTENA_Msk; + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t system_reset_cfg(void) +{ + uint32_t reg_value = SCB->AIRCR; + + /* Clear SCB_AIRCR_VECTKEY value */ + reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk); + + /* Enable system reset request only to the secure world */ + reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk); + + SCB->AIRCR = reg_value; + + return TFM_PLAT_ERR_SUCCESS; +} + +FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void) +{ +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug features are set during provisioning." +#endif + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be WI */ + for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ITNS); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that MPC and PPC are targeted to S state */ + NVIC_ClearTargetState(MPC_IRQn); + NVIC_ClearTargetState(PPC_IRQn); + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + int32_t ret = ARM_DRIVER_OK; + + /* MPC interrupt enabling */ + ret = Driver_SRAM0_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM1_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM2_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM3_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + ret = Driver_SRAM4_MPC.EnableInterrupt(); + if (ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + NVIC_EnableIRQ(MPC_IRQn); + + /* PPC interrupt enabling */ + Driver_PPC.Initialize(); + /* Clear pending PPC interrupts */ + Driver_PPC.ClearInterrupt(); + + /* Enable PPC interrupts */ + ret = Driver_PPC.EnableInterrupt(); + if(ret != ARM_DRIVER_OK) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + NVIC_EnableIRQ(PPC_IRQn); + + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ +#if defined(PSA_API_TEST_NS) && !defined(PSA_API_TEST_IPC) +#define DEV_APIS_TEST_NVMEM_REGION_START (NS_DATA_LIMIT + 1) +#define DEV_APIS_TEST_NVMEM_REGION_LIMIT \ + (DEV_APIS_TEST_NVMEM_REGION_START + DEV_APIS_TEST_NVMEM_REGION_SIZE - 1) +#endif + +struct sau_cfg_t { + uint32_t RBAR; + uint32_t RLAR; + bool nsc; +}; + +const struct sau_cfg_t sau_cfg[] = { + { + ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base)), + ((uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1), + false, + }, + { + NS_DATA_START, + NS_DATA_LIMIT, + false, + }, + { + (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1, + true, + }, + { + PERIPHERALS_BASE_NS_START, + PERIPHERALS_BASE_NS_END, + false, + }, +}; + +FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void) +{ + uint32_t i; + + /* Ensure all memory accesses are completed */ + __DMB(); + + /* Enables SAU */ + TZ_SAU_Enable(); + + for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) { + SAU->RNR = i; + SAU->RBAR = sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk; + SAU->RLAR = (sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | + (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | + SAU_RLAR_ENABLE_Msk; + } + + /* Allows SAU to define the code region as a NSC */ + MXC_SPC_SetCode_NSC(true); + + /* Ensure the write is completed and flush pipeline */ + __DSB(); + __ISB(); + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_sau_and_idau_cfg(void) +{ + uint32_t i; + + /* Check SAU is enabled */ + if ((SAU->CTRL & (SAU_CTRL_ENABLE_Msk)) != (SAU_CTRL_ENABLE_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + + for (i = 0; i < ARRAY_SIZE(sau_cfg); i++) { + SAU->RNR = i; + if (SAU->RBAR != (sau_cfg[i].RBAR & SAU_RBAR_BADDR_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + if (SAU->RLAR != ((sau_cfg[i].RLAR & SAU_RLAR_LADDR_Msk) | + (sau_cfg[i].nsc ? SAU_RLAR_NSC_Msk : 0U) | + SAU_RLAR_ENABLE_Msk)) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + if ((MXC_SPC->nscidau & MXC_F_SPC_NSCIDAU_CODE) != MXC_F_SPC_NSCIDAU_CODE) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +/*------------------- Memory configuration functions -------------------------*/ +FIH_RET_TYPE(int32_t) mpc_init_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + + for(int i = 0; i < ARRAY_SIZE(ns_mpc_config_arr); i++) { + ARM_DRIVER_MPC Driver_MPC = *(ns_mpc_config_arr[i].Driver_MPC); + uint32_t base = ns_mpc_config_arr[i].base; + uint32_t limit = ns_mpc_config_arr[i].limit; + + ret = Driver_MPC.Initialize(); + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.ConfigRegion(base, + limit, + ARM_MPC_ATTR_NONSECURE); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.EnableInterrupt(); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + ret = Driver_MPC.LockDown(); + if(ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + /* Add barriers to assure the MPC configuration is done before continue + * the execution. + */ + __DSB(); + __ISB(); + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_mpc_cfg(void) +{ + ARM_MPC_SEC_ATTR attr; + + for(int i = 0; i < ARRAY_SIZE(ns_mpc_config_arr); i++) { + ARM_DRIVER_MPC Driver_MPC = *(ns_mpc_config_arr[i].Driver_MPC); + uint32_t base = ns_mpc_config_arr[i].base; + uint32_t limit = ns_mpc_config_arr[i].limit; + + Driver_MPC.GetRegionConfig(base, limit, &attr); + + if (attr != ARM_MPC_ATTR_NONSECURE) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +/*---------------------- PPC configuration functions -------------------------*/ +FIH_RET_TYPE(int32_t) ppc_init_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + int i; + + ret = Driver_PPC.Initialize(); + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + + for (i = 0; i < NUM_SPC_PERIPH; i++) { + ret = ppc_configure_to_secure(i); + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + ret = ppc_en_secure_unpriv(i); + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + + /* + * Selectively open up and allow interrupts to peripherals in the NS space + * All peripherals will be privileged unless NSPC is configured otherwise + */ + for (i = 0; i < sizeof(ns_periph_arr); i++) { + ppc_configure_to_non_secure(ns_periph_arr[i]); + } + + /* Depend on the configuration set the target state of the interrupts to non-secure */ + for (i = 0; i < sizeof(nvic_set_ns); i++) { + if (NVIC_SetTargetState(nvic_set_ns[i]) != NVIC_NON_SECURE_CONFIG) { + FIH_RET(fih_int_encode(ARM_DRIVER_ERROR)); + } + } + + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int fih_verify_ppc_cfg(void) +{ + int32_t ret = ARM_DRIVER_OK; + + /* Check if non-secure peripherals are partitioned correctly */ + for (int i = 0; i < sizeof(ns_periph_arr); i++) { + if(!Driver_PPC.isPeriphSecure(i)) + ret = ARM_DRIVER_ERROR; + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + + /* Check if non-secure peripherals interrupts are partitioned correctly */ + for (int i = 0; i< sizeof(nvic_set_ns); i++) { + if(NVIC_GetTargetState(i) != NVIC_NON_SECURE_CONFIG) + ret = ARM_DRIVER_ERROR; + + if (ret != ARM_DRIVER_OK) { + FIH_RET(fih_int_encode(ret)); + } + } + FIH_RET(fih_int_encode(ARM_DRIVER_OK)); +} +#endif /* TFM_FIH_PROFILE_ON */ + +void ppc_configure_to_non_secure(uint16_t pos) +{ + /* Will default to privileged only once configured to non-secure */ + Driver_PPC.ConfigPeriph(pos, ARM_PPC_NONSECURE_ONLY, ARM_PPC_PRIV_ONLY); +} + +FIH_RET_TYPE(int32_t) ppc_configure_to_secure(uint16_t pos) +{ + /* Will default to privileged only once configured to secure */ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_ONLY))); +} + +FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(uint16_t pos) +{ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_AND_NONPRIV))); +} + +FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(uint16_t pos) +{ + FIH_RET(fih_int_encode(Driver_PPC.ConfigPeriph(pos, + ARM_PPC_SECURE_ONLY, + ARM_PPC_PRIV_ONLY))); +} + +void ppc_clear_irq(void) +{ + Driver_PPC.ClearInterrupt(); +} diff --git a/platform/ext/target/adi/max32657/target_cfg.h b/platform/ext/target/adi/max32657/target_cfg.h new file mode 100644 index 000000000..ed20a7c5e --- /dev/null +++ b/platform/ext/target/adi/max32657/target_cfg.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2017-2021 Arm Limited + * Portions Copyright (C) 2024-2025 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __TARGET_CFG_H__ +#define __TARGET_CFG_H__ + +#include "uart_stdout.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_defs.h" +#include "fih.h" + +#define TFM_DRIVER_STDIO Driver_USART0 +#define NS_DRIVER_STDIO Driver_USART0 + + +/** + * @brief Defines word offsets of the PPC + */ +enum ppc_bank_e { + PPC_SP_DO_NOT_CONFIGURE = -1, + PPC_SP_PPC0, +}; + +/** + * \brief Defines the bit offsets of within the SPC + */ +enum spc_periph_e { + SPC_GCR = 0, + SPC_SIR, + SPC_FCR, + SPC_WDT, + SPC_AES, + SPC_AESKEY, + SPC_CRC, + SPC_GPIO0, + SPC_TIMER0, + SPC_TIMER1, + SPC_TIMER2, + SPC_TIMER3, + SPC_TIMER4, + SPC_TIMER5, + SPC_I3C, + SPC_UART, + SPC_SPI, + SPC_TRNG, + SPC_BTLE_DBB, + SPC_BTLE_RFFE, + SPC_RSTZ, + SPC_BOOST, + SPC_BBSIR, + SPC_BBFCR, + SPC_RTC, + SPC_WUT0, + SPC_WUT1, + SPC_PWR, + SPC_MCR, + NUM_SPC_PERIPH +}; + +/** + * \brief Store the addresses of memory regions + */ +struct memory_region_limits { + uint32_t non_secure_code_start; + uint32_t non_secure_partition_base; + uint32_t non_secure_partition_limit; + uint32_t veneer_base; + uint32_t veneer_limit; +#ifdef BL2 + uint32_t secondary_partition_base; + uint32_t secondary_partition_limit; +#endif /* BL2 */ +}; + +/** + * \brief Holds the data necessary to do isolation for a specific peripheral. + */ +struct platform_data_t { + uint32_t periph_start; + uint32_t periph_limit; + enum ppc_bank_e periph_ppc_bank; + int16_t periph_ppc_loc; +}; + +/** + * \brief Configures the Memory Protection Controller. + * + * \return Returns error code. + */ +FIH_RET_TYPE(int32_t) mpc_init_cfg(void); + +/** + * \brief Configures the Peripheral Protection Controller. + */ +FIH_RET_TYPE(int32_t) ppc_init_cfg(void); + +/** + * \brief Restict access to peripheral to secure + */ +FIH_RET_TYPE(int32_t) ppc_configure_to_secure(uint16_t loc); + +/** + * \brief Allow non-secure access to peripheral + */ +void ppc_configure_to_non_secure(uint16_t loc); + +/** + * \brief Enable secure unprivileged access to peripheral + */ +FIH_RET_TYPE(int32_t) ppc_en_secure_unpriv(uint16_t pos); + +/** + * \brief Clear secure unprivileged access to peripheral + */ +FIH_RET_TYPE(int32_t) ppc_clr_secure_unpriv(uint16_t pos); + +/** + * \brief Clears PPC interrupt. + */ +void ppc_clear_irq(void); + +/** + * \brief Configures SAU and IDAU. + */ +FIH_RET_TYPE(int32_t) sau_and_idau_cfg(void); + +/** + * \brief Enables the fault handlers and sets priorities. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t enable_fault_handlers(void); + +/** + * \brief Configures the system reset request properties + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t system_reset_cfg(void); + +/** + * \brief Configures the system debug properties. + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +FIH_RET_TYPE(enum tfm_plat_err_t) init_debug(void); + +/** + * \brief Configures all external interrupts to target the + * NS state, apart for the ones associated to secure + * peripherals (plus MPC and PPC) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); + +/** + * \brief This function enable the interrupts associated + * to the secure peripherals (plus the isolation boundary violation + * interrupts) + * + * \return Returns values as specified by the \ref tfm_plat_err_t + */ +enum tfm_plat_err_t nvic_interrupt_enable(void); + +/* Function for FIH to verify that SAU & IDAU are correctly configured. */ +fih_int fih_verify_sau_and_idau_cfg(void); + +/* Function for FIH to verify that MPC is correctly configured. */ +fih_int fih_verify_mpc_cfg(void); + +/* Function for FIH to verify that PPC is correctly configured. */ +fih_int fih_verify_ppc_cfg(void); + +#endif /* __TARGET_CFG_H__ */ diff --git a/platform/ext/target/adi/max32657/tesa-toolkit.cmake b/platform/ext/target/adi/max32657/tesa-toolkit.cmake new file mode 100644 index 000000000..306c1e93f --- /dev/null +++ b/platform/ext/target/adi/max32657/tesa-toolkit.cmake @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------- +# Portions Copyright (C) 2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +if(BL1) + set(FETCHCONTENT_QUIET TRUE) + set(TESA_TOOLKIT_PATH "DOWNLOAD" CACHE PATH "Path to TESA-Toolkit (or DOWNLOAD to fetch automatically") + set(TESA_TOOLKIT_VERSION "v1.0.0" CACHE STRING "The version of TESA-Toolkit to use") + + # Fetch TESA-Toolkit repository to sign image and provision device + fetch_remote_library( + LIB_NAME tesa-toolkit + LIB_SOURCE_PATH_VAR TESA_TOOLKIT_PATH + FETCH_CONTENT_ARGS + GIT_REPOSITORY https://github.com/analogdevicesinc/tesa-toolkit + GIT_TAG ${TESA_TOOLKIT_VERSION} + GIT_PROGRESS TRUE + ) + + # Set TFM_BL2_SIGNING_KEY_PATH as test key if it is not set + if(NOT TFM_BL2_SIGNING_KEY_PATH) + set(TFM_BL2_SIGNING_KEY_PATH "${TESA_TOOLKIT_PATH}/devices/max32657/keys/bl1_dummy.pem") + endif() + + # + # If MAX32657 SecureBoot has been enabled MCUBoot need to be signed + # to it be validated and executed by BootROM. + # + add_custom_target(bl2_signed.bin + ALL + DEPENDS $/bl2.bin + DEPENDS ${TESA_TOOLKIT_PATH}/devices/max32657/scripts/sign/sign_app.py + COMMAND echo "----------------" + COMMAND ${Python3_EXECUTABLE} ${TESA_TOOLKIT_PATH}/devices/max32657/scripts/sign/sign_app.py + --input_file $/bl2.bin + --img_output_file $/bl2_signed.bin + --sign_key_file ${TFM_BL2_SIGNING_KEY_PATH} + COMMAND echo "----------------" + COMMAND echo "Converting bl2_signed.bin to bl2_signed.hex..." + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/../../../../../tools/modules/bin2hex.py + --offset=0x11000000 + $/bl2_signed.bin + $/bl2_signed.hex + COMMAND echo "Bin2Hex conversion done." + COMMAND echo "----------------" + ) +endif() diff --git a/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake b/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..40f15a3e0 --- /dev/null +++ b/platform/ext/target/adi/max32657/tests/psa_arch_tests_config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Paramters for PSA API tests + +set(PSA_API_TEST_TARGET max32657 CACHE STRING "PSA_API_TARGET name") diff --git a/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake new file mode 100644 index 000000000..04dd1d718 --- /dev/null +++ b/platform/ext/target/adi/max32657/tests/tfm_tests_config.cmake @@ -0,0 +1,12 @@ +#------------------------------------------------------------------------------- +# Copyright (C) 2024-2025 Analog Devices, Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +set(TEST_NS_SLIH_IRQ OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests") +set(TEST_NS_PS OFF CACHE BOOL "Whether to build NS PS tests") +set(TEST_NS_PLATFORM OFF ) +set(TEST_NS_IPC OFF ) +set(TEST_NS_FLIH_IRQ OFF ) diff --git a/platform/ext/target/adi/max32657/tfm_hal_isolation.c b/platform/ext/target/adi/max32657/tfm_hal_isolation.c new file mode 100644 index 000000000..cb17df829 --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_hal_isolation.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024 Cypress Semiconductor Corporation (an Infineon + * company) or an affiliate of Cypress Semiconductor Corporation. All rights + * reserved. + * Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#include +#include +#include "array.h" +#include "tfm_hal_device_header.h" +#include "Driver_Common.h" +#include "mmio_defs.h" +#include "region.h" +#include "target_cfg.h" +#include "tfm_hal_defs.h" +#include "tfm_hal_isolation.h" +#include "tfm_plat_defs.h" +#include "region_defs.h" +#include "tfm_peripherals_def.h" +#include "load/partition_defs.h" +#include "load/asset_defs.h" +#include "load/spm_load_api.h" + +#define PROT_BOUNDARY_VAL \ + ((1U << HANDLE_ATTR_PRIV_POS) & HANDLE_ATTR_PRIV_MASK) + +enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( + uintptr_t *p_spm_boundary) +{ + /* Set up isolation boundaries between SPE and NSPE */ + sau_and_idau_cfg(); + if (mpc_init_cfg() != ARM_DRIVER_OK) { + return TFM_HAL_ERROR_GENERIC; + } + + if (ppc_init_cfg() != ARM_DRIVER_OK) { + return TFM_HAL_ERROR_GENERIC; + } + + *p_spm_boundary = (uintptr_t)PROT_BOUNDARY_VAL; + + return TFM_HAL_SUCCESS; +} + +#ifdef TFM_FIH_PROFILE_ON +fih_int tfm_hal_verify_static_boundaries(void) +{ + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} +#endif + +enum tfm_hal_status_t tfm_hal_bind_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t *p_boundary) +{ + uint32_t i, j; + bool privileged; + bool ns_agent; + uint32_t partition_attrs = 0; + const struct asset_desc_t *p_asset; + struct platform_data_t *plat_data_ptr; + + if (!p_ldinf || !p_boundary) { + return TFM_HAL_ERROR_GENERIC; + } + +#if TFM_ISOLATION_LEVEL == 1 + privileged = true; +#else + privileged = IS_PSA_ROT(p_ldinf); +#endif + + ns_agent = IS_NS_AGENT(p_ldinf); + p_asset = LOAD_INFO_ASSET(p_ldinf); + + /* + * Validate if the named MMIO of partition is allowed by the platform. + * Otherwise, skip validation. + * + * NOTE: Need to add validation of numbered MMIO if platform requires. + */ + for (i = 0; i < p_ldinf->nassets; i++) { + if (!(p_asset[i].attr & ASSET_ATTR_NAMED_MMIO)) { + continue; + } + for (j = 0; j < ARRAY_SIZE(partition_named_mmio_list); j++) { + if (p_asset[i].dev.dev_ref == partition_named_mmio_list[j]) { + break; + } + } + + if (j == ARRAY_SIZE(partition_named_mmio_list)) { + /* The MMIO asset is not in the allowed list of platform. */ + return TFM_HAL_ERROR_GENERIC; + } + /* Assume PPC & MPC settings are required even under level 1 */ + plat_data_ptr = REFERENCE_TO_PTR(p_asset[i].dev.dev_ref, + struct platform_data_t *); + + if (plat_data_ptr->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) { + ppc_configure_to_secure(plat_data_ptr->periph_ppc_loc); + if (privileged) { + ppc_clr_secure_unpriv(plat_data_ptr->periph_ppc_loc); + } else { + ppc_en_secure_unpriv(plat_data_ptr->periph_ppc_loc); + } + } + } + + partition_attrs = ((uint32_t)privileged << HANDLE_ATTR_PRIV_POS) & + HANDLE_ATTR_PRIV_MASK; + partition_attrs |= ((uint32_t)ns_agent << HANDLE_ATTR_NS_POS) & + HANDLE_ATTR_NS_MASK; + *p_boundary = (uintptr_t)partition_attrs; + + return TFM_HAL_SUCCESS; +} + +#ifdef TFM_FIH_PROFILE_ON +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_activate_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t boundary) +{ + CONTROL_Type ctrl; + uint32_t local_handle = (uint32_t)boundary; + bool privileged = !!(local_handle & HANDLE_ATTR_PRIV_MASK); + + /* Privileged level is required to be set always */ + ctrl.w = __get_CONTROL(); + ctrl.b.nPRIV = privileged ? 0 : 1; + __set_CONTROL(ctrl.w); + + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} + +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_memory_check(uintptr_t boundary, uintptr_t base, + size_t size, uint32_t access_type) +{ + int flags = 0; + + /* If size is zero, this indicates an empty buffer and base is ignored */ + if (size == 0) { + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); + } + + if (!base) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_INVALID_INPUT)); + } + + if ((access_type & TFM_HAL_ACCESS_READWRITE) == TFM_HAL_ACCESS_READWRITE) { + flags |= CMSE_MPU_READWRITE; + } else if (access_type & TFM_HAL_ACCESS_READABLE) { + flags |= CMSE_MPU_READ; + } else { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_INVALID_INPUT)); + } + + if (!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK)) { + flags |= CMSE_MPU_UNPRIV; + } + + if ((uint32_t)boundary & HANDLE_ATTR_NS_MASK) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV == 1) { + flags |= CMSE_MPU_UNPRIV; + } else { + flags &= ~CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + if (cmse_check_address_range((void *)base, size, flags) != NULL) { + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); + } else { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_MEM_FAULT)); + } +} + +FIH_RET_TYPE(bool) tfm_hal_boundary_need_switch(uintptr_t boundary_from, + uintptr_t boundary_to) +{ + if (boundary_from == boundary_to) { + FIH_RET(fih_int_encode(false)); + } + + if (((uint32_t)boundary_from & HANDLE_ATTR_PRIV_MASK) && + ((uint32_t)boundary_to & HANDLE_ATTR_PRIV_MASK)) { + FIH_RET(fih_int_encode(false)); + } + FIH_RET(fih_int_encode(true)); +} + +#else /* TFM_FIH_PROFILE_ON */ + +enum tfm_hal_status_t tfm_hal_memory_check(uintptr_t boundary, uintptr_t base, + size_t size, uint32_t access_type) +{ + int flags = 0; + + /* If size is zero, this indicates an empty buffer and base is ignored */ + if (size == 0) { + return TFM_HAL_SUCCESS; + } + + if (!base) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if ((access_type & TFM_HAL_ACCESS_READWRITE) == TFM_HAL_ACCESS_READWRITE) { + flags |= CMSE_MPU_READWRITE; + } else if (access_type & TFM_HAL_ACCESS_READABLE) { + flags |= CMSE_MPU_READ; + } else { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK)) { + flags |= CMSE_MPU_UNPRIV; + } + + if ((uint32_t)boundary & HANDLE_ATTR_NS_MASK) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV == 1) { + flags |= CMSE_MPU_UNPRIV; + } else { + flags &= ~CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + if (cmse_check_address_range((void *)base, size, flags) != NULL) { + return TFM_HAL_SUCCESS; + } else { + return TFM_HAL_ERROR_MEM_FAULT; + } +} + +enum tfm_hal_status_t tfm_hal_activate_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t boundary) +{ + CONTROL_Type ctrl; + uint32_t local_handle = (uint32_t)boundary; + bool privileged = !!(local_handle & HANDLE_ATTR_PRIV_MASK); + + /* Privileged level is required to be set always */ + ctrl.w = __get_CONTROL(); + ctrl.b.nPRIV = privileged ? 0 : 1; + __set_CONTROL(ctrl.w); + + return TFM_HAL_SUCCESS; +} + +bool tfm_hal_boundary_need_switch(uintptr_t boundary_from, + uintptr_t boundary_to) +{ + if (boundary_from == boundary_to) { + return false; + } + + if (((uint32_t)boundary_from & HANDLE_ATTR_PRIV_MASK) && + ((uint32_t)boundary_to & HANDLE_ATTR_PRIV_MASK)) { + return false; + } + return true; +} + +#endif /* TFM_FIH_PROFILE_ON */ diff --git a/platform/ext/target/adi/max32657/tfm_hal_platform.c b/platform/ext/target/adi/max32657/tfm_hal_platform.c new file mode 100644 index 000000000..98fd0944f --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_hal_platform.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "target_cfg.h" +#include "tfm_hal_platform.h" +#include "tfm_plat_defs.h" + +extern const struct memory_region_limits memory_regions; + +FIH_RET_TYPE(enum tfm_hal_status_t) tfm_hal_platform_init(void) +{ + enum tfm_plat_err_t plat_err = TFM_PLAT_ERR_SYSTEM_ERR; + + plat_err = system_reset_cfg(); + if (plat_err != TFM_PLAT_ERR_SUCCESS) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); + } + + __enable_irq(); +#if defined(TFM_SPM_LOG_RAW_ENABLED) && \ + !defined(TFM_NS_REG_TEST) && \ + !defined(TFM_S_REG_TEST) + stdio_init(); +#endif + + plat_err = nvic_interrupt_target_state_cfg(); + if (plat_err != TFM_PLAT_ERR_SUCCESS) { + FIH_RET(fih_int_encode(TFM_HAL_ERROR_GENERIC)); + } + + FIH_RET(fih_int_encode(TFM_HAL_SUCCESS)); +} + +uint32_t tfm_hal_get_ns_VTOR(void) +{ + return memory_regions.non_secure_code_start; +} + +uint32_t tfm_hal_get_ns_MSP(void) +{ + return *((uint32_t *)memory_regions.non_secure_code_start); +} + +uint32_t tfm_hal_get_ns_entry_point(void) +{ + return *((uint32_t *)(memory_regions.non_secure_code_start + 4)); +} diff --git a/platform/ext/target/adi/max32657/tfm_peripherals_def.h b/platform/ext/target/adi/max32657/tfm_peripherals_def.h new file mode 100644 index 000000000..91b323f5d --- /dev/null +++ b/platform/ext/target/adi/max32657/tfm_peripherals_def.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. + * Copyright (C) 2024-2025 Analog Devices, Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#include "max32657.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * tfm_peripheral_std_uart is defined for regression test partition + */ + +struct platform_data_t; + +extern struct platform_data_t tfm_peripheral_std_uart; + +#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/platform/ext/target/arm/corstone1000/ci_regression_tests/s_io_storage_test.c b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_io_storage_test.c index f8be384a7..e5a9ab3bc 100644 --- a/platform/ext/target/arm/corstone1000/ci_regression_tests/s_io_storage_test.c +++ b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_io_storage_test.c @@ -14,7 +14,9 @@ #include "io_flash.h" #include "tfm_sp_log.h" +#ifndef ARRAY_LENGTH #define ARRAY_LENGTH(array) (sizeof(array) / sizeof(*(array))) +#endif extern ARM_DRIVER_FLASH Driver_FLASH0; extern ARM_DRIVER_FLASH Driver_TEST_FLASH; diff --git a/platform/ext/target/arm/corstone1000/config_tfm_target.h b/platform/ext/target/arm/corstone1000/config_tfm_target.h index 2c7341afd..bcd6de6fa 100644 --- a/platform/ext/target/arm/corstone1000/config_tfm_target.h +++ b/platform/ext/target/arm/corstone1000/config_tfm_target.h @@ -11,6 +11,9 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + /* Size of output buffer in platform service. */ #define PLATFORM_SERVICE_OUTPUT_BUFFER_SIZE 256 diff --git a/platform/ext/target/arm/corstone1000/partition/region_defs.h b/platform/ext/target/arm/corstone1000/partition/region_defs.h index a80b07737..0ef52720f 100644 --- a/platform/ext/target/arm/corstone1000/partition/region_defs.h +++ b/platform/ext/target/arm/corstone1000/partition/region_defs.h @@ -118,6 +118,9 @@ #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c b/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c index 39b19c535..498f14ed2 100644 --- a/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c +++ b/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2023, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon * company) or an affiliate of Cypress Semiconductor Corporation. All rights * reserved. @@ -99,6 +99,26 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( return ret; } + /* Set the RAM attributes. It is needed because the first region overlaps the whole + * SRAM and it has to be overridden. + * The RAM_MPU_REGION_BLOCK_1_SIZE and RAM_MPU_REGION_BLOCK_2_SIZE are calculated manually + * and added to the platform_region_defs compile definitions. + */ + base = S_DATA_START; + limit = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE; + ret = configure_mpu(rnr++, base, limit, + XN_EXEC_NOT_OK, AP_RW_PRIV_ONLY); + if (ret != TFM_HAL_SUCCESS) { + return ret; + } + + base = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE; + limit = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE + RAM_MPU_REGION_BLOCK_2_SIZE; + ret = configure_mpu(rnr++, base, limit, + XN_EXEC_NOT_OK, AP_RW_PRIV_ONLY); + if (ret != TFM_HAL_SUCCESS) { + return ret; + } /* RW, ZI and stack as one region */ base = (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_START, $$Base); @@ -133,27 +153,6 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( #endif - /* Set the RAM attributes. It is needed because the first region overlaps the whole - * SRAM and it has to be overridden. - * The RAM_MPU_REGION_BLOCK_1_SIZE and RAM_MPU_REGION_BLOCK_2_SIZE are calculated manually - * and added to the platform_region_defs compile definitions. - */ - base = S_DATA_START; - limit = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE; - ret = configure_mpu(rnr++, base, limit, - XN_EXEC_NOT_OK, AP_RW_PRIV_UNPRIV); - if (ret != TFM_HAL_SUCCESS) { - return ret; - } - - base = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE; - limit = S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE + RAM_MPU_REGION_BLOCK_2_SIZE; - ret = configure_mpu(rnr++, base, limit, - XN_EXEC_NOT_OK, AP_RW_PRIV_UNPRIV); - if (ret != TFM_HAL_SUCCESS) { - return ret; - } - arm_mpu_enable(); #endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ diff --git a/platform/ext/target/arm/mps2/an519/partition/region_defs.h b/platform/ext/target/arm/mps2/an519/partition/region_defs.h index e5fa8641d..2aa4b99ef 100644 --- a/platform/ext/target/arm/mps2/an519/partition/region_defs.h +++ b/platform/ext/target/arm/mps2/an519/partition/region_defs.h @@ -145,5 +145,8 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/arm/mps2/an521/partition/region_defs.h b/platform/ext/target/arm/mps2/an521/partition/region_defs.h index 423d11f17..f2653b505 100644 --- a/platform/ext/target/arm/mps2/an521/partition/region_defs.h +++ b/platform/ext/target/arm/mps2/an521/partition/region_defs.h @@ -168,5 +168,8 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/arm/mps3/an524/CMakeLists.txt b/platform/ext/target/arm/mps3/an524/CMakeLists.txt index 9e0f1bae8..dc47bd70e 100644 --- a/platform/ext/target/arm/mps3/an524/CMakeLists.txt +++ b/platform/ext/target/arm/mps3/an524/CMakeLists.txt @@ -138,10 +138,11 @@ target_compile_definitions(platform_region_defs PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} + $<$:MCUBOOT_BUILTIN_KEY> ) if(NOT PLATFORM_DEFAULT_PROVISIONING) - add_subdirectory(${PLATFORM_DIR}/ext/target/arm/mps3/common/provisioning provisioning) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) endif() #========================= Files for building NS side platform ================# diff --git a/platform/ext/target/arm/mps3/an524/partition/region_defs.h b/platform/ext/target/arm/mps3/an524/partition/region_defs.h index 884726f4f..c99bcc392 100644 --- a/platform/ext/target/arm/mps3/an524/partition/region_defs.h +++ b/platform/ext/target/arm/mps3/an524/partition/region_defs.h @@ -140,6 +140,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_DATA_START + BL2_DATA_SIZE) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) diff --git a/platform/ext/target/arm/mps3/corstone300/an547/check_config.cmake b/platform/ext/target/arm/mps3/corstone300/an547/check_config.cmake new file mode 100644 index 000000000..7f5a3dd97 --- /dev/null +++ b/platform/ext/target/arm/mps3/corstone300/an547/check_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +include(${CORSTONE300_COMMON_DIR}/check_config.cmake) diff --git a/platform/ext/target/arm/mps3/corstone300/an552/check_config.cmake b/platform/ext/target/arm/mps3/corstone300/an552/check_config.cmake new file mode 100644 index 000000000..7f5a3dd97 --- /dev/null +++ b/platform/ext/target/arm/mps3/corstone300/an552/check_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +include(${CORSTONE300_COMMON_DIR}/check_config.cmake) diff --git a/platform/ext/target/arm/mps3/corstone300/common/check_config.cmake b/platform/ext/target/arm/mps3/corstone300/common/check_config.cmake index c909512c0..829c94472 100644 --- a/platform/ext/target/arm/mps3/corstone300/common/check_config.cmake +++ b/platform/ext/target/arm/mps3/corstone300/common/check_config.cmake @@ -1,5 +1,5 @@ #------------------------------------------------------------------------------- -# Copyright (c) 2022, Arm Limited. All rights reserved. +# Copyright (c) 2022-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -7,3 +7,4 @@ ## test incompatible compiler tfm_invalid_config(CMAKE_C_COMPILER MATCHES "armclang" AND CMAKE_C_COMPILER_VERSION VERSION_LESS 6.14.0) +tfm_invalid_config(NOT ETHOSU_ARCH MATCHES "U55" AND NOT ETHOSU_ARCH MATCHES "U65") diff --git a/platform/ext/target/arm/mps3/corstone300/common/common.cmake b/platform/ext/target/arm/mps3/corstone300/common/common.cmake index 0ea802d21..27162a1ab 100644 --- a/platform/ext/target/arm/mps3/corstone300/common/common.cmake +++ b/platform/ext/target/arm/mps3/corstone300/common/common.cmake @@ -236,10 +236,11 @@ target_compile_definitions(platform_region_defs PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} + $<$:MCUBOOT_BUILTIN_KEY> ) if(NOT PLATFORM_DEFAULT_PROVISIONING) -add_subdirectory(${PLATFORM_DIR}/ext/target/arm/mps3/common/provisioning provisioning) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) endif() #========================= Files for building NS side platform ================# diff --git a/platform/ext/target/arm/mps3/corstone300/common/config.cmake b/platform/ext/target/arm/mps3/corstone300/common/config.cmake index c4d79eb7a..907e7afec 100644 --- a/platform/ext/target/arm/mps3/corstone300/common/config.cmake +++ b/platform/ext/target/arm/mps3/corstone300/common/config.cmake @@ -29,6 +29,6 @@ set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_MULTI_CORE_TOPOLOGY OFF) # Ethos-U NPU configurations -set(ETHOSU_ARCH "U55") -set(ETHOS_DRIVER_PATH "DOWNLOAD" CACHE PATH "Path to Ethos-U Core Driver (or DOWNLOAD to fetch automatically") -set(ETHOSU_LOG_SEVERITY "-1" CACHE STRING "Ethos-U Core Driver log severity") +set(ETHOSU_ARCH "U55" CACHE STRING "Ethos-U NPU type [U55,U65]") +set(ETHOS_DRIVER_PATH "DOWNLOAD" CACHE PATH "Path to Ethos-U Core Driver (or DOWNLOAD to fetch automatically") +set(ETHOSU_LOG_SEVERITY "-1" CACHE STRING "Ethos-U Core Driver log severity") diff --git a/platform/ext/target/arm/mps3/corstone300/common/partition/region_defs.h b/platform/ext/target/arm/mps3/corstone300/common/partition/region_defs.h index 643e5bd3d..27946fbc2 100644 --- a/platform/ext/target/arm/mps3/corstone300/common/partition/region_defs.h +++ b/platform/ext/target/arm/mps3/corstone300/common/partition/region_defs.h @@ -153,6 +153,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_CODE_START + BL2_CODE_SIZE) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) diff --git a/platform/ext/target/arm/mps3/corstone300/common/target_cfg.c b/platform/ext/target/arm/mps3/corstone300/common/target_cfg.c index 41481eb8d..591f5d21c 100644 --- a/platform/ext/target/arm/mps3/corstone300/common/target_cfg.c +++ b/platform/ext/target/arm/mps3/corstone300/common/target_cfg.c @@ -803,7 +803,7 @@ enum tfm_plat_err_t ppc_init_cfg(void) err |= Driver_PPC_SSE300_PERIPH_EXP3.Initialize(); /* initialize and config NPU */ - err |= ethosu_dev_init(ÐOS_S); + err |= !ethosu_dev_init(ÐOS_S, ETHOS_S.reg, ETHOS_S.secure, ETHOS_S.privileged); /* * Configure the response to a security violation as a diff --git a/platform/ext/target/arm/mps3/corstone300/fvp/check_config.cmake b/platform/ext/target/arm/mps3/corstone300/fvp/check_config.cmake new file mode 100644 index 000000000..7f5a3dd97 --- /dev/null +++ b/platform/ext/target/arm/mps3/corstone300/fvp/check_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +include(${CORSTONE300_COMMON_DIR}/check_config.cmake) diff --git a/platform/ext/target/arm/mps3/corstone310/common/check_config.cmake b/platform/ext/target/arm/mps3/corstone310/common/check_config.cmake index 33f91b4c2..c8cce8ca3 100644 --- a/platform/ext/target/arm/mps3/corstone310/common/check_config.cmake +++ b/platform/ext/target/arm/mps3/corstone310/common/check_config.cmake @@ -1,5 +1,5 @@ #------------------------------------------------------------------------------- -# Copyright (c) 2022, Arm Limited. All rights reserved. +# Copyright (c) 2022-2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -7,3 +7,4 @@ ## test incompatible compiler tfm_invalid_config(CMAKE_C_COMPILER MATCHES "armclang" AND CMAKE_C_COMPILER_VERSION VERSION_LESS 6.18.0) +tfm_invalid_config(NOT ETHOSU_ARCH MATCHES "U55" AND NOT ETHOSU_ARCH MATCHES "U65") diff --git a/platform/ext/target/arm/mps3/corstone310/common/common.cmake b/platform/ext/target/arm/mps3/corstone310/common/common.cmake index 6dc9dfb97..05a89315a 100644 --- a/platform/ext/target/arm/mps3/corstone310/common/common.cmake +++ b/platform/ext/target/arm/mps3/corstone310/common/common.cmake @@ -236,10 +236,11 @@ target_compile_definitions(platform_region_defs PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} + $<$:MCUBOOT_BUILTIN_KEY> ) if(NOT PLATFORM_DEFAULT_PROVISIONING) -add_subdirectory(${PLATFORM_DIR}/ext/target/arm/mps3/common/provisioning provisioning) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) endif() #========================= Files for building NS side platform ================# diff --git a/platform/ext/target/arm/mps3/corstone310/common/config.cmake b/platform/ext/target/arm/mps3/corstone310/common/config.cmake index 07b7c8655..bda3e7a12 100644 --- a/platform/ext/target/arm/mps3/corstone310/common/config.cmake +++ b/platform/ext/target/arm/mps3/corstone310/common/config.cmake @@ -28,6 +28,6 @@ set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_MULTI_CORE_TOPOLOGY OFF) # Ethos-U NPU configurations -set(ETHOSU_ARCH "U55") -set(ETHOS_DRIVER_PATH "DOWNLOAD" CACHE PATH "Path to Ethos-U Core Driver (or DOWNLOAD to fetch automatically") -set(ETHOSU_LOG_SEVERITY "-1" CACHE STRING "Ethos-U Core Driver log severity") +set(ETHOSU_ARCH "U55" CACHE STRING "Ethos-U NPU type [U55,U65]") +set(ETHOS_DRIVER_PATH "DOWNLOAD" CACHE PATH "Path to Ethos-U Core Driver (or DOWNLOAD to fetch automatically") +set(ETHOSU_LOG_SEVERITY "-1" CACHE STRING "Ethos-U Core Driver log severity") diff --git a/platform/ext/target/arm/mps3/corstone310/common/partition/region_defs.h b/platform/ext/target/arm/mps3/corstone310/common/partition/region_defs.h index 689076ab8..dc81223a5 100644 --- a/platform/ext/target/arm/mps3/corstone310/common/partition/region_defs.h +++ b/platform/ext/target/arm/mps3/corstone310/common/partition/region_defs.h @@ -153,6 +153,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_CODE_START + BL2_CODE_SIZE) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) diff --git a/platform/ext/target/arm/mps3/corstone310/common/target_cfg.c b/platform/ext/target/arm/mps3/corstone310/common/target_cfg.c index 285daf004..00465d464 100644 --- a/platform/ext/target/arm/mps3/corstone310/common/target_cfg.c +++ b/platform/ext/target/arm/mps3/corstone310/common/target_cfg.c @@ -782,7 +782,7 @@ enum tfm_plat_err_t ppc_init_cfg(void) err |= Driver_PERIPH_EXP3_PPC_CORSTONE310.Initialize(); /* initialize and config NPU */ - err |= ethosu_dev_init(&NPU0_S); + err |= !ethosu_dev_init(&NPU0_S, NPU0_S.reg, NPU0_S.secure, NPU0_S.privileged); /* * Configure the response to a security violation as a diff --git a/platform/ext/target/arm/mps4/corstone315/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/mps4/corstone315/bl1/boot_hal_bl1_1.c index ee6cb9b3c..390e6e95e 100644 --- a/platform/ext/target/arm/mps4/corstone315/bl1/boot_hal_bl1_1.c +++ b/platform/ext/target/arm/mps4/corstone315/bl1/boot_hal_bl1_1.c @@ -75,7 +75,7 @@ int32_t boot_platform_init(void) } /* Clear boot data area */ - memset((void*)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void*)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); return 0; } diff --git a/platform/ext/target/arm/mps4/corstone315/check_config.cmake b/platform/ext/target/arm/mps4/corstone315/check_config.cmake index e372411be..b3d2c0bbe 100644 --- a/platform/ext/target/arm/mps4/corstone315/check_config.cmake +++ b/platform/ext/target/arm/mps4/corstone315/check_config.cmake @@ -1,9 +1,9 @@ #------------------------------------------------------------------------------- -# Copyright (c) 2024, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors # #------------------------------------------------------------------------------- -## test incompatible compiler -tfm_invalid_config(CMAKE_C_COMPILER MATCHES "armclang" AND CMAKE_C_COMPILER_VERSION VERSION_LESS 6.18.0) +include(${MPS4_COMMON_DIR}/check_config.cmake) +tfm_invalid_config(NOT ETHOSU_ARCH MATCHES "U65") diff --git a/platform/ext/target/arm/mps4/corstone315/config.cmake b/platform/ext/target/arm/mps4/corstone315/config.cmake index 21e72277b..7c11aa1be 100644 --- a/platform/ext/target/arm/mps4/corstone315/config.cmake +++ b/platform/ext/target/arm/mps4/corstone315/config.cmake @@ -26,7 +26,7 @@ set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_MULTI_CORE_TOPOLOGY OFF) # Ethos-U NPU configurations -set(ETHOSU_ARCH "U65") +set(ETHOSU_ARCH "U65" CACHE STRING "Ethos-U NPU type [U65]") set(ETHOS_DRIVER_PATH "DOWNLOAD" CACHE PATH "Path to Ethos-U Core Driver (or DOWNLOAD to fetch automatically") set(ETHOSU_LOG_SEVERITY "-1" CACHE STRING "Ethos-U Core Driver log severity") diff --git a/platform/ext/target/arm/mps4/corstone315/partition/region_defs.h b/platform/ext/target/arm/mps4/corstone315/partition/region_defs.h index 7ccfe6886..293c62641 100644 --- a/platform/ext/target/arm/mps4/corstone315/partition/region_defs.h +++ b/platform/ext/target/arm/mps4/corstone315/partition/region_defs.h @@ -180,6 +180,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_IMAGE_START + BL2_CODE_SIZE) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) diff --git a/platform/ext/target/arm/mps4/corstone315/target_cfg.c b/platform/ext/target/arm/mps4/corstone315/target_cfg.c index a8a631fb5..c774f056f 100644 --- a/platform/ext/target/arm/mps4/corstone315/target_cfg.c +++ b/platform/ext/target/arm/mps4/corstone315/target_cfg.c @@ -785,7 +785,7 @@ enum tfm_plat_err_t ppc_init_cfg(void) err |= Driver_PERIPH_EXP3_PPC_CORSTONE315.Initialize(); /* initialize and config NPU */ - err |= ethosu_dev_init(&NPU0_S); + err |= !ethosu_dev_init(&NPU0_S, NPU0_S.reg, NPU0_S.secure, NPU0_S.privileged); /* * Configure the response to a security violation as a diff --git a/platform/ext/target/arm/musca_b1/config_tfm_target.h b/platform/ext/target/arm/musca_b1/config_tfm_target.h index 599db967d..f34850c96 100644 --- a/platform/ext/target/arm/musca_b1/config_tfm_target.h +++ b/platform/ext/target/arm/musca_b1/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,4 +11,7 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/arm/musca_b1/partition/region_defs.h b/platform/ext/target/arm/musca_b1/partition/region_defs.h index 238f2dbc4..97dceb8a3 100644 --- a/platform/ext/target/arm/musca_b1/partition/region_defs.h +++ b/platform/ext/target/arm/musca_b1/partition/region_defs.h @@ -173,5 +173,8 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/arm/musca_s1/config_tfm_target.h b/platform/ext/target/arm/musca_s1/config_tfm_target.h index 0d9144840..d96a05174 100644 --- a/platform/ext/target/arm/musca_s1/config_tfm_target.h +++ b/platform/ext/target/arm/musca_s1/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #ifdef PSA_API_TEST_CRYPTO #define CRYPTO_STACK_SIZE 0x2500 #endif diff --git a/platform/ext/target/arm/musca_s1/partition/region_defs.h b/platform/ext/target/arm/musca_s1/partition/region_defs.h index 0d2e6d2f5..7ba849281 100644 --- a/platform/ext/target/arm/musca_s1/partition/region_defs.h +++ b/platform/ext/target/arm/musca_s1/partition/region_defs.h @@ -148,5 +148,8 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/arm/rse/common/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/rse/common/bl1/boot_hal_bl1_1.c index 56bd27b84..82504bd7c 100644 --- a/platform/ext/target/arm/rse/common/bl1/boot_hal_bl1_1.c +++ b/platform/ext/target/arm/rse/common/bl1/boot_hal_bl1_1.c @@ -143,7 +143,7 @@ int32_t boot_platform_init(void) } /* Clear boot data area */ - memset((void*)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + memset((void*)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); return 0; } diff --git a/platform/ext/target/arm/rse/common/libraries/sds.c b/platform/ext/target/arm/rse/common/libraries/sds.c index 9e7330463..5e34c7e8a 100644 --- a/platform/ext/target/arm/rse/common/libraries/sds.c +++ b/platform/ext/target/arm/rse/common/libraries/sds.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "host_base_address.h" #include "rse_comms_atu.h" @@ -248,7 +249,7 @@ static enum tfm_plat_err_t sds_region_unmap(uint8_t atu_region) static void sds_region_init(void) { - SPM_ASSERT(PLAT_RSE_AP_SDS_SIZE > MIN_REGION_SIZE); + assert(PLAT_RSE_AP_SDS_SIZE > MIN_REGION_SIZE); struct region_descriptor *region_desc = (struct region_descriptor *)region_config.mapped_addr; diff --git a/platform/ext/target/arm/rse/common/partition/region_defs.h b/platform/ext/target/arm/rse/common/partition/region_defs.h index 2822e1007..f708e5b9c 100644 --- a/platform/ext/target/arm/rse/common/partition/region_defs.h +++ b/platform/ext/target/arm/rse/common/partition/region_defs.h @@ -237,6 +237,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x600) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START VM0_BASE_S #define PROVISIONING_BUNDLE_VALUES_START (BL1_2_DATA_START) diff --git a/platform/ext/target/arm/rse/kronos/config_tfm_target.h b/platform/ext/target/arm/rse/kronos/config_tfm_target.h index 197cad2cd..5ce14fa7e 100644 --- a/platform/ext/target/arm/rse/kronos/config_tfm_target.h +++ b/platform/ext/target/arm/rse/kronos/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,6 +12,9 @@ #undef CRYPTO_NV_SEED #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #define NS_AGENT_MAILBOX_STACK_SIZE 0xC00 /* Run the scheduler after handling a secure interrupt if the NSPE was pre-empted */ diff --git a/platform/ext/target/arm/rse/rdfremont/bl2/boot_hal_bl2.c b/platform/ext/target/arm/rse/rdfremont/bl2/boot_hal_bl2.c index 25ac85b9e..629169415 100644 --- a/platform/ext/target/arm/rse/rdfremont/bl2/boot_hal_bl2.c +++ b/platform/ext/target/arm/rse/rdfremont/bl2/boot_hal_bl2.c @@ -61,19 +61,19 @@ static int boot_add_data_to_shared_area(uint8_t major_type, return -1; } - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; /* Check whether the shared area needs to be initialized. */ if ((boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC) || - (boot_data->header.tlv_tot_len > BOOT_TFM_SHARED_DATA_SIZE)) { - memset((void *)BOOT_TFM_SHARED_DATA_BASE, 0, BOOT_TFM_SHARED_DATA_SIZE); + (boot_data->header.tlv_tot_len > SHARED_BOOT_MEASUREMENT_SIZE)) { + memset((void *)SHARED_BOOT_MEASUREMENT_BASE, 0, SHARED_BOOT_MEASUREMENT_SIZE); boot_data->header.tlv_magic = SHARED_DATA_TLV_INFO_MAGIC; boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE; } /* Get the boundaries of TLV section. */ - tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len; - offset = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE; + tlv_end = SHARED_BOOT_MEASUREMENT_BASE + boot_data->header.tlv_tot_len; + offset = SHARED_BOOT_MEASUREMENT_BASE + SHARED_DATA_HEADER_SIZE; /* * Check whether TLV entry is already added. Iterates over the TLV section @@ -100,7 +100,7 @@ static int boot_add_data_to_shared_area(uint8_t major_type, (UINT16_MAX - boot_data->header.tlv_tot_len)) { return -1; } else if ((SHARED_DATA_ENTRY_SIZE(size) + boot_data->header.tlv_tot_len) > - BOOT_TFM_SHARED_DATA_SIZE) { + SHARED_BOOT_MEASUREMENT_SIZE) { return -1; } diff --git a/platform/ext/target/arm/rse/rdfremont/config_tfm_target.h b/platform/ext/target/arm/rse/rdfremont/config_tfm_target.h index 60a45806a..f998c280a 100644 --- a/platform/ext/target/arm/rse/rdfremont/config_tfm_target.h +++ b/platform/ext/target/arm/rse/rdfremont/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, Arm Limited. All rights reserved. + * Copyright (c) 2023-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + /* Set the initial attestation token profile */ #undef ATTEST_TOKEN_PROFILE_PSA_IOT_1 #undef ATTEST_TOKEN_PROFILE_PSA_2_0_0 diff --git a/platform/ext/target/arm/rse/tc/config_tfm_target.h b/platform/ext/target/arm/rse/tc/config_tfm_target.h index c43652954..62457fbb9 100644 --- a/platform/ext/target/arm/rse/tc/config_tfm_target.h +++ b/platform/ext/target/arm/rse/tc/config_tfm_target.h @@ -11,6 +11,9 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + /* Set the initial attestation token profile */ #undef ATTEST_TOKEN_PROFILE_PSA_IOT_1 #undef ATTEST_TOKEN_PROFILE_PSA_2_0_0 diff --git a/platform/ext/target/armchina/mps3/alcor/common/partition/region_defs.h b/platform/ext/target/armchina/mps3/alcor/common/partition/region_defs.h index 772c3b6ec..2101c2f33 100644 --- a/platform/ext/target/armchina/mps3/alcor/common/partition/region_defs.h +++ b/platform/ext/target/armchina/mps3/alcor/common/partition/region_defs.h @@ -145,6 +145,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #define PROVISIONING_BUNDLE_CODE_START (BL2_CODE_START + BL2_CODE_SIZE) #define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) diff --git a/platform/ext/target/cypress/psoc64/partition/region_defs.h b/platform/ext/target/cypress/psoc64/partition/region_defs.h index cef72f586..baa0e16d6 100644 --- a/platform/ext/target/cypress/psoc64/partition/region_defs.h +++ b/platform/ext/target/cypress/psoc64/partition/region_defs.h @@ -186,5 +186,7 @@ */ #define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET)) #define BOOT_TFM_SHARED_DATA_SIZE 0x400 +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/cypress/psoc64/tfm_hal_platform.c b/platform/ext/target/cypress/psoc64/tfm_hal_platform.c index f98167dd1..d283dc24d 100644 --- a/platform/ext/target/cypress/psoc64/tfm_hal_platform.c +++ b/platform/ext/target/cypress/psoc64/tfm_hal_platform.c @@ -24,7 +24,7 @@ extern const struct memory_region_limits memory_regions; /* FIXME: * Instead of TFM-customized mcuboot, at this moment psoc64 uses * Cypress version of it - CypressBootloader (CYBL). CYBL doesn't - * populate BOOT_TFM_SHARED_DATA. + * populate SHARED_BOOT_MEASUREMENT. * As a temp workaround, mock mcuboot shared data to pass * initialization checks. */ @@ -46,7 +46,7 @@ void mock_tfm_shared_data(void) 0x82482A94, 0x23489DFA, 0xA966B1EF, 0x4A6E6AEF, 0x19197CA3, 0xC0CC1FED, 0x00000049, 0x00000000 }; - uint32_t *boot_data = (uint32_t*)BOOT_TFM_SHARED_DATA_BASE; + uint32_t *boot_data = (uint32_t*)SHARED_BOOT_MEASUREMENT_BASE; memcpy(boot_data, mock_data, sizeof(mock_data)); } diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_read_ranges.h b/platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_platform_user_memory_ranges.h similarity index 72% rename from platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_read_ranges.h rename to platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 83cb01431..be9c72f3b 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_read_ranges.h +++ b/platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef TFM_READ_RANGES_H__ -#define TFM_READ_RANGES_H__ +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ #include @@ -33,4 +33,9 @@ static const struct tfm_read_service_range ranges[] = { { .start = FICR_XOSC32MTRIM_ADDR, .size = FICR_XOSC32MTRIM_SIZE }, }; -#endif /* TFM_READ_RANGES_H__ */ +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/lairdconnectivity/common/bl5340/partition/region_defs.h b/platform/ext/target/lairdconnectivity/common/bl5340/partition/region_defs.h index 819ffb668..877e3c564 100644 --- a/platform/ext/target/lairdconnectivity/common/bl5340/partition/region_defs.h +++ b/platform/ext/target/lairdconnectivity/common/bl5340/partition/region_defs.h @@ -168,5 +168,8 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt index 6547d01bd..de0efa72c 100644 --- a/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/core/CMakeLists.txt @@ -9,6 +9,8 @@ cmake_policy(SET CMP0076 NEW) set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +include(${CMAKE_CURRENT_LIST_DIR}/config.cmake) + if (NOT NRF_BOARD_SELECTED) if (${TFM_PLATFORM} STREQUAL "nordic_nrf/nrf5340") set(hint nordic_nrf/nrf5340dk_nrf5340_cpuapp) @@ -22,12 +24,14 @@ endif() # At the time of writing there is no systematic way to identify which # NVM technology is used by the SoC from the Kconfig, so we just # hardcode this information here instead. -if((NRF_SOC_VARIANT STREQUAL nrf54l15) OR (target STREQUAL nrf54l15)) +if((NRF_SOC_VARIANT MATCHES "^nrf54l1[05]$") OR (TFM_PLATFORM MATCHES "nordic\_nrf\/nrf54l15dk\_nrf54l1[05]\_cpuapp") OR (PSA_API_TEST_TARGET MATCHES "^nrf54l1[05]$")) # Maybe we only need to check one of these options but these # variables keep changing so we check both to be future proof set(HAS_RRAMC 1) + set(HAS_CRACEN 1) else() set(HAS_NVMC 1) + set(HAS_CRACEN 0) endif() #========================= Platform dependencies ===============================# @@ -74,9 +78,11 @@ target_include_directories(platform_s services/include ) +if(PLATFORM_DEFAULT_OTP OR TFM_PARTITION_INTERNAL_TRUSTED_STORAGE) set(nvm_sources ${CMAKE_CURRENT_SOURCE_DIR}/cmsis_drivers/Driver_Flash.c ) +endif() if(HAS_RRAMC) list(APPEND nvm_sources @@ -96,10 +102,12 @@ target_sources(platform_s nrfx_glue.c native_drivers/mpu_armv8m_drv.c native_drivers/spu.c + $<$:${CMAKE_CURRENT_SOURCE_DIR}/native_drivers/tampc.c> $<$:${CMAKE_CURRENT_SOURCE_DIR}/nrf_exception_info.c> $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/plat_test.c> $<$:${CMAKE_CURRENT_SOURCE_DIR}/pal_plat_test.c> - $<$:${CMAKE_CURRENT_SOURCE_DIR}/tfm_hal_its_encryption.c> + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/tfm_hal_its_encryption.c> + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/tfm_hal_its_encryption_cracen.c> ) if (NRF_HW_INIT_RESET_ON_BOOT) @@ -129,6 +137,11 @@ if(TFM_SPM_LOG_RAW_ENABLED) cmsis_drivers/Driver_USART.c ${HAL_NORDIC_PATH}/nrfx/drivers/src/nrfx_uarte.c ) + + target_compile_definitions(platform_s + PUBLIC + NRF_SECURE_UART_INSTANCE=${NRF_SECURE_UART_INSTANCE} + ) endif() target_compile_options(platform_s @@ -194,6 +207,9 @@ target_sources(tfm_spm tfm_hal_platform_common.c faults.c target_cfg.c + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_54l.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg_53_91.c> + secure_peripherals_defs.c ) target_sources(tfm_s @@ -208,6 +224,27 @@ if(BL2) ) endif() +if(NRF_APPROTECT) + target_compile_definitions(tfm_spm + PRIVATE + NRF_APPROTECT + ) +endif() + +if(NRF_SECURE_APPROTECT) + target_compile_definitions(tfm_spm + PRIVATE + NRF_SECURE_APPROTECT + ) +endif() + +if(NRF_TAMPC_ENABLE) + target_compile_definitions(tfm_spm + PRIVATE + NRF_TAMPC_ENABLE + ) +endif() + #========================= Files for building NS side platform ================# configure_file(config_nordic_nrf_spe.cmake.in diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c index fc74a942c..cf0e93281 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_Flash.c @@ -24,8 +24,21 @@ #include +#ifdef __NRF_TFM__ +#include +#endif + #if defined(NRF_NVMC_S) #include +#elif defined(NRF_RRAMC_S) +#include + +#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 +#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE +#else +#define WRITE_BUFFER_SIZE 0 +#endif + #else #error "Unrecognized platform" #endif @@ -87,6 +100,38 @@ static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event) ARG_UNUSED(cb_event); +#ifdef RRAMC_PRESENT + nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); + + config.mode_write = true; + +#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 + config.preload_timeout_enable = true; + config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; +#else + config.preload_timeout_enable = false; + config.preload_timeout = 0; +#endif + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_rramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_rramc_init(&config, handler); + + if(err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } +#endif /* RRAMC_PRESENT */ + return ARM_DRIVER_OK; +} + +// The unitialize function is called by the BL2 bootloader when we build +// the TF-M PSA arch tests in upstream Zephyr, so we need to keep it +// even though it doesn't do anything. +static int32_t ARM_Flash_Unitialize(void) +{ return ARM_DRIVER_OK; } @@ -119,18 +164,37 @@ static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, return ARM_DRIVER_ERROR_PARAMETER; } +#ifdef NRF_NVMC_S nrfx_nvmc_words_write(addr, data, cnt); +#else + nrf_rramc_config_t rramc_config; + nrf_rramc_config_get(NRF_RRAMC, &rramc_config); + const nrf_rramc_config_t orig_rramc_config = rramc_config; + rramc_config.write_buff_size = 0; + nrf_rramc_config_set(NRF_RRAMC, &rramc_config); + + nrfx_rramc_words_write(addr, data, cnt); + + nrf_rramc_config_set(NRF_RRAMC, &orig_rramc_config); +#endif return cnt; } static int32_t ARM_Flash_EraseSector(uint32_t addr) { +#ifdef NRF_NVMC_S nrfx_err_t err_code = nrfx_nvmc_page_erase(addr); if (err_code != NRFX_SUCCESS) { return ARM_DRIVER_ERROR_PARAMETER; } +#else + /* + * Erasure is not needed on RRAM. + * Save lifetime and execution time by not emulating a flash erase. + */ +#endif return ARM_DRIVER_OK; } @@ -144,7 +208,7 @@ ARM_DRIVER_FLASH Driver_FLASH0 = { .GetVersion = NULL, .GetCapabilities = ARM_Flash_GetCapabilities, .Initialize = ARM_Flash_Initialize, - .Uninitialize = NULL, + .Uninitialize = ARM_Flash_Unitialize, .PowerControl = NULL, .ReadData = ARM_Flash_ReadData, .ProgramData = ARM_Flash_ProgramData, diff --git a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c index 953bd629e..db99c0bb7 100644 --- a/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c +++ b/platform/ext/target/nordic_nrf/common/core/cmsis_drivers/Driver_USART.c @@ -28,13 +28,19 @@ #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) #endif +#if !(DOMAIN_NS == 1U) && defined(CONFIG_TFM_LOG_SHARE_UART) && (defined(NRF_SPU) || defined(NRF_SPU00)) +#define SPU_CONFIGURE_UART +#include +#endif + #ifndef ARG_UNUSED #define ARG_UNUSED(arg) (void)arg #endif #define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) -#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART20 || RTE_USART22 +#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || \ + RTE_UART00 || RTE_USART20 || RTE_UART21 || RTE_UART22 || RTE_USART30 #define PSEL_DISCONNECTED 0xFFFFFFFFUL @@ -108,6 +114,11 @@ static int32_t ARM_USARTx_Initialize(ARM_USART_SignalEvent_t cb_event, { ARG_UNUSED(cb_event); +#ifdef SPU_CONFIGURE_UART + spu_peripheral_config_secure((uint32_t)uart_resources->uarte.p_reg, false); + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); +#endif + nrfx_uarte_config_t uart_config = UART_CONFIG_INITIALIZER(); uart_config_set_uart_pins(&uart_config, @@ -135,6 +146,12 @@ static int32_t ARM_USARTx_Uninitialize(UARTx_Resources *uart_resources) nrfx_uarte_uninit(&uart_resources->uarte); uart_resources->initialized = false; + +#ifdef SPU_CONFIGURE_UART + spu_peripheral_config_non_secure((uint32_t)uart_resources->uarte.p_reg, false); + NVIC_SetTargetState(NRFX_IRQ_NUMBER_GET((uint32_t)uart_resources->uarte.p_reg)); +#endif + return ARM_DRIVER_OK; } @@ -422,13 +439,24 @@ DRIVER_USART(2); DRIVER_USART(3); #endif -// TODO: NCSDK-25009: Support choosing an instance for TF-M +#if RTE_USART00 +DRIVER_USART(00); +#endif + #if RTE_USART20 DRIVER_USART(20); #endif +#if RTE_USART21 +DRIVER_USART(21); +#endif + #if RTE_USART22 DRIVER_USART(22); #endif -#endif /* RTE_USART0 || RTE_USART1 || etc. */ +#if RTE_USART30 +DRIVER_USART(30); +#endif + +#endif /* RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART20 || RTE_USART22 */ diff --git a/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h b/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h index 5d2b1da19..da1111179 100644 --- a/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h +++ b/platform/ext/target/nordic_nrf/common/core/common/nrf-pinctrl.h @@ -19,35 +19,21 @@ * - 6..0: Pin number (combination of port and pin). */ +/* NOTE: Keep in sync with Zephyr's nrf-pinctrl.h */ + /** * @name nRF pin configuration bit field positions and masks. * @{ */ /** Position of the function field. */ -#define NRF_FUN_POS 16U +#define NRF_FUN_POS 17U /** Mask for the function field. */ -#define NRF_FUN_MSK 0xFFFFU -/** Position of the invert field. */ -#define NRF_INVERT_POS 14U -/** Mask for the invert field. */ -#define NRF_INVERT_MSK 0x1U -/** Position of the low power field. */ -#define NRF_LP_POS 13U -/** Mask for the low power field. */ -#define NRF_LP_MSK 0x1U -/** Position of the drive configuration field. */ -#define NRF_DRIVE_POS 9U -/** Mask for the drive configuration field. */ -#define NRF_DRIVE_MSK 0xFU -/** Position of the pull configuration field. */ -#define NRF_PULL_POS 7U -/** Mask for the pull configuration field. */ -#define NRF_PULL_MSK 0x3U +#define NRF_FUN_MSK 0x7FFFU /** Position of the pin field. */ #define NRF_PIN_POS 0U /** Mask for the pin field. */ -#define NRF_PIN_MSK 0x7FU +#define NRF_PIN_MSK 0x1FFU /** @} */ diff --git a/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h b/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h index 7cbe5a5be..f8473d622 100644 --- a/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h +++ b/platform/ext/target/nordic_nrf/common/core/common/nrfx_glue.h @@ -32,7 +32,8 @@ #ifndef NRFX_GLUE_H__ #define NRFX_GLUE_H__ -#include +/* Include the spm utilities for the SPM_ASSERT symbol */ +#include #include @@ -59,7 +60,7 @@ extern "C" { #if defined(NDEBUG) #define NRFX_ASSERT(expression) if (0 && (expression)) {} #else -#define NRFX_ASSERT(expression) SPM_ASSERT(expression) +#define NRFX_ASSERT(expression) assert(expression) #endif /** diff --git a/platform/ext/target/nordic_nrf/common/core/config.cmake b/platform/ext/target/nordic_nrf/common/core/config.cmake index 675c541ad..32b3c26c8 100644 --- a/platform/ext/target/nordic_nrf/common/core/config.cmake +++ b/platform/ext/target/nordic_nrf/common/core/config.cmake @@ -9,7 +9,7 @@ #------------------------------------------------------------------------------- set(HAL_NORDIC_PATH "DOWNLOAD" CACHE PATH "Path to the Nordic HAL (or DOWNLOAD to fetch automatically)") -set(HAL_NORDIC_VERSION "nrfx-3.0.0" CACHE STRING "Version of the Nordic HAL to download") +set(HAL_NORDIC_VERSION "nrfx-3.9.0" CACHE STRING "Version of the Nordic HAL to download") set(HAL_NORDIC_REMOTE "https://github.com/zephyrproject-rtos/hal_nordic" CACHE STRING "Remote of the Nordic HAL to download") # Set to FALSE if HAL_NORDIC_VERSION is a SHA. set(HAL_NORDIC_SHALLOW_FETCH CACHE BOOL TRUE "Use shallow fetch to download Nordic HAL.") @@ -33,11 +33,25 @@ if (NRF_HW_INIT_NRF_PERIPHERALS AND NOT NRF_HW_INIT_RESET_ON_BOOT) message(FATAL_ERROR "NRF_HW_INIT_NRF_PERIPHERALS depends on NRF_HW_INIT_RESET_ON_BOOT") endif() -set(SECURE_UART1 ON CACHE BOOL "Enable secure UART1") set(NRF_NS_STORAGE OFF CACHE BOOL "Enable non-secure storage partition") set(BL2 ON CACHE BOOL "Whether to build BL2") set(NRF_NS_SECONDARY ${BL2} CACHE BOOL "Enable non-secure secondary partition") +set(NRF_APPROTECT OFF CACHE BOOL "Enable approtect") +set(NRF_SECURE_APPROTECT OFF CACHE BOOL "Enable secure approtect") +set(NRF_TAMPC_ENABLE ON CACHE BOOL "Enable the tamper controller (TAMPC)") # Platform-specific configurations set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_MULTI_CORE_TOPOLOGY OFF) + +if ((NOT TFM_PARTITION_LOG_LEVEL STREQUAL "" + AND + NOT TFM_PARTITION_LOG_LEVEL STREQUAL "TFM_PARTITION_LOG_LEVEL_SILENCE") + OR + (NOT TFM_SPM_LOG_LEVEL STREQUAL "" + AND + NOT TFM_SPM_LOG_LEVEL STREQUAL "TFM_SPM_LOG_LEVEL_SILENCE")) + +set(NRF_SECURE_UART_INSTANCE 1 CACHE STRING "The UART instance number to use for secure UART") +set(SECURE_UART1 ON CACHE BOOL "Enable secure UART1") +endif() diff --git a/platform/ext/target/nordic_nrf/common/core/faults.c b/platform/ext/target/nordic_nrf/common/core/faults.c index 3d847a7af..58c406626 100644 --- a/platform/ext/target/nordic_nrf/common/core/faults.c +++ b/platform/ext/target/nordic_nrf/common/core/faults.c @@ -22,7 +22,7 @@ void SPU_Handler(void) /* Clear SPU interrupt flag and pending SPU IRQ */ spu_clear_events(); - NVIC_ClearPendingIRQ(SPU_IRQn); + NVIC_ClearPendingIRQ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) - NVIC_USER_IRQ_OFFSET); tfm_core_panic(); } @@ -36,3 +36,112 @@ __attribute__((naked)) void SPU_IRQHandler(void) "B . \n" ); } + +#ifdef NRF_SPU00 +__attribute__((naked)) void SPU00_IRQHandler(void) +{ + EXCEPTION_INFO(); + + __ASM volatile( + "BL SPU_Handler \n" + "B . \n" + ); +} +#endif + +#ifdef NRF_SPU10 +__attribute__((naked)) void SPU10_IRQHandler(void) +{ + EXCEPTION_INFO(); + + __ASM volatile( + "BL SPU_Handler \n" + "B . \n" + ); +} +#endif + +#ifdef NRF_SPU20 +__attribute__((naked)) void SPU20_IRQHandler(void) +{ + EXCEPTION_INFO(); + + __ASM volatile( + "BL SPU_Handler \n" + "B . \n" + ); +} +#endif + +#ifdef NRF_SPU30 +__attribute__((naked)) void SPU30_IRQHandler(void) +{ + EXCEPTION_INFO(); + + __ASM volatile( + "BL SPU_Handler \n" + "B . \n" + ); +} +#endif + +#ifdef NRF_MPC00 +__attribute__((naked)) void MPC_Handler(void) +{ + EXCEPTION_INFO(); + +#ifdef TFM_EXCEPTION_INFO_DUMP + nrf_exception_info_store_context(); +#endif + + /* Clear MPC interrupt flag and pending MPC IRQ */ + mpc_clear_events(); + + NVIC_ClearPendingIRQ(MPC00_IRQn); + + tfm_core_panic(); + + __ASM volatile( + "B . \n" + ); +} + +void MPC00_IRQHandler(void) +{ + /* Address 0xFFFFFFFE is used by TF-M as a return address in some cases + * (e.g., THRD_GENERAL_EXIT). This causes the debugger to access this + * address when analyzing stack frames upon hitting a breakpoint in TF-M. + * Attempting to access this address triggers the MPC MEMACCERR event, + * disrupting debugging. To prevent this, we ignore events from this address. + * Note that this does not affect exception information in MPC_Handler, + * except for scratch registers (R0-R3). + **/ + if( nrf_mpc_event_check(NRF_MPC00, NRF_MPC_EVENT_MEMACCERR)){ + if(NRF_MPC00->MEMACCERR.ADDRESS == 0xFFFFFFFE) + { + mpc_clear_events(); + NVIC_ClearPendingIRQ(MPC00_IRQn); + return; + } + } + + MPC_Handler(); +} +#endif + +#ifdef NRF_TAMPC +__attribute__((naked)) void TAMPC_IRQHandler(void) +{ + EXCEPTION_INFO(); + +#ifdef TFM_EXCEPTION_INFO_DUMP + nrf_exception_info_store_context(); +#endif + + tfm_core_panic(); + + __ASM volatile( + "B . \n" + ); +} +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/hw_init.c b/platform/ext/target/nordic_nrf/common/core/hw_init.c index fb8bba324..a64b3ce77 100644 --- a/platform/ext/target/nordic_nrf/common/core/hw_init.c +++ b/platform/ext/target/nordic_nrf/common/core/hw_init.c @@ -10,7 +10,9 @@ #include "array.h" #include +#if defined(RTC_PRESENT) #include +#endif #include #include #include diff --git a/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.c b/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.c index 63b89f6c5..8190ad00f 100644 --- a/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.c +++ b/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.c @@ -16,8 +16,14 @@ #include "spu.h" #include "region_defs.h" +#include "array.h" /* Platform-specific configuration */ +#if NRF_SPU_HAS_MEMORY + +#define DEVICE_FLASH_BASE_ADDRESS FLASH_BASE_ADDRESS +#define DEVICE_SRAM_BASE_ADDRESS SRAM_BASE_ADDRESS + #define FLASH_SECURE_ATTRIBUTION_REGION_SIZE SPU_FLASH_REGION_SIZE #define SRAM_SECURE_ATTRIBUTION_REGION_SIZE SPU_SRAM_REGION_SIZE @@ -29,9 +35,6 @@ #define NUM_SRAM_SECURE_ATTRIBUTION_REGIONS \ (TOTAL_RAM_SIZE / SRAM_SECURE_ATTRIBUTION_REGION_SIZE) -#define DEVICE_FLASH_BASE_ADDRESS FLASH_BASE_ADDRESS -#define DEVICE_SRAM_BASE_ADDRESS SRAM_BASE_ADDRESS - /* Convenience macros for SPU Non-Secure Callable (NCS) attribution */ /* @@ -56,39 +59,6 @@ */ #define FLASH_NSC_SIZE_REG(size) ((31 - __builtin_clz(size)) - 4) - -void spu_enable_interrupts(void) -{ - nrf_spu_int_enable(NRF_SPU, - NRF_SPU_INT_FLASHACCERR_MASK | - NRF_SPU_INT_RAMACCERR_MASK | - NRF_SPU_INT_PERIPHACCERR_MASK); -} - -uint32_t spu_events_get(void) -{ - uint32_t events = 0; - - if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_RAMACCERR)) { - events |= SPU_EVENT_RAMACCERR; - } - if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_FLASHACCERR)) { - events |= SPU_EVENT_FLASHACCERR; - } - if (nrf_spu_event_check(NRF_SPU, NRF_SPU_EVENT_PERIPHACCERR)) { - events |= SPU_EVENT_PERIPHACCERR; - } - - return events; -} - -void spu_clear_events(void) -{ - nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_RAMACCERR); - nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_FLASHACCERR); - nrf_spu_event_clear(NRF_SPU, NRF_SPU_EVENT_PERIPHACCERR); -} - #if defined(REGION_MCUBOOT_ADDRESS) || defined(REGION_B0_ADDRESS) || defined(REGION_S0_ADDRESS) || defined(REGION_S1_ADDRESS) static bool spu_region_is_flash_region_in_address_range(uint8_t region_id, uint32_t start_address, uint32_t end_address) { @@ -98,46 +68,118 @@ static bool spu_region_is_flash_region_in_address_range(uint8_t region_id, uint3 } #endif -#if defined(REGION_PCD_SRAM_ADDRESS) -static bool spu_region_is_sram_region_in_address_range(uint8_t region_id, uint32_t start_address, uint32_t end_address) -{ - size_t start_id = (start_address - DEVICE_SRAM_BASE_ADDRESS) / SRAM_SECURE_ATTRIBUTION_REGION_SIZE; - size_t end_id = (end_address - DEVICE_SRAM_BASE_ADDRESS) / SRAM_SECURE_ATTRIBUTION_REGION_SIZE; - return region_id >= start_id && region_id <= end_id; -} -#endif - static bool spu_region_is_bootloader_region(NRF_SPU_Type * p_reg, uint8_t region_id) { bool is_bootloader = false; #ifdef REGION_MCUBOOT_ADDRESS - is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_MCUBOOT_ADDRESS, REGION_MCUBOOT_END_ADDRESS); + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_MCUBOOT_ADDRESS, REGION_MCUBOOT_LIMIT); #endif #ifdef REGION_B0_ADDRESS - is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_B0_ADDRESS, REGION_B0_END_ADDRESS); + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_B0_ADDRESS, REGION_B0_LIMIT); #endif #ifdef REGION_S0_ADDRESS - is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S0_ADDRESS, REGION_S0_END_ADDRESS); + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S0_ADDRESS, REGION_S0_LIMIT); #endif #ifdef REGION_S1_ADDRESS - is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S1_ADDRESS, REGION_S1_END_ADDRESS); + is_bootloader = is_bootloader || spu_region_is_flash_region_in_address_range(region_id, REGION_S1_ADDRESS, REGION_S1_LIMIT); #endif return is_bootloader; } -static bool spu_region_is_pcd_region(NRF_SPU_Type * p_reg, uint8_t region_id) +#endif /* NRF_SPU_HAS_MEMORY */ + +void spu_enable_interrupts(void) +{ + uint32_t mask = 0; + +#if NRF_SPU_HAS_MEMORY + mask |= NRF_SPU_INT_RAMACCERR_MASK; + mask |= NRF_SPU_INT_FLASHACCERR_MASK; +#endif + + mask |= NRF_SPU_INT_PERIPHACCERR_MASK; + + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + nrf_spu_int_enable(spu_instances[i], mask); + } +} + +uint32_t spu_events_get(void) +{ + uint32_t events = 0; + + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + if(nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_PERIPHACCERR)){ + events |= SPU_EVENT_PERIPHACCERR; + } +#if NRF_SPU_HAS_MEMORY + if (nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_RAMACCERR)) { + events |= SPU_EVENT_RAMACCERR; + } + if (nrf_spu_event_check(spu_instances[i], NRF_SPU_EVENT_FLASHACCERR)) { + events |= SPU_EVENT_FLASHACCERR; + } +#endif /* NRF_SPU_HAS_MEMORY */ + } + + return events; +} + +#ifdef MPC_PRESENT +void mpc_enable_interrupts(void) +{ + uint32_t mask = NRF_MPC_INT_MEMACCERR_MASK; + nrf_mpc_int_enable(NRF_MPC00, mask); +} + +uint32_t mpc_events_get(void) { - bool is_pcd = false; + uint32_t events = 0; -#ifdef PM_PCD_SRAM_ADDRESS - is_pcd = is_pcd || spu_region_is_sram_region_in_address_range(region_id, PM_PCD_SRAM_ADDRESS, PM_PCD_SRAM_END_ADDRESS); + if (nrf_mpc_event_check(NRF_MPC00, NRF_MPC_EVENT_MEMACCERR)){ + events |= MPC_EVENT_MEMACCERR; + } + + return events; +} + +void mpc_clear_events() +{ + nrf_mpc_event_clear(NRF_MPC00, NRF_MPC_EVENT_MEMACCERR); +} +#endif /* MPC_PRESENT */ + +void spu_clear_events(void) +{ + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { +#if NRF_SPU_HAS_MEMORY + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_RAMACCERR); + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_FLASHACCERR); #endif + nrf_spu_event_clear(spu_instances[i], NRF_SPU_EVENT_PERIPHACCERR); + } +} + +#ifdef SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk +uint32_t spu_get_peri_addr(void) { + uint32_t addr = 0; - return is_pcd; + for(int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + if(spu_instances[i]->EVENTS_PERIPHACCERR){ + /* Only the lower 16 bits of the address are captured into the register. The upper + * 16 bits correspond to the upper 16 bits of the SPU's base address. + */ + addr = spu_instances[i]->PERIPHACCERR.ADDRESS | ((uint32_t)spu_instances[i] & 0xFFFF0000); + } + } + + return addr; } +#endif +#if NRF_SPU_HAS_MEMORY void spu_regions_reset_unlocked_secure(void) { for (size_t i = 0; i < NUM_FLASH_SECURE_ATTRIBUTION_REGIONS ; i++) { @@ -152,14 +194,12 @@ void spu_regions_reset_unlocked_secure(void) } for (size_t i = 0; i < NUM_SRAM_SECURE_ATTRIBUTION_REGIONS ; i++) { - if (!spu_region_is_pcd_region(NRF_SPU, i)) { - nrf_spu_ramregion_set(NRF_SPU, i, - SPU_SECURE_ATTR_SECURE, - NRF_SPU_MEM_PERM_READ - | NRF_SPU_MEM_PERM_WRITE - | NRF_SPU_MEM_PERM_EXECUTE, - SPU_LOCK_CONF_UNLOCKED); - } + nrf_spu_ramregion_set(NRF_SPU, i, + SPU_SECURE_ATTR_SECURE, + NRF_SPU_MEM_PERM_READ + | NRF_SPU_MEM_PERM_WRITE + | NRF_SPU_MEM_PERM_EXECUTE, + SPU_LOCK_CONF_UNLOCKED); } } @@ -283,8 +323,13 @@ uint32_t spu_regions_sram_get_region_size(void) { return SRAM_SECURE_ATTRIBUTION_REGION_SIZE; } -void spu_peripheral_config_secure(const uint8_t periph_id, bool periph_lock) +#endif /* NRF_SPU_HAS_MEMORY */ + +void spu_peripheral_config_secure(const uint32_t periph_base_address, bool periph_lock) { + uint8_t periph_id = NRFX_PERIPHERAL_ID_GET(periph_base_address); + +#if NRF_SPU_HAS_MEMORY /* ASSERT checking that this is not an explicit Non-Secure peripheral */ NRFX_ASSERT((NRF_SPU->PERIPHID[periph_id].PERM & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) != @@ -295,10 +340,26 @@ void spu_peripheral_config_secure(const uint8_t periph_id, bool periph_lock) 1 /* Secure */, 1 /* Secure DMA */, periph_lock); + +#else + + NRF_SPU_Type * nrf_spu = spu_instance_from_peripheral_addr(periph_base_address); + + uint8_t spu_id = NRFX_PERIPHERAL_ID_GET(nrf_spu); + + uint8_t index = periph_id - spu_id; + + nrf_spu_periph_perm_secattr_set(nrf_spu, index, true /* Secure */); + nrf_spu_periph_perm_dmasec_set(nrf_spu, index, true /* Secure */); + nrf_spu_periph_perm_lock_enable(nrf_spu, index); +#endif } -void spu_peripheral_config_non_secure(const uint8_t periph_id, bool periph_lock) +void spu_peripheral_config_non_secure(const uint32_t periph_base_address, bool periph_lock) { + uint8_t periph_id = NRFX_PERIPHERAL_ID_GET(periph_base_address); + +#if NRF_SPU_HAS_MEMORY /* ASSERT checking that this is not an explicit Secure peripheral */ NRFX_ASSERT((NRF_SPU->PERIPHID[periph_id].PERM & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) != @@ -309,4 +370,15 @@ void spu_peripheral_config_non_secure(const uint8_t periph_id, bool periph_lock) 0 /* Non-Secure */, 0 /* Non-Secure DMA */, periph_lock); +#else + NRF_SPU_Type * nrf_spu = spu_instance_from_peripheral_addr(periph_base_address); + + uint8_t spu_id = NRFX_PERIPHERAL_ID_GET(nrf_spu); + + uint8_t index = periph_id - spu_id; + + nrf_spu_periph_perm_secattr_set(nrf_spu, index, false /* Non-Secure */); + nrf_spu_periph_perm_dmasec_set(nrf_spu, index, false /* Non-Secure */); + nrf_spu_periph_perm_lock_enable(nrf_spu, index); +#endif } diff --git a/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.h b/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.h index 6561a894c..59f53b7ba 100644 --- a/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.h +++ b/platform/ext/target/nordic_nrf/common/core/native_drivers/spu.h @@ -20,14 +20,36 @@ #include #include #include +#include #include +#ifdef MPC_PRESENT +#include +#endif #define SPU_LOCK_CONF_LOCKED true #define SPU_LOCK_CONF_UNLOCKED false #define SPU_SECURE_ATTR_SECURE true #define SPU_SECURE_ATTR_NONSECURE false +__attribute__((unused)) static NRF_SPU_Type * spu_instances[] = { +#ifdef NRF_SPU + NRF_SPU, +#endif +#ifdef NRF_SPU00 + NRF_SPU00, +#endif +#ifdef NRF_SPU10 + NRF_SPU10, +#endif +#ifdef NRF_SPU20 + NRF_SPU20, +#endif +#ifdef NRF_SPU30 + NRF_SPU30, +#endif +}; + /** * \brief SPU interrupt enabling * @@ -40,6 +62,7 @@ enum spu_events { SPU_EVENT_RAMACCERR = 1 << 0, SPU_EVENT_FLASHACCERR = 1 << 1, SPU_EVENT_PERIPHACCERR= 1 << 2, + MPC_EVENT_MEMACCERR = 1 << 3 }; /** @@ -100,54 +123,32 @@ void spu_regions_flash_config_non_secure_callable(uint32_t start_addr, uint32_t * * Configure a device peripheral to be accessible from Secure domain only. * - * \param periph_id ID number of a particular peripheral. + * \param periph_base_address Base address of a particular peripheral. * \param periph_lock Variable indicating whether to lock peripheral security * * \note * - peripheral shall not be a Non-Secure only peripheral * - DMA transactions are configured as Secure */ -void spu_peripheral_config_secure(const uint8_t periph_id, bool periph_lock); +void spu_peripheral_config_secure(const uint32_t periph_base_address, bool periph_lock); /** * Configure a device peripheral to be accessible from Non-Secure domain. * - * \param periph_id ID number of a particular peripheral. + * \param periph_base_address Base address of a particular peripheral. * \param periph_lock Variable indicating whether to lock peripheral security * * \note * - peripheral shall not be a Secure-only peripheral * - DMA transactions are configured as Non-Secure */ -void spu_peripheral_config_non_secure(const uint8_t periph_id, bool periph_lock); +void spu_peripheral_config_non_secure(const uint32_t periph_base_address, bool periph_lock); /** - * Configure DPPI channels to be accessible from Non-Secure domain. + * /brief Retrieve the address of the transaction that triggered PERIPHACCERR. * - * \param channels_mask Bitmask with channels configuration. - * \param lock_conf Variable indicating whether to lock DPPI channel security - * - * \note all channels are configured as Non-Secure */ -static inline void spu_dppi_config_non_secure(uint32_t channels_mask, bool lock_conf) -{ - nrf_spu_dppi_config_set(NRF_SPU, 0, channels_mask, lock_conf); -} - -/** - * Configure GPIO pins to be accessible from Non-Secure domain. - * - * \param port_number GPIO Port number - * \param gpio_mask Bitmask with gpio configuration. - * \param lock_conf Variable indicating whether to lock GPIO port security - * - * \note all pins are configured as Non-Secure - */ -static inline void spu_gpio_config_non_secure(uint8_t port_number, uint32_t gpio_mask, - bool lock_conf) -{ - nrf_spu_gpio_config_set(NRF_SPU, port_number, gpio_mask, lock_conf); -} +uint32_t spu_get_peri_addr(void); /** * \brief Return base address of a Flash SPU regions @@ -235,4 +236,37 @@ uint32_t spu_regions_sram_get_last_id(void); */ uint32_t spu_regions_sram_get_region_size(void); +/** + * \brief MPC interrupt enabling + * + * Enable security violations outside the Cortex-M33 + * to trigger SPU interrupts. + */ +void mpc_enable_interrupts(void); + +/** + * \brief Retrieve bitmask of MPC events. + */ +uint32_t mpc_events_get(void); + +/** + * \brief MPC event clearing + * + * Clear MPC event registers + */ +void mpc_clear_events(void); + +/** + * Return the SPU instance that can be used to configure the + * peripheral at the given base address. + */ +static inline NRF_SPU_Type * spu_instance_from_peripheral_addr(uint32_t peripheral_addr) +{ + /* See the SPU chapter in the IPS for how this is calculated */ + + uint32_t apb_bus_number = peripheral_addr & 0x00FC0000; + + return (NRF_SPU_Type *)(0x50000000 | apb_bus_number); +} + #endif diff --git a/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.c b/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.c new file mode 100644 index 000000000..e07a05e1a --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#ifndef __TAMPC_H__ +#define __TAMPC_H__ + +#include "target_cfg.h" +#include +#include +#include +#include +#include + +void tampc_enable_interrupts(void) +{ + nrf_tampc_int_enable(NRF_TAMPC, NRF_TAMPC_ALL_INTS_MASK); +} + +static void tampc_clear_events(void) +{ + nrf_tampc_event_clear(NRF_TAMPC, NRF_TAMPC_EVENT_TAMPER); + nrf_tampc_event_clear(NRF_TAMPC, NRF_TAMPC_EVENT_WRITE_ERROR); +} + +static void tampc_clear_statuses(void) +{ + /* The datasheet states that they detectors must be reset before the status is cleared. */ + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_CRACEN, false); + nrf_tampc_protector_status_clear(NRF_TAMPC, NRF_TAMPC_PROTECT_CRACEN); + + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST, false); + nrf_tampc_protector_status_clear(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST); + + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW, false); + nrf_tampc_protector_status_clear(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW); +} + +void tampc_configuration(void) +{ + + tampc_clear_events(); + tampc_clear_statuses(); + + /* Make sure that the CRACEN detector and the glitch detectors are enabled and lock + * their configuration. + */ + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_CRACEN, true); + nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC, NRF_TAMPC_PROTECT_CRACEN, true); + + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST, true); + nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_FAST, true); + + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW, true); + nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC, NRF_TAMPC_PROTECT_GLITCH_DOMAIN_SLOW, true); + + /* The INTRESETEN reset value is enabled on reset, in order to use the TAMPC interrupt + * and not reset the device immediately the INTRESETEN is set to 0 here. + */ + nrf_tampc_protector_ctrl_value_set(NRF_TAMPC, NRF_TAMPC_PROTECT_RESETEN_INT, false); + nrf_tampc_protector_ctrl_lock_set(NRF_TAMPC, NRF_TAMPC_PROTECT_RESETEN_INT, false); + + /* The active shield is not configured here yet, this will be added later. */ +} + +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.h b/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.h new file mode 100644 index 000000000..0a8639405 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/native_drivers/tampc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#ifndef __TAMPC_H__ +#define __TAMPC_H__ + + +#include "target_cfg.h" +#include +#include +#include +#include +#include + +/** + * \brief Enable TAMPC interrupts + * + * Enable interrupts in the INTENSET register of TAMPC. + */ +void tampc_enable_interrupts(void); + +/** + * \brief TAMPC configuration + * + * Configures the TAMPC peripheral to monitor for Cracen and slow/fast domain hardware + * attacks and disables the default reset behavior in order to hanlde the event in the + * interrupt handler. It also locks the configuration of the CTRL registers + * so that they cannot be altered until reset. + * + */ +void tampc_configuration(void); + +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c index 16ac5a5d1..a5df17e8e 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c +++ b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.c @@ -11,29 +11,60 @@ static struct nrf_exception_info nrf_exc_info; -static void spu_dump_context(struct nrf_exception_info *ctx) +static void dump_exception_info(struct nrf_exception_info *ctx) { - SPMLOG_ERRMSG("Platform Exception: SPU Fault\r\n"); + SPMLOG_ERRMSG("Platform Exception:\r\n"); /* Report which type of violation occured */ if (ctx->events & SPU_EVENT_RAMACCERR) { - SPMLOG_DBGMSG(" RAMACCERR\r\n"); + SPMLOG_DBGMSG(" SPU.RAMACCERR\r\n"); } if (ctx->events & SPU_EVENT_PERIPHACCERR) { - SPMLOG_DBGMSG(" PERIPHACCERR\r\n"); + SPMLOG_DBGMSG(" SPU.PERIPHACCERR\r\n"); + SPMLOG_DBGMSGVAL(" Target addr: ", ctx->periphaccerr.address); } if (ctx->events & SPU_EVENT_FLASHACCERR) { - SPMLOG_DBGMSG(" FLASHACCERR\r\n"); + SPMLOG_DBGMSG(" SPU.FLASHACCERR\r\n"); } + +#if MPC_PRESENT + if (ctx->events & MPC_EVENT_MEMACCERR) { + SPMLOG_DBGMSG(" MPC.MEMACCERR\r\n"); + SPMLOG_DBGMSGVAL(" Target addr: ", ctx->memaccerr.address); + SPMLOG_DBGMSGVAL(" Access information: ", ctx->memaccerr.info); + SPMLOG_DBGMSGVAL(" Owner id: ", ctx->memaccerr.info & 0xf); + SPMLOG_DBGMSGVAL(" Masterport: ", (ctx->memaccerr.info & 0x1f0) >> 4); + SPMLOG_DBGMSGVAL(" Read: ", (ctx->memaccerr.info >> 12) & 1); + SPMLOG_DBGMSGVAL(" Write: ", (ctx->memaccerr.info >> 13) & 1); + SPMLOG_DBGMSGVAL(" Execute: ", (ctx->memaccerr.info >> 14) & 1); + SPMLOG_DBGMSGVAL(" Secure: ", (ctx->memaccerr.info >> 15) & 1); + SPMLOG_DBGMSGVAL(" Error source: ", (ctx->memaccerr.info >> 16) & 1); + } +#endif } void nrf_exception_info_store_context(void) { nrf_exc_info.events = spu_events_get(); - spu_dump_context(&nrf_exc_info); +#ifdef SPU_PERIPHACCERR_ADDRESS_ADDRESS_Msk + if (nrf_exc_info.events & SPU_EVENT_PERIPHACCERR){ + nrf_exc_info.periphaccerr.address = spu_get_peri_addr(); + } +#endif + +#ifdef MPC_PRESENT + nrf_exc_info.events |= mpc_events_get(); + if (nrf_exc_info.events & MPC_EVENT_MEMACCERR) + { + nrf_exc_info.memaccerr.address = NRF_MPC00->MEMACCERR.ADDRESS; + nrf_exc_info.memaccerr.info = NRF_MPC00->MEMACCERR.INFO; + } +#endif + + dump_exception_info(&nrf_exc_info); } void nrf_exception_info_get_context(struct nrf_exception_info *ctx) diff --git a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.h b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.h index 7f297c800..04b2eb8ba 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.h +++ b/platform/ext/target/nordic_nrf/common/core/nrf_exception_info.h @@ -11,6 +11,16 @@ struct nrf_exception_info { uint32_t events; + union{ + struct { + uint32_t address; + } periphaccerr; + + struct { + uint32_t address; + uint32_t info; + } memaccerr; + }; }; void nrf_exception_info_store_context(void); diff --git a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h index dadddeb97..8d192b588 100644 --- a/platform/ext/target/nordic_nrf/common/core/nrfx_config.h +++ b/platform/ext/target/nordic_nrf/common/core/nrfx_config.h @@ -48,7 +48,8 @@ #endif /* RTE_FLASH0 */ -#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || RTE_USART20 || RTE_USART22 +#if RTE_USART0 || RTE_USART1 || RTE_USART2 || RTE_USART3 || \ + RTE_USART00 || RTE_USART20 || RTE_USART21 || RTE_USART22 || RTE_USART30 #define NRFX_UARTE_ENABLED 1 #endif #if RTE_USART0 @@ -64,13 +65,22 @@ #define NRFX_UARTE3_ENABLED 1 #endif -// TODO: NCSDK-25009: Moonlight: Make it possible to use different UARTS with TF-M +/* 54L15 has different UART instances */ +#if RTE_USART00 +#define NRFX_UARTE00_ENABLED 1 +#endif #if RTE_USART20 #define NRFX_UARTE20_ENABLED 1 #endif +#if RTE_USART21 +#define NRFX_UARTE21_ENABLED 1 +#endif #if RTE_USART22 #define NRFX_UARTE22_ENABLED 1 #endif +#if RTE_USART30 +#define NRFX_UARTE30_ENABLED 1 +#endif /* * For chips with TrustZone support, MDK provides CMSIS-Core peripheral @@ -90,8 +100,8 @@ #include #elif defined(NRF91_SERIES) #include -#elif defined(NRF54L15_ENGA_XXAA) - #include +#elif defined(NRF54L_SERIES) + #include #else #error "Unknown device." #endif diff --git a/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c new file mode 100644 index 000000000..7316baa08 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/secure_peripherals_defs.c @@ -0,0 +1,667 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#if TFM_PERIPHERAL_DCNF_SECURE +struct platform_data_t tfm_peripheral_dcnf = { + NRF_DCNF_S_BASE, + NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_OSCILLATORS_SECURE +struct platform_data_t tfm_peripheral_oscillators = { + NRF_OSCILLATORS_S_BASE, + NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_REGULATORS_SECURE +struct platform_data_t tfm_peripheral_regulators = { + NRF_REGULATORS_S_BASE, + NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_CLOCK_SECURE +struct platform_data_t tfm_peripheral_clock = { + NRF_CLOCK_S_BASE, + NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_POWER_SECURE +struct platform_data_t tfm_peripheral_power = { + NRF_POWER_S_BASE, + NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RESET_SECURE +struct platform_data_t tfm_peripheral_reset = { + NRF_RESET_S_BASE, + NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM0_SECURE +struct platform_data_t tfm_peripheral_spim0 = { + NRF_SPIM0_S_BASE, + NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM00_SECURE +struct platform_data_t tfm_peripheral_spim00 = { + NRF_SPIM00_S_BASE, + NRF_SPIM00_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM20_SECURE +struct platform_data_t tfm_peripheral_spim20 = { + NRF_SPIM20_S_BASE, + NRF_SPIM20_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +struct platform_data_t tfm_peripheral_spim21 = { + NRF_SPIM21_S_BASE, + NRF_SPIM21_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +struct platform_data_t tfm_peripheral_spim22 = { + NRF_SPIM22_S_BASE, + NRF_SPIM22_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM23_SECURE +struct platform_data_t tfm_peripheral_spim23 = { + NRF_SPIM23_S_BASE, + NRF_SPIM23_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM30_SECURE +struct platform_data_t tfm_peripheral_spim30 = { + NRF_SPIM30_S_BASE, + NRF_SPIM30_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS0_SECURE +struct platform_data_t tfm_peripheral_spis0 = { + NRF_SPIS0_S_BASE, + NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM0_SECURE +struct platform_data_t tfm_peripheral_twim0 = { + NRF_TWIM0_S_BASE, + NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS0_SECURE +struct platform_data_t tfm_peripheral_twis0 = { + NRF_TWIS0_S_BASE, + NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE0_SECURE +struct platform_data_t tfm_peripheral_uarte0 = { + NRF_UARTE0_S_BASE, + NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM1_SECURE +struct platform_data_t tfm_peripheral_spim1 = { + NRF_SPIM1_S_BASE, + NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS1_SECURE +struct platform_data_t tfm_peripheral_spis1 = { + NRF_SPIS1_S_BASE, + NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM1_SECURE +struct platform_data_t tfm_peripheral_twim1 = { + NRF_TWIM1_S_BASE, + NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS1_SECURE +struct platform_data_t tfm_peripheral_twis1 = { + NRF_TWIS1_S_BASE, + NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE1_SECURE +struct platform_data_t tfm_peripheral_uarte1 = { + NRF_UARTE1_S_BASE, + NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM4_SECURE +struct platform_data_t tfm_peripheral_spim4 = { + NRF_SPIM4_S_BASE, + NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM2_SECURE +struct platform_data_t tfm_peripheral_spim2 = { + NRF_SPIM2_S_BASE, + NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS2_SECURE +struct platform_data_t tfm_peripheral_spis2 = { + NRF_SPIS2_S_BASE, + NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM2_SECURE +struct platform_data_t tfm_peripheral_twim2 = { + NRF_TWIM2_S_BASE, + NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS2_SECURE +struct platform_data_t tfm_peripheral_twis2 = { + NRF_TWIS2_S_BASE, + NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE2_SECURE +struct platform_data_t tfm_peripheral_uarte2 = { + NRF_UARTE2_S_BASE, + NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIM3_SECURE +struct platform_data_t tfm_peripheral_spim3 = { + NRF_SPIM3_S_BASE, + NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SPIS3_SECURE +struct platform_data_t tfm_peripheral_spis3 = { + NRF_SPIS3_S_BASE, + NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIM3_SECURE +struct platform_data_t tfm_peripheral_twim3 = { + NRF_TWIM3_S_BASE, + NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TWIS3_SECURE +struct platform_data_t tfm_peripheral_twis3 = { + NRF_TWIS3_S_BASE, + NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE3_SECURE +struct platform_data_t tfm_peripheral_uarte3 = { + NRF_UARTE3_S_BASE, + NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE00_SECURE +struct platform_data_t tfm_peripheral_uarte00 = { + NRF_UARTE00_S_BASE, + NRF_UARTE00_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE20_SECURE +struct platform_data_t tfm_peripheral_uarte20 = { + NRF_UARTE20_S_BASE, + NRF_UARTE20_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE21_SECURE +struct platform_data_t tfm_peripheral_uarte21 = { + NRF_UARTE21_S_BASE, + NRF_UARTE21_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE22_SECURE +struct platform_data_t tfm_peripheral_uarte22 = { + NRF_UARTE22_S_BASE, + NRF_UARTE22_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_UARTE30_SECURE +struct platform_data_t tfm_peripheral_uarte30 = { + NRF_UARTE30_S_BASE, + NRF_UARTE30_S_BASE + (sizeof(NRF_UARTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_SAADC_SECURE +struct platform_data_t tfm_peripheral_saadc = { + NRF_SAADC_S_BASE, + NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER0_SECURE +struct platform_data_t tfm_peripheral_timer0 = { + NRF_TIMER0_S_BASE, + NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER00_SECURE +struct platform_data_t tfm_peripheral_timer00 = { + NRF_TIMER00_S_BASE, + NRF_TIMER00_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER10_SECURE +struct platform_data_t tfm_peripheral_timer10 = { + NRF_TIMER10_S_BASE, + NRF_TIMER10_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER20_SECURE +struct platform_data_t tfm_peripheral_timer20 = { + NRF_TIMER20_S_BASE, + NRF_TIMER20_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER21_SECURE +struct platform_data_t tfm_peripheral_timer21 = { + NRF_TIMER21_S_BASE, + NRF_TIMER21_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER22_SECURE +struct platform_data_t tfm_peripheral_timer22 = { + NRF_TIMER22_S_BASE, + NRF_TIMER22_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER23_SECURE +struct platform_data_t tfm_peripheral_timer23 = { + NRF_TIMER23_S_BASE, + NRF_TIMER23_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER24_SECURE +struct platform_data_t tfm_peripheral_timer24 = { + NRF_TIMER24_S_BASE, + NRF_TIMER24_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER1_SECURE +struct platform_data_t tfm_peripheral_timer1 = { + NRF_TIMER1_S_BASE, + NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_TIMER2_SECURE +struct platform_data_t tfm_peripheral_timer2 = { + NRF_TIMER2_S_BASE, + NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC0_SECURE +struct platform_data_t tfm_peripheral_rtc0 = { + NRF_RTC0_S_BASE, + NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_RTC1_SECURE +struct platform_data_t tfm_peripheral_rtc1 = { + NRF_RTC1_S_BASE, + NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_DPPI_SECURE +struct platform_data_t tfm_peripheral_dppi = { + NRF_DPPIC_S_BASE, + NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT_SECURE +struct platform_data_t tfm_peripheral_wdt = { + NRF_WDT_S_BASE, + NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT0_SECURE +struct platform_data_t tfm_peripheral_wdt0 = { + NRF_WDT0_S_BASE, + NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_WDT1_SECURE +struct platform_data_t tfm_peripheral_wdt1 = { + NRF_WDT1_S_BASE, + NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_COMP_SECURE +struct platform_data_t tfm_peripheral_comp = { + NRF_COMP_S_BASE, + NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_LPCOMP_SECURE +struct platform_data_t tfm_peripheral_lpcomp = { + NRF_LPCOMP_S_BASE, + NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU0_SECURE +struct platform_data_t tfm_peripheral_egu0 = { + NRF_EGU0_S_BASE, + NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU1_SECURE +struct platform_data_t tfm_peripheral_egu1 = { + NRF_EGU1_S_BASE, + NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU2_SECURE +struct platform_data_t tfm_peripheral_egu2 = { + NRF_EGU2_S_BASE, + NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU3_SECURE +struct platform_data_t tfm_peripheral_egu3 = { + NRF_EGU3_S_BASE, + NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU4_SECURE +struct platform_data_t tfm_peripheral_egu4 = { + NRF_EGU4_S_BASE, + NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU5_SECURE +struct platform_data_t tfm_peripheral_egu5 = { + NRF_EGU5_S_BASE, + NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU10_SECURE +struct platform_data_t tfm_peripheral_egu10 = { + NRF_EGU10_S_BASE, + NRF_EGU10_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_EGU20_SECURE +struct platform_data_t tfm_peripheral_egu20 = { + NRF_EGU20_S_BASE, + NRF_EGU20_S_BASE + (sizeof(NRF_EGU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM0_SECURE +struct platform_data_t tfm_peripheral_pwm0 = { + NRF_PWM0_S_BASE, + NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM1_SECURE +struct platform_data_t tfm_peripheral_pwm1 = { + NRF_PWM1_S_BASE, + NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM2_SECURE +struct platform_data_t tfm_peripheral_pwm2 = { + NRF_PWM2_S_BASE, + NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM3_SECURE +struct platform_data_t tfm_peripheral_pwm3 = { + NRF_PWM3_S_BASE, + NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM20_SECURE +struct platform_data_t tfm_peripheral_pwm20 = { + NRF_PWM20_S_BASE, + NRF_PWM20_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM21_SECURE +struct platform_data_t tfm_peripheral_pwm21 = { + NRF_PWM21_S_BASE, + NRF_PWM21_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PWM22_SECURE +struct platform_data_t tfm_peripheral_pwm22 = { + NRF_PWM22_S_BASE, + NRF_PWM22_S_BASE + (sizeof(NRF_PWM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM0_SECURE +struct platform_data_t tfm_peripheral_pdm0 = { + NRF_PDM0_S_BASE, + NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_PDM_SECURE +struct platform_data_t tfm_peripheral_pdm = { + NRF_PDM_S_BASE, + NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S0_SECURE +struct platform_data_t tfm_peripheral_i2s0 = { + NRF_I2S0_S_BASE, + NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_I2S_SECURE +struct platform_data_t tfm_peripheral_i2s = { + NRF_I2S_S_BASE, + NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_IPC_SECURE +struct platform_data_t tfm_peripheral_ipc = { + NRF_IPC_S_BASE, + NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_FPU_SECURE +struct platform_data_t tfm_peripheral_fpu = { + NRF_FPU_S_BASE, + NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QSPI_SECURE +struct platform_data_t tfm_peripheral_qspi = { + NRF_QSPI_S_BASE, + NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NFCT_SECURE +struct platform_data_t tfm_peripheral_nfct = { + NRF_NFCT_S_BASE, + NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_MUTEX_SECURE +struct platform_data_t tfm_peripheral_mutex = { + NRF_MUTEX_S_BASE, + NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC0_SECURE +struct platform_data_t tfm_peripheral_qdec0 = { + NRF_QDEC0_S_BASE, + NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_QDEC1_SECURE +struct platform_data_t tfm_peripheral_qdec1 = { + NRF_QDEC1_S_BASE, + NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBD_SECURE +struct platform_data_t tfm_peripheral_usbd = { + NRF_USBD_S_BASE, + NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_USBREG_SECURE +struct platform_data_t tfm_peripheral_usbreg = { + NRF_USBREGULATOR_S_BASE, + NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_NVMC_SECURE +struct platform_data_t tfm_peripheral_nvmc = { + NRF_NVMC_S_BASE, + NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO0_SECURE +struct platform_data_t tfm_peripheral_gpio0 = { + NRF_P0_S_BASE, + NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIO1_SECURE +struct platform_data_t tfm_peripheral_gpio1 = { + NRF_P1_S_BASE, + NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_VMC_SECURE +struct platform_data_t tfm_peripheral_vmc = { + NRF_VMC_S_BASE, + NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE20_SECURE +struct platform_data_t tfm_peripheral_gpiote20 = { + NRF_GPIOTE20_S_BASE, + NRF_GPIOTE20_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif + +#if TFM_PERIPHERAL_GPIOTE30_SECURE +struct platform_data_t tfm_peripheral_gpiote30 = { + NRF_GPIOTE30_S_BASE, + NRF_GPIOTE30_S_BASE + (sizeof(NRF_GPIOTE_Type) - 1), +}; +#endif \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h b/platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h index df3c8d618..4c604642b 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h +++ b/platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h @@ -29,8 +29,8 @@ extern "C" { */ enum tfm_platform_ioctl_core_reqest_types_t { TFM_PLATFORM_IOCTL_READ_SERVICE, + TFM_PLATFORM_IOCTL_WRITE32_SERVICE, TFM_PLATFORM_IOCTL_GPIO_SERVICE, - /* Last core service, start platform specific from this value. */ TFM_PLATFORM_IOCTL_CORE_LAST }; @@ -50,6 +50,20 @@ struct tfm_read_service_out_t { uint32_t result; }; +/** @brief Argument list for each platform write32 service. + */ +struct tfm_write32_service_args_t { + uint32_t addr; + uint32_t value; + uint32_t mask; +}; +/** @brief Output list for each write32 platform service + */ + +struct tfm_write32_service_out_t { + uint32_t result; +}; + enum tfm_gpio_service_type { /** Select which MCU / Subsystem controls the pin */ TFM_GPIO_SERVICE_TYPE_PIN_MCU_SELECT = 0, @@ -88,6 +102,19 @@ struct tfm_gpio_service_out { enum tfm_platform_err_t tfm_platform_mem_read(void *destination, uint32_t addr, size_t len, uint32_t *result); +/** + * @brief Perform a write32 operation. + * + * @param[in] addr Address to write to + * @param[in] value 32 bit value to write + * @param[in] mask Mask applied to the write value + * @param[out] result An enum tfm_write32_service_result value + * + * @return Returns values as specified by the tfm_platform_err_t + */ +enum tfm_platform_err_t tfm_platform_mem_write32(uint32_t addr, uint32_t value, + uint32_t mask, uint32_t *result); + /** @brief Represents an accepted read range. */ struct tfm_read_service_range { @@ -95,6 +122,22 @@ struct tfm_read_service_range { size_t size; }; +/** @brief Represents the accepted addresses and masks for write32 service. + */ +struct tfm_write32_service_address { + uint32_t addr; + uint32_t mask; + const uint32_t *allowed_values; + const uint32_t allowed_values_array_size; +}; + +enum tfm_write32_service_result { + TFM_WRITE32_SERVICE_SUCCESS, + TFM_WRITE32_SERVICE_ERROR_INVALID_ADDRESS, + TFM_WRITE32_SERVICE_ERROR_INVALID_MASK, + TFM_WRITE32_SERVICE_ERROR_INVALID_VALUE, +}; + /** * @brief Perform a GPIO MCU select operation. * diff --git a/platform/ext/target/nordic_nrf/common/core/services/include/tfm_platform_hal_ioctl.h b/platform/ext/target/nordic_nrf/common/core/services/include/tfm_platform_hal_ioctl.h index abe940b66..ca540b552 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/include/tfm_platform_hal_ioctl.h +++ b/platform/ext/target/nordic_nrf/common/core/services/include/tfm_platform_hal_ioctl.h @@ -26,6 +26,11 @@ tfm_platform_hal_read_service(const psa_invec *in_vec, enum tfm_platform_err_t tfm_platform_hal_gpio_service(const psa_invec *in_vec, const psa_outvec *out_vec); + +enum tfm_platform_err_t +tfm_platform_hal_write32_service(const psa_invec *in_vec, + const psa_outvec *out_vec); + #ifdef __cplusplus } #endif diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c index 2370988e2..32f653a90 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c @@ -66,3 +66,31 @@ enum tfm_platform_err_t tfm_platform_gpio_pin_mcu_select(uint32_t pin_number, ui return TFM_PLATFORM_ERR_NOT_SUPPORTED; #endif } + +enum tfm_platform_err_t tfm_platform_mem_write32(uint32_t addr, uint32_t value, + uint32_t mask, uint32_t *result) +{ + enum tfm_platform_err_t ret; + psa_invec in_vec; + psa_outvec out_vec; + struct tfm_write32_service_args_t args; + struct tfm_write32_service_out_t out; + + in_vec.base = (const void *)&args; + in_vec.len = sizeof(args); + + out_vec.base = (void *)&out; + out_vec.len = sizeof(out); + + args.addr = addr; + args.value = value; + args.mask = mask; + /* Allowed values cannot be specified by the user */ + + ret = tfm_platform_ioctl(TFM_PLATFORM_IOCTL_WRITE32_SERVICE, &in_vec, + &out_vec); + + *result = out.result; + + return ret; +} diff --git a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c index 1fc258743..15fd17e31 100644 --- a/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c +++ b/platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c @@ -15,9 +15,12 @@ #include /* This contains the user provided allowed ranges */ -#include +#include #include +#ifdef NRF91_SERIES +#include +#endif #include "handle_attr.h" @@ -61,6 +64,29 @@ tfm_platform_hal_read_service(const psa_invec *in_vec, if (args->addr >= start && args->addr + args->len <= start + size) { +#ifdef NRF91_SERIES + if (start >= NRF_UICR_S_BASE && + start < (NRF_UICR_S_BASE + sizeof(NRF_UICR_Type))) { + /* Range is inside UICR. Some nRF platforms need special handling */ + uint32_t *src = (uint32_t *)args->addr; + uint32_t *dst = (uint32_t *)args->destination; + uint32_t uicr_end = NRF_UICR_S_BASE + sizeof(NRF_UICR_Type); + + if (!IS_ALIGNED(src, sizeof(uint32_t)) || + (args->len % sizeof(uint32_t)) != 0 || + (args->addr + args->len) > uicr_end) { + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + + while (args->len) { + *dst++ = nrfx_nvmc_uicr_word_read(src++); + args->len -= sizeof(uint32_t); + } + out->result = 0; + err = TFM_PLATFORM_ERR_SUCCESS; + break; + } +#endif memcpy(args->destination, (const void *)args->addr, args->len); @@ -77,10 +103,16 @@ tfm_platform_hal_read_service(const psa_invec *in_vec, static bool valid_mcu_select(uint32_t mcu) { switch (mcu) { +#if defined(NRF54L_SERIES) + case NRF_GPIO_PIN_SEL_GPIO: + case NRF_GPIO_PIN_SEL_VPR: + case NRF_GPIO_PIN_SEL_GRTC: +#else case NRF_GPIO_PIN_SEL_APP: case NRF_GPIO_PIN_SEL_NETWORK: case NRF_GPIO_PIN_SEL_PERIPHERAL: case NRF_GPIO_PIN_SEL_TND: +#endif return true; default: return false; @@ -127,3 +159,76 @@ tfm_platform_hal_gpio_service(const psa_invec *in_vec, const psa_outvec *out_ve } #endif /* NRF_GPIO_HAS_SEL */ +enum tfm_platform_err_t tfm_platform_hal_write32_service(const psa_invec *in_vec, + const psa_outvec *out_vec) +{ + uint32_t addr; + uint32_t mask; + uint32_t allowed_values_array_size; + + struct tfm_write32_service_args_t *args; + struct tfm_write32_service_out_t *out; + + enum tfm_platform_err_t err; + + if (in_vec->len != sizeof(struct tfm_write32_service_args_t) || + out_vec->len != sizeof(struct tfm_write32_service_out_t)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + args = (struct tfm_write32_service_args_t *)in_vec->base; + out = (struct tfm_write32_service_out_t *)out_vec->base; + + /* Assume failure, in case we don't find a match */ + out->result = TFM_WRITE32_SERVICE_ERROR_INVALID_ADDRESS; + err = TFM_PLATFORM_ERR_INVALID_PARAM; + + for (size_t i = 0; i < ARRAY_SIZE(tfm_write32_service_addresses); i++) { + addr = tfm_write32_service_addresses[i].addr; + mask = tfm_write32_service_addresses[i].mask; + allowed_values_array_size = + tfm_write32_service_addresses[i].allowed_values_array_size; + + if (args->addr == addr) { + out->result = TFM_WRITE32_SERVICE_ERROR_INVALID_MASK; + + if (args->mask == mask) { + /* Check for allowed values if provided */ + if (allowed_values_array_size > 0 && + tfm_write32_service_addresses[i].allowed_values != NULL) { + bool is_value_allowed = false; + + for (int j = 0; j < allowed_values_array_size; j++) { + + const uint32_t allowed_value = + tfm_write32_service_addresses[i] + .allowed_values[j]; + + if (allowed_value == (args->value & args->mask)) { + is_value_allowed = true; + break; + } + } + + if (!is_value_allowed) { + out->result = + TFM_WRITE32_SERVICE_ERROR_INVALID_VALUE; + break; + } + } + + uint32_t new_value = *(uint32_t *)addr; + /* Invert the mask to convert the masked bits to 0 first */ + new_value &= ~args->mask; + new_value |= (args->value & args->mask); + *(uint32_t *)addr = new_value; + + out->result = TFM_WRITE32_SERVICE_SUCCESS; + err = TFM_PLATFORM_ERR_SUCCESS; + break; + } + } + } + + return err; +} diff --git a/platform/ext/target/nordic_nrf/common/core/startup.h b/platform/ext/target/nordic_nrf/common/core/startup.h index bb1295886..781b3a2c6 100644 --- a/platform/ext/target/nordic_nrf/common/core/startup.h +++ b/platform/ext/target/nordic_nrf/common/core/startup.h @@ -36,6 +36,16 @@ __NO_RETURN void SecureFault_Handler(void); void SPU_IRQHandler(void); +void SPU00_IRQHandler(void); +void SPU10_IRQHandler(void); +void SPU20_IRQHandler(void); +void SPU30_IRQHandler(void); + +void MPC00_IRQHandler(void); + +void CRACEN_IRQHandler(void); +void TAMPC_IRQHandler(void); + /* * The default irq handler is used as a backup in case of * misconfiguration. diff --git a/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c new file mode 100644 index 000000000..43e1bed7c --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/startup_nrf54l.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM33.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +/* + * Define __VECTOR_TABLE_ATTRIBUTE (which can be provided by cmsis.h) + * before including cmsis.h because TF-M's linker script + * tfm_common_s.ld assumes the vector table section is called .vectors + * while cmsis.h will sometimes (e.g. when cmsis is provided by nrfx) + * default to using the name .isr_vector. + */ +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) + +#include "cmsis.h" +#include "startup.h" +#include "exception_info.h" + +__NO_RETURN __attribute__((naked)) void default_tfm_IRQHandler(void) { + EXCEPTION_INFO(); + + __ASM volatile( + "BL default_irq_handler \n" + "B . \n" + ); +} + +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(SWI00_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI01_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI02_IRQHandler) +DEFAULT_IRQ_HANDLER(SWI03_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR00_CCM00_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB00_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL00_IRQHandler) +DEFAULT_IRQ_HANDLER(RRAMC_IRQHandler) +DEFAULT_IRQ_HANDLER(VPR00_IRQHandler) +DEFAULT_IRQ_HANDLER(CTRLAP_IRQHandler) +DEFAULT_IRQ_HANDLER(CM33SS_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER00_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER10_IRQHandler) +DEFAULT_IRQ_HANDLER(RTC10_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU10_IRQHandler) +DEFAULT_IRQ_HANDLER(AAR10_CCM10_IRQHandler) +DEFAULT_IRQ_HANDLER(ECB10_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_0_IRQHandler) +DEFAULT_IRQ_HANDLER(RADIO_1_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL20_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL21_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL22_IRQHandler) +DEFAULT_IRQ_HANDLER(EGU20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER20_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER21_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER22_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER23_IRQHandler) +DEFAULT_IRQ_HANDLER(TIMER24_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM20_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM21_IRQHandler) +DEFAULT_IRQ_HANDLER(PWM22_IRQHandler) +DEFAULT_IRQ_HANDLER(SAADC_IRQHandler) +DEFAULT_IRQ_HANDLER(NFCT_IRQHandler) +DEFAULT_IRQ_HANDLER(TEMP_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE20_1_IRQHandler) +DEFAULT_IRQ_HANDLER(I2S20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC20_IRQHandler) +DEFAULT_IRQ_HANDLER(QDEC21_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_0_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_1_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_2_IRQHandler) +DEFAULT_IRQ_HANDLER(GRTC_3_IRQHandler) +DEFAULT_IRQ_HANDLER(SERIAL30_IRQHandler) +DEFAULT_IRQ_HANDLER(CLOCK_POWER_IRQHandler) +DEFAULT_IRQ_HANDLER(COMP_LPCOMP_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT30_IRQHandler) +DEFAULT_IRQ_HANDLER(WDT31_IRQHandler) +DEFAULT_IRQ_HANDLER(GPIOTE30_1_IRQHandler) + +#if defined(DOMAIN_NS) || defined(BL2) +DEFAULT_IRQ_HANDLER(MPC00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU00_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU10_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU20_IRQHandler) +DEFAULT_IRQ_HANDLER(SPU30_IRQHandler) +DEFAULT_IRQ_HANDLER(CRACEN_IRQHandler) +#endif + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ +/* Exceptions */ + Reset_Handler, + NMI_Handler, + HardFault_Handler, + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, + UsageFault_Handler, + SecureFault_Handler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SVC_Handler, + DebugMon_Handler, + default_tfm_IRQHandler, + PendSV_Handler, + SysTick_Handler, +/* Device specific interrupt handlers */ + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SWI00_IRQHandler, + SWI01_IRQHandler, + SWI02_IRQHandler, + SWI03_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU00_IRQHandler, + MPC00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + AAR00_CCM00_IRQHandler, + ECB00_IRQHandler, + CRACEN_IRQHandler, + default_tfm_IRQHandler, + SERIAL00_IRQHandler, + RRAMC_IRQHandler, + VPR00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + CTRLAP_IRQHandler, + CM33SS_IRQHandler, + default_tfm_IRQHandler, + TIMER00_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU10_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + TIMER10_IRQHandler, + RTC10_IRQHandler, + EGU10_IRQHandler, + AAR10_CCM10_IRQHandler, + ECB10_IRQHandler, + RADIO_0_IRQHandler, + RADIO_1_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL20_IRQHandler, + SERIAL21_IRQHandler, + SERIAL22_IRQHandler, + EGU20_IRQHandler, + TIMER20_IRQHandler, + TIMER21_IRQHandler, + TIMER22_IRQHandler, + TIMER23_IRQHandler, + TIMER24_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + PWM20_IRQHandler, + PWM21_IRQHandler, + PWM22_IRQHandler, + SAADC_IRQHandler, + NFCT_IRQHandler, + TEMP_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE20_1_IRQHandler, + TAMPC_IRQHandler, + I2S20_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + QDEC20_IRQHandler, + QDEC21_IRQHandler, + GRTC_0_IRQHandler, + GRTC_1_IRQHandler, + GRTC_2_IRQHandler, + GRTC_3_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SPU30_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + SERIAL30_IRQHandler, + CLOCK_POWER_IRQHandler, + COMP_LPCOMP_IRQHandler, + default_tfm_IRQHandler, + WDT30_IRQHandler, + WDT31_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + default_tfm_IRQHandler, + GPIOTE30_1_IRQHandler, +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.c b/platform/ext/target/nordic_nrf/common/core/target_cfg.c index d5f52b277..0ee5db8f9 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.c +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.c @@ -1,7 +1,7 @@ /* - * Copyright (c) 2018-2020 Arm Limited. All rights reserved. * Copyright (c) 2020 Nordic Semiconductor ASA. * Copyright (c) 2021 Laird Connectivity. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,497 +15,10 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - #include "target_cfg.h" #include "region_defs.h" -#include "tfm_plat_defs.h" -#include "tfm_peripherals_config.h" #include "region.h" -#include "array.h" - -#include #include -#include -#include -#include -#include - -#define PIN_XL1 0 -#define PIN_XL2 1 - -#if !(defined(NRF91_SERIES) || defined(NRF53_SERIES)) -#error "Invalid configuration" -#endif - - -#if TFM_PERIPHERAL_DCNF_SECURE -struct platform_data_t tfm_peripheral_dcnf = { - NRF_DCNF_S_BASE, - NRF_DCNF_S_BASE + (sizeof(NRF_DCNF_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_OSCILLATORS_SECURE -struct platform_data_t tfm_peripheral_oscillators = { - NRF_OSCILLATORS_S_BASE, - NRF_OSCILLATORS_S_BASE + (sizeof(NRF_OSCILLATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_REGULATORS_SECURE -struct platform_data_t tfm_peripheral_regulators = { - NRF_REGULATORS_S_BASE, - NRF_REGULATORS_S_BASE + (sizeof(NRF_REGULATORS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_CLOCK_SECURE -struct platform_data_t tfm_peripheral_clock = { - NRF_CLOCK_S_BASE, - NRF_CLOCK_S_BASE + (sizeof(NRF_CLOCK_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_POWER_SECURE -struct platform_data_t tfm_peripheral_power = { - NRF_POWER_S_BASE, - NRF_POWER_S_BASE + (sizeof(NRF_POWER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RESET_SECURE -struct platform_data_t tfm_peripheral_reset = { - NRF_RESET_S_BASE, - NRF_RESET_S_BASE + (sizeof(NRF_RESET_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM0_SECURE -struct platform_data_t tfm_peripheral_spim0 = { - NRF_SPIM0_S_BASE, - NRF_SPIM0_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS0_SECURE -struct platform_data_t tfm_peripheral_spis0 = { - NRF_SPIS0_S_BASE, - NRF_SPIS0_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM0_SECURE -struct platform_data_t tfm_peripheral_twim0 = { - NRF_TWIM0_S_BASE, - NRF_TWIM0_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS0_SECURE -struct platform_data_t tfm_peripheral_twis0 = { - NRF_TWIS0_S_BASE, - NRF_TWIS0_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE0_SECURE -struct platform_data_t tfm_peripheral_uarte0 = { - NRF_UARTE0_S_BASE, - NRF_UARTE0_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM1_SECURE -struct platform_data_t tfm_peripheral_spim1 = { - NRF_SPIM1_S_BASE, - NRF_SPIM1_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS1_SECURE -struct platform_data_t tfm_peripheral_spis1 = { - NRF_SPIS1_S_BASE, - NRF_SPIS1_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM1_SECURE -struct platform_data_t tfm_peripheral_twim1 = { - NRF_TWIM1_S_BASE, - NRF_TWIM1_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS1_SECURE -struct platform_data_t tfm_peripheral_twis1 = { - NRF_TWIS1_S_BASE, - NRF_TWIS1_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE1_SECURE -struct platform_data_t tfm_peripheral_uarte1 = { - NRF_UARTE1_S_BASE, - NRF_UARTE1_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM4_SECURE -struct platform_data_t tfm_peripheral_spim4 = { - NRF_SPIM4_S_BASE, - NRF_SPIM4_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM2_SECURE -struct platform_data_t tfm_peripheral_spim2 = { - NRF_SPIM2_S_BASE, - NRF_SPIM2_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS2_SECURE -struct platform_data_t tfm_peripheral_spis2 = { - NRF_SPIS2_S_BASE, - NRF_SPIS2_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM2_SECURE -struct platform_data_t tfm_peripheral_twim2 = { - NRF_TWIM2_S_BASE, - NRF_TWIM2_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS2_SECURE -struct platform_data_t tfm_peripheral_twis2 = { - NRF_TWIS2_S_BASE, - NRF_TWIS2_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE2_SECURE -struct platform_data_t tfm_peripheral_uarte2 = { - NRF_UARTE2_S_BASE, - NRF_UARTE2_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIM3_SECURE -struct platform_data_t tfm_peripheral_spim3 = { - NRF_SPIM3_S_BASE, - NRF_SPIM3_S_BASE + (sizeof(NRF_SPIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SPIS3_SECURE -struct platform_data_t tfm_peripheral_spis3 = { - NRF_SPIS3_S_BASE, - NRF_SPIS3_S_BASE + (sizeof(NRF_SPIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIM3_SECURE -struct platform_data_t tfm_peripheral_twim3 = { - NRF_TWIM3_S_BASE, - NRF_TWIM3_S_BASE + (sizeof(NRF_TWIM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TWIS3_SECURE -struct platform_data_t tfm_peripheral_twis3 = { - NRF_TWIS3_S_BASE, - NRF_TWIS3_S_BASE + (sizeof(NRF_TWIS_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_UARTE3_SECURE -struct platform_data_t tfm_peripheral_uarte3 = { - NRF_UARTE3_S_BASE, - NRF_UARTE3_S_BASE + (sizeof(NRF_UARTE_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_SAADC_SECURE -struct platform_data_t tfm_peripheral_saadc = { - NRF_SAADC_S_BASE, - NRF_SAADC_S_BASE + (sizeof(NRF_SAADC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER0_SECURE -struct platform_data_t tfm_peripheral_timer0 = { - NRF_TIMER0_S_BASE, - NRF_TIMER0_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER1_SECURE -struct platform_data_t tfm_peripheral_timer1 = { - NRF_TIMER1_S_BASE, - NRF_TIMER1_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_TIMER2_SECURE -struct platform_data_t tfm_peripheral_timer2 = { - NRF_TIMER2_S_BASE, - NRF_TIMER2_S_BASE + (sizeof(NRF_TIMER_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC0_SECURE -struct platform_data_t tfm_peripheral_rtc0 = { - NRF_RTC0_S_BASE, - NRF_RTC0_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_RTC1_SECURE -struct platform_data_t tfm_peripheral_rtc1 = { - NRF_RTC1_S_BASE, - NRF_RTC1_S_BASE + (sizeof(NRF_RTC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_DPPI_SECURE -struct platform_data_t tfm_peripheral_dppi = { - NRF_DPPIC_S_BASE, - NRF_DPPIC_S_BASE + (sizeof(NRF_DPPIC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT_SECURE -struct platform_data_t tfm_peripheral_wdt = { - NRF_WDT_S_BASE, - NRF_WDT_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT0_SECURE -struct platform_data_t tfm_peripheral_wdt0 = { - NRF_WDT0_S_BASE, - NRF_WDT0_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_WDT1_SECURE -struct platform_data_t tfm_peripheral_wdt1 = { - NRF_WDT1_S_BASE, - NRF_WDT1_S_BASE + (sizeof(NRF_WDT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_COMP_SECURE -struct platform_data_t tfm_peripheral_comp = { - NRF_COMP_S_BASE, - NRF_COMP_S_BASE + (sizeof(NRF_COMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_LPCOMP_SECURE -struct platform_data_t tfm_peripheral_lpcomp = { - NRF_LPCOMP_S_BASE, - NRF_LPCOMP_S_BASE + (sizeof(NRF_LPCOMP_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU0_SECURE -struct platform_data_t tfm_peripheral_egu0 = { - NRF_EGU0_S_BASE, - NRF_EGU0_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU1_SECURE -struct platform_data_t tfm_peripheral_egu1 = { - NRF_EGU1_S_BASE, - NRF_EGU1_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU2_SECURE -struct platform_data_t tfm_peripheral_egu2 = { - NRF_EGU2_S_BASE, - NRF_EGU2_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU3_SECURE -struct platform_data_t tfm_peripheral_egu3 = { - NRF_EGU3_S_BASE, - NRF_EGU3_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU4_SECURE -struct platform_data_t tfm_peripheral_egu4 = { - NRF_EGU4_S_BASE, - NRF_EGU4_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_EGU5_SECURE -struct platform_data_t tfm_peripheral_egu5 = { - NRF_EGU5_S_BASE, - NRF_EGU5_S_BASE + (sizeof(NRF_EGU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM0_SECURE -struct platform_data_t tfm_peripheral_pwm0 = { - NRF_PWM0_S_BASE, - NRF_PWM0_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM1_SECURE -struct platform_data_t tfm_peripheral_pwm1 = { - NRF_PWM1_S_BASE, - NRF_PWM1_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM2_SECURE -struct platform_data_t tfm_peripheral_pwm2 = { - NRF_PWM2_S_BASE, - NRF_PWM2_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PWM3_SECURE -struct platform_data_t tfm_peripheral_pwm3 = { - NRF_PWM3_S_BASE, - NRF_PWM3_S_BASE + (sizeof(NRF_PWM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM0_SECURE -struct platform_data_t tfm_peripheral_pdm0 = { - NRF_PDM0_S_BASE, - NRF_PDM0_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_PDM_SECURE -struct platform_data_t tfm_peripheral_pdm = { - NRF_PDM_S_BASE, - NRF_PDM_S_BASE + (sizeof(NRF_PDM_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S0_SECURE -struct platform_data_t tfm_peripheral_i2s0 = { - NRF_I2S0_S_BASE, - NRF_I2S0_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_I2S_SECURE -struct platform_data_t tfm_peripheral_i2s = { - NRF_I2S_S_BASE, - NRF_I2S_S_BASE + (sizeof(NRF_I2S_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_IPC_SECURE -struct platform_data_t tfm_peripheral_ipc = { - NRF_IPC_S_BASE, - NRF_IPC_S_BASE + (sizeof(NRF_IPC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_FPU_SECURE -struct platform_data_t tfm_peripheral_fpu = { - NRF_FPU_S_BASE, - NRF_FPU_S_BASE + (sizeof(NRF_FPU_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QSPI_SECURE -struct platform_data_t tfm_peripheral_qspi = { - NRF_QSPI_S_BASE, - NRF_QSPI_S_BASE + (sizeof(NRF_QSPI_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NFCT_SECURE -struct platform_data_t tfm_peripheral_nfct = { - NRF_NFCT_S_BASE, - NRF_NFCT_S_BASE + (sizeof(NRF_NFCT_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_MUTEX_SECURE -struct platform_data_t tfm_peripheral_mutex = { - NRF_MUTEX_S_BASE, - NRF_MUTEX_S_BASE + (sizeof(NRF_MUTEX_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC0_SECURE -struct platform_data_t tfm_peripheral_qdec0 = { - NRF_QDEC0_S_BASE, - NRF_QDEC0_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_QDEC1_SECURE -struct platform_data_t tfm_peripheral_qdec1 = { - NRF_QDEC1_S_BASE, - NRF_QDEC1_S_BASE + (sizeof(NRF_QDEC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBD_SECURE -struct platform_data_t tfm_peripheral_usbd = { - NRF_USBD_S_BASE, - NRF_USBD_S_BASE + (sizeof(NRF_USBD_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_USBREG_SECURE -struct platform_data_t tfm_peripheral_usbreg = { - NRF_USBREGULATOR_S_BASE, - NRF_USBREGULATOR_S_BASE + (sizeof(NRF_USBREG_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_NVMC_SECURE -struct platform_data_t tfm_peripheral_nvmc = { - NRF_NVMC_S_BASE, - NRF_NVMC_S_BASE + (sizeof(NRF_NVMC_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO0_SECURE -struct platform_data_t tfm_peripheral_gpio0 = { - NRF_P0_S_BASE, - NRF_P0_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_GPIO1_SECURE -struct platform_data_t tfm_peripheral_gpio1 = { - NRF_P1_S_BASE, - NRF_P1_S_BASE + (sizeof(NRF_GPIO_Type) - 1), -}; -#endif - -#if TFM_PERIPHERAL_VMC_SECURE -struct platform_data_t tfm_peripheral_vmc = { - NRF_VMC_S_BASE, - NRF_VMC_S_BASE + (sizeof(NRF_VMC_Type) - 1), -}; -#endif #ifdef PSA_API_TEST_IPC struct platform_data_t @@ -603,335 +116,3 @@ enum tfm_plat_err_t system_reset_cfg(void) return TFM_PLAT_ERR_SUCCESS; } - -enum tfm_plat_err_t init_debug(void) -{ -#if defined(NRF91_SERIES) - -#if !defined(DAUTH_CHIP_DEFAULT) -#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." -#endif - -#elif defined(NRF53_SERIES) - -#if defined(DAUTH_NONE) - /* Disable debugging */ - NRF_CTRLAP->APPROTECT.DISABLE = 0; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_NS_ONLY) - /* Allow debugging Non-Secure only */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; -#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) - /* Allow debugging */ - /* Use the configuration in UICR. */ - NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; - NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; -#else -#error "No debug authentication setting is provided." -#endif - - /* Lock access to APPROTECT, SECUREAPPROTECT */ - NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; - NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked << - CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; - -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt target state to NS configuration ----------*/ -enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) -{ - /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ - for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { - NVIC->ITNS[i] = 0xFFFFFFFF; - } - - /* Make sure that the SPU is targeted to S state */ - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_SPU)); - -#ifdef SECURE_UART1 - /* UARTE1 is a secure peripheral, so its IRQ has to target S state */ - NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_UARTE1)); -#endif - - return TFM_PLAT_ERR_SUCCESS; -} - -/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ -enum tfm_plat_err_t nvic_interrupt_enable(void) -{ - /* SPU interrupt enabling */ - spu_enable_interrupts(); - - NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU)); - NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_SPU)); - - return TFM_PLAT_ERR_SUCCESS; -} - -/*------------------- SAU/IDAU configuration functions -----------------------*/ - -void sau_and_idau_cfg(void) -{ - /* IDAU (SPU) is always enabled. SAU is non-existent. - * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. - */ - TZ_SAU_Disable(); - SAU->CTRL |= SAU_CTRL_ALLNS_Msk; -} - -enum tfm_plat_err_t spu_init_cfg(void) -{ - /* - * Configure SPU Regions for Non-Secure Code and SRAM (Data) - * Configure SPU for Peripheral Security - * Configure Non-Secure Callable Regions - * Configure Secondary Image Partition - * Configure Non-Secure Storage Partition - */ - - /* Reset Flash and SRAM configuration of regions that are not owned by - * the bootloader(s) to all-Secure. - */ - spu_regions_reset_unlocked_secure(); - - uint32_t perm; - - /* Configure Secure Code to be secure and RX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - /* Do not permit writes to secure flash */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configure Secure RAM to be secure and RWX */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - /* Permit execute from Secure RAM because otherwise Crypto fails - * to initialize. */ - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures SPU Code and Data regions to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - perm |= NRF_SPU_MEM_PERM_EXECUTE; - - spu_regions_flash_config(memory_regions.non_secure_partition_base, - memory_regions.non_secure_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); - - spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, - SPU_LOCK_CONF_LOCKED); - - /* Configures veneers region to be non-secure callable */ - spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, - memory_regions.veneer_limit - 1); - -#ifdef NRF_NS_SECONDARY - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - /* Secondary image partition */ - spu_regions_flash_config(memory_regions.secondary_partition_base, - memory_regions.secondary_partition_limit, SPU_SECURE_ATTR_NONSECURE, - perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_SECONDARY */ - -#ifdef NRF_NS_STORAGE_PARTITION_START - /* Configures storage partition to be non-secure */ - perm = 0; - perm |= NRF_SPU_MEM_PERM_READ; - perm |= NRF_SPU_MEM_PERM_WRITE; - - spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, - memory_regions.non_secure_storage_partition_limit, - SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); -#endif /* NRF_NS_STORAGE_PARTITION_START */ - - return TFM_PLAT_ERR_SUCCESS; -} - -enum tfm_plat_err_t spu_periph_init_cfg(void) -{ - /* Peripheral configuration */ -static const uint8_t target_peripherals[] = { - /* The following peripherals share ID: - * - FPU (FPU cannot be configured in NRF91 series, it's always NS) - * - DCNF (On 53, but not 91) - */ -#ifndef NRF91_SERIES - NRFX_PERIPHERAL_ID_GET(NRF_FPU), -#endif - /* The following peripherals share ID: - * - REGULATORS - * - OSCILLATORS - */ - NRFX_PERIPHERAL_ID_GET(NRF_REGULATORS), - /* The following peripherals share ID: - * - CLOCK - * - POWER - * - RESET (On 53, but not 91) - */ - NRFX_PERIPHERAL_ID_GET(NRF_CLOCK), - /* The following peripherals share ID: (referred to as Serial-Box) - * - SPIMx - * - SPISx - * - TWIMx - * - TWISx - * - UARTEx - */ - NRFX_PERIPHERAL_ID_GET(NRF_SPIM0), -#ifndef SECURE_UART1 - /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ - NRFX_PERIPHERAL_ID_GET(NRF_SPIM1), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_SPIM2), - NRFX_PERIPHERAL_ID_GET(NRF_SPIM3), -#ifdef NRF_SPIM4 - NRFX_PERIPHERAL_ID_GET(NRF_SPIM4), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_SAADC), - NRFX_PERIPHERAL_ID_GET(NRF_TIMER0), - NRFX_PERIPHERAL_ID_GET(NRF_TIMER1), - NRFX_PERIPHERAL_ID_GET(NRF_TIMER2), - NRFX_PERIPHERAL_ID_GET(NRF_RTC0), - NRFX_PERIPHERAL_ID_GET(NRF_RTC1), - NRFX_PERIPHERAL_ID_GET(NRF_DPPIC), -#ifndef PSA_API_TEST_IPC -#ifdef NRF_WDT0 - /* WDT0 is used as a secure peripheral in PSA FF tests */ - NRFX_PERIPHERAL_ID_GET(NRF_WDT0), -#endif -#ifdef NRF_WDT - NRFX_PERIPHERAL_ID_GET(NRF_WDT), -#endif -#endif /* PSA_API_TEST_IPC */ -#ifdef NRF_WDT1 - NRFX_PERIPHERAL_ID_GET(NRF_WDT1), -#endif - /* The following peripherals share ID: - * - COMP - * - LPCOMP - */ -#ifdef NRF_COMP - NRFX_PERIPHERAL_ID_GET(NRF_COMP), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_EGU0), - NRFX_PERIPHERAL_ID_GET(NRF_EGU1), - NRFX_PERIPHERAL_ID_GET(NRF_EGU2), - NRFX_PERIPHERAL_ID_GET(NRF_EGU3), - NRFX_PERIPHERAL_ID_GET(NRF_EGU4), -#ifndef PSA_API_TEST_IPC - /* EGU5 is used as a secure peripheral in PSA FF tests */ - NRFX_PERIPHERAL_ID_GET(NRF_EGU5), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_PWM0), - NRFX_PERIPHERAL_ID_GET(NRF_PWM1), - NRFX_PERIPHERAL_ID_GET(NRF_PWM2), - NRFX_PERIPHERAL_ID_GET(NRF_PWM3), -#ifdef NRF_PDM - NRFX_PERIPHERAL_ID_GET(NRF_PDM), -#endif -#ifdef NRF_PDM0 - NRFX_PERIPHERAL_ID_GET(NRF_PDM0), -#endif -#ifdef NRF_I2S - NRFX_PERIPHERAL_ID_GET(NRF_I2S), -#endif -#ifdef NRF_I2S0 - NRFX_PERIPHERAL_ID_GET(NRF_I2S0), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_IPC), -#ifndef SECURE_QSPI -#ifdef NRF_QSPI - NRFX_PERIPHERAL_ID_GET(NRF_QSPI), -#endif -#endif -#ifdef NRF_NFCT - NRFX_PERIPHERAL_ID_GET(NRF_NFCT), -#endif -#ifdef NRF_MUTEX - NRFX_PERIPHERAL_ID_GET(NRF_MUTEX), -#endif -#ifdef NRF_QDEC0 - NRFX_PERIPHERAL_ID_GET(NRF_QDEC0), -#endif -#ifdef NRF_QDEC1 - NRFX_PERIPHERAL_ID_GET(NRF_QDEC1), -#endif -#ifdef NRF_USBD - NRFX_PERIPHERAL_ID_GET(NRF_USBD), -#endif -#ifdef NRF_USBREGULATOR - NRFX_PERIPHERAL_ID_GET(NRF_USBREGULATOR), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_NVMC), - NRFX_PERIPHERAL_ID_GET(NRF_P0), -#ifdef NRF_P1 - NRFX_PERIPHERAL_ID_GET(NRF_P1), -#endif - NRFX_PERIPHERAL_ID_GET(NRF_VMC), -}; - - for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { - spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); - } - - /* DPPI channel configuration */ - spu_dppi_config_non_secure(TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, SPU_LOCK_CONF_LOCKED); - - /* GPIO pin configuration */ - spu_gpio_config_non_secure(0, TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, SPU_LOCK_CONF_LOCKED); -#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE - spu_gpio_config_non_secure(1, TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, SPU_LOCK_CONF_LOCKED); -#endif - -#ifdef NRF53_SERIES - /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal - * oscillator (LFXO) can be used. - * This configuration can be done only from secure code, as otherwise those - * register fields are not accessible. That's why it is placed here. - */ - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); -#endif - - /* - * 91 has an instruction cache. - * 53 has both instruction cache and a data cache. - * - * 53's instruction cache has an nrfx driver, but 91's cache is - * not supported by nrfx at time of writing. - * - * We enable all caches available here because non-secure cannot - * configure caches. - */ -#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK - nrfx_nvmc_icache_enable(); -#elif defined(CACHE_PRESENT) // From MDK - NRF_CACHE->ENABLE = CACHE_ENABLE_ENABLE_Enabled; -#endif - - /* Enforce that the nRF5340 Network MCU is in the Non-Secure - * domain. Non-secure is the HW reset value for the network core - * so configuring this should not be necessary, but we want to - * make sure that the bootloader has not accidentally configured - * it to be secure. Additionally we lock the register to make sure - * it doesn't get changed by accident. - */ - nrf_spu_extdomain_set(NRF_SPU, 0, false, true); - - return TFM_PLAT_ERR_SUCCESS; -} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg.h b/platform/ext/target/nordic_nrf/common/core/target_cfg.h index df3dc4fd3..dd767b386 100644 --- a/platform/ext/target/nordic_nrf/common/core/target_cfg.h +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg.h @@ -35,21 +35,39 @@ #include "tfm_plat_defs.h" #include "region_defs.h" -// TODO: NCSDK-25009: Support configuring which UART is used by TF-M on nrf54L +#define NRF_UARTE_INSTANCE(id) NRF_UARTE##id +#define NRF_UARTE_INSTANCE_GET(id) NRF_UARTE_INSTANCE(id) -#if NRF_SECURE_UART_INSTANCE == 0 +#ifndef NRF_SECURE_UART_INSTANCE +#define TFM_DRIVER_STDIO Driver_USART1 +#elif NRF_SECURE_UART_INSTANCE == 0 #define TFM_DRIVER_STDIO Driver_USART0 #elif NRF_SECURE_UART_INSTANCE == 1 #define TFM_DRIVER_STDIO Driver_USART1 +#elif NRF_SECURE_UART_INSTANCE == 00 +#define TFM_DRIVER_STDIO Driver_USART00 +#elif NRF_SECURE_UART_INSTANCE == 20 +#define TFM_DRIVER_STDIO Driver_USART20 +#elif NRF_SECURE_UART_INSTANCE == 21 +#define TFM_DRIVER_STDIO Driver_USART21 #elif NRF_SECURE_UART_INSTANCE == 22 #define TFM_DRIVER_STDIO Driver_USART22 +#elif NRF_SECURE_UART_INSTANCE == 30 +#define TFM_DRIVER_STDIO Driver_USART30 #endif -#ifdef NRF54L15_ENGA_XXAA +/* Only UART20 and UART30 are supported for TF-M tests, which are the + * Non-secure applications build via the TF-M build system + */ +#ifdef NRF54L_SERIES +#if NRF_SECURE_UART_INSTANCE == 20 +#define NS_DRIVER_STDIO Driver_USART30 +#else #define NS_DRIVER_STDIO Driver_USART20 +#endif #else #define NS_DRIVER_STDIO Driver_USART0 -#endif +#endif /* NRF54L_SERIES */ /** * \brief Store the addresses of memory regions @@ -100,11 +118,6 @@ enum tfm_plat_err_t spu_init_cfg(void); */ enum tfm_plat_err_t spu_periph_init_cfg(void); -/** - * \brief Clears SPU interrupt. - */ -void spu_clear_irq(void); - /** * \brief Configures memory permissions via the MPC. * diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c new file mode 100644 index 000000000..c94181a47 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_53_91.c @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include +#include +#include +#include + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +#ifdef NRF53_SERIES +#include +#define PIN_XL1 0 +#define PIN_XL2 1 +#endif + +extern const struct memory_region_limits memory_regions; + +static inline enum tfm_plat_err_t configure_approtect_nvmc(void) +{ +#if defined(NRF_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot.*/ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->APPROTECT, + UICR_APPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif +#if defined(NRF_SECURE_APPROTECT) + /* For nRF53 and nRF91x1 already active. For nRF9160, active in the next boot. */ + if (nrfx_nvmc_word_writable_check((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected)) { + nrfx_nvmc_word_write((uint32_t)&NRF_UICR_S->SECUREAPPROTECT, + UICR_SECUREAPPROTECT_PALL_Protected); + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +#if defined(NRF53_SERIES) + +static inline enum tfm_plat_err_t configure_approtect_registers(void) +{ +#if defined(DAUTH_NONE) + /* Disable debugging */ + NRF_CTRLAP->APPROTECT.DISABLE = 0; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_NS_ONLY) + /* Allow debugging Non-Secure only */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = 0; +#elif defined(DAUTH_FULL) || defined(DAUTH_CHIP_DEFAULT) + /* Allow debugging */ + /* Use the configuration in UICR. */ + NRF_CTRLAP->APPROTECT.DISABLE = NRF_UICR->APPROTECT; + NRF_CTRLAP->SECUREAPPROTECT.DISABLE = NRF_UICR->SECUREAPPROTECT; +#else +#error "No debug authentication setting is provided." +#endif + + /* Lock access to APPROTECT, SECUREAPPROTECT */ + NRF_CTRLAP->APPROTECT.LOCK = CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk; + NRF_CTRLAP->SECUREAPPROTECT.LOCK = CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked + << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk; + + return TFM_PLAT_ERR_SUCCESS; +} +#endif + +enum tfm_plat_err_t init_debug(void) +{ + +#if (defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT)) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access controlled by NRF_APPROTECT and NRF_SECURE_APPROTECT." +#elif defined(NRF91_SERIES) && !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on the nRF91 series can only be configured by programming the corresponding registers in UICR." +#endif + +#if defined(NRF_APPROTECT) || defined(NRF_SECURE_APPROTECT) + return configure_approtect_nvmc(); +#elif defined(NRF53_SERIES) + return configure_approtect_registers(); +#endif +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* IDAU (SPU) is always enabled. SAU is non-existent. + * Allow SPU to have precedence over (non-existing) ARMv8-M SAU. + */ + TZ_SAU_Disable(); + SAU->CTRL |= SAU_CTRL_ALLNS_Msk; +} + +enum tfm_plat_err_t spu_init_cfg(void) +{ + /* + * Configure SPU Regions for Non-Secure Code and SRAM (Data) + * Configure SPU for Peripheral Security + * Configure Non-Secure Callable Regions + * Configure Secondary Image Partition + * Configure Non-Secure Storage Partition + */ + + /* Reset Flash and SRAM configuration of regions that are not owned by + * the bootloader(s) to all-Secure. + */ + spu_regions_reset_unlocked_secure(); + + uint32_t perm; + + /* Configure Secure Code to be secure and RX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + /* Do not permit writes to secure flash */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(S_CODE_START, S_CODE_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configure Secure RAM to be secure and RWX */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + /* Permit execute from Secure RAM because otherwise Crypto fails + * to initialize. */ + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_sram_config(S_DATA_START, S_DATA_LIMIT, SPU_SECURE_ATTR_SECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures SPU Code and Data regions to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + perm |= NRF_SPU_MEM_PERM_EXECUTE; + + spu_regions_flash_config(memory_regions.non_secure_partition_base, + memory_regions.non_secure_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); + + spu_regions_sram_config(NS_DATA_START, NS_DATA_LIMIT, SPU_SECURE_ATTR_NONSECURE, perm, + SPU_LOCK_CONF_LOCKED); + + /* Configures veneers region to be non-secure callable */ + spu_regions_flash_config_non_secure_callable(memory_regions.veneer_base, + memory_regions.veneer_limit - 1); + +#ifdef NRF_NS_SECONDARY + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + /* Secondary image partition */ + spu_regions_flash_config(memory_regions.secondary_partition_base, + memory_regions.secondary_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_SECONDARY */ + +#ifdef NRF_NS_STORAGE_PARTITION_START + /* Configures storage partition to be non-secure */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + perm |= NRF_SPU_MEM_PERM_WRITE; + + spu_regions_flash_config(memory_regions.non_secure_storage_partition_base, + memory_regions.non_secure_storage_partition_limit, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* NRF_NS_STORAGE_PARTITION_START */ + +#ifdef REGION_PCD_SRAM_ADDRESS + enum tfm_plat_err_t err; + bool provisioning_required; + /* Netcore needs PCD memory area to be non-secure. */ + perm = 0; + perm |= NRF_SPU_MEM_PERM_READ; + + err = tfm_plat_provisioning_is_required(&provisioning_required); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + if (provisioning_required) { + perm |= NRF_SPU_MEM_PERM_WRITE; + } + + spu_regions_sram_config(REGION_PCD_SRAM_ADDRESS, REGION_PCD_SRAM_LIMIT, + SPU_SECURE_ATTR_NONSECURE, perm, SPU_LOCK_CONF_LOCKED); +#endif /* REGION_PCD_SRAM_ADDRESS */ + + return TFM_PLAT_ERR_SUCCESS; +} + +static void dppi_channel_configuration(void) +{ + /* The SPU HW and corresponding NRFX HAL API have two different + * API's for DPPI security configuration. The defines + * NRF_SPU_HAS_OWNERSHIP and NRF_SPU_HAS_MEMORY identify which of the two API's + * are present. + * + * TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE is configurable, but + * usually defaults to 0, which results in all DPPI channels being + * non-secure. + */ + /* There is only one dppi_id */ + uint8_t dppi_id = 0; + nrf_spu_dppi_config_set(NRF_SPU, dppi_id, TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE, + SPU_LOCK_CONF_LOCKED); +} + +static void cache_configuration(void) +{ + /* + * 91 has an instruction cache. + * 53 has both instruction cache and a data cache. + * + * 53's instruction cache has an nrfx driver, but 91's cache is + * not supported by nrfx at time of writing. + * + * We enable all caches available here because non-secure cannot + * configure caches. + */ +#if defined(NVMC_FEATURE_CACHE_PRESENT) // From MDK + nrfx_nvmc_icache_enable(); +#endif +#if defined(CACHE_PRESENT) // From MDK + nrf_cache_enable(NRF_CACHE); +#endif +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + /* Note that there are two different API's for SPU configuration */ + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + nrf_spu_gpio_config_set(NRF_SPU, port, secure_pins[port], SPU_LOCK_CONF_LOCKED); + } + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ +#ifdef NRF53_SERIES + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); +#endif /* NRF53_SERIES */ +} + +static void peripheral_configuration(void) +{ + /* Peripheral configuration */ + static const uint32_t target_peripherals[] = { + /* The following peripherals share ID: + * - FPU (FPU cannot be configured in NRF91 series, it's always NS) + * - DCNF (On 53, but not 91) + */ +#ifndef NRF91_SERIES + NRF_FPU_S_BASE, +#endif + /* The following peripherals share ID: + * - REGULATORS + * - OSCILLATORS + */ + NRF_REGULATORS_S_BASE, + /* The following peripherals share ID: + * - CLOCK + * - POWER + * - RESET (On 53, but not 91) + */ + NRF_CLOCK_S_BASE, + /* The following peripherals share ID: (referred to as Serial-Box) + * - SPIMx + * - SPISx + * - TWIMx + * - TWISx + * - UARTEx + */ + + /* When UART0 is a secure peripheral we need to leave Serial-Box 0 as Secure. + * The UART Driver will configure it as non-secure when it uninitializes. + */ +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 0) + NRF_SPIM0_S_BASE, +#endif +#if !(defined(SECURE_UART1) && NRF_SECURE_UART_INSTANCE == 1) + /* UART1 is a secure peripheral, so we need to leave Serial-Box 1 as Secure */ + NRF_SPIM1_S_BASE, +#endif + NRF_SPIM2_S_BASE, + NRF_SPIM3_S_BASE, +#ifdef NRF_SPIM4 + NRF_SPIM4_S_BASE, +#endif + NRF_SAADC_S_BASE, + NRF_TIMER0_S_BASE, + NRF_TIMER1_S_BASE, + NRF_TIMER2_S_BASE, + NRF_RTC0_S_BASE, + NRF_RTC1_S_BASE, + NRF_DPPIC_S_BASE, +#ifndef PSA_API_TEST_IPC +#ifdef NRF_WDT0 + /* WDT0 is used as a secure peripheral in PSA FF tests */ + NRF_WDT0_S_BASE, +#endif +#ifdef NRF_WDT + NRF_WDT_S_BASE, +#endif +#endif /* PSA_API_TEST_IPC */ +#ifdef NRF_WDT1 + NRF_WDT1_S_BASE, +#endif + /* The following peripherals share ID: + * - COMP + * - LPCOMP + */ +#ifdef NRF_COMP + NRF_COMP_S_BASE, +#endif + NRF_EGU0_S_BASE, + NRF_EGU1_S_BASE, + NRF_EGU2_S_BASE, + NRF_EGU3_S_BASE, + NRF_EGU4_S_BASE, +#ifndef PSA_API_TEST_IPC + /* EGU5 is used as a secure peripheral in PSA FF tests */ + NRF_EGU5_S_BASE, +#endif + NRF_PWM0_S_BASE, + NRF_PWM1_S_BASE, + NRF_PWM2_S_BASE, + NRF_PWM3_S_BASE, +#ifdef NRF_PDM + NRF_PDM_S_BASE, +#endif +#ifdef NRF_PDM0 + NRF_PDM0_S_BASE, +#endif +#ifdef NRF_I2S + NRF_I2S_S_BASE, +#endif +#ifdef NRF_I2S0 + NRF_I2S0_S_BASE, +#endif + NRF_IPC_S_BASE, +#ifndef SECURE_QSPI +#ifdef NRF_QSPI + NRF_QSPI_S_BASE, +#endif +#endif +#ifdef NRF_NFCT + NRF_NFCT_S_BASE, +#endif +#ifdef NRF_MUTEX + NRF_MUTEX_S_BASE, +#endif +#ifdef NRF_QDEC0 + NRF_QDEC0_S_BASE, +#endif +#ifdef NRF_QDEC1 + NRF_QDEC1_S_BASE, +#endif +#ifdef NRF_USBD + NRF_USBD_S_BASE, +#endif +#ifdef NRF_USBREGULATOR + NRF_USBREGULATOR_S_BASE, +#endif /* NRF_USBREGULATOR */ + NRF_NVMC_S_BASE, + NRF_P0_S_BASE, +#ifdef NRF_P1 + NRF_P1_S_BASE, +#endif /*NRF_P1 */ + NRF_VMC_S_BASE + }; + + for (int i = 0; i < ARRAY_SIZE(target_peripherals); i++) { + spu_peripheral_config_non_secure(target_peripherals[i], SPU_LOCK_CONF_UNLOCKED); + } +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + + /* The default peripheral configuration sets most of the peripherals with split-security + * as non-secure by default. The peripherals explicitly configured as secure + * will be configured as secure later in the tfm_hal_bind_boundary function. + */ + peripheral_configuration(); + dppi_channel_configuration(); + gpio_configuration(); + cache_configuration(); + +#ifdef NRF53_SERIES + /* Enforce that the nRF5340 Network MCU is in the Non-Secure + * domain. Non-secure is the HW reset value for the network core + * so configuring this should not be necessary, but we want to + * make sure that the bootloader has not accidentally configured + * it to be secure. Additionally we lock the register to make sure + * it doesn't get changed by accident. + */ + nrf_spu_extdomain_set(NRF_SPU, 0, false, true); +#endif /* NRF53_SERIES */ + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c new file mode 100644 index 000000000..5aec9a613 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/target_cfg_54l.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "target_cfg.h" +#include "region_defs.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include "tfm_plat_provisioning.h" +#include "utilities.h" +#include "region.h" +#include "array.h" + +#ifdef __NRF_TFM__ +#include +#endif + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#if CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE > 0 +#define WRITE_BUFFER_SIZE CONFIG_NRF_RRAM_WRITE_BUFFER_SIZE +#else +#define WRITE_BUFFER_SIZE 0 +#endif + +#if !defined(DAUTH_CHIP_DEFAULT) +#error "Debug access on this platform can only be configured by programming the corresponding registers in UICR." +#endif + +#define SPU_ADDRESS_REGION (0x50000000) +#define GET_SPU_SLAVE_INDEX(periph) ((periph.periph_start & 0x0003F000) >> 12) +#define GET_SPU_INSTANCE(periph) \ + ((NRF_SPU_Type *)(SPU_ADDRESS_REGION | (periph.periph_start & 0x00FC0000))) + +/* On nRF54L15 XL1 and XL2 are(P1.00) and XL2(P1.01) */ +#define PIN_XL1 32 +#define PIN_XL2 33 + +/* During TF-M system initialization we invoke a function that comes + * from Zephyr. This function does not have a header file so we + * declare its prototype here. + */ +int nordicsemi_nrf54l_init(void); + +extern const struct memory_region_limits memory_regions; + +struct mpc_region_override { + nrf_mpc_override_config_t config; + nrf_owner_t owner_id; + uintptr_t start_address; + size_t endaddr; + uint32_t perm; + uint32_t permmask; + size_t index; +}; + +static void mpc_configure_override(NRF_MPC_Type *mpc, struct mpc_region_override *override) +{ + nrf_mpc_override_startaddr_set(mpc, override->index, override->start_address); + nrf_mpc_override_endaddr_set(mpc, override->index, override->endaddr); + nrf_mpc_override_perm_set(mpc, override->index, override->perm); + nrf_mpc_override_permmask_set(mpc, override->index, override->permmask); +#if defined(NRF_MPC_HAS_OVERRIDE_OWNERID) && NRF_MPC_HAS_OVERRIDE_OWNERID + nrf_mpc_override_ownerid_set(mpc, override->index, override->owner_id); +#endif + nrf_mpc_override_config_set(mpc, override->index, &override->config); +} + +/* + * Configure the override struct with reasonable defaults. This includes: + * + * Use a slave number of 0 to avoid redirecting bus transactions from + * one slave to another. + * + * Lock the override to prevent the code that follows from tampering + * with the configuration. + * + * Enable the override so it takes effect. + * + * Indicate that secdom is not enabled as this driver is not used on + * platforms with secdom. + */ +static void init_mpc_region_override(struct mpc_region_override *override) +{ + *override = (struct mpc_region_override){ + .config = + (nrf_mpc_override_config_t){ + .slave_number = 0, + .lock = true, + .enable = true, + .secdom_enable = false, + .secure_mask = true, + }, + .perm = 0, /* 0 for non-secure */ + .owner_id = 0, + }; + + override->permmask = MPC_OVERRIDE_PERM_SECATTR_Msk; +} + +static nrfx_err_t rramc_configuration(void) +{ + nrfx_rramc_config_t config = NRFX_RRAMC_DEFAULT_CONFIG(WRITE_BUFFER_SIZE); + + config.mode_write = true; + +#if CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE > 0 + config.preload_timeout_enable = true; + config.preload_timeout = CONFIG_NRF_RRAM_READYNEXT_TIMEOUT_VALUE; +#else + config.preload_timeout_enable = false; + config.preload_timeout = 0; +#endif + + /* Don't use an event handler until it's understood whether we + * want it or not + */ + nrfx_rramc_evt_handler_t handler = NULL; + + nrfx_err_t err = nrfx_rramc_init(&config, handler); + if (err != NRFX_SUCCESS && err != NRFX_ERROR_ALREADY) { + return err; + } + + return NRFX_SUCCESS; +} + +enum tfm_plat_err_t init_debug(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +/*------------------- SAU/IDAU configuration functions -----------------------*/ + +void sau_and_idau_cfg(void) +{ + /* + * This SAU configuration aligns with ARM's RSS implementation of + * sau_and_idau_cfg when possible. + */ + + /* Enables SAU */ + TZ_SAU_Enable(); + + /* Configures SAU regions to be non-secure */ + + /* Note that this SAU configuration assumes that there is only one + * secure NVM partition and one non-secure NVM partition. Meaning, + * memory_regions.non_secure_partition_limit is at the end of + * NVM. + */ + + /* Configure the end of NVM, and the FICR, to be non-secure using + a single region. Note that the FICR is placed after the + non-secure NVM and before the UICR.*/ + SAU->RNR = 0; + SAU->RBAR = (memory_regions.non_secure_partition_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (NRF_UICR_S_BASE & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Leave SAU region 1 disabled until we find a use for it */ + + /* Configures veneers region to be non-secure callable */ + SAU->RNR = 2; + SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk | + SAU_RLAR_NSC_Msk; + + /* Configures SAU region 3 to cover both the end of SRAM and + * regions above it as shown in the "Example memory map" in the + * "Product Specification" */ + SAU->RNR = 3; + SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (0xFFFFFFFFul & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; +} + +enum tfm_plat_err_t nrf_mpc_init_cfg(void) +{ + /* On 54l the NRF_MPC00->REGION[]'s are fixed in HW and the + * OVERRIDE indexes (that are useful to us) start at 0 and end + * (inclusive) at 4. + * + * Note that the MPC regions configure all volatile and non-volatile memory as secure, so we + * only need to explicitly OVERRIDE the non-secure addresses to permit non-secure access. + * + * Explicitly configuring memory as secure is not necessary. + * + * The last OVERRIDE in 54L is fixed in HW and exists to prevent + * other bus masters than the KMU from accessing CRACEN protected RAM. + * + * Note that we must take care not to configure an OVERRIDE that + * affects an active bus transaction. + * + * Note that we don't configure the NSC region to be NS because + * from the MPC's perspective it is secure. NSC is only configurable from the SAU. + * + * Note that OVERRIDE[n].MASTERPORT has a reasonable reset value + * so it is left unconfigured. + * + * Note that there are two owners in 54L. KMU with owner ID 1, and everything else with + * owner ID 0. + */ + + uint32_t index = 0; + /* + * Configure the non-secure partition of the non-volatile + * memory. This MPC region is intended to cover both the + * non-secure partition in the NVM and also the FICR. The FICR + * starts after the NVM and ends just before the UICR. + */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = memory_regions.non_secure_partition_base; + override.endaddr = NRF_UICR_S_BASE; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + /* Configure the non-secure partition of the volatile memory */ + { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.start_address = NS_DATA_START; + override.endaddr = 1 + NS_DATA_LIMIT; + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + if (index > 4) { + /* Used more overrides than are available */ + tfm_core_panic(); + } + + /* Lock and disable any unused MPC overrides to prevent malicious configuration */ + while (index <= 4) { + struct mpc_region_override override; + + init_mpc_region_override(&override); + + override.config.enable = false; + + override.index = index++; + + mpc_configure_override(NRF_MPC00, &override); + } + + return TFM_PLAT_ERR_SUCCESS; +} + +void peripheral_configuration(void) +{ +#if SECURE_UART1 + /* Configure TF-M's UART peripheral to be secure */ +#if NRF_SECURE_UART_INSTANCE == 00 + uint32_t uart_periph_start = tfm_peripheral_uarte00.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 20 + uint32_t uart_periph_start = tfm_peripheral_uarte20.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 21 + uint32_t uart_periph_start = tfm_peripheral_uarte21.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 22 + uint32_t uart_periph_start = tfm_peripheral_uarte22.periph_start; +#elif NRF_SECURE_UART_INSTANCE == 30 + uint32_t uart_periph_start = tfm_peripheral_uarte30.periph_start; +#endif + spu_peripheral_config_secure(uart_periph_start, SPU_LOCK_CONF_LOCKED); +#endif /* SECURE_UART1 */ + + /* Configure the CTRL-AP mailbox interface to be secure as it is used by the secure ADAC + * service */ + spu_peripheral_config_secure(NRF_CTRLAP_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure NRF_MEMCONF to be secure as it could otherwise be used to corrupt secure RAM. + */ + spu_peripheral_config_secure(NRF_MEMCONF_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure trace to be secure, as the security implications of non-secure trace are not + * understood */ + spu_peripheral_config_secure(NRF_TAD_S_BASE, SPU_LOCK_CONF_LOCKED); + + /* Configure these HW features, which are not in the MDK, to be + * secure, as the security implications of them being non-secure + * are not understood + */ + uint32_t base_addresses[4] = {0x50056000, 0x5008C000, 0x500E6000, 0x5010F000}; + for (int i = 0; i < 4; i++) { + spu_peripheral_config_secure(base_addresses[i], SPU_LOCK_CONF_LOCKED); + } + + /* Configure NRF_REGULATORS, and NRF_OSCILLATORS to be secure as NRF_REGULATORS.POFCON is + * needed to prevent glitches when the power supply is attacked. + * + * NB: Note that NRF_OSCILLATORS and NRF_REGULATORS have the same base address and must + * therefore have the same security configuration. + */ + spu_peripheral_config_secure(NRF_REGULATORS_S_BASE, SPU_LOCK_CONF_LOCKED); +} + +static void gpiote_channel_configuration(void) +{ + /* Configure GPIOTE channels to be secure */ + uint32_t secure_gpiote_channels[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + uint32_t gpiote_instances[] = { +#if TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK + NRF_GPIOTE20_S_BASE, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK + NRF_GPIOTE30_S_BASE, +#endif + 0 /* Not used, its here to avoid compilation failures */ + }; + + /* Configure the SPU GPIOTE registers. Each GPIOTE can fire 2 interrupts for + * each available channel. If a channel is configured as secure both of the + * interrupts will only available in secure mode so a single configuration + * should suffice. + */ + for (int i = 0; i < ARRAY_SIZE(gpiote_instances) - 1; i++) { + + NRF_SPU_Type *spu_instance = spu_instance_from_peripheral_addr(gpiote_instances[i]); + for (int channel = 0; channel < NRF_SPU_FEATURE_GPIOTE_CHANNEL_COUNT; channel++) { + if (secure_gpiote_channels[i] & (1 << channel)) { + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_CHANNEL, 0, channel); + + nrf_spu_feature_secattr_set(spu_instance, + NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, + channel, true); + nrf_spu_feature_lock_enable( + spu_instance, NRF_SPU_FEATURE_GPIOTE_INTERRUPT, 0, channel); + } + } + } +} + +static void gpio_configuration(void) +{ + /* GPIO pin configuration */ + uint32_t secure_pins[] = { +#ifdef TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO1_PIN_MASK_SECURE, +#endif +#ifdef TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE + TFM_PERIPHERAL_GPIO2_PIN_MASK_SECURE, +#endif + }; + + for (int port = 0; port < ARRAY_SIZE(secure_pins); port++) { + for (int pin = 0; pin < 32; pin++) { + if (secure_pins[port] & (1 << pin)) { + bool enable = true; // secure + + /* + * Unfortunately, NRF_P0 is not configured by NRF_SPU00, etc. + * so it is a bit convoluted to find the SPU instance for port x. + */ + uint32_t gpio_port_addr[2] = { + NRF_P0_S_BASE, + NRF_P1_S_BASE, + }; + + NRF_SPU_Type *spu_instance = + spu_instance_from_peripheral_addr(gpio_port_addr[port]); + + nrf_spu_feature_secattr_set(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin, enable); + nrf_spu_feature_lock_enable(spu_instance, NRF_SPU_FEATURE_GPIO_PIN, + port, pin); + } + } + } + + /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal + * oscillator (LFXO) can be used. + * This configuration can be done only from secure code, as otherwise those + * register fields are not accessible. That's why it is placed here. + */ + nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_GPIO); + nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_GPIO); +} + +enum tfm_plat_err_t spu_periph_init_cfg(void) +{ + /* Peripheral configuration */ + /* Configure features to be non-secure */ + + /* + * Due to MLT-7600, many SPU HW reset values are wrong. The docs + * generally features being non-secure when coming out of HW + * reset, but the HW has a good mix of both. + * + * When configuring NRF_SPU 0 will indicate non-secure and 1 will + * indicate secure. + * + * Most of the chip should be non-secure so to simplify and be + * consistent, we memset the entire memory map of each SPU + * peripheral to 0. + * + * Just after memsetting to 0 we explicitly configure the + * peripherals that should be secure back to secure again. + */ + // TODO: Evaluate if it is safe to memset everything + // in NRF_SPU to 0. + memset(NRF_SPU00, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU10, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU20, 0, sizeof(NRF_SPU_Type)); + memset(NRF_SPU30, 0, sizeof(NRF_SPU_Type)); + + peripheral_configuration(); + + /* TODO_NRF54L15: Use the nrf_spu_feature API to configure DPPI + channels according to a user-controllable config similar to + TFM_PERIPHERAL_DPPI_CHANNEL_MASK_SECURE. */ + + gpiote_channel_configuration(); + gpio_configuration(); + +#if defined(NRF_TAMPC_ENABLE) + tampc_configuration(); +#endif + + nrf_cache_enable(NRF_ICACHE); + + nrfx_err_t nrfx_err = rramc_configuration(); + if (nrfx_err != NRFX_SUCCESS) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* SOC configuration from Zephyr's soc.c. */ + int soc_err = nordicsemi_nrf54l_init(); + if (soc_err) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + return TFM_PLAT_ERR_SUCCESS; +} + + +/*----------------- NVIC interrupt target state to NS configuration ----------*/ +enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void) +{ + /* Target every interrupt to NS; unimplemented interrupts will be Write-Ignored */ + for (uint8_t i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { + NVIC->ITNS[i] = 0xFFFFFFFF; + } + + /* Make sure that the SPU instance(s) are targeted to S state */ + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_CRACEN)); + NVIC_ClearTargetState(MPC00_IRQn); + NVIC_ClearTargetState(NRFX_IRQ_NUMBER_GET(NRF_TAMPC)); + +#ifdef SECURE_UART1 + /* IRQ for the selected secure UART has to target S state */ + NVIC_ClearTargetState( + NRFX_IRQ_NUMBER_GET(NRF_UARTE_INSTANCE_GET(NRF_SECURE_UART_INSTANCE))); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} + +/*----------------- NVIC interrupt enabling for S peripherals ----------------*/ +enum tfm_plat_err_t nvic_interrupt_enable(void) +{ + /* SPU interrupt enabling */ + spu_enable_interrupts(); + + for (int i = 0; i < ARRAY_SIZE(spu_instances); i++) { + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(spu_instances[i])); + } + + mpc_clear_events(); + /* MPC interrupt enabling */ + mpc_enable_interrupts(); + + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_MPC00)); + + /* The CRACEN driver configures the NVIC for CRACEN and is + * therefore omitted here. + */ + +#if defined(NRF_TAMPC_ENABLE) + tampc_enable_interrupts(); + NVIC_ClearPendingIRQ(NRFX_IRQ_NUMBER_GET(NRF_TAMPC)); + NVIC_EnableIRQ(NRFX_IRQ_NUMBER_GET(NRF_TAMPC)); +#endif + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c index 69411eaed..33b1d0376 100644 --- a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c +++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c @@ -50,9 +50,16 @@ enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( /* Set up isolation boundaries between SPE and NSPE */ sau_and_idau_cfg(); +#if NRF_SPU_HAS_MEMORY if (spu_init_cfg() != TFM_PLAT_ERR_SUCCESS) { return TFM_HAL_ERROR_GENERIC; } +#else + /* If the SPU doesn't configure MEMORY on this platform then the NRF_MPC does */ + if (nrf_mpc_init_cfg() != TFM_PLAT_ERR_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } +#endif if (spu_periph_init_cfg() != TFM_PLAT_ERR_SUCCESS) { return TFM_HAL_ERROR_GENERIC; @@ -124,7 +131,7 @@ tfm_hal_bind_boundary(const struct partition_load_info_t *p_ldinf, continue; } - spu_peripheral_config_secure(NRFX_PERIPHERAL_ID_GET(plat_data_ptr->periph_start), + spu_peripheral_config_secure(plat_data_ptr->periph_start, SPU_LOCK_CONF_LOCKED); /* diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption.c index 6e2b097d4..5ac449cb2 100644 --- a/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption.c +++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Nordic Semiconductor ASA. + * Copyright (c) 2024, Arm Limited. All rights reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -112,7 +113,7 @@ static bool ctx_is_valid(struct tfm_hal_its_auth_crypt_ctx *ctx) } ret = (ctx->deriv_label == NULL && ctx->deriv_label_size != 0) || - (ctx->aad == NULL && ctx->add_size != 0) || + (ctx->aad == NULL && ctx->aad_size != 0) || (ctx->nonce == NULL && ctx->nonce_size != 0); return !ret; @@ -153,7 +154,7 @@ static enum tfm_hal_status_t tfm_hal_its_aead_init( ctx->nonce, ctx->nonce_size, ctx->aad, - ctx->add_size, + ctx->aad_size, tag, tag_size); if (err != NRF_CC3XX_PLATFORM_SUCCESS) { diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption_cracen.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption_cracen.c new file mode 100644 index 000000000..3e636a019 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_its_encryption_cracen.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "config_tfm.h" +#include "platform/include/tfm_hal_its_encryption.h" +#include "platform/include/tfm_hal_its.h" + +typedef uint64_t psa_drv_slot_number_t; +#include +#include + + +#define CHACHA20_KEY_SIZE 32 +#define TFM_ITS_AEAD_ALG PSA_ALG_CHACHA20_POLY1305 + + +/* Global encryption counter which resets per boot. The counter ensures that + * the nonce will not be identical for consecutive file writes during the same + * boot. + */ +static uint32_t g_enc_counter; + +/* The global nonce seed which is fetched once in every boot. The seed is used + * as part of the nonce and allows the platforms to diversify their nonces + * across resets. Note that the way that this seed is generated is platform + * specific, so the diversification is optional. + */ +static uint8_t g_enc_nonce_seed[TFM_ITS_ENC_NONCE_LENGTH - + sizeof(g_enc_counter)]; + +/* TFM_ITS_ENC_NONCE_LENGTH is configurable but this implementation expects + * the seed to be 8 bytes and the nonce length to be 12. + */ +#if TFM_ITS_ENC_NONCE_LENGTH != 12 +#error "This implementation only supports a ITS nonce of size 12" +#endif + +/* + * This implementation doesn't use monotonic counters, but therfore a 64 bit + * seed combined with a counter, that gets reset on each reboot. + * This still has the risk of getting a collision on the seed resulting in + * nonce's beeing the same after a reboot. + * It would still need 3.3x10^9 resets to get a collision with a probability of + * 0.25. + */ +enum tfm_hal_status_t tfm_hal_its_aead_generate_nonce(uint8_t *nonce, + const size_t nonce_size) +{ + if(nonce == NULL){ + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if(nonce_size < sizeof(g_enc_nonce_seed) + sizeof(g_enc_counter)){ + return TFM_HAL_ERROR_INVALID_INPUT; + } + + /* To avoid wrap-around of the g_enc_counter and subsequent re-use of the + * nonce we check the counter value for its max value + */ + if(g_enc_counter == UINT32_MAX) { + return TFM_HAL_ERROR_GENERIC; + } + + if (g_enc_counter == 0) { + psa_status_t status = cracen_get_random(NULL, g_enc_nonce_seed, sizeof(g_enc_nonce_seed)); + if (status != PSA_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + } + + memcpy(nonce, g_enc_nonce_seed, sizeof(g_enc_nonce_seed)); + memcpy(nonce + sizeof(g_enc_nonce_seed), + &g_enc_counter, + sizeof(g_enc_counter)); + + g_enc_counter++; + + return TFM_HAL_SUCCESS; +} + +static bool ctx_is_valid(struct tfm_hal_its_auth_crypt_ctx *ctx) +{ + bool ret; + + if (ctx == NULL) { + return false; + } + + ret = (ctx->deriv_label == NULL && ctx->deriv_label_size != 0) || + (ctx->aad == NULL && ctx->aad_size != 0) || + (ctx->nonce == NULL && ctx->nonce_size != 0); + + return !ret; +} + +psa_status_t tfm_hal_its_get_aead(struct tfm_hal_its_auth_crypt_ctx *ctx, + const uint8_t *input, + const size_t input_size, + uint8_t *output, + const size_t output_size, + uint8_t *tag, + const size_t tag_size, + bool encrypt) +{ + psa_status_t status; + uint8_t key_out[CHACHA20_KEY_SIZE]; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + cracen_aead_operation_t operation = {0}; + size_t out_length; + size_t tag_length = PSA_AEAD_TAG_LENGTH(PSA_KEY_TYPE_CHACHA20, + PSA_BYTES_TO_BITS(CHACHA20_KEY_SIZE), + TFM_ITS_AEAD_ALG); + + if (!ctx_is_valid(ctx) || tag == NULL) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if(tag_size < tag_length){ + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (encrypt && (output_size < PSA_AEAD_UPDATE_OUTPUT_SIZE(PSA_KEY_TYPE_CHACHA20, + TFM_ITS_AEAD_ALG, + input_size))){ + return TFM_HAL_ERROR_INVALID_INPUT; + } + + status = hw_unique_key_derive_key(HUK_KEYSLOT_MKEK, NULL, 0, ctx->deriv_label, ctx->deriv_label_size, key_out, sizeof(key_out)); + if (status != HW_UNIQUE_KEY_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + psa_set_key_usage_flags(&attributes, (PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT)); + psa_set_key_algorithm(&attributes, TFM_ITS_AEAD_ALG); + psa_set_key_type(&attributes, PSA_KEY_TYPE_CHACHA20); + psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(CHACHA20_KEY_SIZE)); + + if (encrypt) { + status = cracen_aead_encrypt_setup(&operation, &attributes, key_out, sizeof(key_out), TFM_ITS_AEAD_ALG); + } else { + status = cracen_aead_decrypt_setup(&operation, &attributes, key_out, sizeof(key_out), TFM_ITS_AEAD_ALG); + } + + if (status != PSA_SUCCESS) { + return status; + } + + status = cracen_aead_set_nonce(&operation, ctx->nonce, ctx->nonce_size); + if (status != PSA_SUCCESS) { + return status; + } + + status = cracen_aead_update_ad(&operation, ctx->aad, ctx->aad_size); + if (status != PSA_SUCCESS) { + return status; + } + + status = cracen_aead_update(&operation, input, input_size, output, output_size, &out_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (encrypt) { + status = cracen_aead_finish(&operation, output + out_length, output_size - out_length, &out_length, tag, tag_size, &tag_length); + } else { + status = cracen_aead_verify(&operation, output + out_length, output_size - out_length, &out_length , tag, tag_size); + } + + return status; +} + +enum tfm_hal_status_t tfm_hal_its_aead_encrypt(struct tfm_hal_its_auth_crypt_ctx *ctx, + const uint8_t *plaintext, + const size_t plaintext_size, + uint8_t *ciphertext, + const size_t ciphertext_size, + uint8_t *tag, + const size_t tag_size) +{ + psa_status_t status = tfm_hal_its_get_aead(ctx, + plaintext, + plaintext_size, + ciphertext, + ciphertext_size, + tag, + tag_size, + true); + if (status != PSA_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + return TFM_HAL_SUCCESS; +} + +enum tfm_hal_status_t tfm_hal_its_aead_decrypt(struct tfm_hal_its_auth_crypt_ctx *ctx, + const uint8_t *ciphertext, + const size_t ciphertext_size, + uint8_t *tag, + const size_t tag_size, + uint8_t *plaintext, + const size_t plaintext_size) +{ + psa_status_t status = tfm_hal_its_get_aead(ctx, + ciphertext, + ciphertext_size, + plaintext, + plaintext_size, + tag, + tag_size, + false); + + if (status != PSA_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + return TFM_HAL_SUCCESS; +} diff --git a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt index 84f0bf0f6..7ef642dcf 100644 --- a/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf5340/CMakeLists.txt @@ -63,5 +63,6 @@ install(FILES nrfx_config_nrf5340_application.h ) install(DIRECTORY tests + partition DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf5340 ) diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h similarity index 100% rename from platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/partition/flash_layout.h rename to platform/ext/target/nordic_nrf/common/nrf5340/partition/flash_layout.h diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h similarity index 97% rename from platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/partition/region_defs.h rename to platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h index 7db37f89b..e8ef168b8 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf5340/partition/region_defs.h @@ -190,6 +190,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT /* Regions used by psa-arch-tests to keep state */ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake new file mode 100644 index 000000000..e35ee17eb --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/config.cmake @@ -0,0 +1,14 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/config.cmake) + +set(SECURE_UART30 ON CACHE BOOL "Enable secure UART" FORCE) +set(BL2 OFF CACHE BOOL "Whether to build BL2" FORCE) +set(NRF_NS_SECONDARY OFF CACHE BOOL "Enable non-secure secondary partition" FORCE) +set(NRF_SECURE_UART_INSTANCE 30 CACHE STRING "The UART instance number to use for secure UART" FORCE) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h new file mode 100644 index 000000000..dc66ce12f --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/mmio_defs.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * + */ + +#ifndef __MMIO_DEFS_H__ +#define __MMIO_DEFS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "handle_attr.h" +#include "tfm_peripherals_config.h" +#include "tfm_peripherals_def.h" +#include + +/* Allowed named MMIO of this platform */ +const uintptr_t partition_named_mmio_list[] = { +#if TFM_PERIPHERAL_TIMER00_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER00, +#endif +#if TFM_PERIPHERAL_TIMER10_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER10, +#endif +#if TFM_PERIPHERAL_TIMER20_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER20, +#endif +#if TFM_PERIPHERAL_TIMER21_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER21, +#endif +#if TFM_PERIPHERAL_TIMER22_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER22, +#endif +#if TFM_PERIPHERAL_TIMER23_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER23, +#endif +#if TFM_PERIPHERAL_TIMER24_SECURE + (uintptr_t)TFM_PERIPHERAL_TIMER24, +#endif +#if TFM_PERIPHERAL_SPIM00_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM00, +#endif +#if TFM_PERIPHERAL_SPIM20_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM20, +#endif +#if TFM_PERIPHERAL_SPIM21_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM21, +#endif +#if TFM_PERIPHERAL_SPIM22_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM22, +#endif +#if TFM_PERIPHERAL_SPIM23_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM23, +#endif +#if TFM_PERIPHERAL_SPIM30_SECURE + (uintptr_t)TFM_PERIPHERAL_SPIM30, +#endif +#if TFM_PERIPHERAL_EGU10_SECURE + (uintptr_t)TFM_PERIPHERAL_EGU10, +#endif +#if TFM_PERIPHERAL_EGU20_SECURE + (uintptr_t)TFM_PERIPHERAL_EGU20, +#endif +#if TFM_PERIPHERAL_PWM20_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM20, +#endif +#if TFM_PERIPHERAL_PWM21_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM21, +#endif +#if TFM_PERIPHERAL_PWM22_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM22, +#endif +#if TFM_PERIPHERAL_PWM20_SECURE + (uintptr_t)TFM_PERIPHERAL_PWM20, +#endif +#if TFM_PERIPHERAL_UARTE00_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE00, +#endif +#if TFM_PERIPHERAL_UARTE20_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE20, +#endif +#if TFM_PERIPHERAL_UARTE21_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE21, +#endif +#if TFM_PERIPHERAL_UARTE22_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE22, +#endif +#if TFM_PERIPHERAL_UARTE30_SECURE + (uintptr_t)TFM_PERIPHERAL_UARTE30, +#endif +#if TFM_PERIPHERAL_GPIOTE20_SECURE + (uintptr_t)TFM_PERIPHERAL_GPIOTE20, +#endif +#if TFM_PERIPHERAL_GPIOTE30_SECURE + (uintptr_t)TFM_PERIPHERAL_GPIOTE30, +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __MMIO_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c new file mode 100644 index 000000000..54d14aa3e --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrf54l_init.c @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include + +#ifndef BIT_MASK +/* Use Zephyr BIT_MASK for unasigned integers */ +#define BIT_MASK(n) ((1UL << (n)) - 1UL) +#endif + +/* This handler needs to be ported to the upstream TF-M project when Cracen is supported there. + * The implementation of this is currently in sdk-nrf. We define it to avoid warnings when we build + * the target_cfg.c file which is the same for both upsteam TF-M and sdk-nrf. + * It is defined as weak to allow the sdk-nrf version to be used when available. */ +void __attribute__((weak)) CRACEN_IRQHandler(void){}; + +/* This is a simplified version of the function existing in the Zephyr's soc.c file for + * the nRF54L15. + * This function only supports one static configuration. + * It is defined as weak to allow the sdk-nrf version to be used when available. + * + * The LFXO, HFXO configuration are taken from a sample build in sdk-nrf with the following + * properties: + * + * lfxo: lfxo { + * compatible = "nordic,nrf-lfxo"; + * #clock-cells = < 0x0 >; + * clock-frequency = < 0x8000 >; + * load-capacitors = "internal"; + * load-capacitance-femtofarad = < 0x3c8c >; + * phandle = < 0xc >; + * }; + * hfxo: hfxo { + * compatible = "nordic,nrf-hfxo"; + * #clock-cells = < 0x0 >; + * clock-frequency = < 0x1e84800 >; + * load-capacitors = "internal"; + * load-capacitance-femtofarad = < 0x3a98 >; + * phandle = < 0x6 >; + * }; + * + * The CONFIG_SOC_NRF_FORCE_CONSTLAT is not enabled. + * + * The following vreg configuration is supported: + * + * vregmain: regulator@120600 { + * compatible = "nordic,nrf5x-regulator"; + * reg = < 0x120600 0x1 >; + * status = "okay"; + * regulator-name = "VREGMAIN"; + * regulator-initial-mode = < 0x1 >; # 1 means NRF5X_REG_MODE_DCDC + * }; + * And the NRF54L_ERRATA_31_ENABLE_WORKAROUND is enabled. + * + */ +int __attribute__((weak)) nordicsemi_nrf54l_init(void){ + uint32_t xosc32ktrim = NRF_FICR->XOSC32KTRIM; + + uint32_t offset_k = + (xosc32ktrim & FICR_XOSC32KTRIM_OFFSET_Msk) >> FICR_XOSC32KTRIM_OFFSET_Pos; + + uint32_t slope_field_k = + (xosc32ktrim & FICR_XOSC32KTRIM_SLOPE_Msk) >> FICR_XOSC32KTRIM_SLOPE_Pos; + uint32_t slope_mask_k = FICR_XOSC32KTRIM_SLOPE_Msk >> FICR_XOSC32KTRIM_SLOPE_Pos; + uint32_t slope_sign_k = (slope_mask_k - (slope_mask_k >> 1)); + int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k; + + /* As specified in the nRF54L15 PS: + * CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9) + * + FICR->XOSC32KTRIM.OFFSET/(2^6) ); + * where CAPACITANCE is the desired capacitor value in pF, holding any + * value between 4 pF and 18 pF in 0.5 pF steps. + */ + + /* Encoding of desired capacitance (single ended) to value required for INTCAP core + * calculation: (CAP_VAL - 4 pF)* 0.5 + * That translate to ((CAP_VAL_FEMTO_F - 4000fF) * 2UL) / 1000UL + * + * NOTE: The desired capacitance value is used in encoded from in INTCAP calculation formula + * That is different than in case of HFXO. + */ + uint32_t cap_val_encoded = + (((0x3c8c - 4000UL) * 2UL) / 1000UL); + + /* Calculation of INTCAP code before rounding. Min that calculations here are done on + * values multiplied by 2^9, e.g. 0.765625 * 2^9 = 392. + * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to + * multiply it be 2^3. + */ + uint32_t mid_val = + (cap_val_encoded - 4UL) * (uint32_t)(slope_k + 392UL) + (offset_k << 3UL); + + /* Get integer part of the INTCAP code */ + uint32_t lfxo_intcap = mid_val >> 9UL; + + /* Round based on fractional part */ + if ((mid_val & BIT_MASK(9)) > (BIT_MASK(9) / 2)) { + lfxo_intcap++; + } + + nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, lfxo_intcap); + + uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM; + /* The SLOPE field is in the two's complement form, hence this special + * handling. Ideally, it would result in just one SBFX instruction for + * extracting the slope value, at least gcc is capable of producing such + * output, but since the compiler apparently tries first to optimize + * additions and subtractions, it generates slightly less than optimal + * code. + */ + uint32_t slope_field = + (xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk) >> FICR_XOSC32MTRIM_SLOPE_Pos; + uint32_t slope_mask = FICR_XOSC32MTRIM_SLOPE_Msk >> FICR_XOSC32MTRIM_SLOPE_Pos; + uint32_t slope_sign = (slope_mask - (slope_mask >> 1)); + int32_t slope_m = (int32_t)(slope_field ^ slope_sign) - (int32_t)slope_sign; + uint32_t offset_m = + (xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk) >> FICR_XOSC32MTRIM_OFFSET_Pos; + /* As specified in the nRF54L15 PS: + * CAPVALUE = (((CAPACITANCE-5.5)*(FICR->XOSC32MTRIM.SLOPE+791)) + + * FICR->XOSC32MTRIM.OFFSET<<2)>>8; + * where CAPACITANCE is the desired total load capacitance value in pF, + * holding any value between 4.0 pF and 17.0 pF in 0.25 pF steps. + */ + + /* NOTE 1: Requested HFXO internal capacitance in femto Faradas is used directly in formula + * to calculate INTCAP code. That is different than in case of LFXO. + * + * NOTE 2: PS formula uses piko Farads, the implementation of the formula uses femto Farads + * to avoid use of floating point data type. + */ + uint32_t cap_val_femto_f = 0x3a98; + + uint32_t mid_val_intcap = (((cap_val_femto_f - 5500UL) * (uint32_t)(slope_m + 791UL)) + + (offset_m << 2UL) * 1000UL) >> + 8UL; + + /* Convert the calculated value to piko Farads */ + uint32_t hfxo_intcap = mid_val_intcap / 1000; + + /* Round based on fractional part */ + if (mid_val_intcap % 1000 >= 500) { + hfxo_intcap++; + } + + nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, hfxo_intcap); + + /* Workaround for Errata 31 */ + if (nrf54l_errata_31()) { + *((volatile uint32_t *)0x50120624ul) = 20 | 1<<5; + *((volatile uint32_t *)0x5012063Cul) &= ~(1<<19); + } + + + return 0; +} diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h new file mode 100644 index 000000000..814f022b4 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/nrfx_config_nrf54l.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRFX_CONFIG_NRF54L15_APPLICATION_H__ +#define NRFX_CONFIG_NRF54L15_APPLICATION_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +/** + * @brief NRFX_DEFAULT_IRQ_PRIORITY + * + * Integer value. Minimum: 0 Maximum: 7 + */ +#ifndef NRFX_DEFAULT_IRQ_PRIORITY +#define NRFX_DEFAULT_IRQ_PRIORITY 7 +#endif + +/** + * @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0 Maximum: 7 + */ +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RRAMC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RRAMC_ENABLED +#define NRFX_RRAMC_ENABLED 0 +#endif + +/** + * @brief NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY + * + * Integer value. Minimum: 0. Maximum: 7. + */ +#ifndef NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RRAMC_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY +#endif + +/** + * @brief NRFX_RRAMC_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRFX_RRAMC_CONFIG_LOG_ENABLED +#define NRFX_RRAMC_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_RRAMC_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_RRAMC_CONFIG_LOG_LEVEL +#define NRFX_RRAMC_CONFIG_LOG_LEVEL 3 +#endif + +#endif // NRFX_CONFIG_NRF54L15_APPLICATION_H__ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c new file mode 100644 index 000000000..b3bca1bfc --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_interrupts.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include + +#include "cmsis.h" +#include "spm.h" +#include "tfm_hal_interrupt.h" +#include "tfm_peripherals_def.h" +#include "tfm_peripherals_config.h" +#include "load/interrupt_defs.h" +#include "interrupt.h" + +static enum tfm_hal_status_t irq_init(struct irq_t *irq, IRQn_Type irqn, + void * p_pt, + const struct irq_load_info_t *p_ildi) +{ + irq->p_ildi = p_ildi; + irq->p_pt = p_pt; + + NVIC_SetPriority(irqn, DEFAULT_IRQ_PRIORITY); + NVIC_ClearTargetState(irqn); + NVIC_DisableIRQ(irqn); + + return TFM_HAL_SUCCESS; +} + +#if TFM_PERIPHERAL_FPU_SECURE +static struct irq_t fpu_irq = {0}; + +void FPU_IRQHandler(void) +{ + spm_handle_interrupt(fpu_irq.p_pt, fpu_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_fpu_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&fpu_irq, TFM_FPU_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER00_SECURE +static struct irq_t timer00_irq = {0}; + +void TIMER00_IRQHandler(void) +{ + spm_handle_interrupt(timer00_irq.p_pt, timer00_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer00_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer00_irq, TFM_TIMER00_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER10_SECURE +static struct irq_t timer10_irq = {0}; + +void TIMER10_IRQHandler(void) +{ + spm_handle_interrupt(timer10_irq.p_pt, timer10_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer10_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer10_irq, TFM_TIMER10_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER20_SECURE +static struct irq_t timer20_irq = {0}; + +void TIMER20_IRQHandler(void) +{ + spm_handle_interrupt(timer20_irq.p_pt, timer20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer20_irq, TFM_TIMER20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER21_SECURE +static struct irq_t timer21_irq = {0}; + +void TIMER21_IRQHandler(void) +{ + spm_handle_interrupt(timer21_irq.p_pt, timer21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer21_irq, TFM_TIMER21_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER22_SECURE +static struct irq_t timer22_irq = {0}; + +void TIMER22_IRQHandler(void) +{ + spm_handle_interrupt(timer22_irq.p_pt, timer22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer22_irq, TFM_TIMER22_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER23_SECURE +static struct irq_t timer23_irq = {0}; + +void TIMER23_IRQHandler(void) +{ + spm_handle_interrupt(timer23_irq.p_pt, timer23_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer23_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer23_irq, TFM_TIMER23_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_TIMER24_SECURE +static struct irq_t timer24_irq = {0}; + +void TIMER24_IRQHandler(void) +{ + spm_handle_interrupt(timer24_irq.p_pt, timer24_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_timer24_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&timer24_irq, TFM_TIMER24_IRQ, p_pt, p_ildi); +} +#endif + +/* By NRFX convention GPIOTE interrupt 1 targets secure, while 0 targets non-secure. */ +static struct irq_t gpiote20_1_irq = {0}; + +void GPIOTE20_1_IRQHandler(void) +{ + spm_handle_interrupt(gpiote20_1_irq.p_pt, gpiote20_1_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_gpiote20_1_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&gpiote20_1_irq, TFM_GPIOTE20_1_IRQ, p_pt, p_ildi); +} + +/* By NRFX convention GPIOTE interrupt 1 targets secure, while 0 targets non-secure. */ +static struct irq_t gpiote30_1_irq = {0}; + +void GPIOTE30_1_IRQHandler(void) +{ + spm_handle_interrupt(gpiote30_1_irq.p_pt, gpiote30_1_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_gpiote30_1_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&gpiote30_1_irq, TFM_GPIOTE30_1_IRQ, p_pt, p_ildi); +} + +#if TFM_PERIPHERAL_SPIM00_SECURE +static struct irq_t spim00_irq = {0}; + +void SPIM00_IRQHandler(void) +{ + spm_handle_interrupt(spim00_irq.p_pt, spim00_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim00_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim00_irq, TFM_SPIM00_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM22_SECURE +static struct irq_t spim22_irq = {0}; + +void SPIM22_IRQHandler(void) +{ + spm_handle_interrupt(spim22_irq.p_pt, spim22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim22_irq, TFM_SPIM22_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM23_SECURE +static struct irq_t spim23_irq = {0}; + +void SPIM23_IRQHandler(void) +{ + spm_handle_interrupt(spim23_irq.p_pt, spim23_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim23_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim23_irq, TFM_SPIM23_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_SPIM30_SECURE +static struct irq_t spim30_irq = {0}; + +void SPIM30_IRQHandler(void) +{ + spm_handle_interrupt(spim30_irq.p_pt, spim30_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_spim30_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&spim30_irq, TFM_SPIM30_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_EGU10_SECURE +static struct irq_t egu10_irq = {0}; + +void EGU10_IRQHandler(void) +{ + spm_handle_interrupt(egu10_irq.p_pt, egu10_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_egu10_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&egu10_irq, TFM_EGU10_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_EGU20_SECURE +static struct irq_t egu20_irq = {0}; + +void EGU20_IRQHandler(void) +{ + spm_handle_interrupt(egu20_irq.p_pt, egu20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_egu20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&egu20_irq, TFM_EGU20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM20_SECURE +static struct irq_t pwm20_irq = {0}; + +void PWM20_IRQHandler(void) +{ + spm_handle_interrupt(pwm20_irq.p_pt, pwm20_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm20_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm20_irq, TFM_PWM20_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM21_SECURE +static struct irq_t pwm21_irq = {0}; + +void PWM21_IRQHandler(void) +{ + spm_handle_interrupt(pwm21_irq.p_pt, pwm21_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm21_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm21_irq, TFM_PWM21_IRQ, p_pt, p_ildi); +} +#endif + +#if TFM_PERIPHERAL_PWM22_SECURE +static struct irq_t pwm22_irq = {0}; + +void PWM22_IRQHandler(void) +{ + spm_handle_interrupt(pwm22_irq.p_pt, pwm22_irq.p_ildi); +} + +enum tfm_hal_status_t tfm_pwm22_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + return irq_init(&pwm22_irq, TFM_PWM22_IRQ, p_pt, p_ildi); +} +#endif + +#ifdef PSA_API_TEST_IPC +enum tfm_hal_status_t ff_test_uart_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +__attribute__((alias("tfm_egu10_irq_init"))); + +#endif diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h new file mode 100644 index 000000000..a03b92d31 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_config_nrf54l.h @@ -0,0 +1,40 @@ + +#ifndef TFM_PERIPHERAL_TIMER00_SECURE +#define TFM_PERIPHERAL_TIMER00_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE00_SECURE +#define TFM_PERIPHERAL_UARTE00_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE20_SECURE +#define TFM_PERIPHERAL_UARTE20_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE21_SECURE +#define TFM_PERIPHERAL_UARTE21_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE22_SECURE +#define TFM_PERIPHERAL_UARTE22_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_UARTE30_SECURE +#define TFM_PERIPHERAL_UARTE30_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE20_SECURE +#define TFM_PERIPHERAL_GPIOTE20_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK +#define TFM_PERIPHERAL_GPIOTE20_SECURE_CHANNELS_MASK 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE30_SECURE +#define TFM_PERIPHERAL_GPIOTE30_SECURE 0 +#endif + +#ifndef TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK +#define TFM_PERIPHERAL_GPIOTE30_SECURE_CHANNELS_MASK 0 +#endif diff --git a/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h new file mode 100644 index 000000000..77227a3fb --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l/tfm_peripherals_def.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define TFM_FPU_IRQ (NRFX_IRQ_NUMBER_GET(NRF_FPU)) +#define TFM_TIMER00_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER00)) +#define TFM_TIMER10_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER10)) +#define TFM_TIMER20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER20)) +#define TFM_TIMER21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER21)) +#define TFM_TIMER22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER22)) +#define TFM_TIMER23_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER23)) +#define TFM_TIMER24_IRQ (NRFX_IRQ_NUMBER_GET(NRF_TIMER24)) +#define TFM_SPIM00_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM00)) +#define TFM_SPIM20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM20)) +#define TFM_SPIM21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM21)) +#define TFM_SPIM22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM22)) +#define TFM_SPIM23_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM23)) +#define TFM_SPIM30_IRQ (NRFX_IRQ_NUMBER_GET(NRF_SPIM30)) +#define TFM_EGU10_IRQ (NRFX_IRQ_NUMBER_GET(NRF_EGU10)) +#define TFM_EGU20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_EGU20)) +#define TFM_GPIOTE20_1_IRQ GPIOTE20_1_IRQn +#define TFM_GPIOTE30_1_IRQ GPIOTE30_1_IRQn +#define TFM_PWM20_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM20)) +#define TFM_PWM21_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM21)) +#define TFM_PWM22_IRQ (NRFX_IRQ_NUMBER_GET(NRF_PWM22)) + +extern struct platform_data_t tfm_peripheral_timer00; +extern struct platform_data_t tfm_peripheral_timer10; +extern struct platform_data_t tfm_peripheral_timer20; +extern struct platform_data_t tfm_peripheral_timer21; +extern struct platform_data_t tfm_peripheral_timer22; +extern struct platform_data_t tfm_peripheral_timer23; +extern struct platform_data_t tfm_peripheral_timer24; +extern struct platform_data_t tfm_peripheral_spim00; +extern struct platform_data_t tfm_peripheral_spim20; +extern struct platform_data_t tfm_peripheral_spim21; +extern struct platform_data_t tfm_peripheral_spim22; +extern struct platform_data_t tfm_peripheral_spim23; +extern struct platform_data_t tfm_peripheral_spim30; +extern struct platform_data_t tfm_peripheral_egu10; +extern struct platform_data_t tfm_peripheral_egu20; +extern struct platform_data_t tfm_peripheral_gpiote20; +extern struct platform_data_t tfm_peripheral_gpiote30; +extern struct platform_data_t tfm_peripheral_pwm20; +extern struct platform_data_t tfm_peripheral_pwm21; +extern struct platform_data_t tfm_peripheral_pwm22; + +#define TFM_PERIPHERAL_TIMER00 (&tfm_peripheral_timer00) +#define TFM_PERIPHERAL_TIMER10 (&tfm_peripheral_timer10) +#define TFM_PERIPHERAL_TIMER20 (&tfm_peripheral_timer20) +#define TFM_PERIPHERAL_TIMER21 (&tfm_peripheral_timer21) +#define TFM_PERIPHERAL_TIMER22 (&tfm_peripheral_timer22) +#define TFM_PERIPHERAL_TIMER23 (&tfm_peripheral_timer23) +#define TFM_PERIPHERAL_TIMER24 (&tfm_peripheral_timer24) +#define TFM_PERIPHERAL_SPIM00 (&tfm_peripheral_spim00) +#define TFM_PERIPHERAL_SPIM20 (&tfm_peripheral_spim20) +#define TFM_PERIPHERAL_SPIM21 (&tfm_peripheral_spim21) +#define TFM_PERIPHERAL_SPIM22 (&tfm_peripheral_spim22) +#define TFM_PERIPHERAL_SPIM23 (&tfm_peripheral_spim23) +#define TFM_PERIPHERAL_SPIM30 (&tfm_peripheral_spim30) +#define TFM_PERIPHERAL_EGU10 (&tfm_peripheral_egu10) +#define TFM_PERIPHERAL_EGU20 (&tfm_peripheral_egu20) +#define TFM_PERIPHERAL_GPIOTE20 (&tfm_peripheral_gpiote20) +#define TFM_PERIPHERAL_GPIOTE30 (&tfm_peripheral_gpiote30) +#define TFM_PERIPHERAL_PWM20 (&tfm_peripheral_pwm20) +#define TFM_PERIPHERAL_PWM21 (&tfm_peripheral_pwm21) +#define TFM_PERIPHERAL_PWM22 (&tfm_peripheral_pwm22) + +/* + * Quantized default IRQ priority, the value is: + * (Number of configurable priority) / 4: (1UL << __NVIC_PRIO_BITS) / 4 + */ +#define DEFAULT_IRQ_PRIORITY (1UL << (__NVIC_PRIO_BITS - 2)) + +extern struct platform_data_t tfm_peripheral_uarte00; +extern struct platform_data_t tfm_peripheral_uarte20; +extern struct platform_data_t tfm_peripheral_uarte21; +extern struct platform_data_t tfm_peripheral_uarte22; +extern struct platform_data_t tfm_peripheral_uarte30; + +#define TFM_PERIPHERAL_UARTE00 (&tfm_peripheral_uarte00) +#define TFM_PERIPHERAL_UARTE20 (&tfm_peripheral_uarte20) +#define TFM_PERIPHERAL_UARTE21 (&tfm_peripheral_uarte21) +#define TFM_PERIPHERAL_UARTE22 (&tfm_peripheral_uarte22) +#define TFM_PERIPHERAL_UARTE30 (&tfm_peripheral_uarte30) + +#define TFM_PERIPHERAL_STD_UART TFM_PERIPHERAL_UARTE30 + +extern struct platform_data_t tfm_peripheral_uarte00; +extern struct platform_data_t tfm_peripheral_uarte20; +extern struct platform_data_t tfm_peripheral_uarte21; +extern struct platform_data_t tfm_peripheral_uarte22; +extern struct platform_data_t tfm_peripheral_uarte30; + +#define TFM_PERIPHERAL_UARTE00 (&tfm_peripheral_uarte00) +#define TFM_PERIPHERAL_UARTE20 (&tfm_peripheral_uarte20) +#define TFM_PERIPHERAL_UARTE21 (&tfm_peripheral_uarte21) +#define TFM_PERIPHERAL_UARTE22 (&tfm_peripheral_uarte22) +#define TFM_PERIPHERAL_UARTE30 (&tfm_peripheral_uarte30) + +#define TFM_PERIPHERAL_STD_UART TFM_PERIPHERAL_UARTE30 + +#ifdef PSA_API_TEST_IPC +/* see other platforms when supporting this */ +#error "Not supported yet" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt new file mode 100644 index 000000000..bfde663af --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l10 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake new file mode 100644 index 000000000..2222734d2 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake new file mode 100644 index 000000000..ddd6400b4 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54L10_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt new file mode 100644 index 000000000..6e8396c35 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h new file mode 100644 index 000000000..ab55734ec --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54L15 Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (384 KB) + * 0x0006_0000 Protected Storage Area (16 KB) + * 0x0006_4000 Internal Trusted Storage Area (16 KB) + * 0x0006_8000 OTP / NV counters area (8 KB) + * 0x0006_A000 Non-secure image primary (504 KB) + * 0x000E_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the last 62kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0xF0000) /* 960 kB since the last 62kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54L10 has 192 kB of volatile memory (SRAM) but the last 48kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00024000) /* 144 kB since the last 48kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x60000) /* S partition: 384 kB*/ +#define FLASH_NS_PARTITION_SIZE (0x7E000) /* NS partition: 504 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h new file mode 100644 index 000000000..79112d5ba --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..39adcd4da --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l10/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54l10") diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt new file mode 100644 index 000000000..8325faa57 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/CMakeLists.txt @@ -0,0 +1,52 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. +# Copyright (c) 2020, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(../core nrf_common) + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + ../nrf54l +) + +target_sources(platform_s + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c + ../nrf54l/nrf54l_init.c +) + +target_compile_definitions(platform_s + PUBLIC + NRF_SKIP_FICR_NS_COPY_TO_RAM +) + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/../nrf54l/tfm_interrupts.c> +) + +#========================= Files for building NS side platform ================# + +install(FILES ../nrf54l/nrfx_config_nrf54l.h + ../nrf54l/config.cmake + ns/CMakeLists.txt + cpuarch.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l15 +) + +install(DIRECTORY partition + tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf54l15 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake new file mode 100644 index 000000000..2222734d2 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2020-2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l/config.cmake) + diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake new file mode 100644 index 000000000..24d4703f9 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/cpuarch.cmake @@ -0,0 +1,24 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# cpuarch.cmake is used to set things that related to the platform that are both +# immutable and global, which is to say they should apply to any kind of project +# that uses this platform. In practice this is normally compiler definitions and +# variables related to hardware. + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) +set(CONFIG_TFM_FP_ARCH "fpv5-sp-d16") + +add_compile_definitions( + NRF54L15_XXAA + NRF54L_SERIES + NRF_APPLICATION + # SKIP configuring the SAU from the MDK as it does not fit TF-M's needs + NRF_SKIP_SAU_CONFIGURATION + NRF_SKIP_FICR_NS_COPY_TO_RAM +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt new file mode 100644 index 000000000..6e8396c35 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/ns/CMakeLists.txt @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(target nrf54l) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../core nrf_common) + +target_include_directories(platform_ns + PUBLIC + ${CMAKE_CURRENT_LIST_DIR} +) + +target_sources(platform_ns + PRIVATE + ${HAL_NORDIC_PATH}/nrfx/mdk/system_nrf54l.c +) + +target_compile_definitions(platform_ns + PUBLIC + NRF_TRUSTZONE_NONSECURE + NRF_SKIP_CLOCK_CONFIGURATION + DOMAIN_NS=1 +) diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/flash_layout.h new file mode 100644 index 000000000..6f46f82cc --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/flash_layout.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +#ifdef BL2 +#error "BL2 is not supported for this platform" +#endif + +/* Flash layout on NRF54L15 Application MCU without BL2: + * + * 0x0000_0000 Secure image primary (512 KB) + * 0x0008_0000 Protected Storage Area (16 KB) + * 0x0008_4000 Internal Trusted Storage Area (16 KB) + * 0x0008_8000 OTP / NV counters area (8 KB) + * 0x0008_A000 Non-secure image primary (844 KB) + * 0x0015_D000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, + * otherwise unused (32 KB) + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_base_address.h to access flash related defines. To resolve + * this some of the values are redefined here with different names, these are + * marked with comment. + */ + +/* Use Flash memory to store Code data */ +#define FLASH_BASE_ADDRESS (0x0) + +/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR non volatile memory is not used by TF-M. */ +#define FLASH_TOTAL_SIZE (0x165000) /* 1428 kB since the last 96kB are reserved for FLPR */ +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE + +/* nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved + * for FLPR MCU in Zephyr. For simplicity and for possible support for running FLPR along + * with TF-M later FLPR volatile memory is not used by TF-M. */ +#define SRAM_BASE_ADDRESS (0x20000000) +#define TOTAL_RAM_SIZE (0x00028000) /* 160 kB, since the last 96kB are reserved for FLPR */ + +#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 kB*/ +#define FLASH_NS_PARTITION_SIZE (0xD3000) /* NS partition: 844 kB*/ + +#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS +#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS + +/* Use SRAM memory to store RW data */ +#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS +#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS + +/* Sector size of the embedded flash hardware (erase/program) */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ + +#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) +#define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE +#else +#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE +#endif + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +#define SECURE_STORAGE_PARTITIONS_START (FLASH_BASE_ADDRESS + FLASH_S_PARTITION_SIZE) + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (SECURE_STORAGE_PARTITIONS_START) +#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x4000) /* 16 KB */ + +/* OTP_definitions */ +#define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (0x2000) /* 8KB */ + +#define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +#define SECURE_STORAGE_PARTITIONS_END (FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +/* END OF PARTITIONS LAYOUT */ + +#define SECURE_IMAGE_OFFSET (0x0) +#define NON_SECURE_IMAGE_OFFSET (SECURE_STORAGE_PARTITIONS_END) + +/* Non-secure storage region */ +#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ + NRF_FLASH_NS_STORAGE_AREA_SIZE) + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +//#define FLASH_DEV_NAME Driver_FLASH0 +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Size of dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_RAM_FS_SIZE TFM_HAL_PS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +/* Base address of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Size of dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_RAM_FS_SIZE TFM_HAL_ITS_FLASH_AREA_SIZE +/* Number of physical erase sectors per logical FS block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) +/* Smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* OTP / NV counter definitions */ +#define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) +#define TFM_OTP_NV_COUNTERS_AREA_ADDR FLASH_OTP_NV_COUNTERS_AREA_OFFSET +#define TFM_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_OTP_NV_COUNTERS_SECTOR_SIZE +#define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ + TFM_OTP_NV_COUNTERS_AREA_SIZE) + + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h new file mode 100644 index 000000000..79112d5ba --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/partition/region_defs.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#ifdef ENABLE_HEAP + #define S_HEAP_SIZE (0x0002000) /* 8k */ +#endif + +#define S_MSP_STACK_SIZE (0x0002000) /* 8k */ +#define S_PSP_STACK_SIZE (0x0002000) /* 8k */ + +#define NS_HEAP_SIZE (0x00002000) /* 8k */ +#define NS_STACK_SIZE (0x00002000) /* 8k */ + +/* Size of nRF MPC regions is 4k */ +#define MPC_FLASH_REGION_SIZE (0x00001000) +#define MPC_SRAM_REGION_SIZE (0x00001000) + +#ifdef NRF_NS_SECONDARY +#error "NRF_NS_SECONDARY is not supported for this platform" +#endif /* NRF_NS_SECONDARY */ + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_CODE_START (S_ROM_ALIAS(SECURE_IMAGE_OFFSET)) +#define S_CODE_SIZE (FLASH_S_PARTITION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Copied from the CONFIG_TFM_S_CODE_VECTOR_TABLE_SIZE in sdk-nrf */ +#define S_CODE_VECTOR_TABLE_SIZE (0x47C) + +#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 +/* If this image is placed at the beginning of flash make sure we + * don't put any code in the first 256 bytes of flash as that area + * is used for null-pointer dereference detection. + */ +#define TFM_LINKER_CODE_START_RESERVED (256) +#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED +#error "The interrupt table is too short too for null pointer detection" +#endif +#endif + +/* Non-secure regions */ +#define NS_CODE_START (NS_ROM_ALIAS(SECURE_STORAGE_PARTITIONS_END)) +#define NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) + +#ifdef PSA_API_TEST_IPC +/* Last SRAM region must be kept secure for PSA FF tests */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - MPC_SRAM_REGION_SIZE) +#else +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#endif +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU and MPC configuration */ +#define NS_PARTITION_START NS_CODE_START +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Non-secure storage region */ +#ifdef NRF_NS_STORAGE +#define NRF_NS_STORAGE_PARTITION_START \ + (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) +#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) +#endif /* NRF_NS_STORAGE */ + +/* Regions used by psa-arch-tests to keep state */ +#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) + +/* Even though BL2 is not supported now this needs to be defined becaused it is used by scatter files */ +#define BOOT_TFM_SHARED_DATA_SIZE (0x0) + +#ifdef PSA_API_TEST_IPC +/* Firmware Framework test suites */ +#define FF_TEST_PARTITION_SIZE 0x100 +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE - \ + FF_TEST_PARTITION_SIZE) + +/* The psa-arch-tests implementation requires that the test partitions are + * placed in this specific order: + * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER + * + * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER + * must be in SPE. + * + * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, + * and it should be placed at the end of the NSPE area, after + * PSA_TEST_SCRATCH_AREA. + */ +#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) +#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) +#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ + FF_TEST_PARTITION_SIZE - 1) +#else +/* Development APIs test suites */ +#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ + PSA_TEST_SCRATCH_AREA_SIZE) +#endif /* PSA_API_TEST_IPC */ + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/common/nrf54l15/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/common/nrf54l15/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..88586c115 --- /dev/null +++ b/platform/ext/target/nordic_nrf/common/nrf54l15/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +# Platform-specific configurations +set(PSA_API_TEST_TARGET "nrf54l15") diff --git a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt index 7caf8ffe0..308627c7a 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/common/nrf91/CMakeLists.txt @@ -64,5 +64,6 @@ install(FILES nrfx_config_nrf91.h ) install(DIRECTORY tests + partition DESTINATION ${INSTALL_PLATFORM_NS_DIR}/common/nrf91 ) diff --git a/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h b/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h index 8519278be..e95f3920a 100644 --- a/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h +++ b/platform/ext/target/nordic_nrf/common/nrf91/nrfx_config_nrf91.h @@ -36,6 +36,17 @@ #error "This file should not be included directly. Include nrfx_config.h instead." #endif +/* + * The MDK for nRF9120 used in the nRF9161 target doesn't define the Secure FPU + * as it doesn't exist, but for other platforms like the 9160 it has a dummy + * define. + * Therefore we define it here manually until it is fixed in the MDK. + * See: NCSDK-23046 + */ +#ifdef NRF9120_XXAA +#define NRF_FPU_S 1 +#endif + #define NRF_CLOCK NRF_PERIPH(NRF_CLOCK) #define NRF_DPPIC NRF_PERIPH(NRF_DPPIC) #define NRF_EGU0 NRF_PERIPH(NRF_EGU0) diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/partition/flash_layout.h b/platform/ext/target/nordic_nrf/common/nrf91/partition/flash_layout.h similarity index 100% rename from platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/partition/flash_layout.h rename to platform/ext/target/nordic_nrf/common/nrf91/partition/flash_layout.h diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/region_defs.h b/platform/ext/target/nordic_nrf/common/nrf91/partition/region_defs.h similarity index 97% rename from platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/region_defs.h rename to platform/ext/target/nordic_nrf/common/nrf91/partition/region_defs.h index 4a4ad59a6..d1b546842 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/region_defs.h +++ b/platform/ext/target/nordic_nrf/common/nrf91/partition/region_defs.h @@ -193,6 +193,9 @@ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT /* Regions used by psa-arch-tests to keep state */ #define PSA_TEST_SCRATCH_AREA_SIZE (0x400) diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/CMakeLists.txt index 271aad1c9..47db2eb47 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/CMakeLists.txt @@ -14,7 +14,7 @@ add_subdirectory(../common/nrf5340 nrf5340) target_include_directories(platform_region_defs INTERFACE - partition + ../common/nrf5340/partition ) target_sources(platform_s @@ -25,14 +25,14 @@ target_sources(platform_s target_include_directories(platform_s PUBLIC . - partition + ../common/nrf5340/partition services/include ) if(BL2) target_include_directories(platform_bl2 PUBLIC - partition + ../common/nrf5340/partition PRIVATE . ) @@ -64,7 +64,7 @@ install(FILES RTE_Device.h DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) -install(DIRECTORY partition +install(DIRECTORY ../common/nrf5340/partition tests DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/ns/CMakeLists.txt index dd7b1c36c..12391d56c 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/ns/CMakeLists.txt @@ -27,5 +27,5 @@ target_link_libraries(platform_ns target_include_directories(platform_region_defs INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/partition + ${CMAKE_CURRENT_LIST_DIR}/common/nrf5340/partition ) diff --git a/platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_read_ranges.h b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h similarity index 72% rename from platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_read_ranges.h rename to platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h index 83cb01431..be9c72f3b 100644 --- a/platform/ext/target/lairdconnectivity/bl5340_dvk_cpuapp/services/include/tfm_read_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef TFM_READ_RANGES_H__ -#define TFM_READ_RANGES_H__ +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ #include @@ -33,4 +33,9 @@ static const struct tfm_read_service_range ranges[] = { { .start = FICR_XOSC32MTRIM_ADDR, .size = FICR_XOSC32MTRIM_SIZE }, }; -#endif /* TFM_READ_RANGES_H__ */ +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/tfm_peripherals_config.h index 7a8885712..18a044094 100644 --- a/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf5340dk_nrf5340_cpuapp/tfm_peripherals_config.h @@ -13,8 +13,12 @@ extern "C" { #endif #ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 0 +#define TFM_PERIPHERAL_UARTE0_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 1 #define TFM_PERIPHERAL_UARTE1_SECURE 1 #endif +#endif #if TFM_PARTITION_SLIH_TEST || TFM_PARTITION_FLIH_TEST #define TFM_PERIPHERAL_TIMER0_SECURE 1 diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt new file mode 100644 index 000000000..e54ab7721 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/CMakeLists.txt @@ -0,0 +1,70 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54l10 nrf54l10) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf54l10/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54l10/partition + services/include +) + +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + partition + ../common/nrf54l10/partition + PRIVATE + . + ) +endif() + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h new file mode 100644 index 000000000..3cba0224c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake new file mode 100644 index 000000000..72efe7db7 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54l10/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake new file mode 100644 index 000000000..eb59334c8 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54l10/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h new file mode 100644 index 000000000..22ddb39ce --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 000000000..97f8d1209 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54l10/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 000000000..0847daa21 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 000000000..9ff8f6c37 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..796ca6674 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l10/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 000000000..619f1f92c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c new file mode 100644 index 000000000..5f682a825 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h new file mode 100644 index 000000000..82ab7ad3b --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/CMakeLists.txt new file mode 100644 index 000000000..4ac65556a --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/CMakeLists.txt @@ -0,0 +1,70 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2020, Nordic Semiconductor ASA. +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(NRF_BOARD_SELECTED True) + +add_subdirectory(../common/nrf54l15 nrf54l15) + +target_include_directories(platform_region_defs + INTERFACE + ../common/nrf54l15/partition +) + +target_sources(platform_s + PRIVATE + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> +) + +target_include_directories(platform_s + PUBLIC + . + ../common/nrf54l15/partition + services/include +) + +if(BL2) + target_include_directories(platform_bl2 + PUBLIC + partition + ../common/nrf54l15/partition + PRIVATE + . + ) +endif() + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + tfm_hal_platform.c +) + +#========================= Files for building NS side platform ================# + +install(FILES ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} + RENAME cpuarch.cmake) + +if (TFM_PARTITION_PLATFORM) + install(FILES services/include/tfm_ioctl_api.h + DESTINATION ${INSTALL_INTERFACE_INC_DIR} +) +endif() + +install(FILES RTE_Device.h + device_cfg.h + ns/CMakeLists.txt + config.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) + +install(DIRECTORY tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR} +) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/RTE_Device.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/RTE_Device.h new file mode 100644 index 000000000..3cba0224c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/RTE_Device.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +#define RTE_USART20 1 + +#define RTE_USART20_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 36),\ + NRF_PSEL(UART_RX, 0, 37),\ + NRF_PSEL(UART_RTS, 0, 38),\ + NRF_PSEL(UART_CTS, 0, 39),\ +} + + +#define RTE_USART30 1 + +#define RTE_USART30_PINS \ +{ \ + NRF_PSEL(UART_TX, 0, 0),\ + NRF_PSEL(UART_RX, 0, 1),\ + NRF_PSEL(UART_RTS, 0, 2),\ + NRF_PSEL(UART_CTS, 0, 3),\ +} + + +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake new file mode 100644 index 000000000..b2e0fb28b --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# +#------------------------------------------------------------------------------- + +# This file is used by the upstream TF-M, the file in the common folder is used when +# TF-M is build with upstream Zephyr. +include(${PLATFORM_PATH}/common/nrf54l15/config.cmake) \ No newline at end of file diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake new file mode 100644 index 000000000..3c4e40608 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/cpuarch.cmake @@ -0,0 +1,9 @@ +# +# Copyright (c) 2023, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +set(PLATFORM_PATH platform/ext/target/${TFM_PLATFORM}/..) + +include(${PLATFORM_PATH}/common/nrf54l15/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/device_cfg.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/device_cfg.h new file mode 100644 index 000000000..22ddb39ce --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/device_cfg.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016-2019 ARM Limited + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief + * This is the default device configuration file with all peripherals + * defined and configured to be use via the secure and/or non-secure base + * address. + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake new file mode 100644 index 000000000..622a3414f --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/ns/cpuarch_ns.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024, Nordic Semiconductor ASA. +# +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause +# + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR}) + +add_compile_definitions(NRF_CONFIG_CPU_FREQ_MHZ=128) + +include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54l15/cpuarch.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h new file mode 100644 index 000000000..0847daa21 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/include/tfm_platform_user_memory_ranges.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ + +#include + +#include "nrf.h" + + +static const struct tfm_read_service_range ranges[] = { + { .start = 0xFFFFFFFF, .size = 0x0}, +}; + +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/src/tfm_platform_system.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/src/tfm_platform_system.c new file mode 100644 index 000000000..9ff8f6c37 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/services/src/tfm_platform_system.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "platform/include/tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_platform_hal_ioctl.h" +#include "tfm_ioctl_core_api.h" + +void tfm_platform_hal_system_reset(void) +{ + /* Reset the system */ + NVIC_SystemReset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + /* Core IOCTL services */ + switch (request) { + /* Not a supported IOCTL service.*/ + default: + return TFM_PLATFORM_ERR_NOT_SUPPORTED; + } + +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/psa_arch_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..327e36c66 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/psa_arch_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/nrf54l15/tests/psa_arch_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/tfm_tests_config.cmake b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/tfm_tests_config.cmake new file mode 100644 index 000000000..619f1f92c --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tests/tfm_tests_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +#------------------------------------------------------------------------------- + +include(${PLATFORM_PATH}/common/core/tests/tfm_tests_config.cmake) diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_hal_platform.c b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_hal_platform.c new file mode 100644 index 000000000..5f682a825 --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_hal_platform.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "tfm_hal_defs.h" +#include "tfm_hal_platform_common.h" + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + return tfm_hal_platform_common_init(); +} diff --git a/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h new file mode 100644 index 000000000..5a123d1da --- /dev/null +++ b/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l15_cpuapp/tfm_peripherals_config.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef TFM_PERIPHERALS_CONFIG_H__ +#define TFM_PERIPHERALS_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 30 +#define TFM_PERIPHERAL_UARTE30_SECURE 1 +#endif +#endif + +/* The target_cfg.c requires this to be set */ +#define TFM_PERIPHERAL_GPIO0_PIN_MASK_SECURE 0 + +#if defined(NRF54L_SERIES) + #include +#else + #error "Unknown device." +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* TFM_PERIPHERAL_CONFIG_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/CMakeLists.txt index ff57ee98e..272064be9 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/CMakeLists.txt @@ -14,7 +14,7 @@ add_subdirectory(../common/nrf91 nrf91) target_include_directories(platform_region_defs INTERFACE - partition + ../common/nrf91/partition ) target_sources(platform_s @@ -25,14 +25,14 @@ target_sources(platform_s target_include_directories(platform_s PUBLIC . - partition + ../common/nrf91/partition services/include ) if(BL2) target_include_directories(platform_bl2 PUBLIC - partition + ../common/nrf91/partition PRIVATE . ) @@ -69,7 +69,7 @@ install(FILES RTE_Device.h DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) -install(DIRECTORY partition +install(DIRECTORY ../common/nrf91/partition tests DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/CMakeLists.txt index c6678de0d..999a6f774 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/ns/CMakeLists.txt @@ -17,7 +17,7 @@ add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/common/nrf91 nrf91) target_include_directories(platform_region_defs INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/partition + ${CMAKE_CURRENT_LIST_DIR}/common/nrf91/partition ) target_include_directories(platform_ns diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/partition/region_defs.h b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/partition/region_defs.h deleted file mode 100644 index 4a4ad59a6..000000000 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/partition/region_defs.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2017-2022 Arm Limited. All rights reserved. - * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "flash_layout.h" - -#define BL2_HEAP_SIZE (0x00001000) -#define BL2_MSP_STACK_SIZE (0x00001800) - -#ifdef ENABLE_HEAP - #define S_HEAP_SIZE (0x0000200) -#endif - -#define S_MSP_STACK_SIZE (0x00000800) -#define S_PSP_STACK_SIZE (0x00000800) - -#define NS_HEAP_SIZE (0x00001000) -#define NS_STACK_SIZE (0x000001E0) - -/* Size of nRF SPU (Nordic IDAU) regions */ -#define SPU_FLASH_REGION_SIZE (0x00008000) -#define SPU_SRAM_REGION_SIZE (0x00002000) - -/* - * SPU flash region granularity is 32 KB on nRF91. Alignment - * of partitions is defined in accordance with this constraint. - */ -#ifdef NRF_NS_SECONDARY -#ifndef LINK_TO_SECONDARY_PARTITION -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) -#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) -#else -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) -#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) -#endif /* !LINK_TO_SECONDARY_PARTITION */ -#else -#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) -#endif /* NRF_NS_SECONDARY */ - -#ifndef LINK_TO_SECONDARY_PARTITION -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ - + FLASH_S_PARTITION_SIZE) -#else -#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ - + FLASH_S_PARTITION_SIZE) -#endif /* !LINK_TO_SECONDARY_PARTITION */ - -/* Boot partition structure if MCUBoot is used: - * 0x0_0000 Bootloader header - * 0x0_0400 Image area - * 0x0_FC00 Trailer - */ -/* IMAGE_CODE_SIZE is the space available for the software binary image. - * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE - * because we reserve space for the image header and trailer introduced - * by the bootloader. - */ - -#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ - (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) -/* If secure image and nonsecure image are concatenated, and nonsecure image - * locates at the higher memory range, then the secure image does not need - * the trailer area. - */ -#define IMAGE_S_CODE_SIZE \ - (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) -#else -#define IMAGE_S_CODE_SIZE \ - (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) -#endif - -#define IMAGE_NS_CODE_SIZE \ - (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) - -/* Alias definitions for secure and non-secure areas*/ -#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) -#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) - -#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) -#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) - -/* Secure regions */ -#define S_IMAGE_PRIMARY_AREA_OFFSET \ - (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) -#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) -#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) - -#define S_DATA_START (S_RAM_ALIAS(0x0)) -/* Assign to SPE the minimum amount of RAM (aligned to the SPU region boundary) - * that is needed for the most demanding configuration, which turns out to be - * the RegressionIPC one. */ -#define S_DATA_SIZE 0x16000 /* 88 KB */ -#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) - -#define S_CODE_VECTOR_TABLE_SIZE (0x144) - -#if defined(NULL_POINTER_EXCEPTION_DETECTION) && S_CODE_START == 0 -/* If this image is placed at the beginning of flash make sure we - * don't put any code in the first 256 bytes of flash as that area - * is used for null-pointer dereference detection. - */ -#define TFM_LINKER_CODE_START_RESERVED (256) -#if S_CODE_VECTOR_TABLE_SIZE < TFM_LINKER_CODE_START_RESERVED -#error "The interrupt table is too short too for null pointer detection" -#endif -#endif - -/* The veneers needs to be placed at the end of the secure image. - * This is because the NCS sub-region is defined as starting at the highest - * address of an SPU region and going downwards. - */ -#define TFM_LINKER_VENEERS_LOCATION_END -/* The CMSE veneers shall be placed in an NSC region - * which will be placed in a secure SPU region with the given alignment. - */ -#define TFM_LINKER_VENEERS_SIZE (0x400) -/* The Nordic SPU has different alignment requirements than the ARM SAU, so - * these override the default start and end alignments. */ -#define TFM_LINKER_VENEERS_START \ - (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE + \ - (. > (ALIGN(SPU_FLASH_REGION_SIZE) - TFM_LINKER_VENEERS_SIZE) \ - ? SPU_FLASH_REGION_SIZE : 0)) - -#define TFM_LINKER_VENEERS_END ALIGN(SPU_FLASH_REGION_SIZE) - -/* Non-secure regions */ -#define NS_IMAGE_PRIMARY_AREA_OFFSET \ - (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) -#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) -#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) -#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) - -#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) -#ifdef PSA_API_TEST_IPC -/* Last SRAM region must be kept secure for PSA FF tests */ -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE - SPU_SRAM_REGION_SIZE) -#else -#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) -#endif -#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) - -/* NS partition information is used for SPU configuration */ -#define NS_PARTITION_START \ - (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) -#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) - -/* Secondary partition for new images in case of firmware upgrade */ -#define SECONDARY_PARTITION_START \ - (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) -#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ - FLASH_NS_PARTITION_SIZE) - -/* Non-secure storage region */ -#ifdef NRF_NS_STORAGE -#define NRF_NS_STORAGE_PARTITION_START \ - (NS_ROM_ALIAS(NRF_FLASH_NS_STORAGE_AREA_OFFSET)) -#define NRF_NS_STORAGE_PARTITION_SIZE (NRF_FLASH_NS_STORAGE_AREA_SIZE) -#endif /* NRF_NS_STORAGE */ - -#ifdef BL2 -/* Bootloader regions */ -#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) -#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) -#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) - -#define BL2_DATA_START (S_RAM_ALIAS(0x0)) -#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) -#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) -#endif /* BL2 */ - -/* Shared data area between bootloader and runtime firmware. - * Shared data area is allocated at the beginning of the RAM, it is overlapping - * with TF-M Secure code's MSP stack - */ -#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE -#define BOOT_TFM_SHARED_DATA_SIZE (0x400) -#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ - BOOT_TFM_SHARED_DATA_SIZE - 1) - -/* Regions used by psa-arch-tests to keep state */ -#define PSA_TEST_SCRATCH_AREA_SIZE (0x400) - -#ifdef PSA_API_TEST_IPC -/* Firmware Framework test suites */ -#define FF_TEST_PARTITION_SIZE 0x100 -#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ - PSA_TEST_SCRATCH_AREA_SIZE - \ - FF_TEST_PARTITION_SIZE) - -/* The psa-arch-tests implementation requires that the test partitions are - * placed in this specific order: - * TEST_NSPE_MMIO < TEST_SERVER < TEST_DRIVER - * - * TEST_NSPE_MMIO region must be in the NSPE, while TEST_SERVER and TEST_DRIVER - * must be in SPE. - * - * The TEST_NSPE_MMIO region is defined in the psa-arch-tests implementation, - * and it should be placed at the end of the NSPE area, after - * PSA_TEST_SCRATCH_AREA. - */ -#define FF_TEST_SERVER_PARTITION_MMIO_START (NS_DATA_LIMIT + 1) -#define FF_TEST_SERVER_PARTITION_MMIO_END (FF_TEST_SERVER_PARTITION_MMIO_START + \ - FF_TEST_PARTITION_SIZE - 1) -#define FF_TEST_DRIVER_PARTITION_MMIO_START (FF_TEST_SERVER_PARTITION_MMIO_END + 1) -#define FF_TEST_DRIVER_PARTITION_MMIO_END (FF_TEST_DRIVER_PARTITION_MMIO_START + \ - FF_TEST_PARTITION_SIZE - 1) -#else -/* Development APIs test suites */ -#define PSA_TEST_SCRATCH_AREA_BASE (NS_DATA_LIMIT + 1 - \ - PSA_TEST_SCRATCH_AREA_SIZE) -#endif /* PSA_API_TEST_IPC */ - -#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_read_ranges.h b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h similarity index 62% rename from platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_read_ranges.h rename to platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h index c5e1b09e6..f1419bd6a 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_read_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/services/include/tfm_platform_user_memory_ranges.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef TFM_READ_RANGES_H__ -#define TFM_READ_RANGES_H__ +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ #include @@ -25,4 +25,9 @@ static const struct tfm_read_service_range ranges[] = { { .start = FICR_RESTRICTED_ADDR, .size = FICR_RESTRICTED_SIZE }, }; -#endif /* TFM_READ_RANGES_H__ */ +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/tfm_peripherals_config.h b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/tfm_peripherals_config.h index 80f8540c5..cc980516e 100644 --- a/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/tfm_peripherals_config.h +++ b/platform/ext/target/nordic_nrf/nrf9160dk_nrf9160/tfm_peripherals_config.h @@ -13,8 +13,12 @@ extern "C" { #endif #ifdef SECURE_UART1 +#if NRF_SECURE_UART_INSTANCE == 0 +#define TFM_PERIPHERAL_UARTE0_SECURE 1 +#elif NRF_SECURE_UART_INSTANCE == 1 #define TFM_PERIPHERAL_UARTE1_SECURE 1 #endif +#endif #if TFM_PARTITION_SLIH_TEST || TFM_PARTITION_FLIH_TEST #define TFM_PERIPHERAL_TIMER0_SECURE 1 diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt index 4103ad6ee..33e914283 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/CMakeLists.txt @@ -12,7 +12,7 @@ add_subdirectory(../common/nrf91 nrf91) target_include_directories(platform_region_defs INTERFACE - partition + ../common/nrf91/partition ) target_sources(platform_s @@ -23,14 +23,14 @@ target_sources(platform_s target_include_directories(platform_s PUBLIC . - partition + ../common/nrf91/partition services/include ) if(BL2) target_include_directories(platform_bl2 PUBLIC - partition + ../common/nrf91/partition PRIVATE . ) @@ -67,7 +67,7 @@ install(FILES RTE_Device.h DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) -install(DIRECTORY partition +install(DIRECTORY ../common/nrf91/partition tests DESTINATION ${INSTALL_PLATFORM_NS_DIR} ) diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt index 00e268234..e65f7a969 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/ns/CMakeLists.txt @@ -16,7 +16,7 @@ add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/common/nrf91 nrf91) target_include_directories(platform_region_defs INTERFACE - ${CMAKE_CURRENT_LIST_DIR}/partition + ${CMAKE_CURRENT_LIST_DIR}/common/nrf91/partition ) target_include_directories(platform_ns diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_read_ranges.h b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h similarity index 62% rename from platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_read_ranges.h rename to platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h index 2b159f721..61c8fd0e2 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_read_ranges.h +++ b/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/services/include/tfm_platform_user_memory_ranges.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef TFM_READ_RANGES_H__ -#define TFM_READ_RANGES_H__ +#ifndef TFM_PLATFORM_USER_MEMORY_RANGES_H__ +#define TFM_PLATFORM_USER_MEMORY_RANGES_H__ #include @@ -25,4 +25,9 @@ static const struct tfm_read_service_range ranges[] = { { .start = FICR_RESTRICTED_ADDR, .size = FICR_RESTRICTED_SIZE }, }; -#endif /* TFM_READ_RANGES_H__ */ +static const struct tfm_write32_service_address tfm_write32_service_addresses[] = { + /* This is a dummy value because this table cannot be empty */ + {.addr = 0xFFFFFFFF, .mask = 0x0, .allowed_values = NULL, .allowed_values_array_size = 0}, +}; + +#endif /* TFM_PLATFORM_USER_MEMORY_RANGES_H__ */ diff --git a/platform/ext/target/nuvoton/m2351/partition/region_defs.h b/platform/ext/target/nuvoton/m2351/partition/region_defs.h index f6e3b5d5c..fb962c08a 100644 --- a/platform/ext/target/nuvoton/m2351/partition/region_defs.h +++ b/platform/ext/target/nuvoton/m2351/partition/region_defs.h @@ -129,5 +129,8 @@ #define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nuvoton/m2354/partition/region_defs.h b/platform/ext/target/nuvoton/m2354/partition/region_defs.h index 4428ba8ef..a9d25370a 100644 --- a/platform/ext/target/nuvoton/m2354/partition/region_defs.h +++ b/platform/ext/target/nuvoton/m2354/partition/region_defs.h @@ -129,5 +129,8 @@ #define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c new file mode 100644 index 000000000..5644f385d --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.c @@ -0,0 +1,499 @@ +/* + * Copyright 2018-2019, 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_component_generic_list.h" + +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +#define LIST_ENTER_CRITICAL() \ + OSA_SR_ALLOC(); \ + OSA_ENTER_CRITICAL() +#define LIST_EXIT_CRITICAL() OSA_EXIT_CRITICAL() +#else +#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif +#else +#define LIST_ENTER_CRITICAL() uint32_t regPrimask = DisableGlobalIRQ(); +#define LIST_EXIT_CRITICAL() EnableGlobalIRQ(regPrimask); +#endif + +static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + list_element_handle_t element = list->head; +#endif + if ((list->max != 0U) && (list->max == list->size)) + { + listStatus = kLIST_Full; /*List is full*/ + } +#if (defined(GENERIC_LIST_DUPLICATED_CHECKING) && (GENERIC_LIST_DUPLICATED_CHECKING > 0U)) + else + { + while (element != NULL) /*Scan list*/ + { + /* Determine if element is duplicated */ + if (element == newElement) + { + listStatus = kLIST_DuplicateError; + break; + } + element = element->next; + } + } +#endif + return listStatus; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initializes the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t listElement) +{ + return listElement->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, listElement); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + if (list->size == 0U) + { + list->head = listElement; + } + else + { + list->tail->next = listElement; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + listElement->prev = list->tail; +#endif + listElement->list = list; + listElement->next = NULL; + list->tail = listElement; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement) +{ + LIST_ENTER_CRITICAL(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, listElement); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + /* Links element to the head of the list */ + if (list->size == 0U) + { + list->tail = listElement; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + list->head->prev = listElement; + } + listElement->prev = NULL; +#endif + listElement->list = list; + listElement->next = list->head; + list->head = listElement; + list->size++; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t listElement; + + LIST_ENTER_CRITICAL(); + + if ((NULL == list) || (list->size == 0U)) + { + listElement = NULL; /*LIST_ is empty*/ + } + else + { + listElement = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + listElement->next->prev = NULL; + } +#endif + listElement->list = NULL; + list->head = listElement->next; /*Is NULL if element is head*/ + } + + LIST_EXIT_CRITICAL(); + return listElement; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t listElement) +{ + return listElement->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement) +{ +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + return NULL; +#else + return listElement->prev; +#endif +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t listElement) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (listElement->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = listElement->list->head; + list_element_handle_t element_Prev = NULL; + while (NULL != element_list) + { + if (listElement->list->head == listElement) + { + listElement->list->head = element_list->next; + break; + } + if (element_list->next == listElement) + { + element_Prev = element_list; + element_list->next = listElement->next; + break; + } + element_list = element_list->next; + } + if (listElement->next == NULL) + { + listElement->list->tail = element_Prev; + } +#else + if (listElement->prev == NULL) /*Element is head or solo*/ + { + listElement->list->head = listElement->next; /*is null if solo*/ + } + if (listElement->next == NULL) /*Element is tail or solo*/ + { + listElement->list->tail = listElement->prev; /*is null if solo*/ + } + if (listElement->prev != NULL) /*Element is not head*/ + { + listElement->prev->next = listElement->next; + } + if (listElement->next != NULL) /*Element is not tail*/ + { + listElement->next->prev = listElement->prev; + } +#endif + listElement->list->size--; + listElement->list = NULL; + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + LIST_ENTER_CRITICAL(); + + if (listElement->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { + listStatus = LIST_Error_Check(listElement->list, newElement); + if (listStatus == kLIST_Ok) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = listElement->list->head; + while (NULL != element_list) + { + if ((element_list->next == listElement) || (element_list == listElement)) + { + if (element_list == listElement) + { + listElement->list->head = newElement; + } + else + { + element_list->next = newElement; + } + newElement->list = listElement->list; + newElement->next = listElement; + listElement->list->size++; + break; + } + element_list = element_list->next; + } + +#else + if (listElement->prev == NULL) /*Element is list head*/ + { + listElement->list->head = newElement; + } + else + { + listElement->prev->next = newElement; + } + newElement->list = listElement->list; + listElement->list->size++; + newElement->next = listElement; + newElement->prev = listElement->prev; + listElement->prev = newElement; +#endif + } + } + + LIST_EXIT_CRITICAL(); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return (list->max - list->size); /*Gets the number of free places in the list*/ +} diff --git a/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h new file mode 100644 index 000000000..ab7ea1a46 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/lists/fsl_component_generic_list.h @@ -0,0 +1,219 @@ +/* + * Copyright 2018-2020, 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +#ifndef SDK_COMPONENT_DEPENDENCY_FSL_COMMON +#define SDK_COMPONENT_DEPENDENCY_FSL_COMMON (1U) +#endif +#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U)) +#include "fsl_common.h" +#else +#endif +/*! + * @addtogroup GenericList + * @{ + */ + +/********************************************************************************** + * Include + ***********************************************************************************/ + +/********************************************************************************** + * Public macro definitions + ***********************************************************************************/ +/*! @brief Definition to determine whether use list light. */ +#ifndef GENERIC_LIST_LIGHT +#define GENERIC_LIST_LIGHT (1) +#endif + +/*! @brief Definition to determine whether enable list duplicated checking. */ +#ifndef GENERIC_LIST_DUPLICATED_CHECKING +#define GENERIC_LIST_DUPLICATED_CHECKING (0) +#endif + +/********************************************************************************** + * Public type definitions + ***********************************************************************************/ +/*! @brief The list status */ +#if (defined(SDK_COMPONENT_DEPENDENCY_FSL_COMMON) && (SDK_COMPONENT_DEPENDENCY_FSL_COMMON > 0U)) +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ + kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */ +} list_status_t; +#else +typedef enum _list_status +{ + kLIST_Ok = 0, /*!< Success */ + kLIST_DuplicateError = 1, /*!< Duplicate Error */ + kLIST_Full = 2, /*!< FULL */ + kLIST_Empty = 3, /*!< Empty */ + kLIST_OrphanElement = 4, /*!< Orphan Element */ + kLIST_NotSupport = 5, /*!< Not Support */ +} list_status_t; +#endif + +/*! @brief The list structure*/ +typedef struct list_label +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint32_t size; /*!< list size */ + uint32_t max; /*!< list max number of elements */ +} list_label_t, *list_handle_t; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#else +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#endif +/********************************************************************************** + * Public prototypes + ***********************************************************************************/ +/********************************************************************************** + * API + **********************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param listElement - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t listElement); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param listElement - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t listElement); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param listElement - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t listElement); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param listElement - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t listElement); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param listElement - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t listElement); + +/*! + * @brief Unlinks an element from its list. + * + * @param listElement - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t listElement); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param listElement - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t listElement, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c new file mode 100644 index 000000000..d1570d9a0 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.c @@ -0,0 +1,2093 @@ +/* + * Copyright 2018-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#include "fsl_component_generic_list.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#include "fsl_os_abstraction.h" +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#else + +#endif + +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__DSC__) || defined(__CW__) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define SERIAL_EVENT_DATA_RECEIVED (0U) +#define SERIAL_EVENT_DATA_SENT (1U) +#define SERIAL_EVENT_DATA_START_SEND (2U) +#define SERIAL_EVENT_DATA_RX_NOTIFY (3U) +#define SERIAL_EVENT_DATA_NUMBER (4U) + +#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U +#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U + +#ifndef RINGBUFFER_WATERMARK_THRESHOLD +#define RINGBUFFER_WATERMARK_THRESHOLD 95U / 100U +#endif + +#ifndef gSerialManagerLpConstraint_c +#define gSerialManagerLpConstraint_c 0 +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +typedef enum _serial_manager_transmission_mode +{ + kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/ + kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/ +} serial_manager_transmission_mode_t; + +/* TX transfer structure */ +typedef struct _serial_manager_transfer +{ + uint8_t *buffer; + volatile uint32_t length; + volatile uint32_t soFar; + serial_manager_transmission_mode_t mode; + serial_manager_status_t status; +} serial_manager_transfer_t; +#endif + +/* write handle structure */ +typedef struct _serial_manager_send_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_element_t link; /*!< list element of the link */ + serial_manager_transfer_t transfer; +#endif + struct _serial_manager_handle *serialManagerHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_callback_t callback; + void *callbackParam; + uint32_t tag; +#endif +} serial_manager_write_handle_t; +typedef struct _serial_manager_send_block_handle +{ + struct _serial_manager_handle *serialManagerHandle; + +} serial_manager_write_block_handle_t; + +typedef serial_manager_write_handle_t serial_manager_read_handle_t; +typedef serial_manager_write_block_handle_t serial_manager_read_block_handle_t; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/* receive state structure */ +typedef struct _serial_manager_read_ring_buffer +{ + uint8_t *ringBuffer; + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; +} serial_manager_read_ring_buffer_t; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +typedef struct _serial_manager_block_handle +{ + serial_manager_type_t handleType; + serial_port_type_t type; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_BLOCK_HANDLE_SIZE]; +#endif + }; + +} serial_manager_block_handle_t; +#endif + +/* The serial manager handle structure */ +typedef struct _serial_manager_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_type_t handleType; +#endif + serial_port_type_t serialPortType; + serial_manager_read_handle_t *volatile openedReadHandleHead; + volatile uint32_t openedWriteHandleCount; + union + { + uint32_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + uint8_t uartDmaHandleBuffer[SERIAL_PORT_UART_DMA_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_VIRTUAL_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + uint8_t rpmsgHandleBuffer[SERIAL_PORT_RPMSG_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + uint8_t spiMasterHandleBuffer[SERIAL_PORT_SPI_MASTER_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + uint8_t spiSlaveHandleBuffer[SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + uint8_t bleWuHandleBuffer[SERIAL_PORT_BLE_WU_HANDLE_SIZE]; +#endif + }; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_read_ring_buffer_t ringBuffer; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; +#else + OSA_SEMAPHORE_HANDLE_DEFINE(serSemaphore); /*!< Semaphore instance */ + OSA_TASK_HANDLE_DEFINE(taskId); /*!< Task handle */ +#endif + uint8_t serialManagerState[SERIAL_EVENT_DATA_NUMBER]; /*!< Used to indicate the serial mnager state */ + +#endif + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_label_t runningWriteHandleHead; /*!< The queue of running write handle */ + list_label_t completedWriteHandleHead; /*!< The queue of completed write handle */ +#endif + +} serial_manager_handle_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_Task(void *param); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + +#else + /* + * \brief Defines the serial manager task's stack + */ +static OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false); +#endif + +#endif + +#endif +static const serial_manager_lowpower_critical_CBs_t *s_pfserialLowpowerCriticalCallbacks = NULL; +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_AddTail(list_label_t *queue, serial_manager_write_handle_t *node) +{ + (void)LIST_AddTail(queue, &node->link); +} + +static void SerialManager_RemoveHead(list_label_t *queue) +{ + (void)LIST_RemoveHead(queue); +} + +static int32_t SerialManager_SetLpConstraint(int32_t power_mode) +{ + int32_t status = -1; + if ((s_pfserialLowpowerCriticalCallbacks != NULL) && + (s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc != NULL)) + { + status = s_pfserialLowpowerCriticalCallbacks->serialEnterLowpowerCriticalFunc(power_mode); + } + return status; +} +static int32_t SerialManager_ReleaseLpConstraint(int32_t power_mode) +{ + int32_t status = -1; + if ((s_pfserialLowpowerCriticalCallbacks != NULL) && + (s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc != NULL)) + { + status = s_pfserialLowpowerCriticalCallbacks->serialExitLowpowerCriticalFunc(power_mode); + } + return status; +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + serial_manager_write_handle_t *writeHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); + + if (writeHandle != NULL) + { + (void)SerialManager_SetLpConstraint(gSerialManagerLpConstraint_c); + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + status = Serial_SpiSlaveWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif + + default: + status = kStatus_SerialManager_Error; + break; + } + if (kStatus_SerialManager_Success != status) + { + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (NULL != readHandle) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (serHandle->serialPortType == kSerialPort_UsbCdc) + { + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (serHandle->serialPortType == kSerialPort_Virtual) + { + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (serHandle->serialPortType == kSerialPort_SpiMaster) + { + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + if (serHandle->serialPortType == kSerialPort_SpiSlave) + { + status = Serial_SpiSlaveRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif + +#if 0 +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (serHandle->serialPortType == kSerialPort_Rpmsg) + { + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (serHandle->serialPortType == kSerialPort_BleWu) + { + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif + } + return status; +} + +#else /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *serHandle, + serial_manager_write_handle_t *writeHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ + { + status = Serial_SwoWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port Rpmsg */ + { + status = Serial_RpmsgWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ + { + status = Serial_SpiMasterWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ + { + status = Serial_PortBleWuWrite(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *serHandle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + if (kSerialPort_Uart == serHandle->serialPortType) /* Serial port UART */ + { + status = Serial_UartRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (kSerialPort_UsbCdc == serHandle->serialPortType) /* Serial port UsbCdc */ + { + status = Serial_UsbCdcRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + if (kSerialPort_Swo == serHandle->serialPortType) /* Serial port SWO */ + { + status = Serial_SwoRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + if (kSerialPort_Virtual == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_PortVirtualRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + if (kSerialPort_Rpmsg == serHandle->serialPortType) /* Serial port UsbCdcVirtual */ + { + status = Serial_RpmsgRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + if (kSerialPort_SpiMaster == serHandle->serialPortType) /* Serial port Spi Master */ + { + status = Serial_SpiMasterRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + if (kSerialPort_BleWu == serHandle->serialPortType) /* Serial port BLE WU */ + { + status = Serial_PortBleWuRead(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), buffer, length); + } + else +#endif + { + /*MISRA rule*/ + } + return status; +} +#endif /*SERIAL_MANAGER_NON_BLOCKING_MODE > 0U*/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_IsrFunction(serial_manager_handle_t *serHandle) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + Serial_UartIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + Serial_UsbCdcIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + Serial_SwoIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + Serial_PortVirtualIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + Serial_PortBleWuIsrFunction(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + EnableGlobalIRQ(regPrimask); +} + +static void SerialManager_Task(void *param) +{ + serial_manager_handle_t *serHandle = (serial_manager_handle_t *)param; + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + serial_manager_callback_message_t serialMsg; +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + uint32_t ringBufferLength; +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + + if (NULL != serHandle) + { +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + + do + { + if (KOSA_StatusSuccess == + OSA_SemaphoreWait((osa_semaphore_handle_t)serHandle->serSemaphore, osaWaitForever_c)) + { +#endif +#endif +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + uint8_t *ev = serHandle->serialManagerState; + EnableGlobalIRQ(primask); + if (0U != (ev[SERIAL_EVENT_DATA_START_SEND])) +#endif +#endif + { + (void)SerialManager_StartWriting(serHandle); +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]--; + EnableGlobalIRQ(primask); +#endif +#endif + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_SENT])) +#endif + +#endif + { + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); + while (NULL != serialWriteHandle) + { + SerialManager_RemoveHead(&serHandle->completedWriteHandleHead); + serialMsg.buffer = serialWriteHandle->transfer.buffer; + serialMsg.length = serialWriteHandle->transfer.soFar; + serialWriteHandle->transfer.buffer = NULL; + if (NULL != serialWriteHandle->callback) + { + serialWriteHandle->callback(serialWriteHandle->callbackParam, &serialMsg, + serialWriteHandle->transfer.status); + } + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->completedWriteHandleHead); + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]--; + EnableGlobalIRQ(primask); +#endif +#endif + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_RECEIVED])) +#endif + +#endif + { + primask = DisableGlobalIRQ(); + serialReadHandle = serHandle->openedReadHandleHead; + EnableGlobalIRQ(primask); + + if (NULL != serialReadHandle) + { + if (NULL != serialReadHandle->transfer.buffer) + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialMsg.buffer = serialReadHandle->transfer.buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, + serialReadHandle->transfer.status); + } + } + } + } +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]--; + EnableGlobalIRQ(primask); +#endif +#endif + } + +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (0U != (ev[SERIAL_EVENT_DATA_RX_NOTIFY])) +#endif + { + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] = 0; + ringBufferLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; + EnableGlobalIRQ(primask); + /* Notify there are data in ringbuffer */ + if (0U != ringBufferLength) + { + serialMsg.buffer = NULL; + serialMsg.length = ringBufferLength; + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) + { + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, &serialMsg, + kStatus_SerialManager_Notify); + } + } + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + } + } while (0U != gUseRtos_c); +#endif + +#endif + } +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_TxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *serHandle; + serial_manager_write_handle_t *writeHandle; +#if (defined(OSA_USED)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + uint32_t primask; +#endif +#endif + assert(NULL != callbackParam); + assert(NULL != message); + + serHandle = (serial_manager_handle_t *)callbackParam; + + writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&serHandle->runningWriteHandleHead); + + if (NULL != writeHandle) + { + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + if (kSerialManager_TransmissionBlocking == writeHandle->transfer.mode) + { + (void)SerialManager_StartWriting(serHandle); + } +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + writeHandle->transfer.soFar = message->length; + writeHandle->transfer.status = status; + if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) + { + SerialManager_AddTail(&serHandle->completedWriteHandleHead, writeHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif + } + else + { + writeHandle->transfer.buffer = NULL; + (void)SerialManager_ReleaseLpConstraint(gSerialManagerLpConstraint_c); + } + } +} + +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); +void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *serHandle; +#if (!((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)))) + uint32_t ringBufferLength = 0; + uint32_t primask; +#endif + assert(NULL != callbackParam); + assert(NULL != message); + + serHandle = (serial_manager_handle_t *)callbackParam; +#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \ + (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))) + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + serHandle->openedReadHandleHead->transfer.soFar = message->length; + serHandle->openedReadHandleHead->transfer.length = message->length; + serHandle->openedReadHandleHead->transfer.buffer = message->buffer; +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif +#else + status = kStatus_SerialManager_Notify; + + primask = DisableGlobalIRQ(); + + /* If wrap around is expected copy byte one after the other. Note that this could also be done with 2 memcopy for + * better efficiency. */ + if (serHandle->ringBuffer.ringHead + message->length >= serHandle->ringBuffer.ringBufferSize) + { + for (uint32_t i = 0; i < message->length; i++) + { + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead++] = message->buffer[i]; + + if (serHandle->ringBuffer.ringHead >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringHead = 0U; + } + if (serHandle->ringBuffer.ringHead == serHandle->ringBuffer.ringTail) + { + status = kStatus_SerialManager_RingBufferOverflow; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + } + } + else /*No wrap is expected so do a memcpy*/ + { + (void)memcpy(&serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringHead], message->buffer, + message->length); + serHandle->ringBuffer.ringHead += message->length; + } + + ringBufferLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % serHandle->ringBuffer.ringBufferSize; + + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->transfer.buffer)) + { + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) + { + uint32_t remainLength = + serHandle->openedReadHandleHead->transfer.length - serHandle->openedReadHandleHead->transfer.soFar; + for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) + { + serHandle->openedReadHandleHead->transfer.buffer[serHandle->openedReadHandleHead->transfer.soFar] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + serHandle->openedReadHandleHead->transfer.soFar++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); + } + + if (serHandle->openedReadHandleHead->transfer.length > serHandle->openedReadHandleHead->transfer.soFar) + { + } + else + { + if (kSerialManager_TransmissionBlocking == serHandle->openedReadHandleHead->transfer.mode) + { + serHandle->openedReadHandleHead->transfer.buffer = NULL; + } + else + { + serHandle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serHandle->commontaskMsg.callback = SerialManager_Task; + serHandle->commontaskMsg.callbackParam = serHandle; + COMMON_TASK_post_message(&serHandle->commontaskMsg); +#else + serHandle->serialManagerState[SERIAL_EVENT_DATA_RECEIVED]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serHandle); +#endif + } + } + } +#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) + uint32_t ringBufferWaterMark = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + { + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); + } +#else + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); +#endif + if (0U != ringBufferLength) + { +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) + if (serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY] == 0) + { + serHandle->serialManagerState[SERIAL_EVENT_DATA_RX_NOTIFY]++; + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + } + + (void)status; /* Fix "set but never used" warning. */ +#else /* !SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + message->buffer = NULL; + message->length = ringBufferLength; + if ((NULL != serHandle->openedReadHandleHead) && (NULL != serHandle->openedReadHandleHead->callback)) + { + serHandle->openedReadHandleHead->callback(serHandle->openedReadHandleHead->callbackParam, message, status); + } +#endif /* SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY */ + } + +#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) + if (kSerialManager_Blocking == + serHandle->handleType) /* No need to check for (NULL != serHandle->openedReadHandleHead) condition as it is + already done in SerialManager_StartReading() */ +#else + if (NULL != serHandle->openedReadHandleHead) +#endif + { + ringBufferLength = serHandle->ringBuffer.ringBufferSize - 1U - ringBufferLength; + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, ringBufferLength); + } + EnableGlobalIRQ(primask); +#endif +} + +/* + * This function is used for perdiodic check if the transfer is complete, and will be called in blocking transfer at + * non-blocking mode. The perdiodic unit is ms and default value is define by + * SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE/SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE. The function + * SerialManager_WriteTimeDelay()/SerialManager_ReadTimeDelay() is a weak function, so it could be re-implemented by + * upper layer. + */ +__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms); +__WEAK_FUNC void SerialManager_WriteTimeDelay(uint32_t ms) +{ +#if defined(OSA_USED) + OSA_TimeDelay(ms); +#endif +} + +__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms); +__WEAK_FUNC void SerialManager_ReadTimeDelay(uint32_t ms) +{ +#if defined(OSA_USED) + OSA_TimeDelay(ms); +#endif +} + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *serHandle; + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + /* Do nothing. */ +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + serial_manager_status_t status = kStatus_SerialManager_Success; +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + + uint32_t primask; + uint8_t isEmpty = 0U; + + assert(NULL != writeHandle); + assert(NULL != buffer); + assert(length > 0U); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serHandle = serialWriteHandle->serialManagerHandle; + assert(NULL != serHandle); + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialWriteHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialWriteHandle->transfer.buffer = buffer; + serialWriteHandle->transfer.length = length; + serialWriteHandle->transfer.soFar = 0U; + serialWriteHandle->transfer.mode = mode; + + if (NULL == LIST_GetHead(&serHandle->runningWriteHandleHead)) + { + isEmpty = 1U; + } + SerialManager_AddTail(&serHandle->runningWriteHandleHead, serialWriteHandle); + EnableGlobalIRQ(primask); + + if (0U != isEmpty) + { +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + status = SerialManager_StartWriting(serHandle); + if ((serial_manager_status_t)kStatus_SerialManager_Success != status) + { +#if (defined(USB_CDC_SERIAL_MANAGER_RUN_NO_HOST) && (USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1)) + if (status == kStatus_SerialManager_NotConnected) + { + SerialManager_RemoveHead(&serHandle->runningWriteHandleHead); + serialWriteHandle->transfer.buffer = 0U; + serialWriteHandle->transfer.length = 0U; + } +#endif /* USB_CDC_SERIAL_MANAGER_RUN_NO_HOST == 1 */ + return status; + } +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar) + { + if (SerialManager_needPollingIsr()) + { + SerialManager_IsrFunction(serHandle); + } + else + { + SerialManager_WriteTimeDelay(SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE); + } + } + } + return kStatus_SerialManager_Success; +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode, + uint32_t *receivedLength) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *serHandle; + uint32_t dataLength; + uint32_t primask; + + assert(NULL != readHandle); + assert(NULL != buffer); + assert(length > 0U); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + serHandle = serialReadHandle->serialManagerHandle; + assert(NULL != serHandle); + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); + + primask = DisableGlobalIRQ(); + if (NULL != serialReadHandle->transfer.buffer) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialReadHandle->transfer.buffer = buffer; + serialReadHandle->transfer.length = length; + serialReadHandle->transfer.soFar = 0U; + serialReadHandle->transfer.mode = mode; + + /* This code is reached if (serHandle->handleType != kSerialManager_Blocking)*/ +#if (!((defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))) && \ + !((defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)))) + if (length == 1U) + { + if (serHandle->ringBuffer.ringHead != serHandle->ringBuffer.ringTail) + { + buffer[serialReadHandle->transfer.soFar++] = + serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + } + else +#endif /*(!defined(SERIAL_PORT_TYPE_USBCDC) && !defined(SERIAL_PORT_TYPE_VIRTUAL))*/ + { + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; + + for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); + serialReadHandle->transfer.soFar++) + { + buffer[serialReadHandle->transfer.soFar] = serHandle->ringBuffer.ringBuffer[serHandle->ringBuffer.ringTail]; + serHandle->ringBuffer.ringTail++; + if (serHandle->ringBuffer.ringTail >= serHandle->ringBuffer.ringBufferSize) + { + serHandle->ringBuffer.ringTail = 0U; + } + } + + dataLength = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + dataLength = dataLength % serHandle->ringBuffer.ringBufferSize; + dataLength = serHandle->ringBuffer.ringBufferSize - 1U - dataLength; + + (void)SerialManager_StartReading(serHandle, readHandle, NULL, dataLength); + } + + if (NULL != receivedLength) + { + *receivedLength = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + } + else + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + if (kSerialManager_TransmissionNonBlocking == mode) + { + if (NULL != serialReadHandle->callback) + { + serial_manager_callback_message_t serialMsg; + serialMsg.buffer = buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + } + else + { + EnableGlobalIRQ(primask); + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar) + { + SerialManager_ReadTimeDelay(SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE); + } + } + } +#if (defined(SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL) && (SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL > 0U)) + uint32_t ringBufferWaterMark = + serHandle->ringBuffer.ringHead + serHandle->ringBuffer.ringBufferSize - serHandle->ringBuffer.ringTail; + ringBufferWaterMark = ringBufferWaterMark % serHandle->ringBuffer.ringBufferSize; + if (ringBufferWaterMark < (uint32_t)(serHandle->ringBuffer.ringBufferSize * RINGBUFFER_WATERMARK_THRESHOLD)) + { + (void)SerialManager_StartReading(serHandle, serHandle->openedReadHandleHead, NULL, + serialReadHandle->transfer.length); + } +#endif + return kStatus_SerialManager_Success; +} + +#else + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *serHandle; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serHandle = serialWriteHandle->serialManagerHandle; + + assert(serHandle); + + return SerialManager_StartWriting(serHandle, serialWriteHandle, buffer, length); +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *serHandle; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + serHandle = serialReadHandle->serialManagerHandle; + + assert(serHandle); + + return SerialManager_StartReading(serHandle, serialReadHandle, buffer, length); +} +#endif + +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialConfig); + + assert(NULL != serialHandle); + assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + assert(NULL != serialConfig->ringBuffer); + assert(serialConfig->ringBufferSize > 0U); + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); + serHandle->handleType = serialConfig->blockType; +#else + (void)memset(serHandle, 0, SERIAL_MANAGER_HANDLE_SIZE); +#endif + serHandle->serialPortType = serialConfig->type; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serHandle->ringBuffer.ringBuffer = serialConfig->ringBuffer; + serHandle->ringBuffer.ringBufferSize = serialConfig->ringBufferSize; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + + COMMON_TASK_init(); + +#else + if (KOSA_StatusSuccess != OSA_SemaphoreCreate((osa_semaphore_handle_t)serHandle->serSemaphore, 1U)) + { + return kStatus_SerialManager_Error; + } + + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)serHandle->taskId, OSA_TASK(SerialManager_Task), serHandle)) + { + return kStatus_SerialManager_Error; + } +#endif + +#endif + +#endif + + switch (serialConfig->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + (void)Serial_UartInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + + (void)Serial_UartInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + (void)Serial_UartDmaInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + + (void)Serial_UartDmaInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } +#endif + break; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SwoInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + status = + Serial_PortVirtualInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortVirtualInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + status = Serial_RpmsgInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), (void *)serialConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_RpmsgInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + status = + Serial_SpiMasterInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiMasterInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiMasterInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + status = Serial_SpiSlaveInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiSlaveInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_SpiSlaveInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + status = + Serial_PortBleWuInit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), serialConfig->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortBleWuInstallTxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, serHandle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_PortBleWuInstallRxCallback(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, serHandle); + } + } +#endif + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + + return status; +} + +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + if ((NULL != serHandle->openedReadHandleHead) || (0U != serHandle->openedWriteHandleCount)) + { + serialManagerStatus = kStatus_SerialManager_Busy; /*Serial Manager Busy*/ + } + else + { + switch (serHandle->serialPortType) /*serial port type*/ + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + case kSerialPort_Rpmsg: + (void)Serial_RpmsgDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + (void)Serial_SpiSlaveDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + (void)Serial_SpiMasterDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + (void)Serial_PortBleWuDeinit(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + (void)OSA_SemaphoreDestroy((osa_event_handle_t)serHandle->serSemaphore); + (void)OSA_TaskDestroy((osa_task_handle_t)serHandle->taskId); +#endif + +#endif + +#endif + } + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(NULL != serialHandle); + assert(NULL != writeHandle); + assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + primask = DisableGlobalIRQ(); + serHandle->openedWriteHandleCount++; + EnableGlobalIRQ(primask); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (serHandle->handleType == kSerialManager_Blocking) + { + serialWriteHandle->serialManagerHandle = serHandle; + return kStatus_SerialManager_Success; + } + else +#endif + { + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + } + + serialWriteHandle->serialManagerHandle = serHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *serialHandle; + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; + + assert(NULL != serialHandle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelWriting(writeHandle); +#endif + primask = DisableGlobalIRQ(); + if (serialHandle->openedWriteHandleCount > 0U) + { + serialHandle->openedWriteHandleCount--; + } + EnableGlobalIRQ(primask); +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); +#else + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE); +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_read_handle_t *serialReadHandle; /* read handle structure */ + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + uint32_t primask; + + assert(NULL != serialHandle); + assert(NULL != readHandle); + assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); + + serHandle = (serial_manager_handle_t *)serialHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (serHandle->handleType == kSerialManager_Blocking) + { + serialReadHandle->serialManagerHandle = serHandle; + return kStatus_SerialManager_Success; + } +#endif + primask = DisableGlobalIRQ(); + if (serHandle->openedReadHandleHead != NULL) + { + serialManagerStatus = kStatus_SerialManager_Busy; + } + else + { + serHandle->openedReadHandleHead = serialReadHandle; + + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + serialReadHandle->serialManagerHandle = serHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; +#endif + } + EnableGlobalIRQ(primask); + return serialManagerStatus; +} + +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) +{ + serial_manager_handle_t *serialHandle; + serial_manager_read_handle_t *serialReadHandle; + uint32_t primask; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + serialHandle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; + + assert((NULL != serialHandle) && (serialHandle->openedReadHandleHead == serialReadHandle)); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelReading(readHandle); +#endif + + primask = DisableGlobalIRQ(); + serialHandle->openedReadHandleHead = NULL; + EnableGlobalIRQ(primask); +#if (defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_TRANSFER_NON_BLOCKING > 0U)) + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); +#else + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE); +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking); +#else + return SerialManager_Write(writeHandle, buffer, length); +#endif +} + +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL); +#else + return SerialManager_Read(readHandle, buffer, length); +#endif +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length) +{ + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking); +} + +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if ((defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) || \ + (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U))) + + serial_manager_read_handle_t *serialReadHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + return (serial_manager_status_t)SerialManager_StartReading(serialReadHandle->serialManagerHandle, readHandle, + buffer, length); +#else + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL); +#endif +} + +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle) +{ + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + uint8_t isNotUsed = 0U; + uint8_t isNotNeed2Cancel = 0U; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(NULL != serialWriteHandle->serialManagerHandle); + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + if ((NULL != serialWriteHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead( + &serialWriteHandle->serialManagerHandle->runningWriteHandleHead)) + { + if (kLIST_Ok == LIST_RemoveElement(&serialWriteHandle->link)) + { + isNotUsed = 1U; + } + else + { + isNotNeed2Cancel = 1U; + } + } + EnableGlobalIRQ(primask); + + if (0U == isNotNeed2Cancel) + { + if (0U != isNotUsed) + { + serialWriteHandle->transfer.soFar = 0; + serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled; + + SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task; + serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = + serialWriteHandle->serialManagerHandle; + COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg); +#else + primask = DisableGlobalIRQ(); + serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_SENT]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore); +#endif + +#else + SerialManager_Task(serialWriteHandle->serialManagerHandle); +#endif + } + else + { + switch (serialWriteHandle->serialManagerHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + (void)Serial_PortVirtualCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + (void)Serial_SpiMasterCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + (void)Serial_SpiSlaveCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + (void)Serial_PortBleWuCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + } + +#if (defined(OSA_USED) && defined(SERIAL_MANAGER_TASK_HANDLE_TX) && (SERIAL_MANAGER_TASK_HANDLE_TX == 1)) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + /* Need to support common_task. */ +#else /* SERIAL_MANAGER_USE_COMMON_TASK */ + primask = DisableGlobalIRQ(); + serialWriteHandle->serialManagerHandle->serialManagerState[SERIAL_EVENT_DATA_START_SEND]++; + EnableGlobalIRQ(primask); + (void)OSA_SemaphorePost((osa_semaphore_handle_t)serialWriteHandle->serialManagerHandle->serSemaphore); + +#endif /* SERIAL_MANAGER_USE_COMMON_TASK */ +#else /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle); +#endif /* OSA_USED && SERIAL_MANAGER_TASK_HANDLE_TX */ + } + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_callback_message_t serialMsg; + uint8_t *buffer; + uint32_t primask; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + if ((NULL != serialReadHandle->transfer.buffer) && + (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + buffer = serialReadHandle->transfer.buffer; + serialReadHandle->transfer.buffer = NULL; + serialReadHandle->transfer.length = 0; + serialMsg.buffer = buffer; + serialMsg.length = serialReadHandle->transfer.soFar; + EnableGlobalIRQ(primask); + + if (NULL != buffer) + { + if (NULL != serialReadHandle->callback) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &serialMsg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength) +{ + assert(NULL != receivedLength); + + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength); +} + +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_write_handle_t *serialWriteHandle; + + assert(NULL != writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + serialWriteHandle->callbackParam = callbackParam; + serialWriteHandle->callback = callback; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_read_handle_t *serialReadHandle; + + assert(NULL != readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + serialReadHandle->callbackParam = callbackParam; + serialReadHandle->callback = callback; + + return kStatus_SerialManager_Success; +} +#endif + +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaEnterLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} + +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) +{ + serial_manager_handle_t *serHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(NULL != serialHandle); + + serHandle = (serial_manager_handle_t *)serialHandle; + + switch (serHandle->serialPortType) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) + case kSerialPort_UartDma: + status = Serial_UartDmaExitLowpower(((serial_handle_t)&serHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Virtual: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + case kSerialPort_Rpmsg: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) + case kSerialPort_SpiMaster: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) + case kSerialPort_SpiSlave: + break; +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + case kSerialPort_BleWu: + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + return status; +} +/*! + * @brief This function performs initialization of the callbacks structure used to disable lowpower + * when serial manager is active. + * + * + * @param pfCallback Pointer to the function structure used to allow/disable lowpower. + * + */ +void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback) +{ + s_pfserialLowpowerCriticalCallbacks = pfCallback; + (void)s_pfserialLowpowerCriticalCallbacks; +} diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h new file mode 100644 index 000000000..16d7ef5a5 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_manager.h @@ -0,0 +1,856 @@ +/* + * Copyright 2018-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_MANAGER_H__ +#define __SERIAL_MANAGER_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup serialmanager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U)) +#error When SERIAL_MANAGER_NON_BLOCKING_MODE=0, DEBUG_CONSOLE_TRANSFER_NON_BLOCKING can not be set. +#else +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#endif +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U) +#endif +#endif + +/*! @brief Enable or ring buffer flow control (1 - enable, 0 - disable) */ +#ifndef SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL +#define SERIAL_MANAGER_RING_BUFFER_FLOWCONTROL (0U) +#endif + +/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART +#define SERIAL_PORT_TYPE_UART (0U) +#endif + +/*! @brief Enable or disable uart dma port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART_DMA +#define SERIAL_PORT_TYPE_UART_DMA (0U) +#endif +/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_USBCDC +#define SERIAL_PORT_TYPE_USBCDC (0U) +#endif + +/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SWO +#define SERIAL_PORT_TYPE_SWO (0U) +#endif + +/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_VIRTUAL +#define SERIAL_PORT_TYPE_VIRTUAL (0U) +#endif + +/*! @brief Enable or disable rPMSG port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_RPMSG +#define SERIAL_PORT_TYPE_RPMSG (0U) +#endif + +/*! @brief Enable or disable SPI Master port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SPI_MASTER +#define SERIAL_PORT_TYPE_SPI_MASTER (0U) +#endif + +/*! @brief Enable or disable SPI Slave port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SPI_SLAVE +#define SERIAL_PORT_TYPE_SPI_SLAVE (0U) +#endif + +/*! @brief Enable or disable BLE WU port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_BLE_WU +#define SERIAL_PORT_TYPE_BLE_WU (0U) +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE == 1U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE == 0U)) +#warning When SERIAL_PORT_TYPE_SPI_SLAVE=1, SERIAL_MANAGER_NON_BLOCKING_MODE should be set. +#undef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#endif +#endif + +/*! @brief Set the default delay time in ms used by SerialManager_WriteTimeDelay(). */ +#ifndef SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE +#define SERIAL_MANAGER_WRITE_TIME_DELAY_DEFAULT_VALUE (1U) +#endif + +/*! @brief Set the default delay time in ms used by SerialManager_ReadTimeDelay(). */ +#ifndef SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE +#define SERIAL_MANAGER_READ_TIME_DELAY_DEFAULT_VALUE (1U) +#endif + +/*! @brief Enable or disable SerialManager_Task() handle RX data available notify */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY +#define SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY (0U) +#endif +#if (defined(SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY) && (SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY > 0U)) +#ifndef OSA_USED +#error When SERIAL_MANAGER_TASK_HANDLE_RX_AVAILABLE_NOTIFY=1, OSA_USED must be set. +#endif +#endif + +/*! @brief Set serial manager write handle size */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#else +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE (4U) +#endif + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "fsl_component_serial_port_uart.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#include "fsl_component_serial_port_uart.h" +#endif +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +#include "fsl_component_serial_port_rpmsg.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_usb.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +#include "fsl_component_serial_port_swo.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) +#include "fsl_component_serial_port_spi.h" +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +#include "fsl_component_serial_port_spi.h" +#endif +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "fsl_component_serial_port_virtual.h" +#endif +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for BLE WU. +#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */ + +#include "fsl_component_serial_port_ble_wu.h" +#endif /* SERIAL_PORT_TYPE_BLE_WU */ + +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + +#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#if (SERIAL_PORT_UART_DMA_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_DMA_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + +#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && (SERIAL_PORT_TYPE_SPI_MASTER > 0U)) +#if (SERIAL_PORT_SPI_MASTER_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_MASTER_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +#if (SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SPI_SLAVE_HANDLE_SIZE +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + +#if (SERIAL_PORT_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_VIRTUAL_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) + +#if (SERIAL_PORT_RPMSG_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_RPMSG_HANDLE_SIZE + +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) + +#if (SERIAL_PORT_BLE_WU_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_BLE_WU_HANDLE_SIZE +#endif + +#endif + +/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */ +#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U))) +#else +#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO, SERIAL_PORT_TYPE_VIRTUAL, and SERIAL_PORT_TYPE_BLE_WU should not be cleared at same time. +#endif + +/*! @brief Macro to determine whether use common task. */ +#ifndef SERIAL_MANAGER_USE_COMMON_TASK +#define SERIAL_MANAGER_USE_COMMON_TASK (0U) +#endif + +#if defined(OSA_USED) +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#endif +/*! @brief Enable or disable SerialManager_Task() handle TX to prevent recursive calling */ +#ifndef SERIAL_MANAGER_TASK_HANDLE_TX +#define SERIAL_MANAGER_TASK_HANDLE_TX (1U) +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) +#include "fsl_os_abstraction.h" +#endif +#endif + +/*! @brief Definition of serial manager handle size. */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(OSA_USED) && !(defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))) +#define SERIAL_MANAGER_HANDLE_SIZE \ + (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U + OSA_TASK_HANDLE_SIZE + OSA_EVENT_HANDLE_SIZE) +#else /*defined(OSA_USED)*/ +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 124U) +#endif /*defined(OSA_USED)*/ +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 16U) +#else +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#define SERIAL_MANAGER_BLOCK_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#endif + +/*! + * @brief Defines the serial manager handle + * + * This macro is used to define a 4 byte aligned serial manager handle. + * Then use "(serial_handle_t)name" to get the serial manager handle. + * + * The macro should be global and could be optional. You could also define serial manager handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_HANDLE_DEFINE(serialManagerHandle); + * @endcode + * + * @param name The name string of the serial manager handle. + */ +#define SERIAL_MANAGER_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager write handle + * + * This macro is used to define a 4 byte aligned serial manager write handle. + * Then use "(serial_write_handle_t)name" to get the serial manager write handle. + * + * The macro should be global and could be optional. You could also define serial manager write handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialManagerwriteHandle); + * @endcode + * + * @param name The name string of the serial manager write handle. + */ +#define SERIAL_MANAGER_WRITE_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_WRITE_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +/*! + * @brief Defines the serial manager read handle + * + * This macro is used to define a 4 byte aligned serial manager read handle. + * Then use "(serial_read_handle_t)name" to get the serial manager read handle. + * + * The macro should be global and could be optional. You could also define serial manager read handle by yourself. + * + * This is an example, + * @code + * SERIAL_MANAGER_READ_HANDLE_DEFINE(serialManagerReadHandle); + * @endcode + * + * @param name The name string of the serial manager read handle. + */ +#define SERIAL_MANAGER_READ_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#define SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(name) \ + uint32_t name[((SERIAL_MANAGER_READ_BLOCK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +/*! @brief Macro to set serial manager task priority. */ +#ifndef SERIAL_MANAGER_TASK_PRIORITY +#define SERIAL_MANAGER_TASK_PRIORITY (2U) +#endif + +/*! @brief Macro to set serial manager task stack size. */ +#ifndef SERIAL_MANAGER_TASK_STACK_SIZE +#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U) +#endif + +/*! @brief The handle of the serial manager module */ +typedef void *serial_handle_t; + +/*! @brief The write handle of the serial manager module */ +typedef void *serial_write_handle_t; + +/*! @brief The read handle of the serial manager module */ +typedef void *serial_read_handle_t; + +#ifndef _SERIAL_PORT_T_ +#define _SERIAL_PORT_T_ +/*! @brief serial port type*/ +typedef enum _serial_port_type +{ + kSerialPort_None = 0U, /*!< Serial port is none */ + kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_Virtual, /*!< Serial port Virtual */ + kSerialPort_Rpmsg, /*!< Serial port RPMSG */ + kSerialPort_UartDma, /*!< Serial port UART DMA*/ + kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/ + kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/ + kSerialPort_BleWu, /*!< Serial port BLE WU */ +} serial_port_type_t; +#endif + +/*! @brief serial manager type*/ +typedef enum _serial_manager_type +{ + kSerialManager_NonBlocking = 0x0U, /*!< None blocking handle*/ + kSerialManager_Blocking = 0x8F41U, /*!< Blocking handle*/ +} serial_manager_type_t; +/*! @brief serial manager config structure*/ +typedef struct _serial_manager_config +{ +#if defined(SERIAL_MANAGER_NON_BLOCKING_MODE) + uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. + Besides, the memory space cannot be free during the lifetime of the serial + manager module. */ + uint32_t ringBufferSize; /*!< The size of the ring buffer */ +#endif + serial_port_type_t type; /*!< Serial port type */ + serial_manager_type_t blockType; /*!< Serial manager port type */ + void *portConfig; /*!< Serial port configuration */ +} serial_manager_config_t; + +/*! @brief serial manager error code*/ +typedef enum _serial_manager_status +{ + kStatus_SerialManager_Success = kStatus_Success, /*!< Success */ + kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */ + kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */ + kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */ + kStatus_SerialManager_Canceled = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */ + kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */ + kStatus_SerialManager_RingBufferOverflow = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */ + kStatus_SerialManager_NotConnected = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 7), /*!< The host is not connected */ +} serial_manager_status_t; + +/*! @brief Callback message structure */ +typedef struct _serial_manager_callback_message +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ +} serial_manager_callback_message_t; + +/*! @brief serial manager callback function */ +typedef void (*serial_manager_callback_t)(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); + +/*! @brief serial manager Lowpower Critical callback function */ +typedef int32_t (*serial_manager_lowpower_critical_callback_t)(int32_t power_mode); +typedef struct _serial_manager_lowpower_critical_CBs_t +{ + serial_manager_lowpower_critical_callback_t serialEnterLowpowerCriticalFunc; + serial_manager_lowpower_critical_callback_t serialExitLowpowerCriticalFunc; +} serial_manager_lowpower_critical_CBs_t; +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure. + * + * This function configures the Serial Manager module with user-defined settings. + * The user can configure the configuration structure. + * The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE + * allocated by the caller. + * The Serial Manager module supports three types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc), USB + * CDC and swo. + * Please refer to #serial_port_type_t for serial port setting. + * These three types can be set by using #serial_manager_config_t. + * + * Example below shows how to use this API to configure the Serial Manager. + * For UART, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_uart_config_t uartConfig; + * config.type = kSerialPort_Uart; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * uartConfig.instance = 0; + * uartConfig.clockRate = 24000000; + * uartConfig.baudRate = 115200; + * uartConfig.parityMode = kSerialManager_UartParityDisabled; + * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * config.portConfig = &uartConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * For USB CDC, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static SERIAL_MANAGER_HANDLE_DEFINE(s_serialHandle); + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_usb_cdc_config_t usbCdcConfig; + * config.type = kSerialPort_UsbCdc; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0; + * config.portConfig = &usbCdcConfig; + * SerialManager_Init((serial_handle_t)s_serialHandle, &config); + * @endcode + * + * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_HANDLE_DEFINE(serialHandle); + * or + * uint32_t serialHandle[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param serialConfig Pointer to user-defined configuration structure. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. + */ +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, const serial_manager_config_t *serialConfig); + +/*! + * @brief De-initializes the serial manager module instance. + * + * This function de-initializes the serial manager module instance. If the opened writing or + * reading handle is not closed, the function will return kStatus_SerialManager_Busy. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed. + * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed. + */ +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle); + +/*! + * @brief Opens a writing handle for the serial manager module. + * + * This function Opens a writing handle for the serial manager module. If the serial manager needs to + * be used in different tasks, the task should open a dedicated write handle for itself by calling + * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing + * handle at the same time, multiple writing handles need to be opened when the multiple transmission + * is needed for a task. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param writeHandle The serial manager module writing handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_WRITE_HANDLE_DEFINE(writeHandle); + * or + * uint32_t writeHandle[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_HandleConflict The writing handle was opened. + * @retval kStatus_SerialManager_Success The writing handle is opened. + * + * Example below shows how to use this API to write data. + * For task 1, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle1); + * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle1); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle1, + * Task1_SerialManagerTxCallback, + * s_serialWriteHandle1); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle1, + * s_nonBlockingWelcome1, + * sizeof(s_nonBlockingWelcome1) - 1U); + * @endcode + * For task 2, + * @code + * static SERIAL_MANAGER_WRITE_HANDLE_DEFINE(s_serialWriteHandle2); + * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n"; + * SerialManager_OpenWriteHandle((serial_handle_t)serialHandle, (serial_write_handle_t)s_serialWriteHandle2); + * SerialManager_InstallTxCallback((serial_write_handle_t)s_serialWriteHandle2, + * Task2_SerialManagerTxCallback, + * s_serialWriteHandle2); + * SerialManager_WriteNonBlocking((serial_write_handle_t)s_serialWriteHandle2, + * s_nonBlockingWelcome2, + * sizeof(s_nonBlockingWelcome2) - 1U); + * @endcode + */ +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle); + +/*! + * @brief Closes a writing handle for the serial manager module. + * + * This function Closes a writing handle for the serial manager module. + * + * @param writeHandle The serial manager module writing handle pointer. + * @retval kStatus_SerialManager_Success The writing handle is closed. + */ +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle); + +/*! + * @brief Opens a reading handle for the serial manager module. + * + * This function Opens a reading handle for the serial manager module. The reading handle can not be + * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when + * the previous reading handle is not closed. And there can only be one buffer for receiving for the + * reading handle at the same time. + * + * @param serialHandle The serial manager module handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * @param readHandle The serial manager module reading handle pointer. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SERIAL_MANAGER_READ_HANDLE_DEFINE(readHandle); + * or + * uint32_t readHandle[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The reading handle is opened. + * @retval kStatus_SerialManager_Busy Previous reading handle is not closed. + * + * Example below shows how to use this API to read data. + * @code + * static SERIAL_MANAGER_READ_HANDLE_DEFINE(s_serialReadHandle); + * SerialManager_OpenReadHandle((serial_handle_t)serialHandle, (serial_read_handle_t)s_serialReadHandle); + * static uint8_t s_nonBlockingBuffer[64]; + * SerialManager_InstallRxCallback((serial_read_handle_t)s_serialReadHandle, + * APP_SerialManagerRxCallback, + * s_serialReadHandle); + * SerialManager_ReadNonBlocking((serial_read_handle_t)s_serialReadHandle, + * s_nonBlockingBuffer, + * sizeof(s_nonBlockingBuffer)); + * @endcode + */ +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle); + +/*! + * @brief Closes a reading for the serial manager module. + * + * This function Closes a reading for the serial manager module. + * + * @param readHandle The serial manager module reading handle pointer. + * @retval kStatus_SerialManager_Success The reading handle is closed. + */ +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle); + +/*! + * @brief Transmits data with the blocking mode. + * + * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function SerialManager_WriteNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelWriting cannot be used to abort the transmission of this function. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the blocking mode. + * + * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function SerialManager_ReadNonBlocking + * cannot be used at the same time. + * And, the function SerialManager_CancelReading cannot be used to abort the transmission of this function. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief Transmits data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be sent. + * When all data is sent, the module notifies the upper layer through a TX callback function and passes + * the status parameter @ref kStatus_SerialManager_Success. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking + * cannot be used at the same time. And, the TX callback is mandatory before the function could be used. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be received. + * When all data is received, the module driver notifies the upper layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking + * cannot be used at the same time. And, the RX callback is mandatory before the function could be used. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Tries to read data. + * + * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be + * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length. + * After the data is copied, the actual data length is passed by the parameter length. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @param receivedLength Length received from the ring buffer directly. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength); + +/*! + * @brief Cancels unfinished send transmission. + * + * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer + * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of + * the function #SerialManager_WriteBlocking. + * + * @param writeHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the sending. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle); + +/*! + * @brief Cancels unfinished receive transmission. + * + * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper + * layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of + * the function #SerialManager_ReadBlocking. + * + * @param readHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the receiving. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle); + +/*! + * @brief Installs a TX callback and callback parameter. + * + * This function is used to install the TX callback and callback parameter for the serial manager module. + * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param writeHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Installs a RX callback and callback parameter. + * + * This function is used to install the RX callback and callback parameter for the serial manager module. + * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param readHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Check if need polling ISR. + * + * This function is used to check if need polling ISR. + * + * @retval TRUE if need polling. + */ +static inline bool SerialManager_needPollingIsr(void) +{ +#if (defined(__DSC__) && defined(__CW__)) + return !(isIRQAllowed()); +#elif defined(CPSR_M_Msk) + return (0x13 == (__get_CPSR() & CPSR_M_Msk)); +#elif defined(DAIF_I_BIT) + return (__get_DAIF() & DAIF_I_BIT); +#elif defined(__XCC__) + return (xthal_get_interrupt() & xthal_get_intenable()); +#else + return (0U != __get_IPSR()); +#endif +} +#endif + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle); + +/*! + * @brief This function performs initialization of the callbacks structure used to disable lowpower + * when serial manager is active. + * + * + * @param pfCallback Pointer to the function structure used to allow/disable lowpower. + * + */ +void SerialManager_SetLowpowerCriticalCb(const serial_manager_lowpower_critical_CBs_t *pfCallback); + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* __SERIAL_MANAGER_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h new file mode 100644 index 000000000..c2090348d --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_internal.h @@ -0,0 +1,189 @@ +/* + * Copyright 2019-2020, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_INTERNAL_H__ +#define __SERIAL_PORT_INTERNAL_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartIsrFunction(serial_handle_t serialHandle); +#endif +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle); +#endif +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartDmaIsrFunction(serial_handle_t serialHandle); +#endif +serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_RPMSG) && (SERIAL_PORT_TYPE_RPMSG > 0U)) +serial_manager_status_t Serial_RpmsgInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_RpmsgDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_RpmsgWriteBlocking(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_RpmsgCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_RpmsgInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +#endif +serial_manager_status_t Serial_RpmsgEnterLowpower(serial_handle_t serialHandle); +serial_manager_status_t Serial_RpmsgExitLowpower(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) +serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_SwoIsrFunction(serial_handle_t serialHandle); +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) +serial_manager_status_t Serial_PortVirtualInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_PortVirtualDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortVirtualCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortVirtualInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_PortVirtualInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_PortVirtualIsrFunction(serial_handle_t serialHandle); +#endif +#if (defined(SERIAL_PORT_TYPE_SPI_MASTER) && SERIAL_PORT_TYPE_SPI_MASTER > 0U) +serial_manager_status_t Serial_SpiMasterInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_SpiMasterDeinit(serial_handle_t serialHandle); +void Serial_SpiMasterTxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam); +void Serial_SpiMasterRxCallback(hal_spi_master_handle_t handle, hal_spi_status_t status, void *callbackParam); +serial_manager_status_t Serial_SpiMasterWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_SpiMasterRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SpiMasterInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiMasterInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiMasterCancelWrite(serial_handle_t serialHandle); + +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_SPI_SLAVE) && (SERIAL_PORT_TYPE_SPI_SLAVE > 0U)) +serial_manager_status_t Serial_SpiSlaveInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_SpiSlaveDeinit(serial_handle_t serialHandle); +void Serial_SpiSlaveTxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam); +void Serial_SpiSlaveRxCallback(hal_spi_slave_handle_t handle, hal_spi_status_t status, void *callbackParam); +serial_manager_status_t Serial_SpiSlaveWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_SpiSlaveRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SpiSlaveInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiSlaveInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SpiSlaveCancelWrite(serial_handle_t serialHandle); + +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_BLE_WU) && (SERIAL_PORT_TYPE_BLE_WU > 0U)) +serial_manager_status_t Serial_PortBleWuInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_PortBleWuDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortBleWuWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortBleWuRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_PortBleWuCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_PortBleWuInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_PortBleWuInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_PortBleWuIsrFunction(serial_handle_t serialHandle); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __SERIAL_PORT_INTERNAL_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c new file mode 100644 index 000000000..c2073f798 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.c @@ -0,0 +1,717 @@ +/* + * Copyright 2018 -2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_component_serial_manager.h" +#include "fsl_component_serial_port_internal.h" + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) || \ + (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#include "fsl_adapter_uart.h" + +#include "fsl_component_serial_port_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U +typedef struct _serial_uart_send_state +{ + uint8_t *buffer; + uint32_t length; + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; +} serial_uart_send_state_t; + +typedef struct _serial_uart_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + volatile uint8_t rxEnable; + uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH]; +} serial_uart_recv_state_t; + +typedef struct _serial_uart_dma_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + volatile uint8_t rxEnable; + uint8_t readBuffer[SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH]; +} serial_uart_dma_recv_state_t; + +typedef struct _serial_uart_block_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +} serial_uart_block_state_t; +#endif + +typedef struct _serial_uart_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_recv_state_t rx; +#endif +} serial_uart_state_t; +#endif +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +typedef struct _serial_uart_dma_state +{ + UART_HANDLE_DEFINE(usartHandleBuffer); + UART_DMA_HANDLE_DEFINE(uartDmaHandle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_dma_recv_state_t rx; +#endif +} serial_uart_dma_state_t; +#endif +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static serial_manager_status_t Serial_UartEnableReceiving(serial_uart_state_t *serialUartHandle) +{ +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + if (1U == serialUartHandle->rx.rxEnable) + { + serialUartHandle->rx.busy = 1U; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + if (kStatus_HAL_UartSuccess != + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if (kStatus_HAL_UartSuccess != + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } + return kStatus_SerialManager_Success; +} + +/* UART user callback */ +static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + + assert(userData); + serialUartHandle = (serial_uart_state_t *)userData; + + if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status) + { +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if ((NULL != serialUartHandle->rx.callback)) + { + serialMsg.buffer = &serialUartHandle->rx.readBuffer[0]; + serialMsg.length = sizeof(serialUartHandle->rx.readBuffer); + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) + { + if (0U != serialUartHandle->tx.busy) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Success); + } + } + } + else + { + } +} +#endif + +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_state_t *serialUartHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_port_uart_config_t *uartConfig = (serial_port_uart_config_t *)serialConfig; +#endif + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +#if 0 /* Not used below! */ + hal_uart_transfer_t transfer; +#endif +#endif +#endif + + assert(serialConfig); + assert(serialHandle); + assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t)); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + serialManagerStatus = (serial_manager_status_t)HAL_UartInit( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig); + assert(kStatus_SerialManager_Success == serialManagerStatus); + (void)serialManagerStatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->rx.rxEnable = uartConfig->enableRx; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + + (void)HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartCallback, serialUartHandle); +#else + (void)HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), Serial_UartCallback, + serialUartHandle); +#endif +#endif + + return serialManagerStatus; +} + +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif +#endif + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + if (0U != serialUartHandle->tx.busy) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = buffer; + transfer.dataSize = length; + uartstatus = + HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer); +#else + + uartstatus = HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +#endif + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + assert(serialHandle); + (void)buffer; + (void)length; + return (serial_manager_status_t)Serial_UartEnableReceiving(serialHandle); +} + +#else + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + buffer, length); +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartReceiveBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if (0U != isBusy) + { + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)Serial_UartEnableReceiving(serialUartHandle); +#endif + return kStatus_SerialManager_Success; +} + +void Serial_UartIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_status_t status = kStatus_SerialManager_Success; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + status = Serial_UartEnableReceiving(serialUartHandle); +#endif + + return status; +} + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static serial_manager_status_t Serial_UartDmaEnableReceiving(serial_uart_dma_state_t *serialUartHandle) +{ + if (1U == serialUartHandle->rx.rxEnable) + { + serialUartHandle->rx.busy = 1U; + if (kStatus_HAL_UartDmaSuccess != + HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer), + false)) + + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } + return kStatus_SerialManager_Success; +} + +/* UART user callback */ +static void Serial_UartDmaCallback(hal_uart_dma_handle_t handle, hal_dma_callback_msg_t *dmaMsg, void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_callback_message_t cb_msg; + + assert(callbackParam); + serialUartHandle = (serial_uart_dma_state_t *)callbackParam; + + if (((hal_uart_dma_status_t)kStatus_HAL_UartDmaRxIdle == dmaMsg->status) || + (kStatus_HAL_UartDmaIdleline == dmaMsg->status)) + { + if ((NULL != serialUartHandle->rx.callback)) + { + cb_msg.buffer = dmaMsg->data; + cb_msg.length = dmaMsg->dataSize; + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &cb_msg, kStatus_SerialManager_Success); + } + + if (kStatus_HAL_UartDmaSuccess == + HAL_UartDMATransferReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer), + false)) + { + serialUartHandle->rx.busy = 1U; + } + } + else if (kStatus_HAL_UartDmaTxIdle == dmaMsg->status) + { + if (0U != serialUartHandle->tx.busy) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + cb_msg.buffer = dmaMsg->data; + cb_msg.length = dmaMsg->dataSize; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &cb_msg, + kStatus_SerialManager_Success); + } + } + } + else + { + } +} + +#endif + +serial_manager_status_t Serial_UartDmaInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_dma_state_t *serialUartHandle; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + serial_port_uart_dma_config_t *uartConfig = (serial_port_uart_dma_config_t *)serialConfig; +#endif + serial_manager_status_t serialManagerStatus = kStatus_SerialManager_Success; + + assert(serialConfig); + assert(serialHandle); + + assert(SERIAL_PORT_UART_DMA_HANDLE_SIZE >= sizeof(serial_uart_dma_state_t)); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + serialManagerStatus = (serial_manager_status_t)HAL_UartInit( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), (const hal_uart_config_t *)serialConfig); + assert(kStatus_SerialManager_Success == serialManagerStatus); + (void)serialManagerStatus; + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + + hal_uart_dma_config_t dmaConfig; + + dmaConfig.uart_instance = uartConfig->instance; + dmaConfig.dma_instance = uartConfig->dma_instance; + dmaConfig.rx_channel = uartConfig->rx_channel; + dmaConfig.tx_channel = uartConfig->tx_channel; + dmaConfig.dma_mux_configure = uartConfig->dma_mux_configure; + dmaConfig.dma_channel_mux_configure = uartConfig->dma_channel_mux_configure; + + // Init uart dma + (void)HAL_UartDMAInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + (hal_uart_dma_handle_t *)serialUartHandle->uartDmaHandle, &dmaConfig); + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + + serialUartHandle->rx.rxEnable = uartConfig->enableRx; + (void)HAL_UartDMATransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartDmaCallback, serialUartHandle); + +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialManagerStatus = Serial_UartDmaEnableReceiving(serialUartHandle); +#endif + + return serialManagerStatus; +} + +serial_manager_status_t Serial_UartDmaDeinit(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + (void)HAL_UartDMAAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + (void)HAL_UartDMADeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartDmaWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_dma_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + if (0U != serialUartHandle->tx.busy) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + + uartstatus = (hal_uart_status_t)HAL_UartDMATransferSend( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); + + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartDmaCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_callback_message_t serialMsg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + + (void)HAL_UartDMAAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + + if (0U != isBusy) + { + if ((NULL != serialUartHandle->tx.callback)) + { + serialMsg.buffer = serialUartHandle->tx.buffer; + serialMsg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &serialMsg, + kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +void Serial_UartDmaIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +serial_manager_status_t Serial_UartDmaEnterLowpower(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + uartstatus = HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDmaExitLowpower(serial_handle_t serialHandle) +{ + serial_uart_dma_state_t *serialUartHandle; + serial_manager_status_t status = kStatus_SerialManager_Success; + hal_uart_status_t uartstatus; + + assert(serialHandle); + + serialUartHandle = (serial_uart_dma_state_t *)serialHandle; + + uartstatus = HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + assert(kStatus_HAL_UartSuccess == uartstatus); + (void)uartstatus; + + return status; +} +#endif +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h new file mode 100644 index 000000000..a4221cbfe --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/serial_manager/fsl_component_serial_port_uart.h @@ -0,0 +1,106 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_UART_H__ +#define __SERIAL_PORT_UART_H__ + +#include "fsl_adapter_uart.h" + +/*! + * @addtogroup serial_port_uart + * @ingroup serialmanager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief serial port uart handle size*/ + +#ifndef SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH +#define SERIAL_PORT_UART_DMA_RECEIVE_DATA_LENGTH (64U) +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE) +#define SERIAL_PORT_UART_BLOCK_HANDLE_SIZE (HAL_UART_BLOCK_HANDLE_SIZE) +#else +#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE) +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#define SERIAL_PORT_UART_DMA_HANDLE_SIZE (76U + HAL_UART_DMA_HANDLE_SIZE + 132U) +#endif + +#ifndef SERIAL_USE_CONFIGURE_STRUCTURE +#define SERIAL_USE_CONFIGURE_STRUCTURE (0U) /*!< Enable or disable the confgure structure pointer */ +#endif + +/*! @brief serial port uart parity mode*/ +typedef enum _serial_port_uart_parity_mode +{ + kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kSerialManager_UartParityEven = 0x2U, /*!< Parity even enabled */ + kSerialManager_UartParityOdd = 0x3U, /*!< Parity odd enabled */ +} serial_port_uart_parity_mode_t; + +/*! @brief serial port uart stop bit count*/ +typedef enum _serial_port_uart_stop_bit_count +{ + kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */ + kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */ +} serial_port_uart_stop_bit_count_t; + +typedef struct _serial_port_uart_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ + +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} serial_port_uart_config_t; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +typedef struct _serial_port_uart_dma_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif + uint8_t dma_instance; + uint8_t rx_channel; + uint8_t tx_channel; + void *dma_mux_configure; + void *dma_channel_mux_configure; + +} serial_port_uart_dma_config_t; +#endif +/*! @} */ +#endif /* __SERIAL_PORT_UART_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h new file mode 100644 index 000000000..5bb9f8269 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_uart.h @@ -0,0 +1,829 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_UART_ADAPTER_H__ +#define __HAL_UART_ADAPTER_H__ + +#include "fsl_common.h" +#if defined(SDK_OS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/*! + * @addtogroup UART_Adapter + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define UART_ADAPTER_NON_BLOCKING_MODE (1U) +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define UART_ADAPTER_NON_BLOCKING_MODE (0U) +#else +#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif +#endif + +#if defined(__GIC_PRIO_BITS) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (25U) +#endif +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#endif +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#ifndef HAL_UART_ISR_PRIORITY +#define HAL_UART_ISR_PRIORITY (3U) +#endif +#endif +#endif + +#ifndef HAL_UART_ADAPTER_LOWPOWER +#define HAL_UART_ADAPTER_LOWPOWER (0U) +#endif /* HAL_UART_ADAPTER_LOWPOWER */ + +/*! @brief Enable or disable uart hardware FIFO mode (1 - enable, 0 - disable) */ +#ifndef HAL_UART_ADAPTER_FIFO +#define HAL_UART_ADAPTER_FIFO (1U) +#endif /* HAL_UART_ADAPTER_FIFO */ + +#if (defined(SERIAL_PORT_TYPE_UART_DMA) && (SERIAL_PORT_TYPE_UART_DMA > 0U)) +#ifndef HAL_UART_DMA_ENABLE +#define HAL_UART_DMA_ENABLE (1U) +#endif +#endif + +#ifndef HAL_UART_DMA_ENABLE +#define HAL_UART_DMA_ENABLE (0U) +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief Enable or disable uart DMA adapter int mode (1 - enable, 0 - disable) */ +#ifndef HAL_UART_DMA_INIT_ENABLE +#define HAL_UART_DMA_INIT_ENABLE (1U) +#endif /* HAL_SPI_MASTER_DMA_INIT_ENABLE */ + +/*! @brief Definition of uart dma adapter software idleline detection timeout value in ms. */ +#ifndef HAL_UART_DMA_IDLELINE_TIMEOUT +#define HAL_UART_DMA_IDLELINE_TIMEOUT (1U) +#endif /* HAL_UART_DMA_IDLELINE_TIMEOUT */ + +/*! @brief Definition of uart adapter handle size. */ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#define HAL_UART_BLOCK_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#else +#define HAL_UART_HANDLE_SIZE (8U + HAL_UART_ADAPTER_LOWPOWER * 16U + HAL_UART_DMA_ENABLE * 4U) +#endif + +/*! @brief Definition of uart dma adapter handle size. */ +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) +#define HAL_UART_DMA_HANDLE_SIZE (124U + HAL_UART_ADAPTER_LOWPOWER * 36U) +#elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) +#define HAL_UART_DMA_HANDLE_SIZE (140U + HAL_UART_ADAPTER_LOWPOWER * 36U) +#else +#error This SOC does not have DMA or EDMA available! +#endif +#endif /* HAL_UART_DMA_ENABLE */ + +/*! + * @brief Defines the uart handle + * + * This macro is used to define a 4 byte aligned uart handle. + * Then use "(hal_uart_handle_t)name" to get the uart handle. + * + * The macro should be global and could be optional. You could also define uart handle by yourself. + * + * This is an example, + * @code + * UART_HANDLE_DEFINE(uartHandle); + * @endcode + * + * @param name The name string of the uart handle. + */ +#define UART_HANDLE_DEFINE(name) uint32_t name[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#define UART_DMA_HANDLE_DEFINE(name) \ + uint32_t name[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] +#endif + +/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */ +#ifndef HAL_UART_TRANSFER_MODE +#define HAL_UART_TRANSFER_MODE (0U) +#endif + +/*! @brief The handle of uart adapter. */ +typedef void *hal_uart_handle_t; + +/*! @brief The handle of uart dma adapter. */ +typedef void *hal_uart_dma_handle_t; + +/*! @brief UART status */ +typedef enum _hal_uart_status +{ + kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */ + kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */ + kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */ + kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */ + kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */ + kStatus_HAL_UartBaudrateNotSupport = + MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */ + kStatus_HAL_UartProtocolError = MAKE_STATUS( + kStatusGroup_HAL_UART, + 6), /*!< Error occurs for Noise, Framing, Parity, etc. + For transactional transfer, The up layer needs to abort the transfer and then starts again */ + kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */ +} hal_uart_status_t; + +/*! @brief UART parity mode. */ +typedef enum _hal_uart_parity_mode +{ + kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kHAL_UartParityEven = 0x2U, /*!< Parity even enabled */ + kHAL_UartParityOdd = 0x3U, /*!< Parity odd enabled */ +} hal_uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _hal_uart_stop_bit_count +{ + kHAL_UartOneStopBit = 0U, /*!< One stop bit */ + kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */ +} hal_uart_stop_bit_count_t; + +/*! @brief UART configuration structure. */ +typedef struct _hal_uart_config +{ + uint32_t srcClock_Hz; /*!< Source clock */ + uint32_t baudRate_Bps; /*!< Baud rate */ + hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t enableRxRTS; /*!< Enable RX RTS */ + uint8_t enableTxCTS; /*!< Enable TX CTS */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the + SOC corresponding RM. + Invalid instance value will cause initialization failure. */ +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + uint8_t txFifoWatermark; + uint8_t rxFifoWatermark; +#endif +} hal_uart_config_t; + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +/*! @brief UART DMA status */ +typedef enum _hal_uart_dma_status +{ + kStatus_HAL_UartDmaSuccess = 0U, + kStatus_HAL_UartDmaRxIdle = (1U << 1U), + kStatus_HAL_UartDmaRxBusy = (1U << 2U), + kStatus_HAL_UartDmaTxIdle = (1U << 3U), + kStatus_HAL_UartDmaTxBusy = (1U << 4U), + kStatus_HAL_UartDmaIdleline = (1U << 5U), + kStatus_HAL_UartDmaError = (1U << 6U), +} hal_uart_dma_status_t; + +typedef struct _dma_mux_configure_t +{ + union + { + struct + { + uint8_t dma_mux_instance; + uint32_t rx_request; + uint32_t tx_request; + } dma_dmamux_configure; + }; +} dma_mux_configure_t; +typedef struct _dma_channel_mux_configure_t +{ + union + { + struct + { + uint32_t dma_rx_channel_mux; + uint32_t dma_tx_channel_mux; + } dma_dmamux_configure; + }; +} dma_channel_mux_configure_t; + +typedef struct _hal_uart_dma_config_t +{ + uint8_t uart_instance; + uint8_t dma_instance; + uint8_t rx_channel; + uint8_t tx_channel; + void *dma_mux_configure; + void *dma_channel_mux_configure; +} hal_uart_dma_config_t; +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam); + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +typedef struct _dma_callback_msg +{ + hal_uart_dma_status_t status; + uint8_t *data; + uint32_t dataSize; +} hal_dma_callback_msg_t; + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_dma_transfer_callback_t)(hal_uart_dma_handle_t handle, + hal_dma_callback_msg_t *msg, + void *callbackParam); +#endif /* HAL_UART_DMA_ENABLE */ + +/*! @brief UART transfer structure. */ +typedef struct _hal_uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} hal_uart_transfer_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with the UART handle and the user configuration structure. + * + * This function configures the UART module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by + * the caller. Example below shows how to use this API to configure the UART. + * @code + * UART_HANDLE_DEFINE(g_UartHandle); + * hal_uart_config_t config; + * config.srcClock_Hz = 48000000; + * config.baudRate_Bps = 115200U; + * config.parityMode = kHAL_UartParityDisabled; + * config.stopBitCount = kHAL_UartOneStopBit; + * config.enableRx = 1; + * config.enableTx = 1; + * config.enableRxRTS = 0; + * config.enableTxCTS = 0; + * config.instance = 0; + * HAL_UartInit((hal_uart_handle_t)g_UartHandle, &config); + * @endcode + * + * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #UART_HANDLE_DEFINE(handle); + * or + * uint32_t handle[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param uart_config Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_HAL_UartSuccess UART initialization succeed + */ +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess UART de-initialization succeed + */ +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle); + +/*! @}*/ + +/*! + * @name Blocking bus Operations + * @{ + */ + +/*! + * @brief Reads RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the RX register. + * + * @note The function #HAL_UartReceiveBlocking and the function HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_HAL_UartError An error occurred while receiving data. + * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data. + * @retval kStatus_HAL_UartSuccess Successfully received all data. + */ +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note The function #HAL_UartSendBlocking and the function HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * And, the function HAL_UartTransferAbortSend cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully sent all data. + */ +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length); + +/*! @}*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +/*! + * @name Transactional + * @note The transactional API and the functional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When any status of the UART changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART driver. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure, see #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure. See #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#else + +/*! + * @name Functional API with non-blocking mode. + * @note The functional API and the transactional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART adapter. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartRxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_HAL_UartTxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param reCount Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param seCount Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#endif +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + +/*! + * @brief Initializes a UART dma instance with the UART dma handle and the user configuration structure. + * + * This function configures the UART dma module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated + * by the caller. Example below shows how to use this API to configure the UART. + * @code + * + * Init TimerManager, only used in UART without Idleline interrupt + * timer_config_t timerConfig; + * timerConfig.srcClock_Hz = 16000000; + * timerConfig.instance = 0; + * TM_Init(&timerConfig); + * + * Init the DMA module + * DMA_Init(DMA0); + * + * Define a uart dma handle + * UART_HANDLE_DEFINE(g_uartHandle); + * UART_DMA_HANDLE_DEFINE(g_UartDmaHandle); + * + * Configure uart settings + * hal_uart_config_t uartConfig; + * uartConfig.srcClock_Hz = 48000000; + * uartConfig.baudRate_Bps = 115200; + * uartConfig.parityMode = kHAL_UartParityDisabled; + * uartConfig.stopBitCount = kHAL_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * uartConfig.enableRxRTS = 0; + * uartConfig.enableTxCTS = 0; + * uartConfig.instance = 0; + * + * Init uart + * HAL_UartInit((hal_uart_handle_t *)g_uartHandle, &uartConfig); + * + * Configure uart dma settings + * hal_uart_dma_config_t dmaConfig; + * dmaConfig.uart_instance = 0; + * dmaConfig.dma_instance = 0; + * dmaConfig.rx_channel = 0; + * dmaConfig.tx_channel = 1; + * + * Init uart dma + * HAL_UartDMAInit((hal_uart_handle_t *)g_uartHandle, (hal_uart_dma_handle_t *)g_uartDmaHandle, &dmaConfig); + * @endcode + * + * @param handle UART handle pointer. + * @param dmaHandle Pointer to point to a memory space of size #HAL_UART_DMA_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #UART_DMA_HANDLE_DEFINE(handle); + * or + * uint32_t handle[((HAL_UART_DMA_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param dmaConfig Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartDmaError UART dma initialization failed. + * @retval kStatus_HAL_UartDmaSuccess UART dma initialization succeed. + */ +hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, + hal_uart_dma_handle_t dmaHandle, + hal_uart_dma_config_t *dmaConfig); + +/*! + * @brief Deinitializes a UART DMA instance. + * + * This function will abort uart dma receive/send transfer and deinitialize UART. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartDmaSuccess UART DMA de-initialization succeed + */ +hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle); + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART DMA module. + * When any status of the UART DMA changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartDmaSuccess Successfully install the callback. + */ +hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, + hal_uart_dma_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an dma method. + * + * This function receives data using an dma method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART DMA driver. + * When all data is received, the UART DMA adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_HAL_UartDmaRxIdle. + * + * When an idleline is detected, the UART DMA adapter notifies the upper layer through a callback function, + * and passes the status parameter @ref kStatus_HAL_UartDmaIdleline. For the UARTs without hardware idleline + * interrupt(like usart), it will use a software idleline detection method with the help of TimerManager. + * + * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API. + * + * @param handle UART handle pointer. + * @param data data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @param receiveAll Idleline interrupt will not end transfer process if set true. + * @retval kStatus_HAL_UartDmaSuccess Successfully start the data receive. + * @retval kStatus_HAL_UartDmaRxBusy Previous receive request is not finished. + */ +hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, + uint8_t *data, + size_t length, + bool receiveAll); + +/*! + * @brief Transmits a buffer of data using an dma method. + * + * This function sends data using an dma method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register by DMA, the UART DMA driver calls the callback + * function and passes the @ref kStatus_HAL_UartDmaTxIdle as status parameter. + * + * When the soc support cache, uplayer should do cache maintain operations for transfer buffer before call this API. + * + * @param handle UART handle pointer. + * @param data data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartDmaSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartDmaTxBusy Previous send request is not finished. + */ +hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param reCount Receive bytes count. + * @retval kStatus_HAL_UartDmaError An error occurred. + * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p reCount. + */ +hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the DMA method. + * + * @param handle UART handle pointer. + * @param seCount Send bytes count. + * @retval kStatus_HAL_UartDmaError An error occurred. + * @retval kStatus_HAL_UartDmaSuccess Get successfully through the parameter \p seCount. + */ +hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the DMA-driven data receiving. + * + * This function aborts the DMA-driven data receiving. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartDmaSuccess Get successfully abort the receiving. + */ +hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the DMA-driven data sending. + * + * This function aborts the DMA-driven data sending. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle); +#endif /* HAL_UART_DMA_ENABLE */ + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess Successful operation. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle); + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param handle UART handle pointer. + */ +void HAL_UartIsrFunction(hal_uart_handle_t handle); +#endif + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* __HAL_UART_ADAPTER_H__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c new file mode 100644 index 000000000..e82731fa7 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/components/uart/fsl_adapter_usart.c @@ -0,0 +1,1101 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_usart.h" +#include "fsl_flexcomm.h" + +#include "fsl_adapter_uart.h" + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +#include "fsl_component_timer_manager.h" +#include "fsl_usart_dma.h" +#endif /* HAL_UART_DMA_ENABLE */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_dma_receive_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; + volatile bool receiveAll; +} hal_uart_dma_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_dma_send_state +{ + uint8_t *volatile buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; + volatile uint32_t timeout; +} hal_uart_dma_send_state_t; + +typedef struct _hal_uart_dma_state +{ + struct _hal_uart_dma_state *next; + uint8_t instance; /* USART instance */ + hal_uart_dma_transfer_callback_t dma_callback; + void *dma_callback_param; + usart_dma_handle_t dmaHandle; + dma_handle_t txDmaHandle; + dma_handle_t rxDmaHandle; + hal_uart_dma_receive_state_t dma_rx; + hal_uart_dma_send_state_t dma_tx; +} hal_uart_dma_state_t; + +typedef struct _uart_dma_list +{ + TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle); + hal_uart_dma_state_t *dma_list; + volatile int8_t activeCount; +} hal_uart_dma_list_t; + +static hal_uart_dma_list_t s_dmaHandleList; +#endif /* HAL_UART_DMA_ENABLE */ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_receive_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_send_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_send_state_t; +#endif +/*! @brief uart state structure. */ +typedef struct _hal_uart_state +{ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_transfer_callback_t callback; + void *callbackParam; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + usart_handle_t hardwareHandle; +#endif + hal_uart_receive_state_t rx; + hal_uart_send_state_t tx; +#endif + uint8_t instance; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + hal_uart_dma_state_t *dmaHandle; +#endif /* HAL_UART_DMA_ENABLE */ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_config_t config; +#endif +} hal_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +/* Array of USART IRQ number. */ +static const IRQn_Type s_UsartIRQ[] = USART_IRQS; +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \ + (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))) +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus = kStatus_HAL_UartError; + switch (status) + { + case kStatus_Success: + uartStatus = kStatus_HAL_UartSuccess; + break; + case kStatus_USART_TxBusy: + uartStatus = kStatus_HAL_UartTxBusy; + break; + case kStatus_USART_RxBusy: + uartStatus = kStatus_HAL_UartRxBusy; + break; + case kStatus_USART_TxIdle: + uartStatus = kStatus_HAL_UartTxIdle; + break; + case kStatus_USART_RxIdle: + uartStatus = kStatus_HAL_UartRxIdle; + break; + case kStatus_USART_BaudrateNotSupport: + uartStatus = kStatus_HAL_UartBaudrateNotSupport; + break; + case kStatus_USART_NoiseError: + case kStatus_USART_FramingError: + case kStatus_USART_ParityError: + uartStatus = kStatus_HAL_UartProtocolError; + break; + default: + /* This comments for MISRA C-2012 Rule 16.4 */ + break; + } + return uartStatus; +} +#else +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + if (kStatus_Success == status) + { + return kStatus_HAL_UartSuccess; + } + else + { + return kStatus_HAL_UartError; + } +} +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + assert(callbackParam); + + uartHandle = (hal_uart_state_t *)callbackParam; + + if (kStatus_HAL_UartProtocolError == uartStatus) + { + if (0U != uartHandle->hardwareHandle.rxDataSize) + { + uartStatus = kStatus_HAL_UartError; + } + } + + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); + } +} + +#else +static void HAL_UartInterruptHandle(USART_Type *base, void *handle) +{ + hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle; + uint32_t status; + uint8_t instance; + + if (NULL == uartHandle) + { + return; + } + instance = uartHandle->instance; + + status = USART_GetStatusFlags(s_UsartAdapterBase[instance]); + + /* Receive data register full */ + if ((0U != (USART_FIFOSTAT_RXNOTEMPTY_MASK & status)) && + (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))) + { + if (NULL != uartHandle->rx.buffer) + { + uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]); + if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); + } + } + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != (USART_FIFOSTAT_TXNOTFULL_MASK & status)) && + (0U != (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))) + { + if (NULL != uartHandle->tx.buffer) + { + USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); + if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + if (NULL != uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); + } + } + } + } + +#if 1 + USART_ClearStatusFlags(s_UsartAdapterBase[instance], status); +#endif +} + +static void HAL_UartInterruptHandle_Wapper(void *base, void *handle) +{ + HAL_UartInterruptHandle((USART_Type *)base, handle); +} +#endif + +#endif + +static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config) +{ + usart_config_t usartConfig; + status_t status; + + assert(handle); + assert(config); + assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *))); + assert(s_UsartAdapterBase[config->instance]); + assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t)); + + USART_GetDefaultConfig(&usartConfig); + usartConfig.baudRate_Bps = config->baudRate_Bps; + + if ((0U != config->enableRxRTS) || (0U != config->enableTxCTS)) + { + usartConfig.enableHardwareFlowControl = true; + } + + if (kHAL_UartParityEven == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityEven; + } + else if (kHAL_UartParityOdd == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityOdd; + } + else + { + usartConfig.parityMode = kUSART_ParityDisabled; + } + + if (kHAL_UartTwoStopBit == config->stopBitCount) + { + usartConfig.stopBitCount = kUSART_TwoStopBit; + } + else + { + usartConfig.stopBitCount = kUSART_OneStopBit; + } + usartConfig.enableRx = (bool)config->enableRx; + usartConfig.enableTx = (bool)config->enableTx; + usartConfig.txWatermark = kUSART_TxFifo0; + usartConfig.rxWatermark = kUSART_RxFifo1; + + status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz); + + if (kStatus_Success != status) + { + return HAL_UartGetStatus(status); + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *uart_config) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t status; + + /* Init serial port */ + status = HAL_UartInitCommon(handle, uart_config); + if (kStatus_HAL_UartSuccess != status) + { + return status; + } + + uartHandle = (hal_uart_state_t *)handle; + uartHandle->instance = uart_config->instance; +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) + uartHandle->dmaHandle = NULL; +#endif /* HAL_UART_DMA_ENABLE */ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + (void)memcpy(&uartHandle->config, uart_config, sizeof(hal_uart_config_t)); +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + USART_TransferCreateHandle(s_UsartAdapterBase[uart_config->instance], &uartHandle->hardwareHandle, + (usart_transfer_callback_t)HAL_UartCallback, handle); +#else + /* Enable interrupt in NVIC. */ + FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[uart_config->instance], HAL_UartInterruptHandle_Wapper, handle); + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uart_config->instance], HAL_UART_ISR_PRIORITY); + (void)EnableIRQ(s_UsartIRQ[uart_config->instance]); +#endif + +#endif + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + USART_Deinit(s_UsartAdapterBase[uartHandle->instance]); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } +#endif + + status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } +#endif + + (void)USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle) +{ + assert(handle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) +{ +#if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) + hal_uart_state_t *uartHandle; + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + (void)HAL_UartInit(handle, &uartHandle->config); +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); +#endif +#endif + return kStatus_HAL_UartSuccess; +} + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer, NULL); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = + USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +#else + +/* None transactional API with non-blocking mode. */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } + + uartHandle->rx.bufferLength = length; + uartHandle->rx.bufferSofar = 0; + uartHandle->rx.buffer = data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } + uartHandle->tx.bufferLength = length; + uartHandle->tx.bufferSofar = 0; + uartHandle->tx.buffer = (volatile uint8_t *)data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(reCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + *reCount = uartHandle->rx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(seCount); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + *seCount = uartHandle->tx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->rx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (NULL != uartHandle->tx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +#endif + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U != HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#else + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(0U == HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#endif + +#endif + +#if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) +static void USART_DMACallbacks(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) +{ + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + hal_dma_callback_msg_t msg; + assert(handle); + + uartDmaHandle = (hal_uart_dma_state_t *)userData; + + if (NULL != uartDmaHandle->dma_callback) + { + if (kStatus_HAL_UartTxIdle == uartStatus) + { + msg.status = kStatus_HAL_UartDmaTxIdle; + msg.data = uartDmaHandle->dma_tx.buffer; + msg.dataSize = uartDmaHandle->dma_tx.bufferLength; + uartDmaHandle->dma_tx.buffer = NULL; + } + else if (kStatus_HAL_UartRxIdle == uartStatus) + { + msg.status = kStatus_HAL_UartDmaRxIdle; + msg.data = uartDmaHandle->dma_rx.buffer; + msg.dataSize = uartDmaHandle->dma_rx.bufferLength; + uartDmaHandle->dma_rx.buffer = NULL; + } + + uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); + } +} + +static void TimeoutTimer_Callbcak(void *param) +{ + hal_uart_dma_list_t *uartDmaHandleList; + hal_uart_dma_state_t *uartDmaHandle; + hal_dma_callback_msg_t msg; + uint32_t newReceived = 0U; + + uartDmaHandleList = &s_dmaHandleList; + uartDmaHandle = uartDmaHandleList->dma_list; + + while (NULL != uartDmaHandle) + { + if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) + { + /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ + USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, + &msg.dataSize); + newReceived = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar; + uartDmaHandle->dma_rx.bufferSofar = msg.dataSize; + + /* 1, If it is in idle state. */ + if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout++; + if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT) + { + /* HAL_UartDMAAbortReceive(uartDmaHandle); */ + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->dmaHandle); + msg.data = uartDmaHandle->dma_rx.buffer; + msg.status = kStatus_HAL_UartDmaIdleline; + uartDmaHandle->dma_rx.buffer = NULL; + uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); + } + } + /* 2, If got new data again. */ + if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) + { + uartDmaHandle->dma_rx.timeout = 0U; + } + } + + uartDmaHandle = uartDmaHandle->next; + } +} + +hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, + hal_uart_dma_handle_t dmaHandle, + hal_uart_dma_config_t *dmaConfig) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + assert(dmaHandle); + + /* DMA init process. */ + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle; + + uartHandle->dmaHandle = uartDmaHandle; + + uartDmaHandle->instance = dmaConfig->uart_instance; + + DMA_Type *dmaBases[] = DMA_BASE_PTRS; + DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); + DMA_EnableChannel(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); + + DMA_CreateHandle(&uartDmaHandle->txDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); + DMA_CreateHandle(&uartDmaHandle->rxDmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); + + /* Timeout timer init. */ + if (0U == s_dmaHandleList.activeCount) + { + s_dmaHandleList.dma_list = uartDmaHandle; + uartDmaHandle->next = NULL; + s_dmaHandleList.activeCount++; + + timer_status_t timerStatus; + timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle); + assert(kStatus_TimerSuccess == timerStatus); + + timerStatus = + TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, NULL); + assert(kStatus_TimerSuccess == timerStatus); + + (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1); + + (void)timerStatus; + } + else + { + uartDmaHandle->next = s_dmaHandleList.dma_list; + s_dmaHandleList.dma_list = uartDmaHandle; + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + hal_uart_dma_state_t *prev; + hal_uart_dma_state_t *curr; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + uartHandle->dmaHandle = NULL; + + assert(uartDmaHandle); + + /* Abort rx/tx */ + /* Here we should not abort before create transfer handle. */ + if (NULL != uartDmaHandle->dmaHandle.txDmaHandle) + { + USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + } + if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle) + { + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + } + + /* Disable rx/tx channels */ + /* Here we should not disable before create transfer handle. */ + if (NULL != uartDmaHandle->dmaHandle.txDmaHandle) + { + DMA_DisableChannel(uartDmaHandle->txDmaHandle.base, uartDmaHandle->txDmaHandle.channel); + } + if (NULL != uartDmaHandle->dmaHandle.rxDmaHandle) + { + DMA_DisableChannel(uartDmaHandle->rxDmaHandle.base, uartDmaHandle->rxDmaHandle.channel); + } + + /* Remove handle from list */ + prev = NULL; + curr = s_dmaHandleList.dma_list; + while (curr != NULL) + { + if (curr == uartDmaHandle) + { + /* 1, if it is the first one */ + if (prev == NULL) + { + s_dmaHandleList.dma_list = curr->next; + } + /* 2, if it is the last one */ + else if (curr->next == NULL) + { + prev->next = NULL; + } + /* 3, if it is in the middle */ + else + { + prev->next = curr->next; + } + break; + } + + prev = curr; + curr = curr->next; + } + + /* Reset all handle data. */ + (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t)); + + s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0; + if (0 == s_dmaHandleList.activeCount) + { + (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle); + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, + hal_uart_dma_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + uartDmaHandle->dma_callback = callback; + uartDmaHandle->dma_callback_param = callbackParam; + + USART_TransferCreateHandleDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, + USART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txDmaHandle, + &uartDmaHandle->rxDmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, + uint8_t *data, + size_t length, + bool receiveAll) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + usart_transfer_t xfer; + + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_rx.buffer) + { + uartDmaHandle->dma_rx.buffer = data; + uartDmaHandle->dma_rx.bufferLength = length; + uartDmaHandle->dma_rx.timeout = 0U; + uartDmaHandle->dma_rx.receiveAll = receiveAll; + } + else + { + /* Already in reading process. */ + return kStatus_HAL_UartDmaRxBusy; + } + + xfer.data = data; + xfer.dataSize = length; + + USART_TransferReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + usart_transfer_t xfer; + + assert(handle); + assert(data); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (NULL == uartDmaHandle->dma_tx.buffer) + { + uartDmaHandle->dma_tx.buffer = data; + uartDmaHandle->dma_tx.bufferLength = length; + uartDmaHandle->dma_tx.bufferSofar = 0U; + uartDmaHandle->dma_tx.timeout = 0U; + } + else + { + /* Already in writing process. */ + return kStatus_HAL_UartDmaTxBusy; + } + + xfer.data = data; + xfer.dataSize = length; + + USART_TransferSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle, &xfer); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + if (kStatus_Success != USART_TransferGetReceiveCountDMA(s_UsartAdapterBase[uartDmaHandle->instance], + &uartDmaHandle->dmaHandle, reCount)) + { + return kStatus_HAL_UartDmaError; + } + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + /* No get send count API */ + return kStatus_HAL_UartDmaError; +} + +hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + USART_TransferAbortReceiveDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} + +hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + hal_uart_dma_state_t *uartDmaHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + uartDmaHandle = uartHandle->dmaHandle; + + assert(uartDmaHandle); + + USART_TransferAbortSendDMA(s_UsartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->dmaHandle); + + return kStatus_HAL_UartDmaSuccess; +} +#endif /* HAL_UART_DMA_ENABLE */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.c new file mode 100644 index 000000000..d3af9fdfc --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.h new file mode 100644 index 000000000..6001b9bd8 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common.h @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*! @{ */ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @} */ + +/*! @name Debug console type definition. */ +/*! @{ */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/*! @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/*! @{ */ +#if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ +#define UINT32_MAX ((uint32_t)-1) +#endif +/*! @} */ + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.h new file mode 100644 index 000000000..3d35d76f8 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_common_arm.h @@ -0,0 +1,898 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#endif +/*! @} */ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/*! @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/*! @} */ + +/*! @name Alignment variable definition macros */ +/*! @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. + */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.c new file mode 100644 index 000000000..e53bebdd0 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.c @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.h new file mode 100644 index 000000000..0ec7286e6 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_ctimer.h @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */ +/*! @} */ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1UL << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1UL << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1UL << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1UL << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +/*! + * @brief Setup the timer prescale value. + * + * Specifies the maximum value for the Prescale Counter. + * + * @param base Ctimer peripheral base address + * @param prescale Prescale value + */ +static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale) +{ + base->PR = CTIMER_PR_PRVAL(prescale); +} + +/*! + * @brief Get capture channel value. + * + * Get the counter/timer value on the corresponding capture channel. + * + * @param base Ctimer peripheral base address + * @param capture Select capture channel + * + * @return The timer count capture value. + */ +static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture) +{ + return base->CR[capture]; +} + +/*! + * @brief Enable reset match channel. + * + * Set the specified match channel reset operation. + * + * @param base Ctimer peripheral base address + * @param match match channel used + * @param enable Enable match channel reset operation. + */ +static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } +} + +/*! + * @brief Enable stop match channel. + * + * Set the specified match channel stop operation. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable match channel stop operation. + */ +static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Enable reload channel falling edge. + * + * Enable the specified match channel reload match shadow value. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable . + */ +static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +/*! + * @brief Enable capture channel rising edge. + * + * Sets the specified capture channel for rising edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable rising edge capture. + */ +static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +/*! + * @brief Enable capture channel falling edge. + * + * Sets the specified capture channel for falling edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable falling edge capture. + */ +static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Set the specified match shadow channel. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param matchvalue Reload the value of the corresponding match register. + */ +static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue) +{ + base->MSR[match] = matchvalue; +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CTIMER_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.c new file mode 100644 index 000000000..890f8bf89 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.c @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if ((uintptr_t)(uint8_t*)base == s_flexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + uint32_t idx = FLEXCOMM_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = flexcommHandle; + s_flexcommIrqHandler[instance] = handler; + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void); +void FLEXCOMM0_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM0); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void); +void FLEXCOMM1_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM1); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void); +void FLEXCOMM2_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM2); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void); +void FLEXCOMM3_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM3); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void); +void FLEXCOMM4_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM4); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void); +void FLEXCOMM5_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM5); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void); +void FLEXCOMM6_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM6); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void); +void FLEXCOMM7_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM7); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void); +void FLEXCOMM8_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM8); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void); +void FLEXCOMM9_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM9); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void); +void FLEXCOMM10_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM10); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void); +void FLEXCOMM11_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM11); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void); +void FLEXCOMM12_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM12); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void); +void FLEXCOMM13_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM13); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void); +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void); +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void); +void FLEXCOMM16_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.h new file mode 100644 index 000000000..3b4669a3d --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCOMM_H_ +#define FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @} */ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_FLEXCOMM_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.c new file mode 100644 index 000000000..be100d5e9 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ +/*! + * @brief Enable GPIO port clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ + GPIO_EnablePortClock(base, port); + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + GPIO_EnablePortClock(base, port); + + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1UL << pin; +#else + base->DIR[port] &= ~(1UL << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1UL << pin); + } + else + { + base->SET[port] = (1UL << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1UL << pin; +#else + base->DIR[port] |= 1UL << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); + + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if ((uint32_t)kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if ((uint32_t)kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1UL << pin; + } + else if ((uint32_t)kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1UL << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.h new file mode 100644 index 000000000..4485603af --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_gpio.h @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) +/*! @} */ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*! @{ */ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*! @} */ + +/*! @name GPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*! @} */ +/*! @name GPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*! @} */ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*! @} */ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*! @} */ +/*! @name GPIO Mask Operations */ +/*! @{ */ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Set the configuration of pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.c new file mode 100644 index 000000000..15b4714d3 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.c @@ -0,0 +1,691 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_iap.h" +#include "fsl_iap_ffr.h" +#include "fsl_iap_kbp.h" +#include "fsl_iap_skboot_authenticate.h" +#include "fsl_device_registers.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iap1" +#endif + +#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ + defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) + +#else +#error "No valid CPU defined!" + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t get_cfpa_higher_version(flash_config_t *config); + +/*! + * @name flash and ffr Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*programCommand)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*verifyProgramCommand)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); +} function_command_option_t; + +/* + *!@brief Structure of version property. + * + *!@ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint32_t bugfix : 8; /*!< bugfix version [7:0] */ + uint32_t minor : 8; /*!< minor version [15:8] */ + uint32_t major : 8; /*!< major version [23:16] */ + uint32_t name : 8; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers. */ +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version1FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + uint32_t reserved[3]; /*! Reserved for future use */ + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version1_flash_driver_interface_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version0FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version0_flash_driver_interface_t; + +typedef union flashDriverInterface +{ + const version1_flash_driver_interface_t *version1FlashDriver; + const version0_flash_driver_interface_t *version0FlashDriver; +} flash_driver_interface_t; + +/*! @}*/ + +/*! + * @name Bootloader API and image authentication Structure + * @{ + */ + +/*! @brief Interface for Bootloader API functions. */ +typedef struct _kb_interface +{ + /*!< Initialize the API. */ + status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); + status_t (*kb_deinit_function)(kb_session_ref_t *session); + status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); +} kb_interface_t; + +//! @brief Interface for image authentication API +typedef struct _skboot_authenticate_interface +{ + skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + void (*skboot_hashcrypt_irq_handler)(void); +} skboot_authenticate_interface_t; +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t reserved0; /*!< Do NOT use. */ + flash_driver_interface_t flashDriver; + const kb_interface_t *kbApi; /*!< Bootloader API. */ + const uint32_t reserved1[4]; /*!< Do NOT use. */ + const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ +} bootloader_tree_t; + +/******************************************************************************* + * Prototype + ******************************************************************************/ +static uint32_t get_rom_api_version(void); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! Get pointer to flash driver API table in ROM. */ +#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver +#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver +#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) +#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) +#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t get_rom_api_version(void) +{ + if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) + { + return 1u; + } + else + { + return 0u; + } +} + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + status_t status; + /* Initialize the clock to 96MHz */ + config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; + if (get_rom_api_version() == 1u) + { + status = VERSION1_FLASH_API_TREE->flash_init(config); + } + else + { + status = VERSION0_FLASH_API_TREE->flash_init(config); + } + + if (config->PFlashTotalSize == 0xA0000U) + { + config->PFlashTotalSize -= 17U * config->PFlashPageSize; + } + + return status; +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t core_frequency = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + /* Flash ERASE operations must be performed with a system clock below or equal to 100 MHz.*/ + if (core_frequency > 100000000U) + { + return (status_t)kStatus_FLASH_EraseFrequencyError; + } + + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); + } + else + { + return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes) +{ + uint32_t core_frequency = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + /* Flash PROGRAM operations must be performed with a system clock below or equal to 100 MHz.*/ + if (core_frequency > 100000000U) + { + return (status_t)kStatus_FLASH_ProgramFrequencyError; + } + + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ + return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + if (get_rom_api_version() == 0u) + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } + else + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) + { + runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; + } + else + { + runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; + } + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } +} + +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + if (get_rom_api_version() == 0u) + { + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ + return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); + } +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); +} +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +static status_t get_cfpa_higher_version(flash_config_t *config) +{ + uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; + uint32_t versionPing = 0U; + uint32_t versionPong = 0U; + + /* Get the CFPA ping page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 1U; + status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPing = pageData[1]; + + /* Get the CFPA pong page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 2U; + status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPong = pageData[1]; + + /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ + if (versionPing > versionPong) + { + config->ffrConfig.cfpaPageVersion = versionPing; + config->ffrConfig.cfpaPageOffset = 1U; + } + else + { + config->ffrConfig.cfpaPageVersion = versionPong; + config->ffrConfig.cfpaPageOffset = 2U; + } + return (int32_t)kStatus_FLASH_Success; +} + +/*! + * Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + status_t status; + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + status = VERSION0_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + status = VERSION1_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } +} + +/*! + * Enable firewall for all flash banks. + */ +status_t FFR_Lock_All(flash_config_t *config) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_lock_all(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_lock_all(config); + } +} + +/*! + * APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } +} + +/*! + * See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } +} + +/*! + * APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } +} + +/*! + * This routine writes the 3 pages allocated for Key store data, + * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } +} + +/*! See fsl_iap_ffr.h for documentation of this function. */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } +} + +/*! + * APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } +} + +/*! + * APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } +} + +/******************************************************************************** + * Bootloader API + *******************************************************************************/ +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); +} + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the @a context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); +} + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param context Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success The operation has completed successfully. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); +} + +/******************************************************************************** + * Image authentication API + *******************************************************************************/ + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, + isSignVerified); +} + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); +} + +/******************************************************************************** + * runBootloader API + *******************************************************************************/ +void BOOTLOADER_UserEntry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} +/******************************************************************************** + * EOF + *******************************************************************************/ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.h new file mode 100644 index 000000000..f6c49c48a --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap.h @@ -0,0 +1,569 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_H_ +#define FSL_IAP_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) /*!< Version 2.1.5. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ +}; + +/*! @} */ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Flash IP Type. */ +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1) +#endif +#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC) +#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0) +#endif + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_EraseFrequencyError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x2A), /*!< Core frequency is over 100MHZ. */ + kStatus_FLASH_ProgramFrequencyError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x2B), /*!< Core frequency is over 100MHZ. */ + +}; +/*! @} */ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*! @} */ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1, /*! ECC is off */ +}; + +/* set flash Controller timing before flash init */ +enum _flash_freq_tag +{ + kSysToFlashFreq_lowInMHz = 12u, + kSysToFlashFreq_defaultInMHz = 96u, +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; +} flash_config_t; + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | +| Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ + +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! @} */ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be 512bytes-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the appropriate number of flash sectors based on the desired + * start address and length were erased successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*! @} */ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * 512bytes-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully + * into flash based on desired start address and length. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, const uint8_t *src, uint32_t lengthInBytes); + +/*! @} */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address need to be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be 512bytes-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. need be 512bytes-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully; + * the desired data have been successfully programed into specified FLASH region. + * + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*! @} */ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void BOOTLOADER_UserEntry(void *arg); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* __FLASH_FLASH_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_ffr.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_ffr.h new file mode 100644 index 000000000..74b1e361f --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_ffr.h @@ -0,0 +1,388 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_FFR_H_ +#define FSL_IAP_FFR_H_ + +#include "fsl_iap.h" + +/*! + * @addtogroup flash_ifr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash IFR version + * @{ + */ +/*! @brief Flash IFR driver version for SDK*/ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*! @} */ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) + +/*! @brief flash ffr page offset. */ +enum _flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */ + kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/ + + kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/ + kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/ + + kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/ + kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/ + kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ +}; + +/*! @brief flash ffr page number. */ +enum _flash_ffr_page_num +{ + kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ + kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/ + kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/ + + kFfrPageNum_CMPA_Cfg = 1, + kFfrPageNum_CMPA_Key = 3, + kFfrPageNum_NMPA_Romcp = 2, + + kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA, + kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA), +}; + +enum _flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1192u, +}; + +typedef enum _cfpa_cfg_cmpa_prog_process +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct _cfpa_cfg_iv_code +{ + uint32_t keycodeHeader; + uint8_t reserved[FLASH_FFR_IV_CODE_SIZE]; +} cfpa_cfg_iv_code_t; + +typedef struct _cfpa_cfg_info +{ + uint32_t header; /*!< [0x000-0x003] */ + uint32_t version; /*!< [0x004-0x007 */ + uint32_t secureFwVersion; /*!< [0x008-0x00b */ + uint32_t nsFwVersion; /*!< [0x00c-0x00f] */ + uint32_t imageKeyRevoke; /*!< [0x010-0x013] */ + uint8_t reserved0[4]; /*!< [0x014-0x017] */ + uint32_t rotkhRevoke; /*!< [0x018-0x01b] */ + uint32_t vendorUsage; /*!< [0x01c-0x01f] */ + uint32_t dcfgNsPin; /*!< [0x020-0x013] */ + uint32_t dcfgNsDflt; /*!< [0x024-0x017] */ + uint32_t enableFaMode; /*!< [0x028-0x02b] */ + uint8_t reserved1[4]; /*!< [0x02c-0x02f] */ + cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */ + uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +typedef struct _cmpa_cfg_info +{ + uint32_t bootCfg; /*!< [0x000-0x003] */ + uint32_t spiFlashCfg; /*!< [0x004-0x007] */ + struct + { + uint16_t vid; + uint16_t pid; + } usbId; /*!< [0x008-0x00b] */ + uint32_t sdioCfg; /*!< [0x00c-0x00f] */ + uint32_t dcfgPin; /*!< [0x010-0x013] */ + uint32_t dcfgDflt; /*!< [0x014-0x017] */ + uint32_t dapVendorUsage; /*!< [0x018-0x01b] */ + uint32_t secureBootCfg; /*!< [0x01c-0x01f] */ + uint32_t princeBaseAddr; /*!< [0x020-0x023] */ + uint32_t princeSr[3]; /*!< [0x024-0x02f] */ + uint8_t reserved0[32]; /*!< [0x030-0x04f] */ + uint32_t rotkh[8]; /*!< [0x050-0x06f] */ + uint8_t reserved1[368]; /*!< [0x070-0x1df] */ + uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ +} cmpa_cfg_info_t; + +typedef struct _cmpa_key_store_header +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +typedef struct _nmpa_cfg_info +{ + uint16_t fro32kCfg; /*!< [0x000-0x001] */ + uint8_t reserved0[6]; /*!< [0x002-0x007] */ + uint8_t sysCfg; /*!< [0x008-0x008] */ + uint8_t reserved1[7]; /*!< [0x009-0x00f] */ + struct + { + uint32_t data; + uint32_t reserved[3]; + } GpoInitData[3]; /*!< [0x010-0x03f] */ + uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */ + uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */ + uint32_t deviceType; /*!< [0x060-0x063] */ + uint32_t finalTestProgVersion; /*!< [0x064-0x067] */ + uint32_t finalTestDate; /*!< [0x068-0x06b] */ + uint32_t finalTestTime; /*!< [0x06c-0x06f] */ + uint32_t uuid[4]; /*!< [0x070-0x07f] */ + uint8_t reserved2[32]; /*!< [0x080-0x09f] */ + uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */ + uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */ + uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */ + uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */ + uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */ + uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */ + uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */ + uint32_t bod; /*!< [0x0f0-0x0f3] */ + uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */ + uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */ + uint8_t sha256[32]; /*!< [0x1c0-0x1df] */ + uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */ + uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */ +} nmpa_cfg_info_t; + +typedef struct _ffr_key_store +{ + uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum _ffr_key_type +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum _ffr_bank_type +{ + kFFR_BankTypeBank0_NMPA = 0x00U, + kFFR_BankTypeBank1_CMPA = 0x01U, + kFFR_BankTypeBank2_CFPA = 0x02U +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Lock_All(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ +status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + */ +status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + * 3. keyIndex specifies which key code is read. + */ +status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + +/*! @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_kbp.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_kbp.h new file mode 100644 index 000000000..2f1283fd0 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_kbp.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_IAP_KBP_H_ +#define FSL_IAP_KBP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kb_driver + * @{ + */ +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief ROM API status group number */ +#define kStatusGroup_RomApi (108U) + +/*! @brief ROM API status codes. */ +enum +{ + kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ + kStatus_RomApiNeedMoreData = + MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ + kStatus_RomApiBufferSizeNotEnough = + MAKE_STATUS(kStatusGroup_RomApi, + 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ + kStatus_RomApiInvalidBuffer = + MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ +}; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum _kb_operation +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ + kRomLoadImage = 2, /*!< Load SB file.*/ + kRomOperationCount = 3, +} kb_operation_t; + +/*! + * @brief Security constraint flags, Security profile flags. + */ +enum _kb_security_profile +{ + kKbootMinRSA4096 = (1 << 16), +}; + +/*! + * @brief Memory region definition. + */ +typedef struct _kb_region +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief User-provided options passed into kb_init(). + * + * The buffer field is a pointer to memory provided by the caller for use by + * Kboot during execution of the operation. Minimum size is the size of each + * certificate in the chain plus 432 bytes additional per certificate. + * + * The profile field is a mask that specifies which features are required in + * the SB file or image being processed. This includes the minimum AES and RSA + * key sizes. See the _kb_security_profile enum for profile mask constants. + * The image being loaded or authenticated must match the profile or an error will + * be returned. + * + * minBuildNumber is an optional field that can be used to prevent version + * rollback. The API will check the build number of the image, and if it is less + * than minBuildNumber will fail with an error. + * + * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes + * value at the beginning of a signed image. It should be set to the length of + * the SB file. If verifying an image in flash, it can be set to the internal + * flash size or a large number like 0x10000000. + * + * userRHK can optionally be used by the user to override the RHK in IFR. If + * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of + * the root certificate's RSA public key. + * + * The regions field points to an array of memory regions that the SB file being + * loaded is allowed to access. If regions is NULL, then all memory is + * accessible by the SB file. This feature is required to prevent a malicious + * image from erasing good code or RAM contents while it is being loaded, only + * for us to find that the image is inauthentic when we hit the end of the + * section. + * + * overrideSBBootSectionID lets the caller override the default section of the + * SB file that is processed during a kKbootLoadSB operation. By default, + * the section specified in the firstBootableSectionID field of the SB header + * is loaded. If overrideSBBootSectionID is non-zero, then the section with + * the given ID will be loaded instead. + * + * The userSBKEK field lets a user provide their own AES-256 key for unwrapping + * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point + * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. + * After kb_init() returns, the caller should zero out the data pointed to by + * userSBKEK, as the API will have installed the key in the CAU3. + */ + +typedef struct _kb_load_sb +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct _kb_authenticate +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct _kb_options +{ + uint32_t version; /*!< Should be set to kKbootApiVersion.*/ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! + * @brief Interface to memory operations for one region of memory. + */ +typedef struct _memory_region_interface +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +/*! + * @brief Structure of a memory map entry. + */ +typedef struct _memory_map_entry +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +typedef struct _kb_opaque_session_ref +{ + kb_options_t context; + bool cau3Initialized; + memory_map_entry_t *memoryMap; +} kb_session_ref_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + * + * @retval #kStatus_Success API was executed successfully. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the + * operation. + * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. + * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. + * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the + * keystore + * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the context parameter can be reused for another operation + * by calling rom_init() again. + * + * @retval #kStatus_Success API was executed successfully + */ +status_t kb_deinit(kb_session_ref_t *session); + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param session Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. + * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for + * use by Kboot during execution of the operation. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_IAP_KBP_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_skboot_authenticate.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_skboot_authenticate.h new file mode 100644 index 000000000..8098a2653 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iap_skboot_authenticate.h @@ -0,0 +1,77 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_IAP_SKBOOT_AUTHENTICATE_H_ +#define FSL_IAP_SKBOOT_AUTHENTICATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup skboot_authenticate + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief SKBOOT return status*/ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = + 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusFail = + 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ +} skboot_status_t; + +/*! @brief Secure bool flag*/ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ + kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ + kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ + kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ + kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ +} secure_bool_t; + +/******************************************************************************* + * Externs + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iocon.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iocon.h new file mode 100644 index 000000000..db8f30bf6 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_iocon.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_IOCON_H_ +#define FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*! @{ */ +/*! @brief IOCON driver version. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ + uint8_t ionumber; /* IO number */ + uint16_t modefunc; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_IOCON_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.c b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.c new file mode 100644 index 000000000..c43bc8d21 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.c @@ -0,0 +1,1298 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + uint32_t i; + + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); + return i; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + USART_SetRxTimeoutConfig(base, (usart_rx_timeout_config *)&(config->rxTimeout)); +#endif + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + if (config->enableMode32k) + { + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + base->FIFORXTIMEOUTCFG = 0U; +#endif +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->enableHardwareFlowControl = false; +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + config->rxTimeout.enable = false; + config->rxTimeout.resetCounterOnEmpty = true; + config->rxTimeout.resetCounterOnReceive = true; + config->rxTimeout.counter = 0U; + config->rxTimeout.prescaler = 0U; +#endif +} +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! + * brief Calculate the USART instance RX timeout prescaler and counter. + * + * This function for calculate the USART RXFIFO timeout config. This function is used to calculate + * suitable prescaler and counter for target_us. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t config; + * config.rxWatermark = kUSART_RxFifo2; + * config.rxTimeout.enable = true; + * config.rxTimeout.resetCounterOnEmpty = true; + * config.rxTimeout.resetCounterOnReceive = true; + * USART_CalcTimeoutConfig(200, &config.rxTimeout.prescaler, &config.rxTimeout.counter, + * CLOCK_GetFreq(kCLOCK_BusClk)); + * endcode + * param target_us Time for rx timeout unit us. + * param rxTimeoutPrescaler The prescaler to be setted after function. + * param rxTimeoutcounter The counter to be setted after function. + * param srcClock_Hz The clockSrc for rx timeout. + */ +void USART_CalcTimeoutConfig(uint32_t target_us, + uint8_t *rxTimeoutPrescaler, + uint32_t *rxTimeoutcounter, + uint32_t srcClock_Hz) +{ + uint16_t counter = 0U; + uint32_t perscalar = 0U, calculate_us = 0U, us_diff = 0U, min_diff = 0xffffffffUL; + /* find the suitable value */ + for (perscalar = 0U; perscalar < 256U; perscalar++) + { + counter = target_us * (srcClock_Hz / 1000000UL) / (16U * (perscalar + 1U)); + calculate_us = 16U * (perscalar + 1U) * counter / (srcClock_Hz / 1000000UL); + us_diff = (calculate_us > target_us) ? (calculate_us - target_us) : (target_us - calculate_us); + if (us_diff == 0U) + { + *rxTimeoutPrescaler = perscalar; + *rxTimeoutcounter = counter; + break; + } + else + { + if (min_diff > us_diff) + { + min_diff = us_diff; + *rxTimeoutPrescaler = perscalar; + *rxTimeoutcounter = counter; + } + } + } +} +/*! + * brief Sets the USART instance RX timeout config. + * + * This function configures the USART RXFIFO timeout config. This function is used to config + * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init. + * + * param base USART peripheral base address. + * param config pointer to receive timeout configuration structure. + */ +void USART_SetRxTimeoutConfig(USART_Type *base, usart_rx_timeout_config *config) +{ + base->FIFORXTIMEOUTCFG = 0U; + base->FIFORXTIMEOUTCFG = USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COW(~config->resetCounterOnReceive) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_COE(~config->resetCounterOnEmpty) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_EN(config->enable) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_VALUE(config->counter) | + USART_FIFORXTIMEOUTCFG_RXTIMEOUT_PRESCALER(config->prescaler); +} +#endif + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate, allowed_error; + + /* check arguments */ + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) + { + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1U; + } + } + else + { + /* Actual baud rate must be within 3% of desired baud rate based on the calculated OSR and BRG value */ + allowed_error = ((baudrate_Bps / 100U) * 3U); + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; (osrval >= 4U); osrval--) + { + /* Break if the best baudrate's diff is in the allowed error range and the osrval is below 8, + only use lower osrval if the baudrate cannot be obtained with an osrval of 8 or above. */ + if ((osrval <= 8U) && (best_diff <= allowed_error)) + { + break; + } + + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated OSR and BRG value */ + baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff > allowed_error) + { + return kStatus_USART_BaudrateNotSupport; + } + + /* value over range */ + if (best_brgval > 0xFFFFU) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base USART peripheral base address. + * param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set USART 9-bit mode, disable parity. */ + temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); + temp |= (uint32_t)USART_CFG_DATALEN(0x2U); + base->CFG = temp; + } + else + { + /* Set USART to 8-bit mode. */ + base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); + base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); + } +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base USART peripheral base address. + * param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address) +{ + assert(base != NULL); + base->FIFOWR = ((uint32_t)address | 0x100UL); +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + /* Check whether txFIFO is enabled */ + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return kStatus_InvalidArgument; + } + for (; length > 0U; length--) + { + /* Loop until txFIFO get some space for new data */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) + { + return kStatus_Fail; + } + for (; length > 0U; length--) + { + /* loop until rxFIFO have some data to read */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif + { + } +#if UART_RETRY_TIMES + if (waitTimes == 0U) + { + status = kStatus_USART_Timeout; + break; + } +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; + } + + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } + } + return status; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + (void)memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the + * handle value. */ + uint32_t interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kUSART_TxBusy; + /* Enable transmiter interrupt and the previously disabled interrupt. */ + USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t interruptMask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* Enable address detect when address match is enabled. */ + if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) + { + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if ((uint8_t)kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable IRQ, protect ring buffer. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kUSART_RxBusy; + } + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up + * the handle value. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); + } + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; + + /* If RX overrun. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) + { + /* Clear tx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxError, handle->userData); + } + } + /* If noise error. */ + if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_RXNOISEINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); + } + } + /* If framing error. */ + if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_FRAMERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); + } + } + /* If parity error. */ + if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_PARITYERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) + { + /* Receive data */ + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) + { + /* Clear address detect when RXFIFO has data. */ + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize != 0U) + { + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) + { + if (NULL == handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer != NULL) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; + /* Increase handle->rxRingBufferHead. */ + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0U; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; + } + } + } + + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + tmpsize = handle->rxDataSize; + + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) + { + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); + } + } +} diff --git a/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.h b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.h new file mode 100644 index 000000000..3d7f8c86c --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/drivers/fsl_usart.h @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Retry times for waiting flag. + * + * Defining to zero means to keep waiting for the flag until it is assert/deassert in blocking transfer, + * otherwise the program will wait until the UART_RETRY_TIMES counts down to 0, + * if the flag still remains unchanged then program will return kStatus_USART_Timeout. + * It is not advised to use this macro in formal application to prevent any hardware error + * because the actual wait period is affected by the compiler and optimization. + */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U +#endif + +/*! @brief Error codes for the USART driver. */ +enum +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +#if UART_RETRY_TIMES + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +#endif +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), + kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsChangeInterruptEnable = + (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ + kUSART_RxBreakChangeInterruptEnable = + (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ + kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ + kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ + kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ + kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ + kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutInterruptEnable = (USART_FIFOINTENSET_RXTIMEOUT_MASK), /*!< Receive timeout detected. */ +#endif + kUSART_AllInterruptEnables = + kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | + kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | + kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutInterruptEnable | +#endif + kUSART_AutoBaudErrorInterruptEnable, +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ + kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ + kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ + kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ + kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ + kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in + the state of receiver break detection. */ + kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ + kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ + kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ + kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ + kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate + counter timeout before the end of start bit. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutFlag = (USART_FIFOSTAT_RXTIMEOUT_MASK), /*!< RXTIMEOUT bit, sets if RX FIFO Timeout. */ +#endif + kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | + kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + kUSART_RxTimeoutFlag | +#endif + kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, +}; + +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! @brief USART receive timeout configuration structure. */ +typedef struct _usart_rx_timeout_config +{ + bool enable; /*!< Enable RX timeout */ + bool resetCounterOnEmpty; /*!< Enable RX timeout counter reset when RX FIFO becames empty. */ + bool resetCounterOnReceive; /*!< Enable RX timeout counter reset when RX FIFO receives data from the transmitter + side. */ + uint32_t counter; /*!< RX timeout counter*/ + uint8_t prescaler; /*!< RX timeout prescaler*/ +} usart_rx_timeout_config; +#endif + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG + usart_rx_timeout_config rxTimeout; /*!< rx timeout configuration */ +#endif +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); +#if defined(FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG) && FSL_FEATURE_USART_HAS_FIFORXTIMEOUTCFG +/*! + * @brief Calculate the USART instance RX timeout prescaler and counter. + * + * This function for calculate the USART RXFIFO timeout config. This function is used to calculate + * suitable prescaler and counter for target_us. + * @code + * usart_config_t config; + * config.rxWatermark = kUSART_RxFifo2; + * config.rxTimeout.enable = true; + * config.rxTimeout.resetCounterOnEmpty = true; + * config.rxTimeout.resetCounterOnReceive = true; + * USART_CalcTimeoutConfig(200U, &config.rxTimeout.prescaler, &config.rxTimeout.counter, + * CLOCK_GetFreq(kCLOCK_BusClk)); + * @endcode + * @param target_us Time for rx timeout unit us. + * @param rxTimeoutPrescaler The prescaler to be setted after function. + * @param rxTimeoutcounter The counter to be setted after function. + * @param srcClock_Hz The clockSrc for rx timeout. + */ +void USART_CalcTimeoutConfig(uint32_t target_us, + uint8_t *rxTimeoutPrescaler, + uint32_t *rxTimeoutcounter, + uint32_t srcClock_Hz); +/*! + * @brief Sets the USART instance RX timeout config. + * + * This function configures the USART RXFIFO timeout config. This function is used to config + * the USART RXFIFO timeout config after the USART module is initialized by the USART_Init. + * + * @param base USART peripheral base address. + * @param config pointer to receive timeout configuration structure. + */ +void USART_SetRxTimeoutConfig(USART_Type *base, usart_rx_timeout_config *config); +#endif +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base USART peripheral base address. + * @param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable); + +/*! + * @brief Set the USART slave address. + * + * This function configures the address for USART module that works as slave in 9-bit data mode. When the address + * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is + * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This + * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. + * To un-address a slave, just send an address frame with unmatched address. + * + * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) +{ + /* Configure match address. */ + base->ADDR = (uint32_t)address; +} + +/*! + * @brief Enable the USART match address feature. + * + * @param base USART peripheral base address. + * @param match true to enable match address, false to disable. + */ +static inline void USART_EnableMatchAddress(USART_Type *base, bool match) +{ + /* Configure match address enable bit. */ + if (match) + { + base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + else + { + base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return (base->FIFOSTAT & 0xFF0000FFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllClearFlags; + /* Clear the clearable status in STAT register. */ + base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENSET = mask & 0xF00000FUL; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENCLR = mask & 0xFUL; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} + +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return (uint8_t)base->FIFORD; +} + +/*! + * @brief Gets the rx FIFO data count. + * + * @param base USART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t USART_GetRxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base USART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t USART_GetTxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c new file mode 100644 index 000000000..1efdbbbbd --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.c @@ -0,0 +1,1417 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef SDK_OS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic; +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic; +#endif +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile bool s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +/* clang-format off */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) +#endif +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \ + do \ + { \ + if(NULL != (mutex)) \ + { \ + vSemaphoreDelete(mutex); \ + (mutex) = NULL; \ + } \ + } while(false) + +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} + +/* Binary semaphore */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#endif +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \ + do \ + { \ + if(NULL != (binary)) \ + { \ + vSemaphoreDelete((binary)); \ + (binary) = NULL; \ + } \ + } while(false) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) (void)(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (void)(binary) +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) (void)(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!(binary)) \ + { \ + } \ + (binary) = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \ + do \ + { \ + (binary) = true; \ + } while(false) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (void)(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (void)(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +/* clang-format on */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer); + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer2); + SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer); +#else + SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer); + SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer); +#endif +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0)) +AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState); +#else +static debug_console_state_struct_t s_debugConsoleState; +#endif +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static status_t DbgConsole_SerialManagerPerformTransfer(debug_console_state_struct_t *ioState) +{ + serial_manager_status_t ret = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t startIndex; + uint32_t regPrimask; + + regPrimask = DisableGlobalIRQ(); + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + if (0U != ioState->writeRingBuffer.ringHead) + { + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer2[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + sendDataLength = ioState->writeRingBuffer.ringHead - 0U; + startIndex = 0U; + } + } + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + } + EnableGlobalIRQ(regPrimask); + return (status_t)ret; +} + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + (void)DbgConsole_SerialManagerPerformTransfer(ioState); + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +static void DbgConsole_SerialManagerTx2Callback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + /* Empty block*/ + } + else if (kStatus_SerialManager_Canceled == status) + { + /* Empty block*/ + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return (status_t)kStatus_Fail; +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + serial_manager_status_t status = kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = + SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + if (kStatus_SerialManager_Success != status) + { + status = (serial_manager_status_t)kStatus_Fail; + } + else + { + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + status = (serial_manager_status_t)kStatus_Success; + } + return (status_t)status; +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + +#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ + + return (status_t)kStatus_Fail; + +#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0U != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + if (sendDataLength < size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + status = DbgConsole_SerialManagerPerformTransfer(&s_debugConsoleState); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + serial_manager_status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + serial_manager_status_t status; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + + if (0U == size) + { + return 0; + } + + if (NULL == g_serialHandle) + { + return 0; + } + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if ((sendDataLength > 0U) && ((sendDataLength >= totalLength) || + (totalLength >= (s_debugConsoleState.writeRingBuffer.ringBufferSize - 1U)))) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], (size_t)sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = (serial_manager_status_t)DbgConsole_Flush(); + if (kStatus_SerialManager_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return ((int)size - (int)totalLength); +#else /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + status = + SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return ((kStatus_SerialManager_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (size_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) +#include "board.h" +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG_UART_INSTANCE, + .clockRate = BOARD_DEBUG_UART_CLK_FREQ, + .baudRate = BOARD_DEBUG_UART_BAUDRATE, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1U, + .enableTx = 1U, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif +}; +#endif +#endif +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig = {0}; + serial_manager_status_t status = kStatus_SerialManager_Success; + +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1, + .enableTx = 1, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif + }; +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serial_port_virtual_config_t serialPortVirtualConfig = { + .controllerIndex = (serial_port_virtual_controller_index_t)instance, + }; +#endif + + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; + serialConfig.blockType = kSerialManager_NonBlocking; +#else + serialConfig.blockType = kSerialManager_Blocking; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) + serialConfig.portConfig = (void *)&uartConfig; +#else + serialConfig.portConfig = &uartConfig; +#endif +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Virtual == device) + { +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serialConfig.portConfig = &serialPortVirtualConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else + { + status = kStatus_SerialManager_Error; + } + + if (kStatus_SerialManager_Error != status) + { + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#if configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#endif + + { + status = + SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); + status = SerialManager_OpenWriteHandle( + s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); + assert(kStatus_SerialManager_Success == status); + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]), + DbgConsole_SerialManagerTx2Callback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = + SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle, + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_EnterLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_ExitLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); +#endif + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + if (NULL != s_debugConsoleState.serialHandle) + { + if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle)) + { + s_debugConsoleState.serialHandle = NULL; + g_serialHandle = NULL; + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return (status_t)kStatus_Success; +} +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE > DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN))) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_Vprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) +{ + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL != g_serialHandle) + { + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + /* print log */ + result = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + } + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_s, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, fmt_s); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, fmt_s, ap); + + va_end(ap); + + return formatResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_BlockingVprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg) +{ + status_t status; + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); +#endif + /* print log */ + status = + (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + (uint8_t *)printBuf, (size_t)logLength); + result = (((status_t)kStatus_Success == status) ? (int)logLength : -1); + + return result; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + if (NULL == g_serialHandle) + { + return kStatus_Fail; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + int ret = -1; + uint8_t ch = 0U; + + /* Get char */ + if (DbgConsole_ReadCharacter(&ch) > 0) + { + ret = (int)ch; + } + + return ret; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = 0U; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + uint8_t buff[512]; + (void)memcpy(buff, buffer, size); + (void)DbgConsole_SendDataReliable((uint8_t *)buff, size); + + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (0 != handle) + { + actualSize = -1; + } + else + { + /* Receive data.*/ + for (; size > 0U; size--) + { + (void)DbgConsole_ReadCharacter(&ch); + if (0U == ch) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + } + return (size_t)actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h new file mode 100644 index 000000000..374148ff8 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#else +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_EnterLowpower(void); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_ExitLowpower(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_EnterLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_ExitLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param fmt_s Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_s, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h new file mode 100644 index 000000000..fd235b1e5 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/debug_console/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +#include "fsl_common.h" + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef SDK_OS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* SDK_OS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.c b/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.c new file mode 100644 index 000000000..cf73a5f09 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2022-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_assert.h" +#include "fsl_debug_console.h" + +/* User can implement its own asser handler (dump logs, registers, etc) by reimplementing the function fsl_assert_hook() */ +__attribute__ ((weak)) int fsl_assert_hook(const char *failedExpr, const char *file, int line) +{ + (void)failedExpr; + (void)file; + (void)line; + + return 0; +} + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + const char *file = NULL; + int line = -1; + + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { + __BKPT(0); + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + + (void)fsl_assert_hook(failedExpr, file, line); + + for (;;) + { + __BKPT(0); + } +} +#endif /* defined(__REDLIB__) */ +#else /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ + +#if (defined(__DSC__) && defined(__CW__)) + +void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line) +{ + PRINTF("\r\nASSERT ERROR\r\n"); + PRINTF(" File : %s\r\n", file); + PRINTF(" Function : %s\r\n", func); /*compiler not support func name yet*/ + PRINTF(" Line : %u\r\n", (uint32_t)line); + PRINTF(" failedExpr: %s\r\n", failedExpr); + asm(DEBUGHLT); +} + +#endif /* (defined(__DSC__) && defined (__CW__)) */ + +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.h b/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.h new file mode 100644 index 000000000..58b50dc9f --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/fsl_assert.h @@ -0,0 +1,51 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ASSERT_H_ +#define _FSL_ASSERT_H_ + +/*! + * @addtogroup assert + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + + +/*! + * @brief Assert hook that can be redifined + * + * @param failedExpr Expression that caused the assert + * @param file File where the exception occured. + * @param line Line on the file where the exception occured. + */ +int fsl_assert_hook(const char *failedExpr, const char *file, int line); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ + diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c new file mode 100644 index 000000000..1c0dccf90 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.c @@ -0,0 +1,1638 @@ +/* + * Copyright 2017, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include /* MISRA C-2012 Rule 22.9 */ +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#ifndef MAX_FIELD_WIDTH +#define MAX_FIELD_WIDTH 99U +#endif + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); + +#endif /* PRINTF_FLOAT_ENABLE */ + +/*************Code for process formatted data*******************************/ +#if PRINTF_ADVANCED_ENABLE +static uint8_t PrintGetSignChar(long long int ival, uint32_t flags_used, char *schar) +{ + uint8_t len = 1U; + if (ival < 0) + { + *schar = '-'; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + *schar = '+'; + } + else if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + *schar = ' '; + } + else + { + *schar = '\0'; + len = 0U; + } + } + return len; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint32_t PrintGetWidth(const char **p, va_list *ap) +{ + uint32_t field_width = 0; + uint8_t done = 0U; + char c; + + while (0U == done) + { + c = *(++(*p)); + if ((c >= '0') && (c <= '9')) + { + (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + (field_width) = (uint32_t)va_arg(*ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --(*p); + done = 1U; + } + } + return field_width; +} + +static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width) +{ + const char *p = *s; + uint32_t precision_width = 6U; + uint8_t done = 0U; + +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = false; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = 0U; + while (0U == done) + { + char c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(*ap, uint32_t); + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = 1U; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } + *s = p; + return precision_width; +} + +static uint32_t PrintIsobpu(const char c) +{ + uint32_t ret = 0U; + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsdi(const char c) +{ + uint32_t ret = 0U; + if ((c == 'd') || (c == 'i')) + { + ret = 1U; + } + return ret; +} + +static void PrintOutputdifFobpu(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + char schar, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + } + } + /* The string was built in reverse order, now display in correct order. */ + if ('\0' != schar) + { + cb(buf, count, schar, 1); + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static void PrintOutputxX(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + bool use_caps, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + uint8_t dschar = 0; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2U; + } + cb(buf, count, ' ', (int)field_width - (int)vlen); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + vlen += 2U; + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static uint32_t PrintIsfF(const char c) +{ + uint32_t ret = 0U; + if ((c == 'f') || (c == 'F')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsxX(const char c) +{ + uint32_t ret = 0U; + if ((c == 'x') || (c == 'X')) + { + ret = 1U; + } + return ret; +} + +#if PRINTF_ADVANCED_ENABLE +static uint32_t PrintCheckFlags(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + bool done = false; + while (false == done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } + *s = p; + return flags_used; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE +/* + * Check for the length modifier. + */ +static uint32_t PrintGetLengthFlag(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } + *s = p; + return flags_used; +} +#else +static void PrintFilterLengthFlag(const char **s) +{ + const char *p = *s; + char ch; + + do + { + ch = *++p; + } while ((ch == 'h') || (ch == 'l')); + + *s = --p; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint8_t PrintGetRadixFromobpu(const char c) +{ + uint8_t radix; + + if (c == 'o') + { + radix = 8U; + } + else if (c == 'b') + { + radix = 2U; + } + else if (c == 'p') + { + radix = 16U; + } + else + { + radix = 10U; + } + return radix; +} + +static uint32_t ScanIsWhiteSpace(const char c) +{ + uint32_t ret = 0U; + if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + ret = 1U; + } + return ret; +} + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint32_t count = 0U; + char c; + + c = **s; + while (1U == ScanIsWhiteSpace(c)) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + long long int a; + long long int b; + long long int c; + + unsigned long long int ua; + unsigned long long int ub; + unsigned long long int uc; + unsigned long long int uc_param; +#else + int a; + int b; + int c; + + unsigned int ua; + unsigned int ub; + unsigned int uc; + unsigned int uc_param; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(PRINTF_ADVANCED_ENABLE > 0) + neg = 0U; +#endif + +#if PRINTF_ADVANCED_ENABLE + a = 0; + b = 0; + c = 0; + ua = 0ULL; + ub = 0ULL; + uc = 0ULL; + uc_param = 0ULL; +#else + a = 0; + b = 0; + c = 0; + ua = 0U; + ub = 0U; + uc = 0U; + uc_param = 0U; +#endif /* PRINTF_ADVANCED_ENABLE */ + + (void)a; + (void)b; + (void)c; + (void)ua; + (void)ub; + (void)uc; + (void)uc_param; + (void)neg; + /* + * Fix MISRA issue: CID 15972928 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3) + * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump); + */ +#if PRINTF_ADVANCED_ENABLE + if (0U != neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(long long int *)nump; +#else + a = *(int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (long long int)a / (long long int)radix; + c = (long long int)a - ((long long int)b * (long long int)radix); + if (c < 0) + { + uc = (unsigned long long int)c; + uc_param = ~uc; + c = (long long int)uc_param + 1 + (long long int)'0'; + } +#else + b = (int)a / (int)radix; + c = (int)a - ((int)b * (int)radix); + if (c < 0) + { + uc = (unsigned int)c; + uc_param = ~uc; + c = (int)uc_param + 1 + (int)'0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + (int)'0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { +#if PRINTF_ADVANCED_ENABLE + ua = *(unsigned long long int *)nump; +#else + ua = *(unsigned int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if PRINTF_ADVANCED_ENABLE + ub = (unsigned long long int)ua / (unsigned long long int)radix; + uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix); +#else + ub = ua / (unsigned int)radix; + uc = ua - (ub * (unsigned int)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + (unsigned int)'0'; + } + else + { + uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < (int32_t)precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= (double)0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < (int32_t)precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(long long int)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt Format string for printf. + * param[in] ap Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + unsigned int radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + char schar; + long long int ival; + unsigned long long int uval = 0; +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned long long int +#define STR_FORMAT_PRINTF_IVAL_TYPE long long int + bool valid_precision_width; +#else + int ival; + unsigned int uval = 0; +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned int +#define STR_FORMAT_PRINTF_IVAL_TYPE int +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = PrintCheckFlags(&p); +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = PrintGetWidth(&p, &ap); + + /* Next check for the width and precision field separator. */ +#if PRINTF_ADVANCED_ENABLE + precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width); +#else + precision_width = PrintGetPrecision(&p, &ap, NULL); + (void)precision_width; +#endif + +#if PRINTF_ADVANCED_ENABLE + /* Check for the length modifier. */ + flags_used |= PrintGetLengthFlag(&p); +#else + /* Filter length modifier. */ + PrintFilterLengthFlag(&p); +#endif + + /* Now we're ready to examine the format. */ + c = *++p; + { + if (1U == PrintIsdi(c)) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + ival = (long long int)va_arg(ap, long long int); + } + else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + ival = (long long int)va_arg(ap, long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (STR_FORMAT_PRINTF_IVAL_TYPE)va_arg(ap, int); + } + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + vlen += (int)PrintGetSignChar(ival, flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsfF(c)) + { +#if PRINTF_FLOAT_ENABLE + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((long long int)-1) : ((long long int)fval)), + flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + +#else + (void)va_arg(ap, double); +#endif /* PRINTF_FLOAT_ENABLE */ + } + else if (1U == PrintIsxX(c)) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int); + } + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputxX(flags_used, field_width, (unsigned int)vlen, use_caps, vstrp, cb, buf, &count); +#else + PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsobpu(c)) + { + if ('p' == c) + { + /* + * Fix MISRA issue: CID 17205581 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA C-2012 + * Rule 11.6) 1.misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void * + * is cast to type uint32_t. + * + * Orignal code: uval = (STR_FORMAT_PRINTF_UVAL_TYPE)(uint32_t)va_arg(ap, void *); + */ + void *pval; + pval = (void *)va_arg(ap, void *); + (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *)); + } + else + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long int); + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + radix = PrintGetRadixFromobpu(c); + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, int); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = (int)precision_width; + } + else + { + vlen = (int)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (0U == (flags_used & (unsigned int)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', (int)field_width - (int)vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*sval)) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_Minus)) + { + cb(buf, &count, ' ', (int)field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + p++; + } + + return (int)count; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanIsFloat(char *c) +{ + uint8_t ret = 0U; + if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) || + ('g' == (*c)) || ('G' == (*c))) + { + ret = 1U; + } + return ret; +} +#endif + +static uint8_t StrFormatScanIsFormatStarting(char *c) +{ + uint8_t ret = 1U; + if ((*c != '%')) + { + ret = 0U; + } + else if (*(c + 1) == '%') + { + ret = 0U; + } + else + { + /*MISRA rule 15.7*/ + } + + return ret; +} + +static uint8_t StrFormatScanGetBase(uint8_t base, const char *s) +{ + if (base == 0U) + { + if (s[0] == '0') + { + if ((s[1] == 'x') || (s[1] == 'X')) + { + base = 16; + } + else + { + base = 8; + } + } + else + { + base = 10; + } + } + return base; +} + +static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg) +{ + uint8_t len; + switch (*p) + { + case '-': + *neg = -1; + len = 1; + break; + case '+': + *neg = 1; + len = 1; + break; + default: + *neg = 1; + len = 0; + break; + } + return len; +} + +static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(*args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(*args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + + return 1u; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + else +#endif /* SCANF_ADVANCED_ENABLE */ + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(*args_ptr, double *) = fnum; + } + else + { + *va_arg(*args_ptr, float *) = (float)fnum; + } + return 1u; + } +} +#endif /* SCANF_FLOAT_ENABLE */ + +static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base) +{ + uint8_t exitPending = 0U; + char *c = *str; + + /* Loop to get full conversion specification. */ + while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask))) + { +#if SCANF_ADVANCED_ENABLE + if ('*' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_Suppress; + } + } + else if ('h' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'h') + { + (*flag) |= (uint32_t)kSCANF_LengthChar; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthShortInt; + } + } + } + else if ('l' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'l') + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongInt; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongInt; + } + } + } + else +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + if ('L' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble; + } + } + else +#endif /* SCANF_FLOAT_ENABLE */ + if (((*c) >= '0') && ((*c) <= '9')) + { + { + char *p; + errno = 0; + (*field_width) = strtoul(c, &p, 10); + if (0 != errno) + { + *field_width = 0U; + } + c = p - 1; + } + } + else if ('d' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_TypeSinged; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('u' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('o' == (*c)) + { + (*base) = 8U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if (('x' == (*c))) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('X' == (*c)) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('i' == (*c)) + { + (*base) = 0U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } +#if SCANF_FLOAT_ENABLE + else if (1U == StrFormatScanIsFloat(c)) + { + (*flag) |= (uint32_t)kSCANF_DestFloat; + } +#endif /* SCANF_FLOAT_ENABLE */ + else if ('c' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestChar; + if (MAX_FIELD_WIDTH == (*field_width)) + { + (*field_width) = 1; + } + } + else if ('s' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestString; + } + else + { + exitPending = 1U; + } + + if (1U == exitPending) + { + break; + } + else + { + c++; + } + } + *str = c; + return exitPending; +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + uint8_t added; + + uint8_t exitPending = 0; + + const char *s; +#if SCANF_FLOAT_ENABLE + char *s_temp; /* MISRA C-2012 Rule 11.3 */ +#endif + + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c))) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if (0U == StrFormatScanIsFormatStarting(c)) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = MAX_FIELD_WIDTH; + base = 0; + added = 0U; + + exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base); + + if (1U == exitPending) + { + /* Format strings are exhausted. */ + break; + } + + /* Matching strings in input streams and assign to argument. */ + if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar) + { + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) +#if SCANF_ADVANCED_ENABLE + && ('\0' != (*p)) +#endif + ) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) && (*p != '\0') && (0U == ScanIsWhiteSpace(*p))) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + base = StrFormatScanGetBase(base, s); + + added = StrFormatScanCheckSymbol(p, &neg); + n_decode += added; + p += added; + field_width -= added; + + s = p; + if (strlen(p) > field_width) + { + char temp[12]; + char *tempEnd; + (void)memcpy(temp, p, sizeof(temp) - 1U); + temp[sizeof(temp) - 1U] = '\0'; + errno = 0; + val = (int32_t)strtoul(temp, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = p + (tempEnd - temp); + } + else + { + char *tempEnd; + val = 0; + errno = 0; + val = (int32_t)strtoul(p, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = tempEnd; + } + n_decode += (uintptr_t)p - (uintptr_t)s; + + val *= neg; + + nassigned += StrFormatScanFillInteger(flag, &args_ptr, val); + } +#if SCANF_FLOAT_ENABLE + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat) + { + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = 0.0; + errno = 0; + + fnum = strtod(p, (char **)&s_temp); + s = s_temp; /* MISRA C-2012 Rule 11.3 */ + + /* MISRA C-2012 Rule 22.9 */ + if (0 != errno) + { + break; + } + + if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL)) + { + n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p; + p = s; + nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum); + } + } +#endif /* SCANF_FLOAT_ENABLE */ + else + { + break; + } + } + } + return (int)nassigned; +} diff --git a/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h new file mode 100644 index 000000000..bf7adcc52 --- /dev/null +++ b/platform/ext/target/nxp/common/Native_Driver/utilities/str/fsl_str.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h new file mode 100644 index 000000000..435ed4bfd --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0.h @@ -0,0 +1,31268 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b231019 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0.h + * @version 1.1 + * @date 2019-05-16 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 + */ + +#if !defined(LPC55S69_CM33_CORE0_H_) +#define LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + +/*! @name TST - ADC Test Register */ +/*! @{ */ + +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) + +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) + +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) + +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) + +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) + +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[1]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[1]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[1]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB port + */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB Full Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif +/* AHB_SECURE_CTRL Mirror address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x500AD000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE_NS (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x500AE000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE_NS (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x500AF000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE_NS (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE_NS) +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + #endif + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[72]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ + +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale + */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ + +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..Reserved. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. + */ +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + */ +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ + +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ + +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ + +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. + */ +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ +/*! @{ */ + +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ + +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name AUX_BIAS - AUX_BIAS */ +/*! @{ */ + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. + */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) + +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. + */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) + +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. + */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. + */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ + +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ + +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + */ +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + */ +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ + +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. + */ +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ + +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ + +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ + +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ + +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ + +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ + +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ + +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ + +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ + +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ + +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ + +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ + +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ + +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ + +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ + +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ + +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + */ +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + */ +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + */ +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + */ +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + */ +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ + +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ + +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + */ +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ + +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. + */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. + */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. + */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. + */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. + */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. + */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. + */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. + */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. + */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. + */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. + */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. + */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. + */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. + */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } +/* Backward compatibility for bitfield SHADOW */ +#define CTIMER_MSR_MATCH_SHADOW_MASK CTIMER_MSR_SHADOW_MASK +#define CTIMER_MSR_MATCH_SHADOW_SHIFT CTIMER_MSR_SHADOW_SHIFT +#define CTIMER_MSR_MATCH_SHADOW CTIMER_MSR_SHADOW + + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DBGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DBGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation + */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) + */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) + */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value + */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. + */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. + */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Register_Masks */ + + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/*! + * @} + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[23]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ + +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ + +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ + +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (23U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (23U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ + +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ + +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ + +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ + +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ + +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (4U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ + +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< , offset: 0x0 */ + __IO uint32_t VERSION; /**< , offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - */ +/*! @{ */ + +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - */ +/*! @{ */ + +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - */ +/*! @{ */ + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. + */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ + +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ + +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ + __IO uint32_t USB_ID; /**< , offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..96MHz FRO + * 0b10..48MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. + */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) +/*! @} */ + +/*! @name USB_ID - */ +/*! @{ */ + +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name CC_SOCU_PIN - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name CC_SOCU_DFLT - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ +/*! @{ */ + +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ + +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ + +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ + +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. + */ +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). + */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ + +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ + +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ + +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ + +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ +/*! @{ */ + +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ + +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from + * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, + * it has to compute the full ICB, quicker when not 0. + */ +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ + +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ + +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ + +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER - Enables mastering. + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ + +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ + +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ + +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name DIGEST0 - */ +/*! @{ */ + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) +/*! @} */ + +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ + +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + */ +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ + +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + */ +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected + */ +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled + */ +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) + +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included + */ +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included + */ +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available + */ +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) + +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +/*! ICB - 1 if ICB over AES included + */ +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ + +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + */ +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ + +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. + */ +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ + +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ + +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ + +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. + */ +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. + */ +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. + */ +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. + */ +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. + */ +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. + */ +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. + */ +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. + */ +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. + */ +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. + */ +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ + +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ + +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. + */ +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. + */ +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. + */ +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. + */ +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. + */ +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. + */ +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. + */ +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + */ +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. + */ +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. + */ +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. + */ +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ + +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ + +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ + +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ + +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. + */ +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ + +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ + +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + */ +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) + +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is + * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ + +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ + +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. + */ +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ + +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ + +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ + +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ + +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain cell. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. + */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. + */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ + +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +/*! EX - Cleared when read, set when written. See usage description above. + */ +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) + */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note: There is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Capture Low Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Capture High Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Match Low Register */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Match High Register */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP_MUX - LUTn input x MUX */ +/*! @{ */ + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..The output of LUT0. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) + +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. + */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) +/*! @} */ + +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ + +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. + */ +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ +/*! @{ */ + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR + */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched + */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ + +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_7[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_8[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'OSTIMER' */ + uint8_t RESERVED_11[24]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_12[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_13[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode. + * 0b10..Latest IC boot was from POWER DOWN low power mode. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) +/*! @} */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) +#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) +/*! BODCORERESETENABLE - BOD CORE reset enable. + * 0b0..BOD CORE reset is disable. + * 0b1..BOD CORE reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) + +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ +/*! @{ */ + +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) + +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. + */ +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. + */ +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. + */ +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. + */ +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. + */ +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. + */ +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ + +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) + +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) +#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) +/*! MISCCTRL_3_8 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) +#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) +/*! MISCCTRL_13_14 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) + +#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) +#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) +/*! WAKUPIO_RST - WAKEUP IO event detector reset control. + * 0b1..Wakeup IO is reset. + * 0b0..Wakeup IO is not reset. + */ +#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. + */ +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. + */ +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. + */ +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. + */ +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + */ +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. + */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. + */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. + */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ + +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! outbase - Base address register for the output region + */ +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ + +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! out_scaler - Output Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ + +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! tmpbase - Base address register for the temporary region + */ +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ + +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ + +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! inabase - Base address register for the input A region + */ +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ + +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ + +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! inbbase - Base address register for the input B region + */ +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ + +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ + +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! decode_opcode - opcode specific to decode_machine + */ +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + */ +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! inst_busy - Instruction busy signal when high indicates processing is on + */ +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ + +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = + * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = + * inst_length[20:16] + */ +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ + +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! cppre_in - co-processor scaling of input + */ +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! cppre_out - co-processor fixed point output + */ +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! cppre_sat - 1 : forces sub-32 bit saturation + */ +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! cppre_sat8 - 0 = 8bits, 1 = 16bits + */ +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ + +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! inst_misc - Misc register. For Matrix : Used for scale factor + */ +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ + +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! cursory - 1 : Enable cursory mode + */ +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! cordic_x - Cordic input x + */ +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! cordic_y - Cordic input y + */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! cordic_z - Cordic input z + */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ + +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - overflow + */ +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - nan + */ +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - fixed_pt_overflow + */ +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - underflow + */ +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - bus_error + */ +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ + +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! intr_oflow - 1 : Enable interrupt on Floating point overflow + */ +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! intr_nan - 1 : Enable interrupt on Floating point NaN + */ +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow + */ +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation + */ +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! intr_berr - 1: Enable interrupt on AHBM Buss Error + */ +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! intr_comp - 1: Enable interrupt on instruction completion + */ +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ + +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! event_oflow - 1 : Enable event trigger on Floating point overflow + */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! event_nan - 1 : Enable event trigger on Floating point NaN + */ +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! event_fixed - 1: Enable event trigger on Fixed point Overflow + */ +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! event_uflow - 1 : Enable event trigger on Subnormal truncation + */ +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! event_berr - 1: Enable event trigger on AHBM Buss Error + */ +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! event_comp - 1: Enable event trigger on instruction completion + */ +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ + +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + */ +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ + +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! gpreg - General purpose register bank + */ +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ + +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! compreg - Compute register bank + */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ + +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ + +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + */ +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + */ +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + */ +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ + +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state + */ +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation + */ +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation + */ +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation + */ +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation + */ +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation + */ +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ + +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations + */ +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ + +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations + */ +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ + +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress + */ +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful + */ +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed + */ +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key + */ +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available + */ +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC + */ +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available + */ +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ + +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed + */ +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed + */ +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed + */ +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed + */ +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ + +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data + */ +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ + +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data + */ +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ + +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data + */ +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ + +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register + */ +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ + +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data + */ +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ + +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + */ +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ + +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +/*! VERSION - Version of the PUF module. + */ +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ + +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ + +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear + */ +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ + +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +/*! RAMON - Power on the PUF RAM. + */ +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) + +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +/*! RAMSTAT - PUF RAM status. + */ +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ + +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ + +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ + +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ + +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) + +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) + +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) + +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) + +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) + +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) + +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) + +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 0 to 7 PUF key indexes + */ +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) + +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) + +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) + +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) + +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) + +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) + +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) + +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_H - */ +/*! @{ */ + +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) + +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) + +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) + +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) + +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) + +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) + +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) + +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) + +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 8 to 15 PUF key indexes + */ +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) + +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) + +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) + +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) + +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) + +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) + +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ + +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register + */ +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register + */ +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register + */ +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register + */ +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + uint8_t RESERVED_1[4068]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ + +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. + */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ + +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + */ +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ + +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. + */ +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. + */ +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. + */ +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. + */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ + +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. + */ +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. + */ +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ + +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ + +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ + +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ + +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - Sub-second counter register */ +/*! @{ */ + +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ + +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + */ +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; + uint8_t RESERVED_0[40]; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EV[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ + +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ + +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ + +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ + +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ + +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ + +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ + +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ + +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. + */ +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. + */ +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ + +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ + +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ + +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ + +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ + +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - SCT DMA request 0 register */ +/*! @{ */ + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - SCT DMA request 1 register */ +/*! @{ */ + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ + +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ + +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ + +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ + +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAPL - SCT_CAPL register */ +/*! @{ */ + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) +/*! @} */ + +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) + +/*! @name CAPH - SCT_CAPH register */ +/*! @{ */ + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) +/*! @} */ + +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) + +/*! @name CAP - SCT capture register of capture channel */ +/*! @{ */ + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCHL - SCT_MATCHL register */ +/*! @{ */ + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) +/*! @} */ + +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) + +/*! @name MATCHH - SCT_MATCHH register */ +/*! @{ */ + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) +/*! @} */ + +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) + +/*! @name MATCH - SCT match value register of match channels */ +/*! @{ */ + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ + +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ + +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ + +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +/*! CONTROLLER_RESET - Controller reset. + */ +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) + +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +/*! FIFO_RESET - Fifo reset. + */ +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) + +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +/*! DMA_RESET - DMA reset. + */ +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) + +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +/*! INT_ENABLE - Global interrupt enable/disable bit. + */ +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) + +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +/*! READ_WAIT - Read/wait. + */ +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) + +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +/*! SEND_IRQ_RESPONSE - Send irq response. + */ +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) + +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +/*! ABORT_READ_DATA - Abort read data. + */ +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) + +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +/*! SEND_CCSD - Send ccsd. + */ +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) + +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. + */ +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) + +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. + */ +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) + +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +/*! USE_INTERNAL_DMAC - SD/MMC DMA use. + */ +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ + +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 0. + */ +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) + +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 1. + */ +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ + +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +/*! CLK_DIVIDER0 - Clock divider-0 value. + */ +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ + +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. + */ +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. + */ +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. + */ +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) + +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. + */ +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ + +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +/*! RESPONSE_TIMEOUT - Response time-out value. + */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) + +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + */ +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ + +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ + +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +/*! BLOCK_SIZE - Block size. + */ +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ + +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + */ +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ + +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) + +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) + +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) + +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) + +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) + +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) + +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) + +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) + +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) + +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) + +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) + +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) + +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) + +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) + +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) + +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/Write no CRC. + */ +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) + +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +/*! SDIO_INT_MASK - Mask SDIO interrupt. + */ +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ + +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +/*! CMD_ARG - Value indicates command argument to be passed to card. + */ +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ + +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +/*! CMD_INDEX - Command index. + */ +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) + +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +/*! RESPONSE_EXPECT - Response expect. + */ +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) + +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +/*! RESPONSE_LENGTH - Response length. + */ +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) + +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +/*! CHECK_RESPONSE_CRC - Check response CRC. + */ +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) + +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +/*! DATA_EXPECTED - Data expected. + */ +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) + +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +/*! READ_WRITE - read/write. + */ +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) + +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +/*! TRANSFER_MODE - Transfer mode. + */ +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) + +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +/*! SEND_AUTO_STOP - Send auto stop. + */ +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) + +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. + */ +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) + +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +/*! STOP_ABORT_CMD - Stop abort command. + */ +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) + +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +/*! SEND_INITIALIZATION - Send initialization. + */ +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) + +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) + +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. + */ +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) + +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +/*! READ_CEATA_DEVICE - Read ceata device. + */ +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) + +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +/*! CCS_EXPECTED - CCS expected. + */ +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) + +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. + */ +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) + +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. + */ +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) + +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +/*! DISABLE_BOOT - Disable Boot. + */ +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) + +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +/*! BOOT_MODE - Boot Mode. + */ +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) + +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +/*! VOLT_SWITCH - Voltage switch bit. + */ +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) + +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +/*! USE_HOLD_REG - Use Hold Register. + */ +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) + +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +/*! START_CMD - Start command. + */ +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ + +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +/*! RESPONSE - Bits of response. + */ +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ + +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) + +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) + +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) + +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) + +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) + +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) + +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) + +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) + +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) + +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) + +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) + +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) + +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) + +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) + +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) + +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) + +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ + +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) + +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) + +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) + +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) + +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) + +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) + +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) + +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) + +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). + */ +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) + +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). + */ +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) + +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) + +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) + +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) + +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) + +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) + +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) + +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ + +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. + */ +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. + */ +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY - FIFO is empty status. + */ +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) + +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +/*! FIFO_FULL - FIFO is full status. + */ +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) + +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx + * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - + * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp + * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The + * command FSM state is represented using 19 bits. + */ +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) + +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + */ +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) + +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + */ +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) + +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. + */ +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) + +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. + */ +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) + +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. + */ +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) + +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +/*! DMA_ACK - DMA acknowledge signal state. + */ +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) + +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +/*! DMA_REQ - DMA request signal state. + */ +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ + +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. + */ +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) + +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. + */ +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) + +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + */ +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ + +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +/*! CARD0_DETECT - Card 0 detect + */ +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) + +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +/*! CARD1_DETECT - Card 1 detect + */ +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ + +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +/*! WRITE_PROTECT - Write protect. + */ +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ + +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. + */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ + +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ + +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ + +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +/*! CARD_RESET - Hardware reset. + */ +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ + +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +/*! SWR - Software Reset. + */ +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) + +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +/*! FB - Fixed Burst. + */ +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) + +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +/*! DSL - Descriptor Skip Length. + */ +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) + +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +/*! DE - SD/MMC DMA Enable. + */ +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) + +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +/*! PBL - Programmable Burst Length. + */ +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ + +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +/*! PD - Poll Demand. + */ +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ + +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +/*! SDL - Start of Descriptor List. + */ +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ + +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +/*! TI - Transmit Interrupt. + */ +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) + +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +/*! RI - Receive Interrupt. + */ +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) + +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Interrupt. + */ +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) + +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) + +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +/*! CES - Card Error Summary. + */ +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) + +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary. + */ +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) + +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary. + */ +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) + +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +/*! EB - Error Bits. + */ +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) + +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +/*! FSM - DMAC state machine present state. + */ +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ + +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +/*! TI - Transmit Interrupt Enable. + */ +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) + +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +/*! RI - Receive Interrupt Enable. + */ +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) + +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Enable. + */ +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) + +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) + +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +/*! CES - Card Error summary Interrupt Enable. + */ +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) + +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary Enable. + */ +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) + +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary Enable. + */ +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ + +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +/*! HDA - Host Descriptor Address Pointer. + */ +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ + +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +/*! HBA - Host Buffer Address Pointer. + */ +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ + +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +/*! CARDRDTHREN - Card Read Threshold Enable. + */ +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) + +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +/*! BSYCLRINTEN - Busy Clear Interrupt Enable. + */ +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) + +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +/*! CARDTHRESHOLD - Card Threshold size. + */ +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ + +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +/*! BACKENDPWR - Back-end Power control for card application. + */ +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ + +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +/*! DATA - SDIF FIFO. + */ +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ + +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ + +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ + +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. + */ +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ + +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ + +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ + +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. + */ +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. + */ +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. + */ +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. + */ +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_13[4]; + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_18[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_19[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_20[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_21[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_22[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ + uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_32[248]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + uint8_t RESERVED_33[4]; + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[520]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_35[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_36[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_37[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_38[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_39[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ + uint8_t RESERVED_40[32]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ + +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +/*! PRI_USB_FS - USB-FS.(USB0) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +/*! PRI_SDIO - SDIO. + */ +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). + */ +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +/*! PRI_HASH_AES - HASH_AES. + */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +/*! PRI_USB_HS - USB-HS.(USB1) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ +/*! @{ */ + +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) + +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) + +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + */ +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + */ +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) + +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ + +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) + +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ + +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ + +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ + +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ + +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ + +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ + +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ + +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ + +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ + +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ + +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ + +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ + +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ + +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ + +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ + +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ + +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ + +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ + +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ + +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ + +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ + +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ + +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) + +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) + +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) + +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ + +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ + +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register */ +/*! @{ */ + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + */ +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. + */ +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. + * 0b1..USB0 Device clock is high. + * 0b0..USB0 Device clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. + * 0b1..USB0 Host clock is high. + * 0b0..USB0 Host clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ + +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b0..input mode. + * 0b1..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. + */ +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b1..Enable drive delay. + * 0b0..Disable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b1..Enables sample delay. + * 0b0..Disables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ + +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ + +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ + +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ + +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ + +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ +/*! @{ */ + +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. + */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ + +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b1..The CPU1 clock is enabled. + * 0b0..The CPU1 clock is not enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) + +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b1..The CPU1 is being reset. + * 0b0..The CPU1 is not being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ + +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +/*! CPBOOT - Coprocessor Boot Address for CPU1. + */ +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) + +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ + +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ + +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ + +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b1010..1010: Enable write access to all 6 registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ +/*! @{ */ + +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. + */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ + +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ + +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ + +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ + +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ + +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ + +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ + +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + */ +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + */ +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + */ +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + */ +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. + */ +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. + */ +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. + */ +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. + */ +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + */ +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. + */ +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ + +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ + +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ + +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. + */ +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. + */ +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. + */ +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. + */ +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. + */ +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. + */ +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. + */ +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. + */ +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. + */ +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ + +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ + +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + */ +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + */ +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ + +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. + */ +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ + +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + */ +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ + +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. + */ +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + */ +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + */ +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. + */ +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + */ +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + */ +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ + +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. + */ +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. + */ +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. + */ +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ + +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ + +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + */ +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ + +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. + */ +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ + +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. + */ +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ + +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + */ +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ + +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + */ +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + */ +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. + */ +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. + */ +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ + +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + */ +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. + */ +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + */ +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + */ +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ + +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + */ +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + */ +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + */ +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + */ +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + */ +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + */ +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + */ +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. + */ +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + */ +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. + */ +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. + */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. + */ +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. + */ +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. + */ +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. + */ +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. + */ +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. + */ +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. + */ +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. + */ +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. + */ +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. + */ +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. + */ +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. + */ +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. + */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. + */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. + */ +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. + */ +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. + */ +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. + */ +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. + */ +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. + */ +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. + */ +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. + */ +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. + */ +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. + */ +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. + */ +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. + */ +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. + */ +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. + */ +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. + */ +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. + */ +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. + */ +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. + */ +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. + */ +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ + +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. + */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. + */ +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. + */ +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. + */ +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ + +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. + */ +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + */ +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. + */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. + */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. + */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. + */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) +/*! @} */ + +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ +/*! @{ */ + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. + */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. + */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) +/*! @} */ + +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. + */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ + +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. + */ +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. + */ +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. + */ +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. + */ +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. + */ +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. + */ +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ + +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + */ +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ + +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ + +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. + */ +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. + */ +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. + */ +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + */ +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. + */ +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. + */ +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + */ +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. + */ +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. + */ +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) + +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + */ +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + */ +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + */ +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + */ +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +/*! @} */ + +/*! @name ATLPTDD - Done map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATLPTDS - Skip map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISOPTDD - Done map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISOPTDS - Skip map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INTPTDD - Done map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) +/*! @} */ + +/*! @name INTPTDS - Skip map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) +/*! @} */ + +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ + +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. + */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. + */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. + */ +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. + */ +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. + */ +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_1[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + uint8_t RESERVED_2[48]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'ANACTRL' */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. + */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. + */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. + */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. + */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. + */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S69_CM33_CORE0_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h new file mode 100644 index 000000000..4f39b7f3e --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core0_features.h @@ -0,0 +1,501 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-05-16 +** Build: b231017 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core0_FEATURES_H_ +#define _LPC55S69_cm33_core0_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief LPC_RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) +/* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) +/* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) +/* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) +/* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) +/* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief SW interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* GINT module features */ + +/* @brief The count of th port which are supported in GINT. */ +#define FSL_FEATURE_GINT_PORT_COUNT (2) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) + +/* RTC module features */ + +/* @brief Has SUBSEC Register (register SUBSEC) */ +#define FSL_FEATURE_RTC_HAS_SUBSEC (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SPI module features */ + +/* @brief SSEL pin count. */ +#define FSL_FEATURE_SPI_SSEL_COUNT (4) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* USBPHY module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) + +#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h new file mode 100644 index 000000000..6f95fa729 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1.h @@ -0,0 +1,31268 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV59_cm33_core1 +** LPC55S69JEV98_cm33_core1 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b231019 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core1.h + * @version 1.1 + * @date 2019-05-16 + * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + * + * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 + */ + +#if !defined(LPC55S69_CM33_CORE1_H_) +#define LPC55S69_CM33_CORE1_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */ + DMA0_IRQn = 1, /**< DMA0 controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + ADC0_IRQn = 22, /**< ADC0 */ + Reserved39_IRQn = 23, /**< Reserved interrupt */ + ACMP_IRQn = 24, /**< ACMP interrupts */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + Reserved55_IRQn = 39, /**< Reserved interrupt */ + Reserved56_IRQn = 40, /**< Reserved interrupt */ + Reserved57_IRQn = 41, /**< Reserved interrupt */ + SDIO_IRQn = 42, /**< SD/MMC */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + Reserved61_IRQn = 45, /**< Reserved interrupt */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ + SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */ + SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */ + PLU_IRQn = 52, /**< PLU interrupt */ + SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */ + HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */ + CASER_IRQn = 55, /**< CASPER interrupt */ + PUF_IRQn = 56, /**< PUF interrupt */ + PQ_IRQn = 57, /**< PQ interrupt */ + DMA1_IRQn = 58, /**< DMA1 interrupt */ + FLEXCOMM8_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 0 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_LPC55S69_cm33_core1.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestHashCrypt = 0U, /**< HashCrypt */ + kDma1RequestHashCrypt = 0U, /**< HashCrypt */ + kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */ + kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */ + kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */ + kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */ + kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ + kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ + kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */ + kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */ + kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */ + kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */ + kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */ + kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_5[136]; + __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[240]; + __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_7[248]; + __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_8[124]; + __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_9[2680]; + __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential/12-bit single ended resolution supported. + * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultanious single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 1 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - ADC Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in Doze mode. + * 0b1..ADC is disabled in Doze mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for auto-calibration has been made. + * 0b1..A request for auto-calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Configure for offset calibration function + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0x70000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - ADC Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Result FIFO1 data level not above watermark level. + * 0b1..Result FIFO1 holding data above watermark level. + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0xF0000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b0000..Command (sequence) associated with Trigger 0 currently being executed. + * 0b0001..Command (sequence) associated with Trigger 1 currently being executed. + * 0b0010..Command (sequence) associated with Trigger 2 currently being executed. + * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command is currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..FIFO1 watermark interrupts are not enabled. + * 0b1..FIFO1 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000000000000000..Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled. + * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - ADC Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC trigger priority control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * after completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11..RESERVED + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b00..Lowest power setting. + * 0b01..Higher power setting than 0b0. + * 0b10..Higher power setting than 0b1. + * 0b11..Highest power setting. + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. + * After this initial delay expires the analog will remain pre-enabled, and no additional delays will be + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - ADC Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software trigger 0 event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software trigger 1 event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software trigger 2 event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software trigger 3 event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + +#define ADC_SWTRIG_SWT4_MASK (0x10U) +#define ADC_SWTRIG_SWT4_SHIFT (4U) +/*! SWT4 - Software trigger 4 event + * 0b0..No trigger 4 event generated. + * 0b1..Trigger 4 event generated. + */ +#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + +#define ADC_SWTRIG_SWT5_MASK (0x20U) +#define ADC_SWTRIG_SWT5_SHIFT (5U) +/*! SWT5 - Software trigger 5 event + * 0b0..No trigger 5 event generated. + * 0b1..Trigger 5 event generated. + */ +#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + +#define ADC_SWTRIG_SWT6_MASK (0x40U) +#define ADC_SWTRIG_SWT6_SHIFT (6U) +/*! SWT6 - Software trigger 6 event + * 0b0..No trigger 6 event generated. + * 0b1..Trigger 6 event generated. + */ +#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + +#define ADC_SWTRIG_SWT7_MASK (0x80U) +#define ADC_SWTRIG_SWT7_SHIFT (7U) +/*! SWT7 - Software trigger 7 event + * 0b0..No trigger 7 event generated. + * 0b1..Trigger 7 event generated. + */ +#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + +#define ADC_SWTRIG_SWT8_MASK (0x100U) +#define ADC_SWTRIG_SWT8_SHIFT (8U) +/*! SWT8 - Software trigger 8 event + * 0b0..No trigger 8 event generated. + * 0b1..Trigger 8 event generated. + */ +#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + +#define ADC_SWTRIG_SWT9_MASK (0x200U) +#define ADC_SWTRIG_SWT9_SHIFT (9U) +/*! SWT9 - Software trigger 9 event + * 0b0..No trigger 9 event generated. + * 0b1..Trigger 9 event generated. + */ +#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + +#define ADC_SWTRIG_SWT10_MASK (0x400U) +#define ADC_SWTRIG_SWT10_SHIFT (10U) +/*! SWT10 - Software trigger 10 event + * 0b0..No trigger 10 event generated. + * 0b1..Trigger 10 event generated. + */ +#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + +#define ADC_SWTRIG_SWT11_MASK (0x800U) +#define ADC_SWTRIG_SWT11_SHIFT (11U) +/*! SWT11 - Software trigger 11 event + * 0b0..No trigger 11 event generated. + * 0b1..Trigger 11 event generated. + */ +#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + +#define ADC_SWTRIG_SWT12_MASK (0x1000U) +#define ADC_SWTRIG_SWT12_SHIFT (12U) +/*! SWT12 - Software trigger 12 event + * 0b0..No trigger 12 event generated. + * 0b1..Trigger 12 event generated. + */ +#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + +#define ADC_SWTRIG_SWT13_MASK (0x2000U) +#define ADC_SWTRIG_SWT13_SHIFT (13U) +/*! SWT13 - Software trigger 13 event + * 0b0..No trigger 13 event generated. + * 0b1..Trigger 13 event generated. + */ +#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + +#define ADC_SWTRIG_SWT14_MASK (0x4000U) +#define ADC_SWTRIG_SWT14_SHIFT (14U) +/*! SWT14 - Software trigger 14 event + * 0b0..No trigger 14 event generated. + * 0b1..Trigger 14 event generated. + */ +#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + +#define ADC_SWTRIG_SWT15_MASK (0x8000U) +#define ADC_SWTRIG_SWT15_SHIFT (15U) +/*! SWT15 - Software trigger 15 event + * 0b0..No trigger 15 event generated. + * 0b1..Trigger 15 event generated. + */ +#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception. + * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts. + * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts. + * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - ADC Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination For Channel A + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination For Channel B + * 0b0..Result written to FIFO 0 + * 0b1..Result written to FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0xF00U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger priority setting + * 0b0000..Set to highest priority, Level 1 + * 0b0001-0b1110..Set to corresponding priority level + * 0b1111..Set to lowest priority, Level 16 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger command select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 is executed + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (16U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written. + * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The gain offset calculation value is invalid. + * 0b1..The gain calibration value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input channel select + * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01..Single-Ended Mode. Only B side channel is converted. + * 0b10..Differential Mode. A-B. + * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select resolution of conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - ADC Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for trigger assertion before execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3 ADCK cycles. + * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. + * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. + * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. + * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. + * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. + * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. + * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0x7000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b000..Single conversion. + * 0b001..2 conversions averaged. + * 0b010..4 conversions averaged. + * 0b011..8 conversions averaged. + * 0b100..16 conversions averaged. + * 0b101..32 conversions averaged. + * 0b110..64 conversions averaged. + * 0b111..128 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..Select CMD1 command buffer register as next command. + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..Select CMD15 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (4U) + +/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0xF0000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b0000..Trigger source 0 initiated this conversion. + * 0b0001..Trigger source 1 initiated this conversion. + * 0b0010-0b1110..Corresponding trigger source initiated this conversion. + * 0b1111..Trigger source 15 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop count value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state + * prior to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b0001..CMD1 buffer used as control settings for this conversion. + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO entry is valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ +#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GAR */ +#define ADC_CAL_GAR_COUNT (33U) + +/*! @name CAL_GBR - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ +#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) +/*! @} */ + +/* The count of ADC_CAL_GBR */ +#define ADC_CAL_GBR_COUNT (33U) + +/*! @name TST - ADC Test Register */ +/*! @{ */ + +#define ADC_TST_CST_LONG_MASK (0x1U) +#define ADC_TST_CST_LONG_SHIFT (0U) +/*! CST_LONG - Calibration Sample Time Long + * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles. + * 0b1..Increased sample time. 67 ADCK cycles total sample time. + */ +#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) + +#define ADC_TST_FOFFM_MASK (0x100U) +#define ADC_TST_FOFFM_SHIFT (8U) +/*! FOFFM - Force M-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on MDAC. + */ +#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) + +#define ADC_TST_FOFFP_MASK (0x200U) +#define ADC_TST_FOFFP_SHIFT (9U) +/*! FOFFP - Force P-side positive offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced positive offset on PDAC. + */ +#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) + +#define ADC_TST_FOFFM2_MASK (0x400U) +#define ADC_TST_FOFFM2_SHIFT (10U) +/*! FOFFM2 - Force M-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on MDAC. + */ +#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) + +#define ADC_TST_FOFFP2_MASK (0x800U) +#define ADC_TST_FOFFP2_SHIFT (11U) +/*! FOFFP2 - Force P-side negative offset + * 0b0..Normal operation. No forced offset. + * 0b1..Test configuration. Forced negative offset on PDAC. + */ +#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) + +#define ADC_TST_TESTEN_MASK (0x800000U) +#define ADC_TST_TESTEN_SHIFT (23U) +/*! TESTEN - Enable test configuration + * 0b0..Normal operation. Test configuration not enabled. + * 0b1..Hardware BIST Test in progress. + */ +#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x500A0000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x400A0000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer + * @{ + */ + +/** AHB_SECURE_CTRL - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for Flash and ROM slaves., array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */ + } SEC_CTRL_FLASH_ROM[1]; + struct { /* offset: 0x30, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAMX slaves., array offset: 0x40, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAMX[1]; + uint8_t RESERVED_0[12]; + struct { /* offset: 0x50, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM0 slaves., array offset: 0x60, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM0[1]; + uint8_t RESERVED_1[8]; + struct { /* offset: 0x70, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM1 slaves., array offset: 0x80, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM1[1]; + uint8_t RESERVED_2[8]; + struct { /* offset: 0x90, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM2 slaves., array offset: 0xA0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM2[1]; + uint8_t RESERVED_3[8]; + struct { /* offset: 0xB0, array step: 0x18 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[2]; /**< Security access rules for RAM3 slaves., array offset: 0xC0, array step: index*0x18, index2*0x4 */ + } SEC_CTRL_RAM3[1]; + uint8_t RESERVED_4[8]; + struct { /* offset: 0xD0, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM4 slaves., array offset: 0xE0, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_RAM4[1]; + uint8_t RESERVED_5[12]; + struct { /* offset: 0xF0, array step: 0x30 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for both APB Bridges slaves., array offset: 0xF0, array step: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ + __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ + } SEC_CTRL_APB_BRIDGE[1]; + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + uint8_t RESERVED_7[8]; + struct { /* offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[1]; + uint8_t RESERVED_8[12]; + struct { /* offset: 0x160, array step: 0x14 */ + __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_USB_HS[1]; + uint8_t RESERVED_9[3212]; + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ + uint8_t RESERVED_10[80]; + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ + uint8_t RESERVED_11[80]; + __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ + uint8_t RESERVED_12[124]; + __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins., offset: 0xF80 */ + __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */ + __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */ + uint8_t RESERVED_14[36]; + __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */ + uint8_t RESERVED_15[16]; + __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ + uint8_t RESERVED_16[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ +} AHB_SECURE_CTRL_Type; + +/* ---------------------------------------------------------------------------- + -- AHB_SECURE_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks + * @{ + */ + +/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) +/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) +/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) + +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) + +/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) +/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) +/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) +/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) +/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) + +/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) +/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) +/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) +/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) +/*! SYSCON_RULE - System Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +/*! IOCON_RULE - I/O Configuration + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +/*! GINT0_RULE - GPIO input Interrupt 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +/*! GINT1_RULE - GPIO input Interrupt 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +/*! PINT_RULE - Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) +/*! CTIMER0_RULE - Standard counter/Timer 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +/*! CTIMER1_RULE - Standard counter/Timer 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +/*! WWDT_RULE - Windiwed wtachdog Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +/*! MRT_RULE - Multi-rate Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +/*! UTICK_RULE - Micro-Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) +/*! ANACTRL_RULE - Analog Modules controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) +/*! PMC_RULE - Power Management Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +/*! SYSCTRL_RULE - System Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) +/*! CTIMER2_RULE - Standard counter/Timer 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +/*! CTIMER3_RULE - Standard counter/Timer 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +/*! CTIMER4_RULE - Standard counter/Timer 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +/*! RTC_RULE - Real Time Counter + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +/*! OSEVENT_RULE - OS Event Timer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) +/*! FLASH_CTRL_RULE - Flash Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +/*! PRINCE_RULE - Prince + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) + +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) +/*! USBHPHY_RULE - USB High Speed Phy controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +/*! RNG_RULE - True Random Number Generator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +/*! PLU_RULE - Programmable Look-Up logic + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) +/*! DMA0_RULE - DMA Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) +/*! FS_USB_DEV_RULE - USB Full-speed device + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) +/*! SCT_RULE - SCTimer + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) +/*! FLEXCOMM0_RULE - Flexcomm interface 0 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) +/*! FLEXCOMM1_RULE - Flexcomm interface 1 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) +/*! FLEXCOMM2_RULE - Flexcomm interface 2 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) +/*! FLEXCOMM3_RULE - Flexcomm interface 3 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) +/*! FLEXCOMM4_RULE - Flexcomm interface 4 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) +/*! MAILBOX_RULE - Inter CPU communication Mailbox + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) +/*! GPIO0_RULE - High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) +/*! USB_HS_DEV_RULE - USB high Speed device registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) +/*! CRC_RULE - CRC engine + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) +/*! FLEXCOMM5_RULE - Flexcomm interface 5 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) +/*! FLEXCOMM6_RULE - Flexcomm interface 6 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) +/*! FLEXCOMM7_RULE - Flexcomm interface 7 + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) +/*! SDIO_RULE - SDMMC card interface + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) +/*! HS_LSPI_RULE - High Speed SPI + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) +/*! @} */ + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) +/*! ADC_RULE - ADC + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) +/*! USB_FS_HOST_RULE - USB Full Speed Host registers. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) +/*! USB_HS_HOST_RULE - USB High speed host registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) +/*! HASH_RULE - SHA-2 crypto registers + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) +/*! CASPER_RULE - RSA/ECC crypto accelerator + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) +/*! DMA1_RULE - DMA Controller (Secure) + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) +/*! GPIO1_RULE - Secure High Speed GPIO + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_RULE - AHB Secure Controller + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) + +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) +/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) +/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) + +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) +/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) + +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) + +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB port + */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ +#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) + +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. + * 0b0..Read access. + * 0b1..Write access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. + * 0b0..Code access. + * 0b1..Data access. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - security violation master number + * 0b0000..CPU0 Code. + * 0b0001..CPU0 System. + * 0b0010..CPU1 Data. + * 0b0011..CPU1 System. + * 0b0100..USB-HS Device. + * 0b0101..SDMA0. + * 0b1000..SDIO. + * 0b1001..PowerQuad. + * 0b1010..HASH. + * 0b1011..USB-FS Host. + * 0b1100..SDMA1. + */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */ +#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (12U) + +/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. + * 0b0..Not valid. + * 0b1..Valid (violation occurred). + */ +#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 + * 0b1..Pin state is readable by non-secure world. + * 0b0..Pin state is blocked to non-secure world. + */ +#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) +/*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) +/*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) +/*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) +/*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) +/*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) +/*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) +/*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) +/*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) +/*! UTICK_IRQ - Micro Tick Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) +/*! MRT_IRQ - Multi-Rate Timer interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) +/*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) +/*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) +/*! SCT_IRQ - SCTimer/PWM interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) +/*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) +/*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) +/*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) +/*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) +/*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) +/*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) +/*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) +/*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) +/*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) +/*! ADC_IRQ - General Purpose ADC interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) +/*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) +/*! USB0_IRQ - USB Full Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) +/*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) +/*! MAILBOX_IRQ - Mailbox interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK) +/*! @} */ + +/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) +/*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) +/*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) +/*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) +/*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) +/*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) +/*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) +/*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) +/*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) +/*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) +/*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) +/*! SDIO_IRQ - SDIO Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) +/*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) +/*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) +/*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) +/*! USB1_IRQ - USB High Speed Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) +/*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) +/*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) +/*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) +/*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) +/*! PLU_IRQ - Programmable Look-Up Controller interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) +/*! SEC_VIO_IRQ - Security Violation interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) +/*! SHA_IRQ - HASH-AES interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) +/*! CASPER_IRQ - CASPER interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) +/*! PQ_IRQ - Power Quad interrupt. + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) +/*! SDMA1_IRQ - System DMA 1 (Secure) interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) +/*! LSPI_HS_IRQ - High Speed SPI interrupt + * 0b0..Interrupt is blocked to CPU1. + * 0b1..Interrupt is readable by CPU1. + */ +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK) +/*! @} */ + +/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ +/*! @{ */ + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) +/*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) +/*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) +/*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) + +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) +/*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_LEVEL - master secure level register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) +/*! SDIO - SDIO. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) +/*! PQ - Power Quad. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) +/*! HASH - Hash. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. + * 0b00..Non-secure and Non-priviledge user access allowed. + * 0b01..Non-secure and Privilege access allowed. + * 0b10..Secure and Non-priviledge user access allowed. + * 0b11..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) +/*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) +/*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) +/*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) +/*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) +/*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) +/*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) +/*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) + * 0b11..Non-secure and Non-priviledge user access allowed. + * 0b10..Non-secure and Privilege access allowed. + * 0b01..Secure and Non-priviledge user access allowed. + * 0b00..Secure and Priviledge user access allowed. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ +/*! @{ */ + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. + * 0b10..Writable. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - secure control duplicate register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - secure control register */ +/*! @{ */ + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write lock. + * 0b10..Secure control registers can be written. + * 0b01..Restricted mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. + * 0b10..Disable check. + * 0b01..Enabled (restricted mode) + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. + * 0b10..Enable abort fort secure checker. + * 0b01..Disable abort fort secure checker. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) +/*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. + * 0b10..Simple master in strict mode. + * 0b01..Simple master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) +/*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. + * 0b10..Smart master in strict mode. + * 0b01..Smart master in tier mode. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - Disable IDAU. + * 0b10..IDAU is enabled. + * 0b01..IDAU is disable. + */ +#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Register_Masks */ + + +/* AHB_SECURE_CTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x500AC000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS } +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_BASE (0x400AC000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE) + /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */ + #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE } + /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */ + #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL } +#endif +/* AHB_SECURE_CTRL Mirror address */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x500AD000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE_NS (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x500AE000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE_NS (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE_NS) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x500AF000u) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE_NS (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE_NS) +#else + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS1_BASE (0x400AD000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS1 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS1_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS2_BASE (0x400AE000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS2 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS2_BASE) + /** Peripheral AHB_SECURE_CTRL base address */ + #define AHB_SECURE_CTRL_ALIAS3_BASE (0x400AF000u) + /** Peripheral AHB_SECURE_CTRL base pointer */ + #define AHB_SECURE_CTRL_ALIAS3 ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_ALIAS3_BASE) + #endif + + +/*! + * @} + */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ANACTRL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer + * @{ + */ + +/** ANACTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */ + __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */ + __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */ + __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ + __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ + __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */ + __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */ + __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ + uint8_t RESERVED_4[100]; + __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[72]; + __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ + __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ +} ANACTRL_Type; + +/* ---------------------------------------------------------------------------- + -- ANACTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks + * @{ + */ + +/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) +/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. + * 0b0..FRO192M trimming and 'Enable' comes from eFUSE. + * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers. + */ +#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK) +/*! @} */ + +/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ +/*! @{ */ + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) +/*! FLASH_PWRDWN - Flash Power Down status. + * 0b0..Flash is not in power down mode. + * 0b1..Flash is in power down mode. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) +/*! FLASH_INIT_ERROR - Flash initialization error status. + * 0b0..No error. + * 0b1..At least one error occured during flash initialization.. + */ +#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) +/*! @} */ + +/*! @name FREQ_ME_CTRL - Frequency Measure function control register */ +/*! @{ */ + +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale + */ +#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + +#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) +#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ +#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) +/*! @} */ + +/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ +/*! @{ */ + +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) +/*! ENA_12MHZCLK - 12 MHz clock control. + * 0b0..12 MHz clock is disabled. + * 0b1..12 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) +/*! ENA_48MHZCLK - 48 MHz clock control. + * 0b0..Reserved. + * 0b1..48 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) +#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. + */ +#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) +#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ +#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + +#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) +#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + */ +#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) + +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) +/*! ENA_96MHZCLK - 96 MHz clock control. + * 0b0..96 MHz clock is disabled. + * 0b1..96 MHz clock is enabled. + */ +#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + +#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) +#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ +#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ +/*! @{ */ + +#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) +#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) +/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. + * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available). + * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by + * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). + */ +#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ +#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) +/*! @} */ + +/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ +/*! @{ */ + +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) +#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) +/*! VBATDIVENABLE - Switch On/Off VBAT divider branch. + * 0b0..VBAT divider branch is disabled. + * 0b1..VBAT divider branch is enabled. + */ +#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) +/*! @} */ + +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ +/*! @{ */ + +#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) +#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. + */ +#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ +#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) +/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. + * 0b0..XO AC buffer bypass is disabled. + * 0b1..XO AC buffer bypass is enabled. + */ +#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. + */ +#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) +/*! @} */ + +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ +/*! @{ */ + +#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) +#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) +/*! XO_READY - Indicates XO out frequency statibilty. + * 0b0..XO output frequency is not yet stable. + * 0b1..XO output frequency is stable. + */ +#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) +/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. + * 0b0..BOD VBAT interrupt is disabled. + * 0b1..BOD VBAT interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) +/*! BODCORE_INT_ENABLE - BOD CORE interrupt control. + * 0b0..BOD CORE interrupt is disabled. + * 0b1..BOD CORE interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) +/*! DCDC_INT_ENABLE - DCDC interrupt control. + * 0b0..DCDC interrupt is disabled. + * 0b1..DCDC interrupt is enabled. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ +#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) +/*! @} */ + +/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ +/*! @{ */ + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) +/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) +/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) +/*! BODVBAT_VAL - Current value of BOD VBAT power status output. + * 0b0..VBAT voltage level is below the threshold. + * 0b1..VBAT voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) +/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) +/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) +/*! BODCORE_VAL - Current value of BOD CORE power status output. + * 0b0..CORE voltage level is below the threshold. + * 0b1..CORE voltage level is above the threshold. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) +/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) +/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. + * 0b0..No interrupt pending.. + * 0b1..Interrupt pending.. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) +/*! DCDC_VAL - Current value of DCDC power status output. + * 0b0..DCDC output Voltage is below the targeted regulation level. + * 0b1..DCDC output Voltage is above the targeted regulation level. + */ +#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK) +/*! @} */ + +/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) +#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) +/*! SL - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + +#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + +#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) +#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) +/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. + * 0b00..Normal mode. + * 0b01..P-Monitor mode. Measure with weak P transistor. + * 0b10..P-Monitor mode. Measure with weak N transistor. + * 0b11..Don't use. + */ +#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + +#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) +#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) +#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) +/*! E_ND0 - First NAND2-based ringo control. + * 0b0..First NAND2-based ringo is disabled. + * 0b1..First NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) +#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) +/*! E_ND1 - Second NAND2-based ringo control. + * 0b0..Second NAND2-based ringo is disabled. + * 0b1..Second NAND2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) +#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) +/*! E_NR0 - First NOR2-based ringo control. + * 0b0..First NOR2-based ringo is disabled. + * 0b1..First NOR2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) +#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) +/*! E_NR1 - Second NOR2-based ringo control. + * 0b0..Second NORD2-based ringo is disabled. + * 0b1..Second NORD2-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) +#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) +/*! E_IV0 - First Inverter-based ringo control. + * 0b0..First INV-based ringo is disabled. + * 0b1..First INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) +#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) +/*! E_IV1 - Second Inverter-based ringo control. + * 0b0..Second INV-based ringo is disabled. + * 0b1..Second INV-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) +#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) +/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..First PN-based ringo is disabled. + * 0b1..First PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + +#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) +#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) +/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. + * 0b0..Second PN-based ringo is disabled. + * 0b1..Second PN-based ringo is enabled. + */ +#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + +#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + +#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + +#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ +/*! @{ */ + +#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) +#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) +/*! S - Select short or long ringo (for all ringos types). + * 0b0..Select short ringo (few elements). + * 0b1..Select long ringo (many elements). + */ +#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + +#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) +#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) +/*! FS - Ringo frequency output divider. + * 0b0..High frequency output (frequency lower than 100 MHz). + * 0b1..Low frequency output (frequency lower than 10 MHz). + */ +#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + +#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) +#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) +/*! PD - Ringo module Power control. + * 0b0..The Ringo module is enabled. + * 0b1..The Ringo module is disabled. + */ +#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) +#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) +/*! E_R24 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + +#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) +#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) +/*! E_R35 - . + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) +#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) +/*! E_M2 - Metal 2 (M2) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) +#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) +/*! E_M3 - Metal 3 (M3) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) +#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) +/*! E_M4 - Metal 4 (M4) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + +#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) +#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) +/*! E_M5 - Metal 5 (M5) monitor control. + * 0b0..Ringo is disabled. + * 0b1..Ringo is enabled. + */ +#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + +#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) +#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ +#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ +#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) +/*! @} */ + +/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ +/*! @{ */ + +#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) +#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) +/*! BYPASS - Activate LDO bypass. + * 0b0..Disable bypass mode (for normal operations). + * 0b1..Activate LDO bypass. + */ +#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + +#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) +#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) +/*! HIGHZ - . + * 0b0..Output in High normal state. + * 0b1..Output in High Impedance state. + */ +#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + +#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) +#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) +/*! VOUT - Sets the LDO output level. + * 0b000..0.750 V. + * 0b001..0.775 V. + * 0b010..0.800 V. + * 0b011..0.825 V. + * 0b100..0.850 V. + * 0b101..0.875 V. + * 0b110..0.900 V. + * 0b111..0.925 V. + */ +#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + +#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) +#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ +#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + +#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) +#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ +#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) +/*! @} */ + +/*! @name AUX_BIAS - AUX_BIAS */ +/*! @{ */ + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. + */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) + +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. + */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) + +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. + */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. + */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) +/*! @} */ + +/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. + */ +#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) +/*! @} */ + +/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ +/*! @{ */ + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . + */ +#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ANACTRL_Register_Masks */ + + +/* ANACTRL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x50013000u) + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE_NS (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS } +#else + /** Peripheral ANACTRL base address */ + #define ANACTRL_BASE (0x40013000u) + /** Peripheral ANACTRL base pointer */ + #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE) + /** Array initializer of ANACTRL peripheral base addresses */ + #define ANACTRL_BASE_ADDRS { ANACTRL_BASE } + /** Array initializer of ANACTRL peripheral base pointers */ + #define ANACTRL_BASE_PTRS { ANACTRL } +#endif + +/*! + * @} + */ /* end of group ANACTRL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CASPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer + * @{ + */ + +/** CASPER - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */ + __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */ + __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */ + __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */ + __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */ + __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */ + __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t AREG; /**< A register, offset: 0x20 */ + __IO uint32_t BREG; /**< B register, offset: 0x24 */ + __IO uint32_t CREG; /**< C register, offset: 0x28 */ + __IO uint32_t DREG; /**< D register, offset: 0x2C */ + __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */ + __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */ + __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */ + __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */ + uint8_t RESERVED_1[32]; + __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */ + __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */ + uint8_t RESERVED_2[24]; + __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */ +} CASPER_Type; + +/* ---------------------------------------------------------------------------- + -- CASPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CASPER_Register_Masks CASPER Register Masks + * @{ + */ + +/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ +/*! @{ */ + +#define CASPER_CTRL0_ABBPAIR_MASK (0x1U) +#define CASPER_CTRL0_ABBPAIR_SHIFT (0U) +/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) +#define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ +#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + +#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) +#define CASPER_CTRL0_CDBPAIR_SHIFT (16U) +/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + +#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ +#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) +/*! @} */ + +/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ +/*! @{ */ + +#define CASPER_CTRL1_ITER_MASK (0xFFU) +#define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + */ +#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + +#define CASPER_CTRL1_MODE_MASK (0xFF00U) +#define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + */ +#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + +#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) +#define CASPER_CTRL1_RESBPAIR_SHIFT (16U) +/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally + * this is not the same bank as ABBPAIR (when 4-up supported) + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + +#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) +#define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ +#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + +#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) +#define CASPER_CTRL1_CSKIP_SHIFT (30U) +/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: + * 0b00..No Skip + * 0b01..Skip if Carry is 1 + * 0b10..Skip if Carry is 0 + * 0b11..Set CTRLOFF to CDOFF and Skip + */ +#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK) +/*! @} */ + +/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ +/*! @{ */ + +#define CASPER_LOADER_COUNT_MASK (0xFFU) +#define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ +#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + +#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) +#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) +/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not + * matter which bank is used as this is loaded when not performing an operation. + * 0b0..Bank-pair 0 (1st) + * 0b1..Bank-pair 1 (2nd) + */ +#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + +#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) +#define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. + */ +#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) +/*! @} */ + +/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ +/*! @{ */ + +#define CASPER_STATUS_DONE_MASK (0x1U) +#define CASPER_STATUS_DONE_SHIFT (0U) +/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. + * 0b0..Busy or just cleared + * 0b1..Completed last operation + */ +#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + +#define CASPER_STATUS_CARRY_MASK (0x10U) +#define CASPER_STATUS_CARRY_SHIFT (4U) +/*! CARRY - Last carry value if operation produced a carry bit + * 0b0..Carry was 0 or no carry + * 0b1..Carry was 1 + */ +#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + +#define CASPER_STATUS_BUSY_MASK (0x20U) +#define CASPER_STATUS_BUSY_SHIFT (5U) +/*! BUSY - Indicates if the accelerator is busy performing an operation + * 0b0..Not busy - is idle + * 0b1..Is busy + */ +#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK) +/*! @} */ + +/*! @name INTENSET - Sets interrupts */ +/*! @{ */ + +#define CASPER_INTENSET_DONE_MASK (0x1U) +#define CASPER_INTENSET_DONE_SHIFT (0U) +/*! DONE - Set if the accelerator should interrupt when done. + * 0b0..Do not interrupt when done + * 0b1..Interrupt when done + */ +#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK) +/*! @} */ + +/*! @name INTENCLR - Clears interrupts */ +/*! @{ */ + +#define CASPER_INTENCLR_DONE_MASK (0x1U) +#define CASPER_INTENCLR_DONE_SHIFT (0U) +/*! DONE - Written to clear an interrupt set with INTENSET. + * 0b0..If written 0, ignored + * 0b1..If written 1, do not Interrupt when done + */ +#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ +/*! @{ */ + +#define CASPER_INTSTAT_DONE_MASK (0x1U) +#define CASPER_INTSTAT_DONE_SHIFT (0U) +/*! DONE - If set, interrupt is caused by accelerator being done. + * 0b0..Not caused by accelerator being done + * 0b1..Caused by accelerator being done + */ +#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK) +/*! @} */ + +/*! @name AREG - A register */ +/*! @{ */ + +#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name BREG - B register */ +/*! @{ */ + +#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name CREG - C register */ +/*! @{ */ + +#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name DREG - D register */ +/*! @{ */ + +#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ +#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES0 - Result register 0 */ +/*! @{ */ + +#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES1 - Result register 1 */ +/*! @{ */ + +#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES2 - Result register 2 */ +/*! @{ */ + +#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) +/*! @} */ + +/*! @name RES3 - Result register 3 */ +/*! @{ */ + +#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) +#define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ +#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) +/*! @} */ + +/*! @name MASK - Optional mask register */ +/*! @{ */ + +#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) +/*! @} */ + +/*! @name REMASK - Optional re-mask register */ +/*! @{ */ + +#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) +#define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ +#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) +/*! @} */ + +/*! @name LOCK - Security lock register */ +/*! @{ */ + +#define CASPER_LOCK_LOCK_MASK (0x1U) +#define CASPER_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. + * 0b0..unlock + * 0b1..Lock to current security level + */ +#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + +#define CASPER_LOCK_KEY_MASK (0x1FFF0U) +#define CASPER_LOCK_KEY_SHIFT (4U) +/*! KEY - Must be written as 0x73D to change the register. + * 0b0011100111101..If set during write, will allow lock or unlock + */ +#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CASPER_Register_Masks */ + + +/* CASPER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x500A5000u) + /** Peripheral CASPER base address */ + #define CASPER_BASE_NS (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Peripheral CASPER base pointer */ + #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS_NS { CASPER_NS } +#else + /** Peripheral CASPER base address */ + #define CASPER_BASE (0x400A5000u) + /** Peripheral CASPER base pointer */ + #define CASPER ((CASPER_Type *)CASPER_BASE) + /** Array initializer of CASPER peripheral base addresses */ + #define CASPER_BASE_ADDRS { CASPER_BASE } + /** Array initializer of CASPER peripheral base pointers */ + #define CASPER_BASE_PTRS { CASPER } +#endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } + +/*! + * @} + */ /* end of group CASPER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ + +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + */ +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + */ +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + */ +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + */ +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + */ +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ + +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ + +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + */ +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ + +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x50095000u) + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE_NS (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS } +#else + /** Peripheral CRC_ENGINE base address */ + #define CRC_ENGINE_BASE (0x40095000u) + /** Peripheral CRC_ENGINE base pointer */ + #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC_ENGINE } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. + */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. + */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. + */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. + */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. + */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. + */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. + */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. + */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of + * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. + */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. + */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. + */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. + */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. + */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment + * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC + * is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which + * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input + * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be + * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the + * same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the + * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to + * 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow Register */ +/*! @{ */ + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. + */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x50008000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x50009000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x50028000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x50029000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x5002A000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x40008000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x40009000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x40028000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x40029000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x4002A000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } +/* Backward compatibility for bitfield SHADOW */ +#define CTIMER_MSR_MATCH_SHADOW_MASK CTIMER_MSR_SHADOW_MASK +#define CTIMER_MSR_MATCH_SHADOW_SHIFT CTIMER_MSR_SHADOW_SHIFT +#define CTIMER_MSR_MATCH_SHADOW CTIMER_MSR_SHADOW + + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DBGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification register, offset: 0xFC */ +} DBGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DBGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - CRC mode register */ +/*! @{ */ + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation + */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) + */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) + */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - CRC seed register */ +/*! @{ */ + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value + */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) +/*! @} */ + +/*! @name RETURN - Return value from ROM. */ +/*! @{ */ + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. + */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification register */ +/*! @{ */ + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. + */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DBGMAILBOX_Register_Masks */ + + +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } +#else + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } +#endif + +/*! + * @} + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[23]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ + +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when + * disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ + +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ + +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ + +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory + * move, any peripheral DMA request associated with that channel can be disabled to prevent any + * interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = + * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the + * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger + * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the + * current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a + * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a + * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is + * complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is + * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this + * could be used to read several sequential registers from a peripheral for each DMA burst, + * reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is + * 'wrapped', meaning that the destination address range for each burst will be the same. As an + * example, this could be used to write several sequential registers to a peripheral for each DMA + * burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (23U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the + * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is + * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ + +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor + * is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current + * descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by + * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not + * be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between + * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By + * convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is + * the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when + * the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. + * This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (23U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50082000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A7000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40082000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A7000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/** FLASH - Register Layout Typedef */ +typedef struct { + __O uint32_t CMD; /**< command register, offset: 0x0 */ + __O uint32_t EVENT; /**< event register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ + __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ + uint8_t RESERVED_1[104]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; + __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ + __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ + __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ + __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ + __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */ + __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */ + uint8_t RESERVED_3[12]; + __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */ +} FLASH_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_Register_Masks FLASH Register Masks + * @{ + */ + +/*! @name CMD - command register */ +/*! @{ */ + +#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) +#define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ +#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) +/*! @} */ + +/*! @name EVENT - event register */ +/*! @{ */ + +#define FLASH_EVENT_RST_MASK (0x1U) +#define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ +#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + +#define FLASH_EVENT_WAKEUP_MASK (0x2U) +#define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ +#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + +#define FLASH_EVENT_ABORT_MASK (0x4U) +#define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ +#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) +/*! @} */ + +/*! @name STARTA - start (or only) address for next flash command */ +/*! @{ */ + +#define FLASH_STARTA_STARTA_MASK (0x3FFFFU) +#define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ +#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) +/*! @} */ + +/*! @name STOPA - end address for next flash command, if command operates on address ranges */ +/*! @{ */ + +#define FLASH_STOPA_STOPA_MASK (0x3FFFFU) +#define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ +#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) +/*! @} */ + +/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ +/*! @{ */ + +#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) +#define FLASH_DATAW_DATAW_SHIFT (0U) +#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) +/*! @} */ + +/* The count of FLASH_DATAW */ +#define FLASH_DATAW_COUNT (4U) + +/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + +#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + +#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + +#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ +#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_ENABLE - Set interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + +#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + +#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + +#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ +#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ +#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + +#define FLASH_INT_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ +#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + +#define FLASH_INT_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ +#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + +#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ +#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_ENABLE - Interrupt enable bits */ +/*! @{ */ + +#define FLASH_INT_ENABLE_FAIL_MASK (0x1U) +#define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + +#define FLASH_INT_ENABLE_ERR_MASK (0x2U) +#define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + +#define FLASH_INT_ENABLE_DONE_MASK (0x4U) +#define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + +#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) +#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ +#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_CLR_STATUS - Clear interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + +#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + +#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + +#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ +#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name INT_SET_STATUS - Set interrupt status bits */ +/*! @{ */ + +#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) +#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + +#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) +#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + +#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) +#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + +#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) +#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ +#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) +/*! @} */ + +/*! @name MODULE_ID - Controller+Memory module identification */ +/*! @{ */ + +#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) +#define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + +#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ +#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + +#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ +#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + +#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) +#define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ + + +/* FLASH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x50034000u) + /** Peripheral FLASH base address */ + #define FLASH_BASE_NS (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Peripheral FLASH base pointer */ + #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS_NS { FLASH_NS } +#else + /** Peripheral FLASH base address */ + #define FLASH_BASE (0x40034000u) + /** Peripheral FLASH base pointer */ + #define FLASH ((FLASH_Type *)FLASH_BASE) + /** Array initializer of FLASH peripheral base addresses */ + #define FLASH_BASE_ADDRS { FLASH_BASE } + /** Array initializer of FLASH peripheral base pointers */ + #define FLASH_BASE_PTRS { FLASH } +#endif + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CFPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t HEADER; /**< , offset: 0x0 */ + __IO uint32_t VERSION; /**< , offset: 0x4 */ + __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ + __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ + __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ + __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ + __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ + __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ + __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ + union { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ + } PRINCE_REGION0_IV_CODE_CORE; + }; + union { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ + struct { /* offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ + } PRINCE_REGION1_IV_CODE_CORE; + }; + union { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ + } PRINCE_REGION2_IV_CODE_CORE; + }; + uint8_t RESERVED_1[40]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CFPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CFPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks + * @{ + */ + +/*! @name HEADER - */ +/*! @{ */ + +#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) +#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name VERSION - */ +/*! @{ */ + +#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) +#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) +/*! @} */ + +/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ +/*! @{ */ + +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) +#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) +/*! @} */ + +/*! @name ROTKH_REVOKE - */ +/*! @{ */ + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. + */ +#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ +/*! @{ */ + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ +/*! @{ */ + +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) +/*! @} */ + +/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ +/*! @{ */ + +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) +#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_IV_CODE - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ +#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_IV_HEADER0 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_HEADER1 - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) +#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_IV_BODY - */ +/*! @{ */ + +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */ +#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_CUSTOMER_DEFINED */ +#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CFPA_SHA256_DIGEST */ +#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CFPA_Register_Masks */ + + +/* FLASH_CFPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x1009E000u) + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE_NS (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x1009E200u) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE_NS (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS } +#else + /** Peripheral FLASH_CFPA0 base address */ + #define FLASH_CFPA0_BASE (0x9E000u) + /** Peripheral FLASH_CFPA0 base pointer */ + #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE) + /** Peripheral FLASH_CFPA1 base address */ + #define FLASH_CFPA1_BASE (0x9E200u) + /** Peripheral FLASH_CFPA1 base pointer */ + #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE) + /** Peripheral FLASH_CFPA_SCRATCH base address */ + #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u) + /** Peripheral FLASH_CFPA_SCRATCH base pointer */ + #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE) + /** Array initializer of FLASH_CFPA peripheral base addresses */ + #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE } + /** Array initializer of FLASH_CFPA peripheral base pointers */ + #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH } +#endif + +/*! + * @} + */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer + * @{ + */ + +/** FLASH_CMPA - Register Layout Typedef */ +typedef struct { + __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ + __IO uint32_t USB_ID; /**< , offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ + __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ + __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ + __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + uint8_t RESERVED_1[144]; + __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ +} FLASH_CMPA_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_CMPA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks + * @{ + */ + +/*! @name BOOT_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) +/*! DEFAULT_ISP_MODE - Default ISP mode: + * 0b000..Auto ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP + * 0b111..Disable ISP fall through + */ +#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) +/*! BOOT_SPEED - Core clock: + * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE + * 0b01..96MHz FRO + * 0b10..48MHz FRO + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ +#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) +/*! @} */ + +/*! @name SPI_FLASH_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. + */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) +/*! @} */ + +/*! @name USB_ID - */ +/*! @{ */ + +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) +#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) +#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) +/*! @} */ + +/*! @name SDIO_CFG - */ +/*! @{ */ + +#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) +#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) +/*! @} */ + +/*! @name CC_SOCU_PIN - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable + * 0b0..Use DAP to enable + * 0b1..Fixed state + */ +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name CC_SOCU_DFLT - */ +/*! @{ */ + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) +/*! NIDEN - Non Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +/*! DBGEN - Non Secure debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +/*! SPNIDEN - Secure non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +/*! SPIDEN - Secure invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +/*! TAPEN - JTAG TAP fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +/*! ISP_CMD_EN - ISP Boot Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +/*! FA_CMD_EN - FA Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +/*! ME_CMD_EN - Flash Mass Erase Command fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state + * 0b0..Disable + * 0b1..Enable + */ +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +/*! @} */ + +/*! @name VENDOR_USAGE - */ +/*! @{ */ + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) +/*! @} */ + +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ +/*! @{ */ + +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) +/*! @} */ + +/*! @name PRINCE_BASE_ADDR - */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ +#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) +/*! @} */ + +/*! @name PRINCE_SR_0 - Region 0, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_1 - Region 1, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_SR_2 - Region 2, sub-region enable */ +/*! @{ */ + +#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) +#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) +/*! @} */ + +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + +#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) +#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_ROTKH */ +#define FLASH_CMPA_ROTKH_COUNT (8U) + +/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ +/*! @{ */ + +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) +#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_CUSTOMER_DEFINED */ +#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) + +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @{ */ + +#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) +#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_CMPA_SHA256_DIGEST */ +#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group FLASH_CMPA_Register_Masks */ + + +/* FLASH_CMPA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x1009E400u) + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE_NS (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS } +#else + /** Peripheral FLASH_CMPA base address */ + #define FLASH_CMPA_BASE (0x9E400u) + /** Peripheral FLASH_CMPA base pointer */ + #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE) + /** Array initializer of FLASH_CMPA peripheral base addresses */ + #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE } + /** Array initializer of FLASH_CMPA peripheral base pointers */ + #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA } +#endif + +/*! + * @} + */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer + * @{ + */ + +/** FLASH_KEY_STORE - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */ + __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */ + } KEY_STORE_HEADER; + __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */ + union { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */ + struct { /* offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */ + __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */ + __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */ + } SBKEY_KEY_CODE_CORE; + }; + union { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */ + struct { /* offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */ + __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */ + __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */ + } USER_KEK_KEY_CODE_CORE; + }; + union { /* offset: 0x520 */ + __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */ + struct { /* offset: 0x520 */ + __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */ + __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */ + __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */ + } UDS_KEY_CODE_CORE; + }; + union { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */ + struct { /* offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */ + __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */ + __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */ + } PRINCE_REGION0_KEY_CODE_CORE; + }; + union { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */ + struct { /* offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */ + __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */ + __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */ + } PRINCE_REGION1_KEY_CODE_CORE; + }; + union { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */ + struct { /* offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */ + __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */ + __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */ + } PRINCE_REGION2_KEY_CODE_CORE; + }; +} FLASH_KEY_STORE_Type; + +/* ---------------------------------------------------------------------------- + -- FLASH_KEY_STORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks + * @{ + */ + +/*! @name HEADER - Valid Key Sore Header : 0x95959595 */ +/*! @{ */ + +#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) +/*! @} */ + +/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ +/*! @{ */ + +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) +/*! @} */ + +/*! @name ACTIVATION_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */ +#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U) + +/*! @name SBKEY_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */ +#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U) + +/*! @name SBKEY_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name SBKEY_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name SBKEY_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_SBKEY_BODY */ +#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U) + +/*! @name USER_KEK_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */ +#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U) + +/*! @name USER_KEK_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name USER_KEK_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name USER_KEK_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_USER_KEK_BODY */ +#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U) + +/*! @name UDS_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */ +#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U) + +/*! @name UDS_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name UDS_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name UDS_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_UDS_BODY */ +#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U) + +/*! @name PRINCE_REGION0_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION0_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION0_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U) + +/*! @name PRINCE_REGION1_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION1_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION1_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U) + +/*! @name PRINCE_REGION2_KEY_CODE - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */ +#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U) + +/*! @name PRINCE_REGION2_HEADER0 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_HEADER1 - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) +/*! @} */ + +/*! @name PRINCE_REGION2_BODY - . */ +/*! @{ */ + +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) +/*! @} */ + +/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */ +#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U) + + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Register_Masks */ + + +/* FLASH_KEY_STORE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x1009E600u) + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE_NS (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS } +#else + /** Peripheral FLASH_KEY_STORE base address */ + #define FLASH_KEY_STORE_BASE (0x9E600u) + /** Peripheral FLASH_KEY_STORE base pointer */ + #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE) + /** Array initializer of FLASH_KEY_STORE peripheral base addresses */ + #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE } + /** Array initializer of FLASH_KEY_STORE peripheral base pointers */ + #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE } +#endif + +/*! + * @} + */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ + +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. + */ +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). + */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x50086000u) + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE_NS (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x50087000u) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE_NS (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x50088000u) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE_NS (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x50089000u) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE_NS (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x5008A000u) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE_NS (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x50096000u) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE_NS (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x50097000u) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE_NS (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x50098000u) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE_NS (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x5009F000u) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE_NS (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS } +#else + /** Peripheral FLEXCOMM0 base address */ + #define FLEXCOMM0_BASE (0x40086000u) + /** Peripheral FLEXCOMM0 base pointer */ + #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) + /** Peripheral FLEXCOMM1 base address */ + #define FLEXCOMM1_BASE (0x40087000u) + /** Peripheral FLEXCOMM1 base pointer */ + #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) + /** Peripheral FLEXCOMM2 base address */ + #define FLEXCOMM2_BASE (0x40088000u) + /** Peripheral FLEXCOMM2 base pointer */ + #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) + /** Peripheral FLEXCOMM3 base address */ + #define FLEXCOMM3_BASE (0x40089000u) + /** Peripheral FLEXCOMM3 base pointer */ + #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) + /** Peripheral FLEXCOMM4 base address */ + #define FLEXCOMM4_BASE (0x4008A000u) + /** Peripheral FLEXCOMM4 base pointer */ + #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) + /** Peripheral FLEXCOMM5 base address */ + #define FLEXCOMM5_BASE (0x40096000u) + /** Peripheral FLEXCOMM5 base pointer */ + #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) + /** Peripheral FLEXCOMM6 base address */ + #define FLEXCOMM6_BASE (0x40097000u) + /** Peripheral FLEXCOMM6 base pointer */ + #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) + /** Peripheral FLEXCOMM7 base address */ + #define FLEXCOMM7_BASE (0x40098000u) + /** Peripheral FLEXCOMM7 base pointer */ + #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) + /** Peripheral FLEXCOMM8 base address */ + #define FLEXCOMM8_BASE (0x4009F000u) + /** Peripheral FLEXCOMM8 base pointer */ + #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) + /** Array initializer of FLEXCOMM peripheral base addresses */ + #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE } + /** Array initializer of FLEXCOMM peripheral base pointers */ + #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 } +#endif +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ + +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ + +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ + +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x50002000u) + /** Peripheral GINT0 base address */ + #define GINT0_BASE_NS (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT0 base pointer */ + #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x50003000u) + /** Peripheral GINT1 base address */ + #define GINT1_BASE_NS (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Peripheral GINT1 base pointer */ + #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS } +#else + /** Peripheral GINT0 base address */ + #define GINT0_BASE (0x40002000u) + /** Peripheral GINT0 base pointer */ + #define GINT0 ((GINT_Type *)GINT0_BASE) + /** Peripheral GINT1 base address */ + #define GINT1_BASE (0x40003000u) + /** Peripheral GINT1 base pointer */ + #define GINT1 ((GINT_Type *)GINT1_BASE) + /** Array initializer of GINT peripheral base addresses */ + #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } + /** Array initializer of GINT peripheral base pointers */ + #define GINT_BASE_PTRS { GINT0, GINT1 } +#endif +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers for all port GPIO pins */ +/*! @{ */ + +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register for all port GPIO pins */ +/*! @{ */ + +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port. Read: output bits for port */ +/*! @{ */ + +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port for all port GPIO pins */ +/*! @{ */ + +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x5008C000u) + /** Peripheral GPIO base address */ + #define GPIO_BASE_NS (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral GPIO base pointer */ + #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x500A8000u) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE_NS (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS } +#else + /** Peripheral GPIO base address */ + #define GPIO_BASE (0x4008C000u) + /** Peripheral GPIO base pointer */ + #define GPIO ((GPIO_Type *)GPIO_BASE) + /** Peripheral SECGPIO base address */ + #define SECGPIO_BASE (0x400A8000u) + /** Peripheral SECGPIO base pointer */ + #define SECGPIO ((GPIO_Type *)SECGPIO_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO, SECGPIO } +#endif + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer + * @{ + */ + +/** HASHCRYPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ + __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ + __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ + __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ + __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ +} HASHCRYPT_Type; + +/* ---------------------------------------------------------------------------- + -- HASHCRYPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks + * @{ + */ + +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ +/*! @{ */ + +#define HASHCRYPT_CTRL_MODE_MASK (0x7U) +#define HASHCRYPT_CTRL_MODE_SHIFT (0U) +/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if + * specific modes beyond SHA1 and SHA2-256 are available. + * 0b000..Disabled + * 0b001..SHA1 is enabled + * 0b010..SHA2-256 is enabled + * 0b100..AES if available (see also CRYPTCFG register for more controls) + * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) + */ +#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + +#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) +#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) +/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING + * Status bit will clear for a cycle during the initialization from New=1. + * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. + */ +#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + +#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) +#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) +/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words + * and then will process the Hash. If Cryptographic, it will load as many words as needed, + * including key if not already loaded. It will then request again. Normal model is that the DMA + * interrupts the processor when its length expires. Note that if the processor will write the key and + * optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be + * expected to load those for the 1st block (when needed). + * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used. + * 0b1..DMA will push in the data. + */ +#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + +#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) +#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) +/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the + * DMA has to know to switch direction and the locations. This can be used for crypto uses. + * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. + */ +#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + +#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) +#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ +#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) +/*! @} */ + +/*! @name STATUS - Indicates status of Hash peripheral. */ +/*! @{ */ + +#define HASHCRYPT_STATUS_WAITING_MASK (0x1U) +#define HASHCRYPT_STATUS_WAITING_SHIFT (0U) +/*! WAITING - If 1, the block is waiting for more data to process. + * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set + * if IsLast is set nor will it set until at least 1 word is read of the output. + * 0b1..Waiting for data to be written in (16 words) + */ +#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. + * 0b0..No Digest is ready + * 0b1..Digest is ready. Application may read it or may write more data + */ +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + +#define HASHCRYPT_STATUS_ERROR_MASK (0x4U) +#define HASHCRYPT_STATUS_ERROR_SHIFT (2U) +/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA + * was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT + * field will indicate which block it was on. + * 0b0..No error. + * 0b1..An error occurred since last cleared (written 1 to clear). + */ +#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + +#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) +#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) +/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) + * 0b0..No Key is needed and writes will not be treated as Key + * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + +#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) +#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) +/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) + * 0b0..No IV/Nonce is needed, either because written already or because not needed. + * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. + */ +#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + +#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) +#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from + * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, + * it has to compute the full ICB, quicker when not 0. + */ +#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) +/*! @} */ + +/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ +/*! @{ */ + +#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) +/*! WAITING - Indicates if should interrupt when waiting for data input. + * 0b0..Will not interrupt when waiting. + * 0b1..Will interrupt when waiting + */ +#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + +#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) +/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). + * 0b0..Will not interrupt when Digest is ready + * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). + */ +#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + +#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) +/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) + * 0b0..Will not interrupt on Error. + * 0b1..Will interrupt on Error (until cleared). + */ +#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK) +/*! @} */ + +/*! @name INTENCLR - Write 1 to clear interrupts. */ +/*! @{ */ + +#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) +#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + +#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) +#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + +#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) +#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. + */ +#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) +/*! @} */ + +/*! @name MEMCTRL - Setup Master to access memory (if available) */ +/*! @{ */ + +#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) +#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) +/*! MASTER - Enables mastering. + * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. + * 0b1..Mastering is enabled and DMA and INDATA should not be used. + */ +#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + +#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ +#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) +/*! @} */ + +/*! @name MEMADDR - Address to start memory access from (if available). */ +/*! @{ */ + +#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ +#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) +/*! @} */ + +/*! @name INDATA - Input of 16 words at a time to load up buffer. */ +/*! @{ */ + +#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) +/*! @} */ + +/*! @name ALIAS - */ +/*! @{ */ + +#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ +#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) +/*! @} */ + +/* The count of HASHCRYPT_ALIAS */ +#define HASHCRYPT_ALIAS_COUNT (7U) + +/*! @name DIGEST0 - */ +/*! @{ */ + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) +/*! @} */ + +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) + +/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ +/*! @{ */ + +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) +#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + +#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) +#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). + */ +#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + +#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) +#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ +#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + +#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) +#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) +/*! AESMODE - AES Cipher mode to use if plain AES + * 0b00..ECB - used as is + * 0b01..CBC mode (see details on IV/nonce) + * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS. + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) +#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) +/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB + * 0b0..Encrypt + * 0b1..Decrypt + */ +#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + +#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) +#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) +/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are + * used, only the highest level is permitted to select this. + * 0b0..User key provided in normal way + * 0b1..Secret key provided in hidden way by HW + */ +#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) +#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) +/*! AESKEYSZ - Sets the AES key size + * 0b00..128 bit key + * 0b01..192 bit key + * 0b10..256 bit key + * 0b11..reserved + */ +#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) +#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ +#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + +#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) +#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + */ +#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) +#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) +/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the + * counter is assumed to occupy the low order bits of the IV. + * 0b00..32 bits of the IV/ctr are used (from 127:96) + * 0b01..64 bits of the IV/ctr are used (from 127:64) + * 0b10..96 bits of the IV/ctr are used (from 127:32) + * 0b11..All 128 bits of the IV/ctr are used + */ +#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) + +#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) +#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) +/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new + * IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st. + * 0b00..8 blocks + * 0b01..16 blocks + * 0b10..32 blocks + * 0b11..64 blocks + */ +#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK) +/*! @} */ + +/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ +/*! @{ */ + +#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) +#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + */ +#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + +#define HASHCRYPT_CONFIG_DMA_MASK (0x2U) +#define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected + */ +#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + +#define HASHCRYPT_CONFIG_AHB_MASK (0x8U) +#define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled + */ +#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) + +#define HASHCRYPT_CONFIG_AES_MASK (0x40U) +#define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included + */ +#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + +#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) +#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included + */ +#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + +#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) +#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available + */ +#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) + +#define HASHCRYPT_CONFIG_ICB_MASK (0x800U) +#define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +/*! ICB - 1 if ICB over AES included + */ +#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) +/*! @} */ + +/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ +/*! @{ */ + +#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) +#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) +/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. + * If locked already, may only write if at same or higher security level as lock. Reads as: 0 if + * unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the + * only readable registers if locked and current state is lower than lock level. + * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests. + * 0b01..Locks to the current security level. AHB Master will issue requests at this level. + */ +#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + +#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) +#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + */ +#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name MASK - */ +/*! @{ */ + +#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) +#define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. + */ +#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) +/*! @} */ + +/* The count of HASHCRYPT_MASK */ +#define HASHCRYPT_MASK_COUNT (4U) + + +/*! + * @} + */ /* end of group HASHCRYPT_Register_Masks */ + + +/* HASHCRYPT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x500A4000u) + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE_NS (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS } +#else + /** Peripheral HASHCRYPT base address */ + #define HASHCRYPT_BASE (0x400A4000u) + /** Peripheral HASHCRYPT base pointer */ + #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE) + /** Array initializer of HASHCRYPT peripheral base addresses */ + #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE } + /** Array initializer of HASHCRYPT peripheral base pointers */ + #define HASHCRYPT_BASE_PTRS { HASHCRYPT } +#endif + +/*! + * @} + */ /* end of group HASHCRYPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ + +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not + * changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not + * changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not + * changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause + * interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able + * to read data provided by the Monitor function before it is overwritten. This mode may be used when + * non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can + * read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive + * and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies + * to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the + * extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, + * such as changing the drive strength or filtering, must be made by software via the IOCON register associated + * with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support + * High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more + * information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on + * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what + * type of software service if any the master expects. This flag will cause an interrupt when set + * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling + * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle + * state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the + * idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the + * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field + * indicates a specific required service for the Master function. All other values are reserved. See + * Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master + * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, + * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to + * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is + * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an + * idle state, no action is required. A request for a Start could be made, or software could attempt to insure + * that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue + * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if + * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the + * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is + * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time + * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section + * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are + * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must + * also be detected automatically, since the address must be acknowledged before the clock can be + * stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for + * the Slave function. All other values are reserved. See Table 401 for state values and actions. + * note that the occurrence of some states and how they are handled are affected by DMA mode and + * Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. + * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave + * operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or + * Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been + * selected by receiving an address that matches one of the slave addresses defined by any enabled + * slave address registers, and provides an identification of the address that was matched. It is + * possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave + * function to acknowledge the address, or when the address has been automatically acknowledged. + * It is cleared when another address cycle presents an address that does not match an enabled + * address on the Slave function, when slave software decides to NACK a matched address, when + * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of + * Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via + * INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently + * selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag + * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not + * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to + * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred + * more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change + * from active to inactive. This can be used by software to decide when to process data + * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the + * INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been + * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock + * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus + * is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the + * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ + +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ + +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. + */ +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. + */ +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. + */ +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. + */ +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. + */ +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. + */ +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. + */ +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. + */ +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. + */ +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. + */ +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ + +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ + +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ + +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. + */ +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. + */ +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. + */ +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. + */ +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. + */ +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. + */ +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. + */ +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + */ +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. + */ +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. + */ +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. + */ +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ + +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing + * transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave + * if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type + * operations such as Start, address, Stop, and address match must always be done with software, + * typically via an interrupt. Address acknowledgement must also be done by software except when + * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by + * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA + * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is + * read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating + * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ + +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this + * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This + * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters + * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this + * master on SCL. Other masters in a multi-master system could shorten this time. This + * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters + * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ + +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag + * in the STAT register. This must be done after writing transmit data, reading received data, or any other + * housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE + * should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches + * SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA + * to allow processing of the data without intervention. If this bit is clear and a header + * matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or + * interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching + * address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, + * allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does + * not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK + * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write + * request on the next header with an address matching SLVADR0. Since DMA needs to be configured to + * match the transfer direction, the direction needs to be specified. This bit allows a direction to + * be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ + +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ + +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. + */ +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows + * software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches + * SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ + +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ + +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + */ +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x50086000u) + /** Peripheral I2C0 base address */ + #define I2C0_BASE_NS (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C0 base pointer */ + #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x50087000u) + /** Peripheral I2C1 base address */ + #define I2C1_BASE_NS (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C1 base pointer */ + #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x50088000u) + /** Peripheral I2C2 base address */ + #define I2C2_BASE_NS (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C2 base pointer */ + #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x50089000u) + /** Peripheral I2C3 base address */ + #define I2C3_BASE_NS (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C3 base pointer */ + #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x5008A000u) + /** Peripheral I2C4 base address */ + #define I2C4_BASE_NS (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C4 base pointer */ + #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x50096000u) + /** Peripheral I2C5 base address */ + #define I2C5_BASE_NS (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C5 base pointer */ + #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x50097000u) + /** Peripheral I2C6 base address */ + #define I2C6_BASE_NS (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C6 base pointer */ + #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x50098000u) + /** Peripheral I2C7 base address */ + #define I2C7_BASE_NS (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Peripheral I2C7 base pointer */ + #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS } +#else + /** Peripheral I2C0 base address */ + #define I2C0_BASE (0x40086000u) + /** Peripheral I2C0 base pointer */ + #define I2C0 ((I2C_Type *)I2C0_BASE) + /** Peripheral I2C1 base address */ + #define I2C1_BASE (0x40087000u) + /** Peripheral I2C1 base pointer */ + #define I2C1 ((I2C_Type *)I2C1_BASE) + /** Peripheral I2C2 base address */ + #define I2C2_BASE (0x40088000u) + /** Peripheral I2C2 base pointer */ + #define I2C2 ((I2C_Type *)I2C2_BASE) + /** Peripheral I2C3 base address */ + #define I2C3_BASE (0x40089000u) + /** Peripheral I2C3 base pointer */ + #define I2C3 ((I2C_Type *)I2C3_BASE) + /** Peripheral I2C4 base address */ + #define I2C4_BASE (0x4008A000u) + /** Peripheral I2C4 base pointer */ + #define I2C4 ((I2C_Type *)I2C4_BASE) + /** Peripheral I2C5 base address */ + #define I2C5_BASE (0x40096000u) + /** Peripheral I2C5 base pointer */ + #define I2C5 ((I2C_Type *)I2C5_BASE) + /** Peripheral I2C6 base address */ + #define I2C6_BASE (0x40097000u) + /** Peripheral I2C6 base pointer */ + #define I2C6 ((I2C_Type *)I2C6_BASE) + /** Peripheral I2C7 base address */ + #define I2C7_BASE (0x40098000u) + /** Peripheral I2C7 base pointer */ + #define I2C7 ((I2C_Type *)I2C7_BASE) + /** Array initializer of I2C peripheral base addresses */ + #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } + /** Array initializer of I2C peripheral base pointers */ + #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +#endif +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags + * are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer + * and the FIFO. This could be done in order to change streams, or while restarting after a data + * underflow or overflow. When paused, FIFO operations can be done without corrupting data that is + * in the process of being sent or received. Once a data pause has been requested, the interface + * may need to complete sending data that was in progress before interrupting the flow of data. + * Software must check that the pause is actually in effect before taking action. This is done by + * monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer + * will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field + * whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this + * Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs + * in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of + * SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all + * supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece + * of left channel data occurring during the first phase, and one pieces of right channel data occurring + * during the second phase. In this mode, the data region begins one clock after the leading WS edge for the + * frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If + * FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left + * and right channel data as it is transferred to or from the FIFO. This bit is not used if the + * data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 + * of this register) = 1, the one channel to be used is the nominally the left channel. POSITION + * can still place that data in the frame where right channel data is normally located. if all + * enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO + * bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting + * from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data + * in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting + * from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would + * correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit + * applies only to the first I2S channel pair. Other channel pairs may select this mode + * independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this + * pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a + * clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel + * of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side + * (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data + * for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) + +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ + +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is + * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ + +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as + * a slave. An error indicates that the incoming WS signal did not transition as expected due to + * a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to + * be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data + * being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for + * an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ + +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX + * FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is + * cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 + * bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. + */ +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ + +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. + */ +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x50086000u) + /** Peripheral I2S0 base address */ + #define I2S0_BASE_NS (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S0 base pointer */ + #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x50087000u) + /** Peripheral I2S1 base address */ + #define I2S1_BASE_NS (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S1 base pointer */ + #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x50088000u) + /** Peripheral I2S2 base address */ + #define I2S2_BASE_NS (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S2 base pointer */ + #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x50089000u) + /** Peripheral I2S3 base address */ + #define I2S3_BASE_NS (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S3 base pointer */ + #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x5008A000u) + /** Peripheral I2S4 base address */ + #define I2S4_BASE_NS (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S4 base pointer */ + #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x50096000u) + /** Peripheral I2S5 base address */ + #define I2S5_BASE_NS (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S5 base pointer */ + #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x50097000u) + /** Peripheral I2S6 base address */ + #define I2S6_BASE_NS (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S6 base pointer */ + #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x50098000u) + /** Peripheral I2S7 base address */ + #define I2S7_BASE_NS (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Peripheral I2S7 base pointer */ + #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS } +#else + /** Peripheral I2S0 base address */ + #define I2S0_BASE (0x40086000u) + /** Peripheral I2S0 base pointer */ + #define I2S0 ((I2S_Type *)I2S0_BASE) + /** Peripheral I2S1 base address */ + #define I2S1_BASE (0x40087000u) + /** Peripheral I2S1 base pointer */ + #define I2S1 ((I2S_Type *)I2S1_BASE) + /** Peripheral I2S2 base address */ + #define I2S2_BASE (0x40088000u) + /** Peripheral I2S2 base pointer */ + #define I2S2 ((I2S_Type *)I2S2_BASE) + /** Peripheral I2S3 base address */ + #define I2S3_BASE (0x40089000u) + /** Peripheral I2S3 base pointer */ + #define I2S3 ((I2S_Type *)I2S3_BASE) + /** Peripheral I2S4 base address */ + #define I2S4_BASE (0x4008A000u) + /** Peripheral I2S4 base pointer */ + #define I2S4 ((I2S_Type *)I2S4_BASE) + /** Peripheral I2S5 base address */ + #define I2S5_BASE (0x40096000u) + /** Peripheral I2S5 base pointer */ + #define I2S5 ((I2S_Type *)I2S5_BASE) + /** Peripheral I2S6 base address */ + #define I2S6_BASE (0x40097000u) + /** Peripheral I2S6 base pointer */ + #define I2S6 ((I2S_Type *)I2S6_BASE) + /** Peripheral I2S7 base address */ + #define I2S7_BASE (0x40098000u) + /** Peripheral I2S7 base pointer */ + #define I2S7 ((I2S_Type *)I2S7_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_3[80]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_4[36]; + __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ + uint8_t RESERVED_6[24]; + __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */ + uint8_t RESERVED_7[16]; + __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_11[1264]; + __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */ + uint8_t RESERVED_12[4]; + __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */ + uint8_t RESERVED_13[4]; + __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */ + uint8_t RESERVED_14[12]; + __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */ + uint8_t RESERVED_15[4]; + __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */ + uint8_t RESERVED_16[4]; + __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */ + uint8_t RESERVED_18[4]; + __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */ + uint8_t RESERVED_19[4]; + __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */ + uint8_t RESERVED_20[12]; + __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */ + uint8_t RESERVED_21[4]; + __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */ + uint8_t RESERVED_22[4]; + __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Input mux register for SCT0 input */ +/*! @{ */ + +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +/*! INP_N - Input number to SCT0 inputs 0 to 6.. + * 0b00000..SCT_GPI0 function selected from IOCON register + * 0b00001..SCT_GPI1 function selected from IOCON register + * 0b00010..SCT_GPI2 function selected from IOCON register + * 0b00011..SCT_GPI3 function selected from IOCON register + * 0b00100..SCT_GPI4 function selected from IOCON register + * 0b00101..SCT_GPI5 function selected from IOCON register + * 0b00110..SCT_GPI6 function selected from IOCON register + * 0b00111..SCT_GPI7 function selected from IOCON register + * 0b01000..T0_OUT0 ctimer 0 match[0] output + * 0b01001..T1_OUT0 ctimer 1 match[0] output + * 0b01010..T2_OUT0 ctimer 2 match[0] output + * 0b01011..T3_OUT0 ctimer 3 match[0] output + * 0b01100..T4_OUT0 ctimer 4 match[0] output + * 0b01101..ADC_IRQ interrupt request from ADC + * 0b01110..GPIOINT_BMATCH + * 0b01111..USB0_FRAME_TOGGLE + * 0b10000..USB1_FRAME_TOGGLE + * 0b10001..COMP_OUTPUT output from analog comparator + * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing + * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing + * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1 + * 0b10111..DEBUG_HALTED from cpu0 or cpu1 + * 0b11000-0b11111..None + */ +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) +/*! @} */ + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER0CAPTSEL */ +#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U) + +/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER1CAPTSEL */ +#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U) + +/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER2CAPTSEL */ +#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U) + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ + +#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). + * 0b00000..Pin interrupt 0 + * 0b00001..Pin interrupt 1 + * 0b00010..Pin interrupt 2 + * 0b00011..Pin interrupt 3 + * 0b00100..Timer CTIMER0 Match 0 + * 0b00101..Timer CTIMER0 Match 1 + * 0b00110..Timer CTIMER1 Match 0 + * 0b00111..Timer CTIMER1 Match 1 + * 0b01000..Timer CTIMER2 Match 0 + * 0b01001..Timer CTIMER2 Match 1 + * 0b01010..Timer CTIMER3 Match 0 + * 0b01011..Timer CTIMER3 Match 1 + * 0b01100..Timer CTIMER4 Match 0 + * 0b01101..Timer CTIMER4 Match 1 + * 0b01110..COMP_OUTPUT + * 0b01111..DMA0 output trigger mux 0 + * 0b10000..DMA0 output trigger mux 1 + * 0b10001..DMA0 output trigger mux 1 + * 0b10010..DMA0 output trigger mux 3 + * 0b10011..SCT0 DMA request 0 + * 0b10100..SCT0 DMA request 1 + * 0b10101..HASH DMA RX trigger + * 0b10110-0b11111..None + */ +#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_ITRIG_INMUX */ +#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U) + +/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + */ +#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA0_OTRIG_INMUX */ +#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + +/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER3CAPTSEL */ +#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U) + +/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) +/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 + * 0b00000..CT_INP0 function selected from IOCON register + * 0b00001..CT_INP1 function selected from IOCON register + * 0b00010..CT_INP2 function selected from IOCON register + * 0b00011..CT_INP3 function selected from IOCON register + * 0b00100..CT_INP4 function selected from IOCON register + * 0b00101..CT_INP5 function selected from IOCON register + * 0b00110..CT_INP6 function selected from IOCON register + * 0b00111..CT_INP7 function selected from IOCON register + * 0b01000..CT_INP8 function selected from IOCON register + * 0b01001..CT_INP9 function selected from IOCON register + * 0b01010..CT_INP10 function selected from IOCON register + * 0b01011..CT_INP11 function selected from IOCON register + * 0b01100..CT_INP12 function selected from IOCON register + * 0b01101..CT_INP13 function selected from IOCON register + * 0b01110..CT_INP14 function selected from IOCON register + * 0b01111..CT_INP15 function selected from IOCON register + * 0b10000..CT_INP16 function selected from IOCON register + * 0b10001..CT_INP17 function selected from IOCON register + * 0b10010..CT_INP18 function selected from IOCON register + * 0b10011..CT_INP19 function selected from IOCON register + * 0b10100..USB0_FRAME_TOGGLE + * 0b10101..USB1_FRAME_TOGGLE + * 0b10110..COMP_OUTPUT output from analog comparator + * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing + * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing + * 0b11001-0b11111..None + */ +#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK) +/*! @} */ + +/* The count of INPUTMUX_TIMER4CAPTSEL */ +#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U) + +/*! @name PINTSECSEL - Pin interrupt secure select register */ +/*! @{ */ + +#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) +#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ +#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSECSEL */ +#define INPUTMUX_PINTSECSEL_COUNT (2U) + +/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) +/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). + * 0b0000..Pin interrupt 0 + * 0b0001..Pin interrupt 1 + * 0b0010..Pin interrupt 2 + * 0b0011..Pin interrupt 3 + * 0b0100..Timer CTIMER0 Match 0 + * 0b0101..Timer CTIMER0 Match 1 + * 0b0110..Timer CTIMER2 Match 0 + * 0b0111..Timer CTIMER4 Match 0 + * 0b1000..DMA1 output trigger mux 0 + * 0b1001..DMA1 output trigger mux 1 + * 0b1010..DMA1 output trigger mux 2 + * 0b1011..DMA1 output trigger mux 3 + * 0b1100..SCT0 DMA request 0 + * 0b1101..SCT0 DMA request 1 + * 0b1110..HASH DMA RX trigger + * 0b1111..None + */ +#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_ITRIG_INMUX */ +#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U) + +/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ +/*! @{ */ + +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) +#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + */ +#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA1_OTRIG_INMUX */ +#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U) + +/*! @name DMA0_REQ_ENA - Enable DMA0 requests */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ +#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA - Enable DMA1 requests */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ +#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ +#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ +#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ +#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) +/*! @} */ + +/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ +/*! @{ */ + +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ +#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x50006000u) + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS } +#else + /** Peripheral INPUTMUX base address */ + #define INPUTMUX_BASE (0x40006000u) + /** Peripheral INPUTMUX base pointer */ + #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX } +#endif + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ + +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b0000..Alternative connection 0. + * 0b0001..Alternative connection 1. + * 0b0010..Alternative connection 2. + * 0b0011..Alternative connection 3. + * 0b0100..Alternative connection 4. + * 0b0101..Alternative connection 5. + * 0b0110..Alternative connection 6. + * 0b0111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + +#define IOCON_PIO_SLEW_MASK (0x40U) +#define IOCON_PIO_SLEW_SHIFT (6U) +/*! SLEW - Driver slew rate. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +/*! DIGIMODE - Select Digital mode. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + +#define IOCON_PIO_OD_MASK (0x200U) +#define IOCON_PIO_OD_SHIFT (9U) +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + +#define IOCON_PIO_ASW_MASK (0x400U) +#define IOCON_PIO_ASW_SHIFT (10U) +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) + */ +#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + +#define IOCON_PIO_SSEL_MASK (0x800U) +#define IOCON_PIO_SSEL_SHIFT (11U) +/*! SSEL - Supply Selection bit. + * 0b0..3V3 Signaling in I2C Mode. + * 0b1..1V8 Signaling in I2C Mode. + */ +#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + +#define IOCON_PIO_FILTEROFF_MASK (0x1000U) +#define IOCON_PIO_FILTEROFF_SHIFT (12U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. + * 0b1..Filter disabled. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + +#define IOCON_PIO_ECS_MASK (0x2000U) +#define IOCON_PIO_ECS_SHIFT (13U) +/*! ECS - Pull-up current source enable in I2C mode. + * 0b1..Enabled. Pull resistor is conencted. + * 0b0..Disabled. IO is in open drain cell. + */ +#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + +#define IOCON_PIO_EGP_MASK (0x4000U) +#define IOCON_PIO_EGP_SHIFT (14U) +/*! EGP - Switch between GPIO mode and I2C mode. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + +#define IOCON_PIO_I2CFILTER_MASK (0x8000U) +#define IOCON_PIO_I2CFILTER_SHIFT (15U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x50001000u) + /** Peripheral IOCON base address */ + #define IOCON_BASE_NS (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Peripheral IOCON base pointer */ + #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS_NS { IOCON_NS } +#else + /** Peripheral IOCON base address */ + #define IOCON_BASE (0x40001000u) + /** Peripheral IOCON base pointer */ + #define IOCON ((IOCON_Type *)IOCON_BASE) + /** Array initializer of IOCON peripheral base addresses */ + #define IOCON_BASE_ADDRS { IOCON_BASE } + /** Array initializer of IOCON peripheral base pointers */ + #define IOCON_BASE_PTRS { IOCON } +#endif + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer + * @{ + */ + +/** MAILBOX - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */ + __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */ + __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } MBOXIRQ[2]; + uint8_t RESERVED_0[216]; + __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */ +} MAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- MAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks + * @{ + */ + +/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + */ +#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQ */ +#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U) + +/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. + */ +#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQSET */ +#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U) + +/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ +/*! @{ */ + +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. + */ +#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) +/*! @} */ + +/* The count of MAILBOX_MBOXIRQ_IRQCLR */ +#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U) + +/*! @name MUTEX - Mutual exclusion register[1] */ +/*! @{ */ + +#define MAILBOX_MUTEX_EX_MASK (0x1U) +#define MAILBOX_MUTEX_EX_SHIFT (0U) +/*! EX - Cleared when read, set when written. See usage description above. + */ +#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MAILBOX_Register_Masks */ + + +/* MAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x5008B000u) + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE_NS (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS } +#else + /** Peripheral MAILBOX base address */ + #define MAILBOX_BASE (0x4008B000u) + /** Peripheral MAILBOX base pointer */ + #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE) + /** Array initializer of MAILBOX peripheral base addresses */ + #define MAILBOX_BASE_ADDRS { MAILBOX_BASE } + /** Array initializer of MAILBOX peripheral base pointers */ + #define MAILBOX_BASE_PTRS { MAILBOX } +#endif +/** Interrupt vectors for the MAILBOX peripheral type */ +#define MAILBOX_IRQS { MAILBOX_IRQn } + +/*! + * @} + */ /* end of group MAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. + * This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the + * time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If + * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt + * are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG + * register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating + * modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) + */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If + * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global + * interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. + */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x5000D000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x4000D000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note: There is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High Register */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Capture Low Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Capture High Register */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Match Low Register */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Match High Register */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x5002D000u) + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE_NS (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS } +#else + /** Peripheral OSTIMER base address */ + #define OSTIMER_BASE (0x4002D000u) + /** Peripheral OSTIMER base pointer */ + #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last + * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the + * PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input + * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only + * cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or + * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit + * is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT base address */ + #define PINT_BASE (0x50004000u) + /** Peripheral PINT base address */ + #define PINT_BASE_NS (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral PINT base pointer */ + #define PINT_NS ((PINT_Type *)PINT_BASE_NS) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x50005000u) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE_NS (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Peripheral SECPINT base pointer */ + #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS } +#else + /** Peripheral PINT base address */ + #define PINT_BASE (0x40004000u) + /** Peripheral PINT base pointer */ + #define PINT ((PINT_Type *)PINT_BASE) + /** Peripheral SECPINT base address */ + #define SECPINT_BASE (0x40005000u) + /** Peripheral SECPINT base pointer */ + #define SECPINT ((PINT_Type *)SECPINT_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT, SECPINT } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PLU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer + * @{ + */ + +/** PLU - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + uint8_t RESERVED_0[12]; + } LUT[26]; + uint8_t RESERVED_0[1216]; + __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_1[152]; + __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + uint8_t RESERVED_2[760]; + __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ +} PLU_Type; + +/* ---------------------------------------------------------------------------- + -- PLU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PLU_Register_Masks PLU Register Masks + * @{ + */ + +/*! @name LUT_INP_MUX - LUTn input x MUX */ +/*! @{ */ + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. + * 0b000000..The PLU primary inputs 0. + * 0b000001..The PLU primary inputs 1. + * 0b000010..The PLU primary inputs 2. + * 0b000011..The PLU primary inputs 3. + * 0b000100..The PLU primary inputs 4. + * 0b000101..The PLU primary inputs 5. + * 0b000110..The output of LUT0. + * 0b000111..The output of LUT1. + * 0b001000..The output of LUT2. + * 0b001001..The output of LUT3. + * 0b001010..The output of LUT4. + * 0b001011..The output of LUT5. + * 0b001100..The output of LUT6. + * 0b001101..The output of LUT7. + * 0b001110..The output of LUT8. + * 0b001111..The output of LUT9. + * 0b010000..The output of LUT10. + * 0b010001..The output of LUT11. + * 0b010010..The output of LUT12. + * 0b010011..The output of LUT13. + * 0b010100..The output of LUT14. + * 0b010101..The output of LUT15. + * 0b010110..The output of LUT16. + * 0b010111..The output of LUT17. + * 0b011000..The output of LUT18. + * 0b011001..The output of LUT19. + * 0b011010..The output of LUT20. + * 0b011011..The output of LUT21. + * 0b011100..The output of LUT22. + * 0b011101..The output of LUT23. + * 0b011110..The output of LUT24. + * 0b011111..The output of LUT25. + * 0b100000..state(0). + * 0b100001..state(1). + * 0b100010..state(2). + * 0b100011..state(3). + */ +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) +/*! @} */ + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) + +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) + +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @{ */ + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. + */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) +/*! @} */ + +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) + +/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ +/*! @{ */ + +#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) +#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. + */ +#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) +/*! @} */ + +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ +/*! @{ */ + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR + */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched + */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) +/*! @} */ + +/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ +/*! @{ */ + +#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) +#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) +/*! OUTPUTn - Selects the source to be connected to PLU Output 7. + * 0b00000..The PLU output 0. + * 0b00001..The PLU output 1. + * 0b00010..The PLU output 2. + * 0b00011..The PLU output 3. + * 0b00100..The PLU output 4. + * 0b00101..The PLU output 5. + * 0b00110..The PLU output 6. + * 0b00111..The PLU output 7. + * 0b01000..The PLU output 8. + * 0b01001..The PLU output 9. + * 0b01010..The PLU output 10. + * 0b01011..The PLU output 11. + * 0b01100..The PLU output 12. + * 0b01101..The PLU output 13. + * 0b01110..The PLU output 14. + * 0b01111..The PLU output 15. + * 0b10000..The PLU output 16. + * 0b10001..The PLU output 17. + * 0b10010..The PLU output 18. + * 0b10011..The PLU output 19. + * 0b10100..The PLU output 20. + * 0b10101..The PLU output 21. + * 0b10110..The PLU output 22. + * 0b10111..The PLU output 23. + * 0b11000..The PLU output 24. + * 0b11001..The PLU output 25. + * 0b11010..state(0). + * 0b11011..state(1). + * 0b11100..state(2). + * 0b11101..state(3). + */ +#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) +/*! @} */ + +/* The count of PLU_OUTPUT_MUX */ +#define PLU_OUTPUT_MUX_COUNT (8U) + + +/*! + * @} + */ /* end of group PLU_Register_Masks */ + + +/* PLU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PLU base address */ + #define PLU_BASE (0x5003D000u) + /** Peripheral PLU base address */ + #define PLU_BASE_NS (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Peripheral PLU base pointer */ + #define PLU_NS ((PLU_Type *)PLU_BASE_NS) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS_NS { PLU_BASE_NS } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS_NS { PLU_NS } +#else + /** Peripheral PLU base address */ + #define PLU_BASE (0x4003D000u) + /** Peripheral PLU base pointer */ + #define PLU ((PLU_Type *)PLU_BASE) + /** Array initializer of PLU peripheral base addresses */ + #define PLU_BASE_ADDRS { PLU_BASE } + /** Array initializer of PLU peripheral base pointers */ + #define PLU_BASE_PTRS { PLU } +#endif + +/*! + * @} + */ /* end of group PLU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ + __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ + uint8_t RESERVED_2[4]; + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; + __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ + __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ + __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ + uint8_t RESERVED_7[8]; + __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ + uint8_t RESERVED_8[12]; + __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; + __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ + __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'OSTIMER' */ + uint8_t RESERVED_11[24]; + __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ + uint8_t RESERVED_12[4]; + __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ + uint8_t RESERVED_13[4]; + __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode. + * 0b10..Latest IC boot was from POWER DOWN low power mode. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) +/*! @} */ + +/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) +/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). + * 0b0..Reset event from DEEP POWER DOWN mode is disable. + * 0b1..Reset event from DEEP POWER DOWN mode is enable. + */ +#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) +#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) +/*! BODVBATRESETENABLE - BOD VBAT reset enable. + * 0b0..BOD VBAT reset is disable. + * 0b1..BOD VBAT reset is enable. + */ +#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) + +#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) +#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) +/*! BODCORERESETENABLE - BOD CORE reset enable. + * 0b0..BOD CORE reset is disable. + * 0b1..BOD CORE reset is enable. + */ +#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) + +#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) +#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) +/*! SWRRESETENABLE - Software reset enable. + * 0b0..Software reset is disable. + * 0b1..Software reset is enable. + */ +#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) +/*! @} */ + +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) +/*! @} */ + +/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) +#define PMC_BODVBAT_TRIGLVL_SHIFT (0U) +/*! TRIGLVL - BoD trigger level. + * 0b00000..1.00 V. + * 0b00001..1.10 V. + * 0b00010..1.20 V. + * 0b00011..1.30 V. + * 0b00100..1.40 V. + * 0b00101..1.50 V. + * 0b00110..1.60 V. + * 0b00111..1.65 V. + * 0b01000..1.70 V. + * 0b01001..1.75 V. + * 0b01010..1.80 V. + * 0b01011..1.90 V. + * 0b01100..2.00 V. + * 0b01101..2.10 V. + * 0b01110..2.20 V. + * 0b01111..2.30 V. + * 0b10000..2.40 V. + * 0b10001..2.50 V. + * 0b10010..2.60 V. + * 0b10011..2.70 V. + * 0b10100..2.806 V. + * 0b10101..2.90 V. + * 0b10110..3.00 V. + * 0b10111..3.10 V. + * 0b11000..3.20 V. + * 0b11001..3.30 V. + * 0b11010..3.30 V. + * 0b11011..3.30 V. + * 0b11100..3.30 V. + * 0b11101..3.30 V. + * 0b11110..3.30 V. + * 0b11111..3.30 V. + */ +#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + +#define PMC_BODVBAT_HYST_MASK (0x60U) +#define PMC_BODVBAT_HYST_SHIFT (5U) +/*! HYST - BoD Hysteresis control. + * 0b00..25 mV. + * 0b01..50 mV. + * 0b10..75 mV. + * 0b11..100 mV. + */ +#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) +/*! @} */ + +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ +/*! @{ */ + +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. + */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) + +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) +/*! @} */ + +/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_XTAL32K_IREF_MASK (0x6U) +#define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. + */ +#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + +#define PMC_XTAL32K_TEST_MASK (0x8U) +#define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. + */ +#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + +#define PMC_XTAL32K_IBIAS_MASK (0x30U) +#define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. + */ +#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + +#define PMC_XTAL32K_AMPL_MASK (0xC0U) +#define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. + */ +#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + +#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) +#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ +#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + +#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) +#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ +#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) +/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. + * 0b0..Sourced from CAPTESTSTART. + * 0b1..Sourced from calibration. + */ +#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + +#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) +#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. + */ +#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + +#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) +#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. + */ +#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + +#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) +#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) +/*! CAPTESTOSCINSEL - Select the input for test. + * 0b0..Oscillator output pin (osc_out). + * 0b1..Oscillator input pin (osc_in). + */ +#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK) +/*! @} */ + +/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_COMP_HYST_MASK (0x2U) +#define PMC_COMP_HYST_SHIFT (1U) +/*! HYST - Hysteris when hyst = '1'. + * 0b0..Hysteresis is disable. + * 0b1..Hysteresis is enable. + */ +#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + +#define PMC_COMP_VREFINPUT_MASK (0x4U) +#define PMC_COMP_VREFINPUT_SHIFT (2U) +/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). + * 0b0..Select internal VREF. + * 0b1..Select VDDA. + */ +#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + +#define PMC_COMP_LOWPOWER_MASK (0x8U) +#define PMC_COMP_LOWPOWER_SHIFT (3U) +/*! LOWPOWER - Low power mode. + * 0b0..High speed mode. + * 0b1..Low power mode (Low speed). + */ +#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + +#define PMC_COMP_PMUX_MASK (0x70U) +#define PMC_COMP_PMUX_SHIFT (4U) +/*! PMUX - Control word for P multiplexer:. + * 0b000..VREF (See fiedl VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + +#define PMC_COMP_NMUX_MASK (0x380U) +#define PMC_COMP_NMUX_SHIFT (7U) +/*! NMUX - Control word for N multiplexer:. + * 0b000..VREF (See field VREFINPUT). + * 0b001..Pin P0_0. + * 0b010..Pin P0_9. + * 0b011..Pin P0_18. + * 0b100..Pin P1_14. + * 0b101..Pin P2_23. + */ +#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + +#define PMC_COMP_VREF_MASK (0x7C00U) +#define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ +#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + +#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) +#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ +#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + +#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) +#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ +#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) +/*! @} */ + +/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ +/*! @{ */ + +#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) +#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) +/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. + */ +#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) +#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) +/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. + */ +#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) +#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) +/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. + */ +#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + +#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) +#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) +/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. + * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3. + * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3. + */ +#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK) +/*! @} */ + +/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) +#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ +#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) + +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) +#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) +/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. + */ +#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) +/*! @} */ + +/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) +#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) +/*! MISCCTRL_3_8 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) +#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) +/*! MISCCTRL_13_14 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) + +#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) +#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) +/*! WAKUPIO_RST - WAKEUP IO event detector reset control. + * 0b1..Wakeup IO is reset. + * 0b0..Wakeup IO is not reset. + */ +#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) +/*! @} */ + +/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_RTCOSC32K_SEL_MASK (0x1U) +#define PMC_RTCOSC32K_SEL_SHIFT (0U) +/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . + * 0b0..FRO 32 KHz. + * 0b1..XTAL 32KHz. + */ +#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) +#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. + */ +#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) +#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. + */ +#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) +#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. + */ +#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. + */ +#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) +/*! @} */ + +/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ +/*! @{ */ + +#define PMC_OSTIMER_SOFTRESET_MASK (0x1U) +#define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ +#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + +#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) +#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. + */ +#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + +#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) +#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ +#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + +#define PMC_OSTIMER_OSC32KPD_MASK (0x8U) +#define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + */ +#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) +/*! @} */ + +/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) +#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) +/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). + * 0b0..BOD VBAT is powered. + * 0b1..BOD VBAT is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) + +#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) +#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) +/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. + * 0b0..FRO32KHz is powered. + * 0b1..FRO32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) +#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) +/*! PDEN_XTAL32K - Controls power to crystal 32 KHz. + * 0b0..Crystal 32KHz is powered. + * 0b1..Crystal 32KHz is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + +#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) +#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) +/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). + * 0b0..PLL0 is powered. + * 0b1..PLL0 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) +#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) +/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). + * 0b0..PLL1 is powered. + * 0b1..PLL1 is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) +#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) +/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. + * 0b0..USB Full Speed phy is powered. + * 0b1..USB Full Speed phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) +#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) +/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. + * 0b0..USB HS phy is powered. + * 0b1..USB HS phy is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + +#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) +#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) +/*! PDEN_COMP - Controls power to Analog Comparator. + * 0b0..Analog Comparator is powered. + * 0b1..Analog Comparator is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) +/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. + * 0b0..USB high speed LDO is powered. + * 0b1..USB high speed LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) +#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) +/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) + * 0b0..auxiliary biasing is powered. + * 0b1..auxiliary biasing is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) +#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) + +#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) +#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) +/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. + * 0b0..TRNG clocks are powered. + * 0b1..TRNG clocks are powered down. + */ +#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) +/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. + * 0b0..PLL0 Sread spectrum module is powered. + * 0b1..PLL0 Sread spectrum module is powered down. + */ +#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) +/*! @} */ + +/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) +/*! @} */ + +/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ +#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) +/*! @} */ + +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. + */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. + */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. + */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PMC base address */ + #define PMC_BASE (0x50020000u) + /** Peripheral PMC base address */ + #define PMC_BASE_NS (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Peripheral PMC base pointer */ + #define PMC_NS ((PMC_Type *)PMC_BASE_NS) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS_NS { PMC_BASE_NS } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS_NS { PMC_NS } +#else + /** Peripheral PMC base address */ + #define PMC_BASE (0x40020000u) + /** Peripheral PMC base pointer */ + #define PMC ((PMC_Type *)PMC_BASE) + /** Array initializer of PMC peripheral base addresses */ + #define PMC_BASE_ADDRS { PMC_BASE } + /** Array initializer of PMC peripheral base pointers */ + #define PMC_BASE_PTRS { PMC } +#endif + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer + * @{ + */ + +/** POWERQUAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */ + __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */ + __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */ + __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */ + __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */ + __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */ + __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */ + __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */ + uint8_t RESERVED_0[224]; + __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */ + __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */ + __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */ + __IO uint32_t MISC; /**< Misc register, offset: 0x10C */ + __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */ + uint8_t RESERVED_1[108]; + __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */ + __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */ + __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */ + __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */ + __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */ + __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */ + __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */ + uint8_t RESERVED_2[100]; + __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */ + __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */ +} POWERQUAD_Type; + +/* ---------------------------------------------------------------------------- + -- POWERQUAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks + * @{ + */ + +/*! @name OUTBASE - Base address register for output region */ +/*! @{ */ + +#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! outbase - Base address register for the output region + */ +#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) +/*! @} */ + +/*! @name OUTFORMAT - Output format */ +/*! @{ */ + +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + +#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) +#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! out_scaler - Output Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) +/*! @} */ + +/*! @name TMPBASE - Base address register for temp region */ +/*! @{ */ + +#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! tmpbase - Base address register for the temporary region + */ +#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) +/*! @} */ + +/*! @name TMPFORMAT - Temp format */ +/*! @{ */ + +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + +#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) +#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) +/*! @} */ + +/*! @name INABASE - Base address register for input A region */ +/*! @{ */ + +#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! inabase - Base address register for the input A region + */ +#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) +/*! @} */ + +/*! @name INAFORMAT - Input A format */ +/*! @{ */ + +#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) +#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + +#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) +#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) +/*! @} */ + +/*! @name INBBASE - Base address register for input B region */ +/*! @{ */ + +#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) +#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! inbbase - Base address register for the input B region + */ +#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) +/*! @} */ + +/*! @name INBFORMAT - Input B format */ +/*! @{ */ + +#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) +#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) +#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) + */ +#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + +#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) +#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) + */ +#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) +/*! @} */ + +/*! @name CONTROL - PowerQuad Control register */ +/*! @{ */ + +#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) +#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! decode_opcode - opcode specific to decode_machine + */ +#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + +#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) +#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + */ +#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + +#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) +#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! inst_busy - Instruction busy signal when high indicates processing is on + */ +#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) +/*! @} */ + +/*! @name LENGTH - Length register */ +/*! @{ */ + +#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) +#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = + * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = + * inst_length[20:16] + */ +#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) +/*! @} */ + +/*! @name CPPRE - Pre-scale register */ +/*! @{ */ + +#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) +#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! cppre_in - co-processor scaling of input + */ +#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + +#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) +#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! cppre_out - co-processor fixed point output + */ +#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) +#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! cppre_sat - 1 : forces sub-32 bit saturation + */ +#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + +#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) +#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! cppre_sat8 - 0 = 8bits, 1 = 16bits + */ +#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) +/*! @} */ + +/*! @name MISC - Misc register */ +/*! @{ */ + +#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) +#define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! inst_misc - Misc register. For Matrix : Used for scale factor + */ +#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) +/*! @} */ + +/*! @name CURSORY - Cursory register */ +/*! @{ */ + +#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) +#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! cursory - 1 : Enable cursory mode + */ +#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) +/*! @} */ + +/*! @name CORDIC_X - Cordic input X register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! cordic_x - Cordic input x + */ +#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) +/*! @} */ + +/*! @name CORDIC_Y - Cordic input Y register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! cordic_y - Cordic input y + */ +#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) +/*! @} */ + +/*! @name CORDIC_Z - Cordic input Z register */ +/*! @{ */ + +#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) +#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! cordic_z - Cordic input z + */ +#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) +/*! @} */ + +/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ +/*! @{ */ + +#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) +#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - overflow + */ +#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) +#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - nan + */ +#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - fixed_pt_overflow + */ +#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) +#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - underflow + */ +#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + +#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) +#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - bus_error + */ +#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) +/*! @} */ + +/*! @name INTREN - INTERRUPT enable register */ +/*! @{ */ + +#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) +#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! intr_oflow - 1 : Enable interrupt on Floating point overflow + */ +#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) +#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! intr_nan - 1 : Enable interrupt on Floating point NaN + */ +#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + +#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) +#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow + */ +#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + +#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) +#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation + */ +#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + +#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) +#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! intr_berr - 1: Enable interrupt on AHBM Buss Error + */ +#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + +#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) +#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! intr_comp - 1: Enable interrupt on instruction completion + */ +#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) +/*! @} */ + +/*! @name EVENTEN - Event Enable register */ +/*! @{ */ + +#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) +#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! event_oflow - 1 : Enable event trigger on Floating point overflow + */ +#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) +#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! event_nan - 1 : Enable event trigger on Floating point NaN + */ +#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + +#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) +#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! event_fixed - 1: Enable event trigger on Fixed point Overflow + */ +#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + +#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) +#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! event_uflow - 1 : Enable event trigger on Subnormal truncation + */ +#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + +#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) +#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! event_berr - 1: Enable event trigger on AHBM Buss Error + */ +#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + +#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) +#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! event_comp - 1: Enable event trigger on instruction completion + */ +#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) +/*! @} */ + +/*! @name INTRSTAT - INTERRUPT STATUS register */ +/*! @{ */ + +#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) +#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + */ +#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) +/*! @} */ + +/*! @name GPREG - General purpose register bank N. */ +/*! @{ */ + +#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! gpreg - General purpose register bank + */ +#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_GPREG */ +#define POWERQUAD_GPREG_COUNT (16U) + +/*! @name COMPREGS_COMPREG - Compute register bank */ +/*! @{ */ + +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) +#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! compreg - Compute register bank + */ +#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) +/*! @} */ + +/* The count of POWERQUAD_COMPREGS_COMPREG */ +#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group POWERQUAD_Register_Masks */ + + +/* POWERQUAD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x500A6000u) + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE_NS (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS } +#else + /** Peripheral POWERQUAD base address */ + #define POWERQUAD_BASE (0x400A6000u) + /** Peripheral POWERQUAD base pointer */ + #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE) + /** Array initializer of POWERQUAD peripheral base addresses */ + #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE } + /** Array initializer of POWERQUAD peripheral base pointers */ + #define POWERQUAD_BASE_PTRS { POWERQUAD } +#endif + +/*! + * @} + */ /* end of group POWERQUAD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PRINCE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer + * @{ + */ + +/** PRINCE - Register Layout Typedef */ +typedef struct { + __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */ + __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */ + __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */ + __IO uint32_t LOCK; /**< Lock register, offset: 0xC */ + __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */ + __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */ + __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */ + __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */ + __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */ + __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */ + __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */ + __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */ + __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */ + __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */ + __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */ + __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */ +} PRINCE_Type; + +/* ---------------------------------------------------------------------------- + -- PRINCE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PRINCE_Register_Masks PRINCE Register Masks + * @{ + */ + +/*! @name ENC_ENABLE - Encryption Enable register */ +/*! @{ */ + +#define PRINCE_ENC_ENABLE_EN_MASK (0x1U) +#define PRINCE_ENC_ENABLE_EN_SHIFT (0U) +/*! EN - Encryption Enable. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. + */ +#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) +/*! @} */ + +/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) +/*! @} */ + +/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ +/*! @{ */ + +#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) +#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ +#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) +/*! @} */ + +/*! @name LOCK - Lock register */ +/*! @{ */ + +#define PRINCE_LOCK_LOCKREG0_MASK (0x1U) +#define PRINCE_LOCK_LOCKREG0_SHIFT (0U) +/*! LOCKREG0 - Lock Region 0 registers. + * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable.. + * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + +#define PRINCE_LOCK_LOCKREG1_MASK (0x2U) +#define PRINCE_LOCK_LOCKREG1_SHIFT (1U) +/*! LOCKREG1 - Lock Region 1 registers. + * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable.. + * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + +#define PRINCE_LOCK_LOCKREG2_MASK (0x4U) +#define PRINCE_LOCK_LOCKREG2_SHIFT (2U) +/*! LOCKREG2 - Lock Region 2 registers. + * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable.. + * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. + */ +#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + +#define PRINCE_LOCK_LOCKMASK_MASK (0x100U) +#define PRINCE_LOCK_LOCKMASK_SHIFT (8U) +/*! LOCKMASK - Lock the Mask registers. + * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable.. + * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable.. + */ +#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK) +/*! @} */ + +/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR0 - Base Address for region 0 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ +#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + */ +#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) +/*! @} */ + +/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR1 - Base Address for region 1 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ +#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + */ +#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) +/*! @} */ + +/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) +/*! @} */ + +/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ +/*! @{ */ + +#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) +#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ +#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) +/*! @} */ + +/*! @name BASE_ADDR2 - Base Address for region 2 register */ +/*! @{ */ + +#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) +#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + +#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) +#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ +#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) +/*! @} */ + +/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ +/*! @{ */ + +#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) +#define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + */ +#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PRINCE_Register_Masks */ + + +/* PRINCE - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x50035000u) + /** Peripheral PRINCE base address */ + #define PRINCE_BASE_NS (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Peripheral PRINCE base pointer */ + #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS_NS { PRINCE_NS } +#else + /** Peripheral PRINCE base address */ + #define PRINCE_BASE (0x40035000u) + /** Peripheral PRINCE base pointer */ + #define PRINCE ((PRINCE_Type *)PRINCE_BASE) + /** Array initializer of PRINCE peripheral base addresses */ + #define PRINCE_BASE_ADDRS { PRINCE_BASE } + /** Array initializer of PRINCE peripheral base pointers */ + #define PRINCE_BASE_PTRS { PRINCE } +#endif + +/*! + * @} + */ /* end of group PRINCE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */ + uint8_t RESERVED_2[20]; + __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */ + uint8_t RESERVED_4[116]; + __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */ + uint8_t RESERVED_5[28]; + __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */ + uint8_t RESERVED_6[240]; + __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< , offset: 0x204 */ + __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */ + __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */ + __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */ + __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */ + uint8_t RESERVED_7[48]; + __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */ + __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */ + __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CTRL - PUF Control register */ +/*! @{ */ + +#define PUF_CTRL_ZEROIZE_MASK (0x1U) +#define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state + */ +#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + +#define PUF_CTRL_ENROLL_MASK (0x2U) +#define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation + */ +#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + +#define PUF_CTRL_START_MASK (0x4U) +#define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation + */ +#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + +#define PUF_CTRL_GENERATEKEY_MASK (0x8U) +#define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation + */ +#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + +#define PUF_CTRL_SETKEY_MASK (0x10U) +#define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation + */ +#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + +#define PUF_CTRL_GETKEY_MASK (0x40U) +#define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation + */ +#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) +/*! @} */ + +/*! @name KEYINDEX - PUF Key Index register */ +/*! @{ */ + +#define PUF_KEYINDEX_KEYIDX_MASK (0xFU) +#define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations + */ +#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) +/*! @} */ + +/*! @name KEYSIZE - PUF Key Size register */ +/*! @{ */ + +#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) +#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations + */ +#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) +/*! @} */ + +/*! @name STAT - PUF Status register */ +/*! @{ */ + +#define PUF_STAT_BUSY_MASK (0x1U) +#define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress + */ +#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + +#define PUF_STAT_SUCCESS_MASK (0x2U) +#define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful + */ +#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + +#define PUF_STAT_ERROR_MASK (0x4U) +#define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed + */ +#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + +#define PUF_STAT_KEYINREQ_MASK (0x10U) +#define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key + */ +#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + +#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available + */ +#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + +#define PUF_STAT_CODEINREQ_MASK (0x40U) +#define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC + */ +#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + +#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available + */ +#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name ALLOW - PUF Allow register */ +/*! @{ */ + +#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) +#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed + */ +#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + +#define PUF_ALLOW_ALLOWSTART_MASK (0x2U) +#define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed + */ +#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + +#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) +#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed + */ +#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + +#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) +#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed + */ +#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) +/*! @} */ + +/*! @name KEYINPUT - PUF Key Input register */ +/*! @{ */ + +#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) +#define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data + */ +#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) +/*! @} */ + +/*! @name CODEINPUT - PUF Code Input register */ +/*! @{ */ + +#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) +#define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data + */ +#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) +/*! @} */ + +/*! @name CODEOUTPUT - PUF Code Output register */ +/*! @{ */ + +#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) +#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data + */ +#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) +/*! @} */ + +/*! @name KEYOUTINDEX - PUF Key Output Index register */ +/*! @{ */ + +#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) +#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register + */ +#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) +/*! @} */ + +/*! @name KEYOUTPUT - PUF Key Output register */ +/*! @{ */ + +#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) +#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data + */ +#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) +/*! @} */ + +/*! @name IFSTAT - PUF Interface Status and clear register */ +/*! @{ */ + +#define PUF_IFSTAT_ERROR_MASK (0x1U) +#define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + */ +#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) +/*! @} */ + +/*! @name VERSION - PUF version register. */ +/*! @{ */ + +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +/*! VERSION - Version of the PUF module. + */ +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) +/*! @} */ + +/*! @name INTEN - PUF Interrupt Enable */ +/*! @{ */ + +#define PUF_INTEN_READYEN_MASK (0x1U) +#define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + +#define PUF_INTEN_SUCCESEN_MASK (0x2U) +#define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + +#define PUF_INTEN_ERROREN_MASK (0x4U) +#define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + +#define PUF_INTEN_KEYINREQEN_MASK (0x10U) +#define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + +#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) +#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + +#define PUF_INTEN_CODEINREQEN_MASK (0x40U) +#define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + +#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) +#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ +#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) +/*! @} */ + +/*! @name INTSTAT - PUF interrupt status */ +/*! @{ */ + +#define PUF_INTSTAT_READY_MASK (0x1U) +#define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear + */ +#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + +#define PUF_INTSTAT_SUCCESS_MASK (0x2U) +#define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + +#define PUF_INTSTAT_ERROR_MASK (0x4U) +#define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + +#define PUF_INTSTAT_KEYINREQ_MASK (0x10U) +#define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + +#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) +#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + +#define PUF_INTSTAT_CODEINREQ_MASK (0x40U) +#define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + +#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) +#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ +#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) +/*! @} */ + +/*! @name PWRCTRL - PUF RAM Power Control */ +/*! @{ */ + +#define PUF_PWRCTRL_RAMON_MASK (0x1U) +#define PUF_PWRCTRL_RAMON_SHIFT (0U) +/*! RAMON - Power on the PUF RAM. + */ +#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) + +#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) +#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +/*! RAMSTAT - PUF RAM status. + */ +#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) +/*! @} */ + +/*! @name CFG - PUF config register for block bits */ +/*! @{ */ + +#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) +#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + +#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) +#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. + */ +#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) +/*! @} */ + +/*! @name KEYLOCK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYLOCK_KEY0_MASK (0x3U) +#define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + +#define PUF_KEYLOCK_KEY1_MASK (0xCU) +#define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + +#define PUF_KEYLOCK_KEY2_MASK (0x30U) +#define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + +#define PUF_KEYLOCK_KEY3_MASK (0xC0U) +#define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ +#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) +/*! @} */ + +/*! @name KEYENABLE - */ +/*! @{ */ + +#define PUF_KEYENABLE_KEY0_MASK (0x3U) +#define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ +#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + +#define PUF_KEYENABLE_KEY1_MASK (0xCU) +#define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ +#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + +#define PUF_KEYENABLE_KEY2_MASK (0x30U) +#define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ +#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + +#define PUF_KEYENABLE_KEY3_MASK (0xC0U) +#define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ +#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) +/*! @} */ + +/*! @name KEYRESET - Reinitialize Keys shift registers counters */ +/*! @{ */ + +#define PUF_KEYRESET_KEY0_MASK (0x3U) +#define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + +#define PUF_KEYRESET_KEY1_MASK (0xCU) +#define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + +#define PUF_KEYRESET_KEY2_MASK (0x30U) +#define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + +#define PUF_KEYRESET_KEY3_MASK (0xC0U) +#define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + */ +#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) +/*! @} */ + +/*! @name IDXBLK_L - */ +/*! @{ */ + +#define PUF_IDXBLK_L_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) + +#define PUF_IDXBLK_L_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) + +#define PUF_IDXBLK_L_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) + +#define PUF_IDXBLK_L_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) + +#define PUF_IDXBLK_L_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) + +#define PUF_IDXBLK_L_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) + +#define PUF_IDXBLK_L_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) + +#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 0 to 7 PUF key indexes + */ +#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_H_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) + +#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) + +#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) + +#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) + +#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) + +#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) + +#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) + +#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) +/*! @} */ + +/*! @name KEYMASK - Only reset in case of full IC reset */ +/*! @{ */ + +#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) +#define PUF_KEYMASK_KEYMASK_SHIFT (0U) +#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) +/*! @} */ + +/* The count of PUF_KEYMASK */ +#define PUF_KEYMASK_COUNT (4U) + +/*! @name IDXBLK_H - */ +/*! @{ */ + +#define PUF_IDXBLK_H_IDX8_MASK (0x3U) +#define PUF_IDXBLK_H_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ +#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) + +#define PUF_IDXBLK_H_IDX9_MASK (0xCU) +#define PUF_IDXBLK_H_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ +#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) + +#define PUF_IDXBLK_H_IDX10_MASK (0x30U) +#define PUF_IDXBLK_H_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ +#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) + +#define PUF_IDXBLK_H_IDX11_MASK (0xC0U) +#define PUF_IDXBLK_H_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ +#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) + +#define PUF_IDXBLK_H_IDX12_MASK (0x300U) +#define PUF_IDXBLK_H_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ +#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) + +#define PUF_IDXBLK_H_IDX13_MASK (0xC00U) +#define PUF_IDXBLK_H_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ +#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) + +#define PUF_IDXBLK_H_IDX14_MASK (0x3000U) +#define PUF_IDXBLK_H_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ +#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) + +#define PUF_IDXBLK_H_IDX15_MASK (0xC000U) +#define PUF_IDXBLK_H_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ +#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) + +#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) +#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 8 to 15 PUF key indexes + */ +#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) +/*! @} */ + +/*! @name IDXBLK_L_DP - */ +/*! @{ */ + +#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) +#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ +#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) + +#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) +#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ +#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) + +#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) +#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ +#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) + +#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) +#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ +#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) + +#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) +#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ +#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) + +#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) +#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ +#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) + +#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) +#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ +#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) +/*! @} */ + +/*! @name SHIFT_STATUS - */ +/*! @{ */ + +#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) +#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register + */ +#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + +#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) +#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register + */ +#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + +#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) +#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register + */ +#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + +#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) +#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register + */ +#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5003B000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4003B000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF } +#endif +/** Interrupt vectors for the PUF peripheral type */ +#define PUF_IRQS { PUF_IRQn } + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ + __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ + __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ + __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ + uint8_t RESERVED_1[4068]; + __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ +/*! @{ */ + +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. + */ +#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) +/*! @} */ + +/*! @name COUNTER_VAL - */ +/*! @{ */ + +#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) +#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ +#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + +#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) +#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + */ +#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) +/*! @} */ + +/*! @name COUNTER_CFG - */ +/*! @{ */ + +#define RNG_COUNTER_CFG_MODE_MASK (0x3U) +#define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. + */ +#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + +#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) +#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. + */ +#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + +#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) +#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. + */ +#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_CFG - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) +#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + */ +#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + +#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) +#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ +#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) +/*! @} */ + +/*! @name ONLINE_TEST_VAL - */ +/*! @{ */ + +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. + */ +#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. + */ +#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) +/*! @} */ + +/*! @name MODULEID - IP identifier */ +/*! @{ */ + +#define RNG_MODULEID_APERTURE_MASK (0xFFU) +#define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ +#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + +#define RNG_MODULEID_MIN_REV_MASK (0xF00U) +#define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. + */ +#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + +#define RNG_MODULEID_MAJ_REV_MASK (0xF000U) +#define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. + */ +#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + +#define RNG_MODULEID_ID_MASK (0xFFFF0000U) +#define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. + */ +#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RNG base address */ + #define RNG_BASE (0x5003A000u) + /** Peripheral RNG base address */ + #define RNG_BASE_NS (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Peripheral RNG base pointer */ + #define RNG_NS ((RNG_Type *)RNG_BASE_NS) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS_NS { RNG_BASE_NS } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS_NS { RNG_NS } +#else + /** Peripheral RNG base address */ + #define RNG_BASE (0x4003A000u) + /** Peripheral RNG base pointer */ + #define RNG ((RNG_Type *)RNG_BASE) + /** Array initializer of RNG peripheral base addresses */ + #define RNG_BASE_ADDRS { RNG_BASE } + /** Array initializer of RNG peripheral base pointers */ + #define RNG_BASE_PTRS { RNG } +#endif + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ + uint8_t RESERVED_0[44]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ + +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value + * except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes + * to set any of the other bits within this register. Do not attempt to write to any bits of this register at + * the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt + * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up + * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz + * timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should + * be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate + * operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the + * high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..See RTC_OSC_BYPASS + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + +#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) +#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) +/*! RTC_OSC_BYPASS - RTC oscillator bypass control. + * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins. + * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. + */ +#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + +#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) +#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) +/*! RTC_SUBSEC_ENA - RTC Sub-second counter control. + * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD + * reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second + * counter, this bit will always read-back as a '0'. + * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first + * one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is + * set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip + * exits deep power-down mode. + */ +#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ + +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ + +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ + +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + +/*! @name SUBSEC - Sub-second counter register */ +/*! @{ */ + +#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) +#define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ +#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) +/*! @} */ + +/*! @name GPREG - General Purpose register */ +/*! @{ */ + +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + */ +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) +/*! @} */ + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC base address */ + #define RTC_BASE (0x5002C000u) + /** Peripheral RTC base address */ + #define RTC_BASE_NS (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Peripheral RTC base pointer */ + #define RTC_NS ((RTC_Type *)RTC_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC_NS } +#else + /** Peripheral RTC base address */ + #define RTC_BASE (0x4002C000u) + /** Peripheral RTC base pointer */ + #define RTC ((RTC_Type *)RTC_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; + uint8_t RESERVED_0[40]; + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + }; + uint8_t RESERVED_2[192]; + union { /* offset: 0x200 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + }; + uint8_t RESERVED_3[192]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EV[16]; + uint8_t RESERVED_4[384]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ + +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are + * only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The + * minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the + * high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the + * counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the + * clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL + * field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system + * clock. The input clock rate must be at least half the system clock rate and can be the same or faster than + * the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent + * on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ + +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ + +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ + +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ + +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ + +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ + +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ + +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. + */ +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. + */ +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ + +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ + +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ + +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ + +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ + +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMAREQ0 - SCT DMA request 0 register */ +/*! @{ */ + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) +/*! @} */ + +/*! @name DMAREQ1 - SCT DMA request 1 register */ +/*! @{ */ + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ + +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ + +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ + +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ + +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name CAPL - SCT_CAPL register */ +/*! @{ */ + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) +/*! @} */ + +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) + +/*! @name CAPH - SCT_CAPH register */ +/*! @{ */ + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) +/*! @} */ + +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) + +/*! @name CAP - SCT capture register of capture channel */ +/*! @{ */ + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) + +/*! @name MATCHL - SCT_MATCHL register */ +/*! @{ */ + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) +/*! @} */ + +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) + +/*! @name MATCHH - SCT_MATCHH register */ +/*! @{ */ + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) +/*! @} */ + +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) + +/*! @name MATCH - SCT match value register of match channels */ +/*! @{ */ + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the + * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state + * detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this + * event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters + * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ + +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ + +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x50085000u) + /** Peripheral SCT0 base address */ + #define SCT0_BASE_NS (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Peripheral SCT0 base pointer */ + #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS_NS { SCT0_NS } +#else + /** Peripheral SCT0 base address */ + #define SCT0_BASE (0x40085000u) + /** Peripheral SCT0 base pointer */ + #define SCT0 ((SCT_Type *)SCT0_BASE) + /** Array initializer of SCT peripheral base addresses */ + #define SCT_BASE_ADDRS { SCT0_BASE } + /** Array initializer of SCT peripheral base pointers */ + #define SCT_BASE_PTRS { SCT0 } +#endif +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +/*! @{ */ + +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +/*! CONTROLLER_RESET - Controller reset. + */ +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) + +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +/*! FIFO_RESET - Fifo reset. + */ +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) + +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +/*! DMA_RESET - DMA reset. + */ +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) + +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +/*! INT_ENABLE - Global interrupt enable/disable bit. + */ +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) + +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +/*! READ_WAIT - Read/wait. + */ +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) + +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +/*! SEND_IRQ_RESPONSE - Send irq response. + */ +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) + +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +/*! ABORT_READ_DATA - Abort read data. + */ +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) + +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +/*! SEND_CCSD - Send ccsd. + */ +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) + +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. + */ +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) + +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. + */ +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) + +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. + */ +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) + +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +/*! USE_INTERNAL_DMAC - SD/MMC DMA use. + */ +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) +/*! @} */ + +/*! @name PWREN - Power Enable register */ +/*! @{ */ + +#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 0. + */ +#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) + +#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) +#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 1. + */ +#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock Divider register */ +/*! @{ */ + +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +/*! CLK_DIVIDER0 - Clock divider-0 value. + */ +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) +/*! @} */ + +/*! @name CLKENA - Clock Enable register */ +/*! @{ */ + +#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. + */ +#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) +#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. + */ +#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) + +#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. + */ +#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) + +#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) +#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. + */ +#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) +/*! @} */ + +/*! @name TMOUT - Time-out register */ +/*! @{ */ + +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +/*! RESPONSE_TIMEOUT - Response time-out value. + */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) + +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + */ +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) +/*! @} */ + +/*! @name CTYPE - Card Type register */ +/*! @{ */ + +#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) +#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ +#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) + +#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ +#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) + +#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) +#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ +#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) +/*! @} */ + +/*! @name BLKSIZ - Block Size register */ +/*! @{ */ + +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +/*! BLOCK_SIZE - Block size. + */ +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @} */ + +/*! @name BYTCNT - Byte Count register */ +/*! @{ */ + +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + */ +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name INTMASK - Interrupt Mask register */ +/*! @{ */ + +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) + +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) + +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) + +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) + +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) + +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) + +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) + +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) + +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) + +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) + +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) + +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) + +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) + +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) + +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) + +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/Write no CRC. + */ +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) + +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +/*! SDIO_INT_MASK - Mask SDIO interrupt. + */ +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) +/*! @} */ + +/*! @name CMDARG - Command Argument register */ +/*! @{ */ + +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +/*! CMD_ARG - Value indicates command argument to be passed to card. + */ +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) +/*! @} */ + +/*! @name CMD - Command register */ +/*! @{ */ + +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +/*! CMD_INDEX - Command index. + */ +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) + +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +/*! RESPONSE_EXPECT - Response expect. + */ +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) + +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +/*! RESPONSE_LENGTH - Response length. + */ +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) + +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +/*! CHECK_RESPONSE_CRC - Check response CRC. + */ +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) + +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +/*! DATA_EXPECTED - Data expected. + */ +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) + +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +/*! READ_WRITE - read/write. + */ +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) + +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +/*! TRANSFER_MODE - Transfer mode. + */ +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) + +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +/*! SEND_AUTO_STOP - Send auto stop. + */ +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) + +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. + */ +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) + +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +/*! STOP_ABORT_CMD - Stop abort command. + */ +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) + +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +/*! SEND_INITIALIZATION - Send initialization. + */ +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) + +#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) +#define SDIF_CMD_CARD_NUMBER_SHIFT (16U) +/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed + * 0b00000..Command will be execute on SDCARD 0 + * 0b00001..Command will be execute on SDCARD 1 + */ +#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) + +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. + */ +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) + +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +/*! READ_CEATA_DEVICE - Read ceata device. + */ +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) + +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +/*! CCS_EXPECTED - CCS expected. + */ +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) + +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. + */ +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) + +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. + */ +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) + +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +/*! DISABLE_BOOT - Disable Boot. + */ +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) + +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +/*! BOOT_MODE - Boot Mode. + */ +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) + +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +/*! VOLT_SWITCH - Voltage switch bit. + */ +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) + +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +/*! USE_HOLD_REG - Use Hold Register. + */ +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) + +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +/*! START_CMD - Start command. + */ +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) +/*! @} */ + +/*! @name RESP - Response register */ +/*! @{ */ + +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +/*! RESPONSE - Bits of response. + */ +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) +/*! @} */ + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +/*! @{ */ + +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) + +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) + +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) + +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) + +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) + +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) + +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) + +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) + +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) + +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) + +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) + +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) + +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) + +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) + +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) + +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) + +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name RINTSTS - Raw Interrupt Status register */ +/*! @{ */ + +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) + +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) + +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) + +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) + +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) + +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) + +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) + +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) + +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). + */ +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) + +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). + */ +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) + +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) + +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) + +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) + +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) + +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) + +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) + +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) +/*! @} */ + +/*! @name STATUS - Status register */ +/*! @{ */ + +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. + */ +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. + */ +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) + +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY - FIFO is empty status. + */ +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) + +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +/*! FIFO_FULL - FIFO is full status. + */ +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) + +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx + * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - + * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp + * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The + * command FSM state is represented using 19 bits. + */ +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) + +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + */ +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) + +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + */ +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) + +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. + */ +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) + +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. + */ +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) + +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. + */ +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) + +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +/*! DMA_ACK - DMA acknowledge signal state. + */ +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) + +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +/*! DMA_REQ - DMA request signal state. + */ +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) +/*! @} */ + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +/*! @{ */ + +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. + */ +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) + +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. + */ +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) + +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + */ +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) +/*! @} */ + +/*! @name CDETECT - Card Detect register */ +/*! @{ */ + +#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +/*! CARD0_DETECT - Card 0 detect + */ +#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) + +#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) +#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +/*! CARD1_DETECT - Card 1 detect + */ +#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) +/*! @} */ + +/*! @name WRTPRT - Write Protect register */ +/*! @{ */ + +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +/*! WRITE_PROTECT - Write protect. + */ +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) +/*! @} */ + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +/*! @{ */ + +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. + */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +/*! @{ */ + +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) +/*! @} */ + +/*! @name DEBNCE - Debounce Count register */ +/*! @{ */ + +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) +/*! @} */ + +/*! @name RST_N - Hardware Reset */ +/*! @{ */ + +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +/*! CARD_RESET - Hardware reset. + */ +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) +/*! @} */ + +/*! @name BMOD - Bus Mode register */ +/*! @{ */ + +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +/*! SWR - Software Reset. + */ +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) + +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +/*! FB - Fixed Burst. + */ +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) + +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +/*! DSL - Descriptor Skip Length. + */ +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) + +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +/*! DE - SD/MMC DMA Enable. + */ +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) + +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +/*! PBL - Programmable Burst Length. + */ +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) +/*! @} */ + +/*! @name PLDMND - Poll Demand register */ +/*! @{ */ + +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +/*! PD - Poll Demand. + */ +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) +/*! @} */ + +/*! @name DBADDR - Descriptor List Base Address register */ +/*! @{ */ + +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +/*! SDL - Start of Descriptor List. + */ +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) +/*! @} */ + +/*! @name IDSTS - Internal DMAC Status register */ +/*! @{ */ + +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +/*! TI - Transmit Interrupt. + */ +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) + +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +/*! RI - Receive Interrupt. + */ +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) + +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Interrupt. + */ +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) + +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) + +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +/*! CES - Card Error Summary. + */ +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) + +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary. + */ +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) + +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary. + */ +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) + +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +/*! EB - Error Bits. + */ +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) + +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +/*! FSM - DMAC state machine present state. + */ +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) +/*! @} */ + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +/*! @{ */ + +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +/*! TI - Transmit Interrupt Enable. + */ +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) + +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +/*! RI - Receive Interrupt Enable. + */ +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) + +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Enable. + */ +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) + +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) + +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +/*! CES - Card Error summary Interrupt Enable. + */ +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) + +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary Enable. + */ +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) + +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary Enable. + */ +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) +/*! @} */ + +/*! @name DSCADDR - Current Host Descriptor Address register */ +/*! @{ */ + +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +/*! HDA - Host Descriptor Address Pointer. + */ +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) +/*! @} */ + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +/*! @{ */ + +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +/*! HBA - Host Buffer Address Pointer. + */ +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) +/*! @} */ + +/*! @name CARDTHRCTL - Card Threshold Control */ +/*! @{ */ + +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +/*! CARDRDTHREN - Card Read Threshold Enable. + */ +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) + +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +/*! BSYCLRINTEN - Busy Clear Interrupt Enable. + */ +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) + +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +/*! CARDTHRESHOLD - Card Threshold size. + */ +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) +/*! @} */ + +/*! @name BACKENDPWR - Power control */ +/*! @{ */ + +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +/*! BACKENDPWR - Back-end Power control for card application. + */ +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) +/*! @} */ + +/*! @name FIFO - SDIF FIFO */ +/*! @{ */ + +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +/*! DATA - SDIF FIFO. + */ +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) +/*! @} */ + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x5009B000u) + /** Peripheral SDIF base address */ + #define SDIF_BASE_NS (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Peripheral SDIF base pointer */ + #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS_NS { SDIF_NS } +#else + /** Peripheral SDIF base address */ + #define SDIF_BASE (0x4009B000u) + /** Peripheral SDIF base pointer */ + #define SDIF ((SDIF_Type *)SDIF_BASE) + /** Array initializer of SDIF peripheral base addresses */ + #define SDIF_BASE_ADDRS { SDIF_BASE } + /** Array initializer of SDIF peripheral base pointers */ + #define SDIF_BASE_PTRS { SDIF } +#endif +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ + +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock + * changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit + * and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ + +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ + +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. + */ +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ + +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ + +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ + +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. + */ +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. + */ +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. + */ +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain + * so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value + * in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay + * value = 0. This control can be used as part of the support for frame lengths greater than 16 + * bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be + * inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to + * read unneeded data from the receiver. Setting this bit simplifies the transmit process and can + * be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit + * will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data + * is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received + * data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. + */ +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. + */ +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x50086000u) + /** Peripheral SPI0 base address */ + #define SPI0_BASE_NS (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI0 base pointer */ + #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x50087000u) + /** Peripheral SPI1 base address */ + #define SPI1_BASE_NS (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI1 base pointer */ + #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x50088000u) + /** Peripheral SPI2 base address */ + #define SPI2_BASE_NS (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI2 base pointer */ + #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x50089000u) + /** Peripheral SPI3 base address */ + #define SPI3_BASE_NS (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI3 base pointer */ + #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x5008A000u) + /** Peripheral SPI4 base address */ + #define SPI4_BASE_NS (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI4 base pointer */ + #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x50096000u) + /** Peripheral SPI5 base address */ + #define SPI5_BASE_NS (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI5 base pointer */ + #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x50097000u) + /** Peripheral SPI6 base address */ + #define SPI6_BASE_NS (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI6 base pointer */ + #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x50098000u) + /** Peripheral SPI7 base address */ + #define SPI7_BASE_NS (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI7 base pointer */ + #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x5009F000u) + /** Peripheral SPI8 base address */ + #define SPI8_BASE_NS (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Peripheral SPI8 base pointer */ + #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS } +#else + /** Peripheral SPI0 base address */ + #define SPI0_BASE (0x40086000u) + /** Peripheral SPI0 base pointer */ + #define SPI0 ((SPI_Type *)SPI0_BASE) + /** Peripheral SPI1 base address */ + #define SPI1_BASE (0x40087000u) + /** Peripheral SPI1 base pointer */ + #define SPI1 ((SPI_Type *)SPI1_BASE) + /** Peripheral SPI2 base address */ + #define SPI2_BASE (0x40088000u) + /** Peripheral SPI2 base pointer */ + #define SPI2 ((SPI_Type *)SPI2_BASE) + /** Peripheral SPI3 base address */ + #define SPI3_BASE (0x40089000u) + /** Peripheral SPI3 base pointer */ + #define SPI3 ((SPI_Type *)SPI3_BASE) + /** Peripheral SPI4 base address */ + #define SPI4_BASE (0x4008A000u) + /** Peripheral SPI4 base pointer */ + #define SPI4 ((SPI_Type *)SPI4_BASE) + /** Peripheral SPI5 base address */ + #define SPI5_BASE (0x40096000u) + /** Peripheral SPI5 base pointer */ + #define SPI5 ((SPI_Type *)SPI5_BASE) + /** Peripheral SPI6 base address */ + #define SPI6_BASE (0x40097000u) + /** Peripheral SPI6 base pointer */ + #define SPI6 ((SPI_Type *)SPI6_BASE) + /** Peripheral SPI7 base address */ + #define SPI7_BASE (0x40098000u) + /** Peripheral SPI7 base pointer */ + #define SPI7 ((SPI_Type *)SPI7_BASE) + /** Peripheral SPI8 base address */ + #define SPI8_BASE (0x4009F000u) + /** Peripheral SPI8 base pointer */ + #define SPI8 ((SPI_Type *)SPI8_BASE) + /** Array initializer of SPI peripheral base addresses */ + #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE } + /** Array initializer of SPI peripheral base pointers */ + #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 } +#endif +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + union { /* offset: 0x100 */ + struct { /* offset: 0x100 */ + __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */ + } PRESETCTRL; + __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_4[20]; + __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ + uint8_t RESERVED_7[156]; + union { /* offset: 0x200 */ + struct { /* offset: 0x200 */ + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */ + } AHBCLKCTRL; + __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_8[20]; + __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_9[20]; + __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_10[20]; + union { /* offset: 0x260 */ + struct { /* offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */ + __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */ + } SYSTICKCLKSEL; + __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */ + }; + __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */ + union { /* offset: 0x26C */ + struct { /* offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */ + __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */ + __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */ + __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */ + __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */ + } CTIMERCLKSEL; + __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */ + }; + __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */ + __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */ + uint8_t RESERVED_11[4]; + __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */ + __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */ + uint8_t RESERVED_12[12]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_13[4]; + union { /* offset: 0x2B0 */ + struct { /* offset: 0x2B0 */ + __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ + __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */ + __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */ + __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */ + __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */ + __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */ + __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */ + __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */ + } FCCLKSEL; + __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ + }; + __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; + __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ + __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ + __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ + uint8_t RESERVED_18[20]; + union { /* offset: 0x320 */ + struct { /* offset: 0x320 */ + __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ + __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */ + __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */ + __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */ + __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */ + __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */ + __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */ + __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */ + } FLEXFRGCTRL; + __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ + }; + uint8_t RESERVED_19[64]; + __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ + __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ + uint8_t RESERVED_20[4]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ + uint8_t RESERVED_21[16]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_22[4]; + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; + __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ + uint8_t RESERVED_25[52]; + __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ + uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; + __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ + __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_29[252]; + __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ + __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */ + __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */ + __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */ + __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */ + uint8_t RESERVED_30[12]; + __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */ + __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */ + __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */ + __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ + __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ + __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ + uint8_t RESERVED_31[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_32[248]; + __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ + __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ + uint8_t RESERVED_33[4]; + __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[520]; + __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ + uint8_t RESERVED_35[244]; + __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ + __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ + uint8_t RESERVED_36[748]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ + __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ + uint8_t RESERVED_37[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_38[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_39[16]; + __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ + uint8_t RESERVED_40[32]; + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name MEMORYREMAP - Memory Remap control register */ +/*! @{ */ + +#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) +#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) +/*! MAP - Select the location of the vector table :. + * 0b00..Vector Table in ROM. + * 0b01..Vector Table in RAM. + * 0b10..Vector Table in Flash. + * 0b11..Vector Table in Flash. + */ +#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +/*! PRI_USB_FS - USB-FS.(USB0) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +/*! PRI_SDIO - SDIO. + */ +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). + */ +#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +/*! PRI_HASH_AES - HASH_AES. + */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +/*! PRI_USB_HS - USB-HS.(USB1) + */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ +#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ +/*! @{ */ + +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) + +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) + +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + */ +#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + */ +#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral reset control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) +/*! ROM_RST - ROM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) +/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) +/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) +/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) +/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + +#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) +/*! FLASH_RST - Flash controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + +#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) +/*! FMC_RST - FMC controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) +/*! IOCON_RST - I/O controller reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) +/*! GPIO0_RST - GPIO0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) +/*! GPIO1_RST - GPIO1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) +/*! GPIO2_RST - GPIO2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) +/*! GPIO3_RST - GPIO3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) +/*! PINT_RST - Pin interrupt (PINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) +/*! GINT_RST - Group interrupt (GINT) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) +/*! DMA0_RST - DMA0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) +/*! CRCGEN_RST - CRCGEN reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + +#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) +/*! WWDT_RST - Watchdog Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + +#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) +/*! RTC_RST - Real Time Clock (RTC) reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) +/*! MAILBOX_RST - Inter CPU communication Mailbox reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + +#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) +/*! ADC_RST - ADC reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral reset control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) +/*! SCTIPU_RST - SCTIPU reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - FC0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - FC1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - FC2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - FC3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - FC4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - FC5 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - FC6 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - FC7 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - Timer 2 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) +/*! USB0_DEV_RST - USB0 DEV reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - Timer 0 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - Timer 1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral reset control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) +/*! COMP_RST - Comparator reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + +#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) +/*! SDIO_RST - SDIO reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) +/*! USB1_HOST_RST - USB1 Host reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) +/*! USB1_DEV_RST - USB1 dev reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) +/*! USB1_RAM_RST - USB1 RAM reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) +/*! USB1_PHY_RST - USB1 PHY reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - Frequency meter reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) +/*! RNG_RST - RNG reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) +/*! USB0_HOSTM_RST - USB0 Host Master reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) +/*! USB0_HOSTS_RST - USB0 Host Slave reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + +#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) +/*! PQ_RST - Power Quad reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + +#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) +/*! PLULUT_RST - PLU LUT reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - Timer 3 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - Timer 4 reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) +/*! CASPER_RST - Casper reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) + +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) +/*! ANALOG_CTRL_RST - analog control reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) +#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) +/*! HS_LSPI_RST - HS LSPI reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) +/*! GPIO_SEC_RST - GPIO secure reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) +/*! GPIO_SEC_INT_RST - GPIO secure int reset control. + * 0b1..Bloc is reset. + * 0b0..Bloc is not reset. + */ +#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLX */ +#define SYSCON_PRESETCTRLX_COUNT (3U) + +/*! @name PRESETCTRLSET - Peripheral reset control set register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SWR_RESET - generate a software_reset */ +/*! @{ */ + +#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) +#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) +/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. + * 0b01011010000000000000000000000001..Generate a software reset. + * 0b00000000000000000000000000000000..Bloc is not reset. + */ +#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL0 - AHB Clock control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) +/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) +/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) +/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) +/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + +#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) +/*! FLASH - Enables the clock for the Flash controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) +/*! FMC - Enables the clock for the FMC controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) +/*! IOCON - Enables the clock for the I/O controller. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) +/*! GPIO0 - Enables the clock for the GPIO0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) +/*! GPIO1 - Enables the clock for the GPIO1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) +/*! GPIO2 - Enables the clock for the GPIO2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) +/*! GPIO3 - Enables the clock for the GPIO3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) +/*! PINT - Enables the clock for the Pin interrupt (PINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) +/*! GINT - Enables the clock for the Group interrupt (GINT). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) +/*! DMA0 - Enables the clock for the DMA0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) +/*! CRCGEN - Enables the clock for the CRCGEN. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) +/*! WWDT - Enables the clock for the Watchdog Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + +#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) +/*! RTC - Enables the clock for the Real Time Clock (RTC). + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + +#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) +/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + +#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) +/*! ADC - Enables the clock for the ADC. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for the MRT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for the FC0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for the FC1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for the FC2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for the FC3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for the FC4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for the FC5. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for the FC6. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for the FC7. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for the Timer 2. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) +/*! USB0_DEV - Enables the clock for the USB0 DEV. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for the Timer 0. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for the Timer 1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for the DMA1. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) +#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) +/*! COMP - Enables the clock for the Comparator. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + +#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) +/*! SDIO - Enables the clock for the SDIO. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) +/*! USB1_HOST - Enables the clock for the USB1 Host. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) +/*! USB1_DEV - Enables the clock for the USB1 dev. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) +/*! USB1_RAM - Enables the clock for the USB1 RAM. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) +/*! USB1_PHY - Enables the clock for the USB1 PHY. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) +/*! RNG - Enables the clock for the RNG. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) +/*! USB0_HOSTM - Enables the clock for the USB0 Host Master. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) +/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + +#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) +/*! PQ - Enables the clock for the Power Quad. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + +#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) +/*! PLULUT - Enables the clock for the PLU LUT. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for the Timer 3. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for the Timer 4. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for the PUF reset control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) +/*! CASPER - Enables the clock for the Casper. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) + +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) +/*! ANALOG_CTRL - Enables the clock for the analog control. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) +/*! HS_LSPI - Enables the clock for the HS LSPI. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) +/*! GPIO_SEC - Enables the clock for the GPIO secure. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) +/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. + * 0b1..Enable Clock. + * 0b0..Disable Clock. + */ +#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLX */ +#define SYSCON_AHBCLKCTRLX_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU0 source select. + * 0b000..System Tick 0 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) +/*! SEL - System Tick Timer for CPU1 source select. + * 0b000..System Tick 1 divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKSELX */ +#define SYSCON_SYSTICKCLKSELX_COUNT (2U) + +/*! @name TRACECLKSEL - Trace clock source select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Trace clock source select. + * 0b000..Trace divided clock. + * 0b001..FRO 1MHz clock. + * 0b010..Oscillator 32 kHz clock. + * 0b011..No clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) +/*! SEL - CTimer 0 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) +/*! SEL - CTimer 1 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) +/*! SEL - CTimer 2 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) +/*! SEL - CTimer 3 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) +/*! SEL - CTimer 4 clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSELX */ +#define SYSCON_CTIMERCLKSELX_COUNT (5U) + +/*! @name MAINCLKSELA - Main clock A source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Main clock A source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select */ +/*! @{ */ + +#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Main clock source select. + * 0b000..Main Clock A. + * 0b001..PLL0 clock. + * 0b010..PLL1 clock. + * 0b011..Oscillator 32 kHz clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSEL - CLKOUT clock source select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..PLL1 clock. + * 0b110..Oscillator 32kHz clock. + * 0b111..No clock. + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL0CLKSEL - PLL0 clock source select */ +/*! @{ */ + +#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL0 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name PLL1CLKSEL - PLL1 clock source select */ +/*! @{ */ + +#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) +/*! SEL - PLL1 clock source select. + * 0b000..FRO 12 MHz clock. + * 0b001..CLKIN clock. + * 0b010..FRO 1MHz clock. + * 0b011..Oscillator 32kHz clock. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ + +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..FRO 96 MHz clock. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USB0CLKSEL - FS USB clock source select */ +/*! @{ */ + +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +/*! SEL - FS USB clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) +/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..MCLK clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSELX - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSELX */ +#define SYSCON_FCCLKSELX_COUNT (8U) + +/*! @name HSLSPICLKSEL - HS LSPI clock source select */ +/*! @{ */ + +#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) +#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) +/*! SEL - HS LSPI clock source select. + * 0b000..Main clock. + * 0b001..system PLL divided clock. + * 0b010..FRO 12 MHz clock. + * 0b011..FRO 96 MHz clock. + * 0b100..FRO 1MHz clock. + * 0b101..No clock. + * 0b110..Oscillator 32 kHz clock. + * 0b111..No clock. + */ +#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ + +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK clock source select. + * 0b000..FRO 96 MHz clock. + * 0b001..PLL0 clock. + * 0b010..Reserved. + * 0b011..Reserved. + * 0b100..No clock. + * 0b101..No clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +/*! @{ */ + +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +/*! SEL - SCTimer/PWM clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..CLKIN clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..MCLK clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SDIOCLKSEL - SDIO clock source select */ +/*! @{ */ + +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - SDIO clock source select. + * 0b000..Main clock. + * 0b001..PLL0 clock. + * 0b010..No clock. + * 0b011..FRO 96 MHz clock. + * 0b100..No clock. + * 0b101..PLL1 clock. + * 0b110..No clock. + * 0b111..No clock. + */ +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK) +/*! @} */ + +/*! @name TRACECLKDIV - TRACE clock divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ +/*! @{ */ + +#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ +/*! @{ */ + +#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ +/*! @{ */ + +#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ +/*! @{ */ + +#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ +/*! @{ */ + +#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ +/*! @{ */ + +#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ +/*! @{ */ + +#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ +/*! @{ */ + +#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) +#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + +#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) +#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ +#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) +/*! @} */ + +/*! @name FLEXFRGXCTRL - Peripheral reset control register */ +/*! @{ */ + +#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value + */ +#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXFRGXCTRL */ +#define SYSCON_FLEXFRGXCTRL_COUNT (8U) + +/*! @name AHBCLKDIV - System clock divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + +#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name WDTCLKDIV - WDT clock divider */ +/*! @{ */ + +#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + +#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + +#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + +#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ + +#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name USB0CLKDIV - USB0 Clock divider */ +/*! @{ */ + +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ + +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +/*! @{ */ + +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name SDIOCLKDIV - SDIO clock divider */ +/*! @{ */ + +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) + +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) + +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) + +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name PLL0CLKDIV - PLL0 clock divider */ +/*! @{ */ + +#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ +#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + +#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter. + * 0b1..Divider is reset. + * 0b0..Divider is not reset. + */ +#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + +#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter. + * 0b1..Divider clock is stoped. + * 0b0..Divider clock is running. + */ +#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + +#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) +/*! REQFLAG - Divider status flag. + * 0b1..Clock frequency is not stable. + * 0b0..Divider clock is stable. + */ +#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK) +/*! @} */ + +/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ +/*! @{ */ + +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) +/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). + * 0b00000000000000000000000000000001..update all clock configuration. + * 0b00000000000000000000000000000000..all hardware clock configruration are freeze. + */ +#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) +/*! @} */ + +/*! @name FMCCR - FMC configuration register */ +/*! @{ */ + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + */ +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. + */ +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + +#define SYSCON_FMCCR_ACCEL_MASK (0x10U) +#define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ +#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + +#define SYSCON_FMCCR_PREFEN_MASK (0x20U) +#define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ +#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + +#define SYSCON_FMCCR_PREFOVR_MASK (0x40U) +#define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ +#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. + * 0b0..Under hardware control. + * 0b1..Forced high. + */ +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. + * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. + * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ +/*! @{ */ + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. + * 0b1..USB0 Device clock is high. + * 0b0..USB0 Device clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. + * 0b1..USB0 Host clock is high. + * 0b0..USB0 Host clock is low. + */ +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name FMCFLUSH - FMCflush control */ +/*! @{ */ + +#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) +#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ +#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK control */ +/*! @{ */ + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) +#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) +/*! MCLKIO - MCLK control. + * 0b0..input mode. + * 0b1..output mode. + */ +#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. + */ +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. + */ +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. + */ +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) +/*! @} */ + +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ +/*! @{ */ + +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. + */ +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) +/*! @} */ + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +/*! @{ */ + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + * 0b00..0 degree shift. + * 0b01..90 degree shift. + * 0b10..180 degree shift. + * 0b11..270 degree shift. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) + +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. + * 0b0..Bypassed. + * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. + */ +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. + * 0b1..Enable drive delay. + * 0b0..Disable drive delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) + +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. + * 0b1..Enables sample delay. + * 0b0..Disables sample delay. + */ +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) +/*! @} */ + +/*! @name PLL1CTRL - PLL1 550m control */ +/*! @{ */ + +#define SYSCON_PLL1CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + +#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + +#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..Enable the output clock. + * 0b0..Disable the output clock. + */ +#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + +#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ +#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - Skew mode. + * 0b1..skewmode is enable. + * 0b0..skewmode is disable. + */ +#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL1STAT - PLL1 550m status */ +/*! @{ */ + +#define SYSCON_PLL1STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + +#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + +#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL1NDEC - PLL1 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + +#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL1MDEC - PLL1 550m M divider */ +/*! @{ */ + +#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) +#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ +#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + +#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) +#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ +#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) +/*! @} */ + +/*! @name PLL1PDEC - PLL1 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + +#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0CTRL - PLL0 550m control */ +/*! @{ */ + +#define SYSCON_PLL0CTRL_SELR_MASK (0xFU) +#define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ +#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + +#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) +#define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ +#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + +#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) +#define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ +#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) +#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) +/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). + * 0b1..Bypass PLL input clock is sent directly to the PLL output. + * 0b0..use PLL. + */ +#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. + * 0b1..bypass of the divide-by-2 divider in the post-divider. + * 0b0..use the divide-by-2 divider in the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + +#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) +#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ +#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + +#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) +#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) +/*! BWDIRECT - Control of the bandwidth of the PLL. + * 0b1..modify the bandwidth of the PLL directly. + * 0b0..the bandwidth is changed synchronously with the feedback-divider. + */ +#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) +#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - bypass of the pre-divider. + * 0b1..bypass of the pre-divider. + * 0b0..use the pre-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - bypass of the post-divider. + * 0b1..bypass of the post-divider. + * 0b0..use the post-divider. + */ +#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + +#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) +#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) +/*! CLKEN - enable the output clock. + * 0b1..enable the output clock. + * 0b0..disable the output clock. + */ +#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + +#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) +#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - free running mode. + * 0b1..free running mode is enable. + * 0b0..free running mode is disable. + */ +#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) +#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ +#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + +#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) +#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) +/*! SKEWEN - skew mode. + * 0b1..skew mode is enable. + * 0b0..skew mode is disable. + */ +#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK) +/*! @} */ + +/*! @name PLL0STAT - PLL0 550m status */ +/*! @{ */ + +#define SYSCON_PLL0STAT_LOCK_MASK (0x1U) +#define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ +#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + +#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) +#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + +#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) +#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + +#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) +#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ +#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + +#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) +#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ +#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) +/*! @} */ + +/*! @name PLL0NDEC - PLL0 550m N divider */ +/*! @{ */ + +#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) +#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ +#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + +#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) +#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ +#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) +/*! @} */ + +/*! @name PLL0PDEC - PLL0 550m P divider */ +/*! @{ */ + +#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) +#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ +#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + +#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) +#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ +#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) +/*! @} */ + +/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) +#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ +#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) +/*! @} */ + +/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ +/*! @{ */ + +#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) +#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ +#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + +#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) +#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ +#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + +#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) +#define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ +#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + +#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) +#define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ +#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + +#define SYSCON_PLL0SSCG1_MC_MASK (0x300U) +#define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ +#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + +#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) +#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ +#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + +#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) +#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ +#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + +#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) +#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ +#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + +#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) +#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ +#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) +/*! @} */ + +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ +/*! @{ */ + +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. + */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) + +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) +/*! @} */ + +/*! @name CPUCTRL - CPU Control for multiple processors */ +/*! @{ */ + +#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) +#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) +/*! CPU1CLKEN - CPU1 clock enable. + * 0b1..The CPU1 clock is enabled. + * 0b0..The CPU1 clock is not enabled. + */ +#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) + +#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) +#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) +/*! CPU1RSTEN - CPU1 reset. + * 0b1..The CPU1 is being reset. + * 0b0..The CPU1 is not being reset. + */ +#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK) +/*! @} */ + +/*! @name CPBOOT - Coprocessor Boot Address */ +/*! @{ */ + +#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) +#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +/*! CPBOOT - Coprocessor Boot Address for CPU1. + */ +#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) +/*! @} */ + +/*! @name CPSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - The CPU0 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) +#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) +/*! CPU1SLEEPING - The CPU1 sleeping state. + * 0b1..the CPU is sleeping. + * 0b0..the CPU is not sleeping. + */ +#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) + +#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - The CPU0 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) + +#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) +#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) +/*! CPU1LOCKUP - The CPU1 lockup state. + * 0b1..the CPU is in lockup. + * 0b0..the CPU is not in lockup. + */ +#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) +/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) +/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) +/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) +/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enable clock_in clock for clock module. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) +/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) +/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) +/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. + * 0b1..The clock is enabled. + * 0b0..The clock is not enabled. + */ +#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK) +/*! @} */ + +/*! @name COMP_INT_CTRL - Comparator Interrupt control */ +/*! @{ */ + +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) +#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) +/*! INT_ENABLE - Analog Comparator interrupt enable control:. + * 0b1..interrupt enable. + * 0b0..interrupt disable. + */ +#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) +#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) +/*! INT_CLEAR - Analog Comparator interrupt clear. + * 0b0..No effect. + * 0b1..Clear the interrupt. Self-cleared bit. + */ +#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) +#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) +/*! INT_CTRL - Comparator interrupt type selector:. + * 0b000..The analog comparator interrupt edge sensitive is disabled. + * 0b010..analog comparator interrupt is rising edge sensitive. + * 0b100..analog comparator interrupt is falling edge sensitive. + * 0b110..analog comparator interrupt is rising and falling edge sensitive. + * 0b001..The analog comparator interrupt level sensitive is disabled. + * 0b011..Analog Comparator interrupt is high level sensitive. + * 0b101..Analog Comparator interrupt is low level sensitive. + * 0b111..The analog comparator interrupt level sensitive is disabled. + */ +#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) +#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) +/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. + * 0b0..Select Analog Comparator filtered output as input for interrupt detection. + * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when + * Analog comparator is used as wake up source in Power down mode. + */ +#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK) +/*! @} */ + +/*! @name COMP_INT_STATUS - Comparator Interrupt status */ +/*! @{ */ + +#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) +#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Interrupt status BEFORE Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) +#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) +/*! INT_STATUS - Interrupt status AFTER Interrupt Enable. + * 0b0..no interrupt pending. + * 0b1..interrupt pending. + */ +#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + +#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) +#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) +/*! VAL - comparator analog output. + * 0b1..P+ is greater than P-. + * 0b0..P+ is smaller than P-. + */ +#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) +/*! ROM - Control automatic clock gating of ROM controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) +/*! RAMX_CTRL - Control automatic clock gating of RAMX controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) +/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) +/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) +/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) +/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) +/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) +/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) +/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) +/*! CRCGEN - Control automatic clock gating of CRCGEN controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) +/*! SDMA0 - Control automatic clock gating of DMA0 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) +/*! SDMA1 - Control automatic clock gating of DMA1 controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) +/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. + * 0b1..Automatic clock gating is overridden (Clock gating is disabled). + * 0b0..Automatic clock gating is not overridden. + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) +/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) +/*! @} */ + +/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ +/*! @{ */ + +#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) +#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) +/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. + * 0b1..bypass of the first stage of synchonization inside GPIO_INT module. + * 0b0..use the first stage of synchonization inside GPIO_INT module. + */ +#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * 0b1010..1010: Enable write access to all 6 registers. + * 0b0000..Any other value than b1010: disable write access to all 6 registers. + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. + * 0b10..10: Invasive debug is enabled. + * 0b01..Any other value than b10: invasive debug is disable. + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) +/*! @} */ + +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ +/*! @{ */ + +#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) +#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. + */ +#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name CPUCFG - CPUs configuration register */ +/*! @{ */ + +#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) +#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) +/*! CPU1ENABLE - Enable CPU1. + * 0b0..CPU1 is disable (Processor in reset). + * 0b1..CPU1 is enable. + */ +#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_REV_ID_MASK (0xFU) +#define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ +#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x50000000u) + /** Peripheral SYSCON base address */ + #define SYSCON_BASE_NS (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Peripheral SYSCON base pointer */ + #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON_NS } +#else + /** Peripheral SYSCON base address */ + #define SYSCON_BASE (0x40000000u) + /** Peripheral SYSCON base pointer */ + #define SYSCON ((SYSCON_Type *)SYSCON_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON } +#endif + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCTL Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer + * @{ + */ + +/** SYSCTL - Register Layout Typedef */ +typedef struct { + __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; + __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */ +} SYSCTL_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCTL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks + * @{ + */ + +/*! @name UPDATELCKOUT - update lock out control */ +/*! @{ */ + +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) +/*! UPDATELCKOUT - All Registers + * 0b0..Normal Mode. Can be written to. + * 0b1..Protected Mode. Cannot be written to. + */ +#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK) +/*! @} */ + +/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ +/*! @{ */ + +#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) +#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) +/*! SCKINSEL - Selects the source for SCK going into this Flexcomm. + * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm. + * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) +#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) +/*! WSINSEL - Selects the source for WS going into this Flexcomm. + * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm. + * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) +#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) +/*! DATAINSEL - Selects the source for DATA input to this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm. + * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) +#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) +/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. + * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm. + * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0). + * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1). + * 0b11..Reserved. + */ +#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK) +/*! @} */ + +/* The count of SYSCTL_FCCTRLSEL */ +#define SYSCTL_FCCTRLSEL_COUNT (8U) + +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @{ */ + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) +/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. + * 0b000..SCK for this shared signal set comes from Flexcomm 0. + * 0b001..SCK for this shared signal set comes from Flexcomm 1. + * 0b010..SCK for this shared signal set comes from Flexcomm 2. + * 0b011..SCK for this shared signal set comes from Flexcomm 3. + * 0b100..SCK for this shared signal set comes from Flexcomm 4. + * 0b101..SCK for this shared signal set comes from Flexcomm 5. + * 0b110..SCK for this shared signal set comes from Flexcomm 6. + * 0b111..SCK for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +/*! SHAREDWSSEL - Selects the source for WS of this shared signal set. + * 0b000..WS for this shared signal set comes from Flexcomm 0. + * 0b001..WS for this shared signal set comes from Flexcomm 1. + * 0b010..WS for this shared signal set comes from Flexcomm 2. + * 0b011..WS for this shared signal set comes from Flexcomm 3. + * 0b100..WS for this shared signal set comes from Flexcomm 4. + * 0b101..WS for this shared signal set comes from Flexcomm 5. + * 0b110..WS for this shared signal set comes from Flexcomm 6. + * 0b111..WS for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. + * 0b000..DATA input for this shared signal set comes from Flexcomm 0. + * 0b001..DATA input for this shared signal set comes from Flexcomm 1. + * 0b010..DATA input for this shared signal set comes from Flexcomm 2. + * 0b011..DATA input for this shared signal set comes from Flexcomm 3. + * 0b100..DATA input for this shared signal set comes from Flexcomm 4. + * 0b101..DATA input for this shared signal set comes from Flexcomm 5. + * 0b110..DATA input for this shared signal set comes from Flexcomm 6. + * 0b111..DATA input for this shared signal set comes from Flexcomm 7. + */ +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC0 does not contribute to this shared set. + * 0b1..Data output from FC0 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC1 does not contribute to this shared set. + * 0b1..Data output from FC1 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC2 does not contribute to this shared set. + * 0b1..Data output from FC2 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC4 does not contribute to this shared set. + * 0b1..Data output from FC4 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC5 does not contribute to this shared set. + * 0b1..Data output from FC5 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC6 does not contribute to this shared set. + * 0b1..Data output from FC6 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. + * 0b0..Data output from FC7 does not contribute to this shared set. + * 0b1..Data output from FC7 does contribute to this shared set. + */ +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +/*! @} */ + +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) + +/*! @name USB_HS_STATUS - Status register for USB HS */ +/*! @{ */ + +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) +/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. + * 0b0..3v3 supply is good. + * 0b1..3v3 supply is too low. + */ +#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCTL_Register_Masks */ + + +/* SYSCTL - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x50023000u) + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE_NS (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS } +#else + /** Peripheral SYSCTL base address */ + #define SYSCTL_BASE (0x40023000u) + /** Peripheral SYSCTL base pointer */ + #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE) + /** Array initializer of SYSCTL peripheral base addresses */ + #define SYSCTL_BASE_ADDRS { SYSCTL_BASE } + /** Array initializer of SYSCTL peripheral base pointers */ + #define SYSCTL_BASE_PTRS { SYSCTL } +#endif + +/*! + * @} + */ /* end of group SYSCTL_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ + +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, + * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control + * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the + * transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, + * and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, + * and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input + * pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial + * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD + * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device + * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the + * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins + * before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the + * possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in + * the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start + * bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is + * 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is + * 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value + * is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ + +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit + * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the + * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled + * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data + * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, + * generating a received data interrupt. Software can then check the data to see if this is an address that + * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled + * normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This + * feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to + * complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on + * Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The + * first start bit of RX is measured and used the update the BRG register to match the received data rate. + * AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ + +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + */ +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + */ +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + */ +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ + +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + */ +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. + */ +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. + */ +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. + */ +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. + */ +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + */ +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. + */ +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ + +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ + +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ + +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. + */ +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. + */ +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. + */ +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. + */ +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. + */ +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. + */ +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. + */ +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. + */ +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. + */ +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ + +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ + +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ + +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in + * FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power + * modes (up to power-down, as long as the peripheral function works in that power mode) without + * enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The + * CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware + * Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in + * FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. + */ +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ + +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ + +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled + * in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases + * to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level + * specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level + * increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ + +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ + +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ + +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ + +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ + +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ + +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USART0 base address */ + #define USART0_BASE (0x50086000u) + /** Peripheral USART0 base address */ + #define USART0_BASE_NS (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART0 base pointer */ + #define USART0_NS ((USART_Type *)USART0_BASE_NS) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x50087000u) + /** Peripheral USART1 base address */ + #define USART1_BASE_NS (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART1 base pointer */ + #define USART1_NS ((USART_Type *)USART1_BASE_NS) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x50088000u) + /** Peripheral USART2 base address */ + #define USART2_BASE_NS (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART2 base pointer */ + #define USART2_NS ((USART_Type *)USART2_BASE_NS) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x50089000u) + /** Peripheral USART3 base address */ + #define USART3_BASE_NS (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART3 base pointer */ + #define USART3_NS ((USART_Type *)USART3_BASE_NS) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x5008A000u) + /** Peripheral USART4 base address */ + #define USART4_BASE_NS (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART4 base pointer */ + #define USART4_NS ((USART_Type *)USART4_BASE_NS) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x50096000u) + /** Peripheral USART5 base address */ + #define USART5_BASE_NS (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART5 base pointer */ + #define USART5_NS ((USART_Type *)USART5_BASE_NS) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x50097000u) + /** Peripheral USART6 base address */ + #define USART6_BASE_NS (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART6 base pointer */ + #define USART6_NS ((USART_Type *)USART6_BASE_NS) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x50098000u) + /** Peripheral USART7 base address */ + #define USART7_BASE_NS (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Peripheral USART7 base pointer */ + #define USART7_NS ((USART_Type *)USART7_BASE_NS) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS } +#else + /** Peripheral USART0 base address */ + #define USART0_BASE (0x40086000u) + /** Peripheral USART0 base pointer */ + #define USART0 ((USART_Type *)USART0_BASE) + /** Peripheral USART1 base address */ + #define USART1_BASE (0x40087000u) + /** Peripheral USART1 base pointer */ + #define USART1 ((USART_Type *)USART1_BASE) + /** Peripheral USART2 base address */ + #define USART2_BASE (0x40088000u) + /** Peripheral USART2 base pointer */ + #define USART2 ((USART_Type *)USART2_BASE) + /** Peripheral USART3 base address */ + #define USART3_BASE (0x40089000u) + /** Peripheral USART3 base pointer */ + #define USART3 ((USART_Type *)USART3_BASE) + /** Peripheral USART4 base address */ + #define USART4_BASE (0x4008A000u) + /** Peripheral USART4 base pointer */ + #define USART4 ((USART_Type *)USART4_BASE) + /** Peripheral USART5 base address */ + #define USART5_BASE (0x40096000u) + /** Peripheral USART5 base pointer */ + #define USART5 ((USART_Type *)USART5_BASE) + /** Peripheral USART6 base address */ + #define USART6_BASE (0x40097000u) + /** Peripheral USART6 base pointer */ + #define USART6 ((USART_Type *)USART6_BASE) + /** Peripheral USART7 base address */ + #define USART7_BASE (0x40098000u) + /** Peripheral USART7 base pointer */ + #define USART7 ((USART_Type *)USART7_BASE) + /** Array initializer of USART peripheral base addresses */ + #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } + /** Array initializer of USART peripheral base pointers */ + #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +#endif +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + */ +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + */ +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USB0 base address */ + #define USB0_BASE (0x50084000u) + /** Peripheral USB0 base address */ + #define USB0_BASE_NS (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Peripheral USB0 base pointer */ + #define USB0_NS ((USB_Type *)USB0_BASE_NS) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS_NS { USB0_BASE_NS } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS_NS { USB0_NS } +#else + /** Peripheral USB0 base address */ + #define USB0_BASE (0x40084000u) + /** Peripheral USB0 base pointer */ + #define USB0 ((USB_Type *)USB0_BASE) + /** Array initializer of USB peripheral base addresses */ + #define USB_BASE_ADDRS { USB0_BASE } + /** Array initializer of USB peripheral base pointers */ + #define USB_BASE_PTRS { USB0 } +#endif +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +/*! @{ */ + +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. + */ +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) +/*! @} */ + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +/*! @{ */ + +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + */ +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) +/*! @} */ + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +/*! @{ */ + +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. + */ +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + */ +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + */ +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + */ +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. + */ +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + */ +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) +/*! @} */ + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) +/*! @} */ + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +/*! @{ */ + +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + */ +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) +/*! @} */ + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +/*! @{ */ + +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. + */ +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) +/*! @} */ + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +/*! @{ */ + +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) +/*! @} */ + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) +/*! @} */ + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +/*! @{ */ + +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. + */ +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) +/*! @} */ + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) +/*! @} */ + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +/*! @{ */ + +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. + */ +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) +/*! @} */ + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +/*! @{ */ + +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) +/*! @} */ + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +/*! @{ */ + +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + */ +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) +/*! @} */ + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +/*! @{ */ + +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. + */ +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) +/*! @} */ + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +/*! @{ */ + +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. + */ +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) +/*! @} */ + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +/*! @{ */ + +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + */ +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) +/*! @} */ + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +/*! @{ */ + +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + */ +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + */ +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. + */ +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + */ +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) +/*! @} */ + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +/*! @{ */ + +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. + */ +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) +/*! @} */ + +/*! @name HCRHSTATUS - This register is divided into two parts */ +/*! @{ */ + +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + */ +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. + */ +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + */ +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + */ +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) +/*! @} */ + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +/*! @{ */ + +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + */ +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + */ +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + */ +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + */ +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + */ +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + */ +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + */ +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. + */ +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + */ +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + */ +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. + */ +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x500A2000u) + /** Peripheral USBFSH base address */ + #define USBFSH_BASE_NS (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Peripheral USBFSH base pointer */ + #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS_NS { USBFSH_NS } +#else + /** Peripheral USBFSH base address */ + #define USBFSH_BASE (0x400A2000u) + /** Peripheral USBFSH base pointer */ + #define USBFSH ((USBFSH_Type *)USBFSH_BASE) + /** Array initializer of USBFSH peripheral base addresses */ + #define USBFSH_BASE_ADDRS { USBFSH_BASE } + /** Array initializer of USBFSH peripheral base pointers */ + #define USBFSH_BASE_PTRS { USBFSH } +#endif +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ + +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. + */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. + */ +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. + */ +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. + */ +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. + */ +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. + */ +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. + */ +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. + */ +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. + */ +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. + */ +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. + */ +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. + */ +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. + */ +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ + +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. + */ +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. + */ +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. + */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. + */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ + +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. + */ +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ + +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. + */ +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ + +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. + */ +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. + */ +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ + +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ + +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. + */ +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ + +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. + */ +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. + */ +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. + */ +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. + */ +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. + */ +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. + */ +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. + */ +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. + */ +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. + */ +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. + */ +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. + */ +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. + */ +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. + */ +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. + */ +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. + */ +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ + +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ + +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ + +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x50094000u) + /** Peripheral USBHSD base address */ + #define USBHSD_BASE_NS (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Peripheral USBHSD base pointer */ + #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS_NS { USBHSD_NS } +#else + /** Peripheral USBHSD base address */ + #define USBHSD_BASE (0x40094000u) + /** Peripheral USBHSD base pointer */ + #define USBHSD ((USBHSD_Type *)USBHSD_BASE) + /** Array initializer of USBHSD peripheral base addresses */ + #define USBHSD_BASE_ADDRS { USBHSD_BASE } + /** Array initializer of USBHSD peripheral base pointers */ + #define USBHSD_BASE_PTRS { USBHSD } +#endif +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +/*! @{ */ + +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. + */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. + */ +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. + */ +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. + */ +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) +/*! @} */ + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +/*! @{ */ + +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. + */ +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + */ +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. + */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. + */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) +/*! @} */ + +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ +/*! @{ */ + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. + */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. + */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) +/*! @} */ + +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ +/*! @{ */ + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. + */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. + */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) +/*! @} */ + +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ +/*! @{ */ + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. + */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command register */ +/*! @{ */ + +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. + */ +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. + */ +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. + */ +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. + */ +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. + */ +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. + */ +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +/*! @} */ + +/*! @name USBSTS - USB Interrupt Status register */ +/*! @{ */ + +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + */ +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + */ +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) +/*! @} */ + +/*! @name USBINTR - USB Interrupt Enable register */ +/*! @{ */ + +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. + */ +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status and Control register */ +/*! @{ */ + +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. + */ +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. + */ +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. + */ +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + */ +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. + */ +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. + */ +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + */ +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. + */ +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. + */ +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) + +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + */ +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + */ +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + */ +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + */ +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +/*! @} */ + +/*! @name ATLPTDD - Done map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) +/*! @} */ + +/*! @name ATLPTDS - Skip map for each ATL PTD */ +/*! @{ */ + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) +/*! @} */ + +/*! @name ISOPTDD - Done map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) +/*! @} */ + +/*! @name ISOPTDS - Skip map for each ISO PTD */ +/*! @{ */ + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) +/*! @} */ + +/*! @name INTPTDD - Done map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) +/*! @} */ + +/*! @name INTPTDS - Skip map for each INT PTD */ +/*! @{ */ + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) +/*! @} */ + +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @{ */ + +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. + */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. + */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) +/*! @} */ + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +/*! @{ */ + +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. + */ +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. + */ +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. + */ +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x500A3000u) + /** Peripheral USBHSH base address */ + #define USBHSH_BASE_NS (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Peripheral USBHSH base pointer */ + #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS_NS { USBHSH_NS } +#else + /** Peripheral USBHSH base address */ + #define USBHSH_BASE (0x400A3000u) + /** Peripheral USBHSH base pointer */ + #define USBHSH ((USBHSH_Type *)USBHSH_BASE) + /** Array initializer of USBHSH peripheral base addresses */ + #define USBHSH_BASE_ADDRS { USBHSH_BASE } + /** Array initializer of USBHSH peripheral base pointers */ + #define USBHSH_BASE_PTRS { USBHSH } +#endif +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; + __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ + uint8_t RESERVED_1[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ + uint8_t RESERVED_2[48]; + __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'ANACTRL' */ + __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the + */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the + */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I + * 0b0..Normal operation. + * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror + */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) + */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 + * 0b0..Normal operation. + * 0b1..Power-down the USB full-speed differential receiver. + */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF + * 0b0..Normal operation. + * 0b1..Power-down the USB high-speed differential receive + */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX + * 0b0..Normal operation. + * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver + */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + +#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + +#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + +#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + +#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + +#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL + * 0b0000..Maximum current, approximately 19% above nominal. + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal. + */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) +#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) +#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + +#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) +#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) +#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ + * 0b000..Trip-Level Voltage is 0.1000 V + * 0b001..Trip-Level Voltage is 0.1125 V + * 0b010..Trip-Level Voltage is 0.1250 V + * 0b011..Trip-Level Voltage is 0.0875 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ + * 0b000..Trip-Level Voltage is 0.56875 V + * 0b001..Trip-Level Voltage is 0.55000 V + * 0b010..Trip-Level Voltage is 0.58125 V + * 0b011..Trip-Level Voltage is 0.60000 V + * 0b100..reserved + * 0b101..reserved + * 0b110..reserved + * 0b111..reserved + */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +/*! RXDBYPASS + * 0b0..Normal operation. + * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver + */ +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) +/*! ENDEVPLUGINDET + * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) + * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS + * 0b0..USB cable disconnect has not been detected at the local host + * 0b1..USB cable disconnect has been detected at the local host + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS + * 0b0..No attachment to a USB host is detected + * 0b1..Cable attachment to a USB host is detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name PLL_SIC - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL + * 0b0..Selects PLL_POWER to control the reference bias + * 0b1..Selects REFBIAS_PWD to control the reference bias + */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL + * 0b000..Divide by 13 + * 0b001..Divide by 15 + * 0b010..Divide by 16 + * 0b011..Divide by 20 + * 0b100..Divide by 22 + * 0b101..Divide by 25 + * 0b110..Divide by 30 + * 0b111..Divide by 240 + */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK + * 0b0..PLL is not currently locked + * 0b1..PLL is currently locked + */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V(Default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN + * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) + * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL + * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL + * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) + * 0b01..Use the Session Valid comparator results for signal reported to the USB controller + * 0b10..Use the Session Valid comparator results for signal reported to the USB controller + * 0b11..Reserved, do not use + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) +/*! VBUSVALID_TO_SESSVALID + * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results + * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) +/*! PWRUP_CMPS + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS + * 0b0..VBUS discharge resistor is disabled (Default) + * 0b1..VBUS discharge resistor is enabled + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name ANACTRL - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - USB PHY Analog Control Register */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. + */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x50038000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x40038000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x5000E000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x4000E000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the + * watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. + */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. + */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. + */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. + */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. + */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x5000C000u) + /** Peripheral WWDT base address */ + #define WWDT_BASE_NS (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Peripheral WWDT base pointer */ + #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT_NS } +#else + /** Peripheral WWDT base address */ + #define WWDT_BASE (0x4000C000u) + /** Peripheral WWDT base pointer */ + #define WWDT ((WWDT_Type *)WWDT_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; + + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; + + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC55S69_CM33_CORE1_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h new file mode 100644 index 000000000..9fb832c67 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/LPC55S69_cm33_core1_features.h @@ -0,0 +1,501 @@ +/* +** ################################################################### +** Version: rev. 1.1, 2019-05-16 +** Build: b231017 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +#ifndef _LPC55S69_cm33_core1_FEATURES_H_ +#define _LPC55S69_cm33_core1_FEATURES_H_ + +/* SOC module features */ + +/* @brief CASPER availability on the SoC. */ +#define FSL_FEATURE_SOC_CASPER_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (2) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief SECGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SECGPIO_COUNT (1) +/* @brief HASHCRYPT availability on the SoC. */ +#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (8) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (1) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (1) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief SECPINT availability on the SoC. */ +#define FSL_FEATURE_SOC_SECPINT_COUNT (1) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (1) +/* @brief POWERQUAD availability on the SoC. */ +#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (1) +/* @brief LPC_RNG1 availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (9) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSCTL1 availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Chip Rev 0A Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_0A (770.0f) +/* @brief Chip Rev 0A Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_0A (289.4f) +/* @brief Chip Rev 0A Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_0A (9.5f) +/* @brief Chip Rev 1B Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A_CHIP_REV_1B (804.0f) +/* @brief Chip Rev 1B Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B_CHIP_REV_1B (280.0f) +/* @brief Chip Rev 1B Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA_CHIP_REV_1B (8.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) + +/* CASPER module features */ + +/* @brief Base address of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) +/* @brief SW interleaving of the CASPER dedicated RAM */ +#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* GINT module features */ + +/* @brief The count of th port which are supported in GINT. */ +#define FSL_FEATURE_GINT_PORT_COUNT (2) + +/* HASHCRYPT module features */ + +/* @brief the address of alias offset */ +#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer. */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (0) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_B (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +/* POWERLIB module features */ + +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* POWERQUAD module features */ + +/* @brief Sine and Cossine fix errata */ +#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) + +/* PUF module features */ + +/* @brief Number of PUF key slots available on device. */ +#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) +/* @brief the shift status value */ +#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (648704) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1192) + +/* RTC module features */ + +/* @brief Has SUBSEC Register (register SUBSEC) */ +#define FSL_FEATURE_RTC_HAS_SUBSEC (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +/* @brief support 2 cards */ +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) + +/* SECPINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) + +/* SPI module features */ + +/* @brief SSEL pin count. */ +#define FSL_FEATURE_SPI_SSEL_COUNT (4) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) +/* @brief Has Power Down mode */ +#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USB version */ +#define FSL_FEATURE_USB_VERSION (200) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBFSH version */ +#define FSL_FEATURE_USBFSH_VERSION (200) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBHSD_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSH version */ +#define FSL_FEATURE_USBHSH_VERSION (300) + +/* USBPHY module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support oscillator lock. */ +#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) + +#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ + diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c new file mode 100644 index 000000000..8a97b6467 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.c @@ -0,0 +1,2137 @@ +/* + * Copyright 2017 - 2021 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) + +/* PLL0 SSCG control1 */ +#define PLL0_SSCG_MD_FRACT_P 0U +#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) + +#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll0_Freq; +static uint32_t s_Pll1_Freq; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_PLU_ClkIn_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void); +/* Get multiplier (M) from PLL0 MDEC and SSCG settings */ +static float findPll0MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_RTCOSC32KCLKSEL) + { + PMC->RTCOSC32K = (PMC->RTCOSC32K & ~PMC_RTCOSC32K_SEL_MASK) | PMC_RTCOSC32K_SEL(sel); + } + else + { + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSELX[0]); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_RTCOSC32KCLKSEL) + { + actualSel = (uint8_t)(PMC->RTCOSC32K); + } + else + { + actualSel = (uint8_t)(pClkSel[mux]); + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV0); + if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) + { + /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = + SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); + } + else + { + if (reset) + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } + } +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1khz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value) +{ + PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK); +} + +/* Set RTC 1KHz Clock Divider */ +/** + * brief Setup rtc 1hz clock divider. + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) +{ + if (divided_by_value == 0U) /*!< halt */ + { + PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + } + else + { + PMC->RTCOSC32K |= + (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Enable Analog Control module */ + SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; + /* Power up the FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + + if (iFreq == 96000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); + } + /* always enable + else if (iFreq == 48000000U) + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); + }*/ + else + { + ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); + } + return kStatus_Success; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ + uint32_t prefetch_enable_mask = SYSCON->FMCCR & SYSCON_FMCCR_PREFEN_MASK; + + if (iFreq <= 11000000UL) + { + /* [0 - 11 MHz] */ + num_wait_states = 0UL; + } + else if (iFreq <= 22000000UL) + { + /* [11 MHz - 22 MHz] */ + num_wait_states = 1UL; + } + else if (iFreq <= 33000000UL) + { + /* [22 MHz - 33 MHz] */ + num_wait_states = 2UL; + } + else if (iFreq <= 44000000UL) + { + /* [33 MHz - 44 MHz] */ + num_wait_states = 3UL; + } + else if (iFreq <= 55000000UL) + { + /* [44 MHz - 55 MHz] */ + num_wait_states = 4UL; + } + else if (iFreq <= 66000000UL) + { + /* [55 MHz - 662 MHz] */ + num_wait_states = 5UL; + } + else if (iFreq <= 77000000UL) + { + /* [66 MHz - 77 MHz] */ + num_wait_states = 6UL; + } + else if (iFreq <= 88000000UL) + { + /* [77 MHz - 88 MHz] */ + num_wait_states = 7UL; + } + else if (iFreq <= 100000000UL) + { + /* [88 MHz - 100 MHz] */ + num_wait_states = 8UL; + } + else if (iFreq <= 115000000UL) + { + /* [100 MHz - 115 MHz] */ + num_wait_states = 9UL; + } + else if (iFreq <= 130000000UL) + { + /* [115 MHz - 130 MHz] */ + num_wait_states = 10UL; + } + else if (iFreq <= 150000000UL) + { + /* [130 MHz - 150 MHz] */ + num_wait_states = 11UL; + } + else + { + /* Above 150 MHz */ + num_wait_states = 12UL; + } + + /*The prefetch bit must be disabled before any flash commands*/ + SYSCON->FMCCR &= ~SYSCON_FMCCR_PREFEN_MASK; + + FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ + + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | + (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + + FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ + + /* Wait until the cmd is completed (without error) */ + while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + { + ; + } + + /* Adjust FMC waiting time cycles (num_wait_states) */ + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | + ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); + + /* restore prefetch enable */ + SYSCON->FMCCR |= prefetch_enable_mask; +} + +/* Set EXT OSC Clk */ +/** + * brief Initialize the external osc clock to given frequency. + * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. + * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + if (iFreq > 32000000U) + { + return kStatus_Fail; + } + /* Turn on power for crystal 32 MHz */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + /* Enable clock_in clock for clock module. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; + + /* Wait for external osc clock to be valid. */ + while((ANACTRL->XO32M_STATUS & ANACTRL_XO32M_STATUS_XO_READY_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + return kStatus_Success; +} + +/* Set I2S MCLK Clk */ +/** + * brief Initialize the I2S MCLK clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) +{ + s_I2S_Mclk_Freq = iFreq; + return kStatus_Success; +} + +/* Set PLU CLKIN Clk */ +/** + * brief Initialize the PLU CLKIN clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) +{ + s_PLU_ClkIn_Freq = iFreq; + return kStatus_Success; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U); +} + +/* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); +} + +/* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); +} + +/* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); +} + +/* Get SDIO Clk */ +/*! brief Return Frequency of SDIO Clock + * return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->SDIOCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + assert(false); + break; + } + + return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void) +{ + return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U); +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + return s_Pll0_Freq; +} + +/* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + return s_Pll1_Freq; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetFro1MFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ + } + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return s_I2S_Mclk_Freq; +} + +/* Get PLU CLKIN Clk */ +/*! brief Return Frequency of PLU CLKIN Clock + * return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void) +{ + return s_PLU_ClkIn_Freq; +} + +/* Get FLEXCOMM input clock */ +/*! brief Return Frequency of flexcomm input clock + * param id : flexcomm instance id + * return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t frgMul = 0U; + uint32_t frgDiv = 0U; + + freq = CLOCK_GetFlexCommInputClock(id); + frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; + frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; + return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); +} + +/* Get HS_LPSI Clk */ +uint32_t CLOCK_GetHsLspiClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->HSLSPICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro1MFreq(); + break; + case 5U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 6U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + assert(false); + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + volatile uint32_t *pSystickClkDiv; + pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0); + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSELX[id]) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetFro1MFreq(); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set FlexComm Clock */ +/** + * brief Set the flexcomm output frequency. + * param id : flexcomm instance id + * freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) +{ + uint32_t input = CLOCK_GetFlexCommClkFreq(id); + uint32_t mul; + + if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0UL; + } + else + { + mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); + SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; + return 1UL; + } +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL0 output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0U; + pllSelI = 0U; + pllSelP = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPll0Config(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetFro1MFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL0 output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL0 Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate) +{ + s_Pll0_Freq = rate; +} + +/* Return PLL0 output clock rate */ +/*! brief Return PLL0 output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return PLL0 output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll0_Freq == 0U)) + { + Setup.pllctrl = SYSCON->PLL0CTRL; + Setup.pllndec = SYSCON->PLL0NDEC; + Setup.pllpdec = SYSCON->PLL0PDEC; + Setup.pllsscg[0] = SYSCON->PLL0SSCG0; + Setup.pllsscg[1] = SYSCON->PLL0SSCG1; + + CLOCK_GetPLL0OutFromSetupUpdate(&Setup); + } + + rate = s_Pll0_Freq; + + return rate; +} + +/* Set PLL0 output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetPLL0InClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL0 output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is stable. + The lock bit could be used to shorten the wait time when freq<20MHZ */ + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL0Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetPLL0OutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll0_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL0); + POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG); + + /* Write PLL setup data */ + SYSCON->PLL0CTRL = pSetup->pllctrl; + SYSCON->PLL0NDEC = pSetup->pllndec; + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec; + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; + SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; + SYSCON->PLL0SSCG1 = + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL0); + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) /* normal mode */ + { + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is + stable. The lock bit could be used to shorten the wait time when freq<20MHZ */ + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL0Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + + /* Update current programmed PLL rate var */ + s_Pll0_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + uint32_t pll_lock_wait_time = 0U; + uint32_t max_pll_lock_wait_time = 0U; + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_PLL1); + + /* Write PLL setup data */ + SYSCON->PLL1CTRL = pSetup->pllctrl; + SYSCON->PLL1NDEC = pSetup->pllndec; + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec; + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec; + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + + /* Need wait at least (500us + 400/Fref) (Fref in Hz result in s) to ensure the PLL is stable. + The lock bit could be used to shorten the wait time when freq<20MHZ */ + max_pll_lock_wait_time = 500U + (400000000U / clkRate); + + if (clkRate < 20000000UL) + { + pll_lock_wait_time = 0U; + while ((CLOCK_IsPLL1Locked() == false) && (pll_lock_wait_time < max_pll_lock_wait_time)) + { + pll_lock_wait_time += 100U; + SDK_DelayAtLeastUs(100U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + else + { + SDK_DelayAtLeastUs(max_pll_lock_wait_time, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + } + + /* Update current programmed PLL rate var */ + s_Pll1_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set PLL0 clock based on the input frequency and multiplier */ +/*! brief Set PLL0 output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + + selr = 0U; + + if (multiply_by >= 8000UL) + { + seli = 1UL; + } + else if (multiply_by >= 122UL) + { + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63U) + { + seli = 63U; + } + + { + selp = 31U; + } + + if (pdec > 1U) + { + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + } + + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); + ndec = 0x1U; /* pre divide by 1 (hardcoded) */ + + SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | + SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | + (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0SSCG1 = + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = + ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbfsSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); + /* Enable FRO 96MHz output */ + ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + /* Select FRO 96 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), + .pllndec = SYSCON_PLL1NDEC_NDIV(1U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), + .pllRate = 48000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); + + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); + CLOCK_AttachClk(kPLL1_to_USB0_CLK); + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB PHY clock */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + volatile uint32_t i; + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool ret = true; + + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); + POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */ + POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ + + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); + + /* wait to make sure PHY power is fully up */ + i = 100000U; + while ((i--) != 0U) + { + __ASM("nop"); + } + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + + multiplier = (uint16_t)(480000000UL / freq); + + switch (multiplier) + { + case 15U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 24U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + ret = false; + break; + } + } + + if (ret) + { + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + } + + return ret; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + return true; +} + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) +{ + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1); + SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1); + + /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1); + + return true; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h new file mode 100644 index 000000000..500ef626e --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_clock.h @@ -0,0 +1,1506 @@ +/* + * Copyright 2017 - 2021 , 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.3.8. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 8)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for Mailbox. */ +#define MAILBOX_CLOCKS \ + { \ + kCLOCK_Mailbox \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer0 \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick0 \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for COMP */ +#define COMP_CLOCKS \ + { \ + kCLOCK_Comp \ + } +/*! @brief Clock ip name array for SDIO. */ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ + } +/*! @brief Clock ip name array for USB1CLK. */ +#define USB1CLK_CLOCKS \ + { \ + kCLOCK_Usb1Clk \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for HashCrypt. */ +#define HASHCRYPT_CLOCKS \ + { \ + kCLOCK_HashCrypt \ + } +/*! @brief Clock ip name array for PowerQuad. */ +#define POWERQUAD_CLOCKS \ + { \ + kCLOCK_PowerQuad \ + } +/*! @brief Clock ip name array for PLULUT. */ +#define PLULUT_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for CASPER. */ +#define CASPER_CLOCKS \ + { \ + kCLOCK_Casper \ + } +/*! @brief Clock ip name array for ANALOGCTRL. */ +#define ANALOGCTRL_CLOCKS \ + { \ + kCLOCK_AnalogCtrl \ + } +/*! @brief Clock ip name array for HS_LSPI. */ +#define HS_LSPI_CLOCKS \ + { \ + kCLOCK_Hs_Lspi \ + } +/*! @brief Clock ip name array for GPIO_SEC. */ +#define GPIO_SEC_CLOCKS \ + { \ + kCLOCK_Gpio_Sec \ + } +/*! @brief Clock ip name array for GPIO_SEC_INT. */ +#define GPIO_SEC_INT_CLOCKS \ + { \ + kCLOCK_Gpio_Sec_Int \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +#define PLU_CLOCKS \ + { \ + kCLOCK_PluLut \ + } +#define SYSCTL_CLOCKS \ + { \ + kCLOCK_Sysctl \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ + + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ + + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */ + + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */ + + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ + + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ + + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ + + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ + + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ + + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ + + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */ + + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */ + + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ + + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ + + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ + + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ + + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ + + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ + + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ + + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ + + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ + + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ + + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ + + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ + + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ + + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ + + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ + + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ + + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ + + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ + + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ + + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ + + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ + + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ + + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ + + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ + + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ + + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ + + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ + + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ + + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ + + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ + + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ + + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ + + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ + + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ + + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ + + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ + + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ + + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ + + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ + + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ + + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ + + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ + + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ + + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ + + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ + + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ + + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ + + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ + + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ + + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ + + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ + + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + + kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */ + + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ + + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ + + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ + + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */ + + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ + + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ + + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ + + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ + + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ + + kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */ + + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ + + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ + + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ + + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ + + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ + + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ + + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ + + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ + + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ + + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ + + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_SYSTICKCLKSEL1 1U +#define CM_TRACECLKSEL 2U +#define CM_CTIMERCLKSEL0 3U +#define CM_CTIMERCLKSEL1 4U +#define CM_CTIMERCLKSEL2 5U +#define CM_CTIMERCLKSEL3 6U +#define CM_CTIMERCLKSEL4 7U +#define CM_MAINCLKSELA 8U +#define CM_MAINCLKSELB 9U +#define CM_CLKOUTCLKSEL 10U +#define CM_PLL0CLKSEL 12U +#define CM_PLL1CLKSEL 13U +#define CM_ADCASYNCCLKSEL 17U +#define CM_USB0CLKSEL 18U +#define CM_FXCOMCLKSEL0 20U +#define CM_FXCOMCLKSEL1 21U +#define CM_FXCOMCLKSEL2 22U +#define CM_FXCOMCLKSEL3 23U +#define CM_FXCOMCLKSEL4 24U +#define CM_FXCOMCLKSEL5 25U +#define CM_FXCOMCLKSEL6 26U +#define CM_FXCOMCLKSEL7 27U +#define CM_HSLSPICLKSEL 28U +#define CM_MCLKCLKSEL 32U +#define CM_SCTCLKSEL 36U +#define CM_SDIOCLKSEL 38U + +#define CM_RTCOSC32KCLKSEL 63U + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ + + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ + + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ + + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ + + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ + + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ + + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ + + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ + + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ + + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ + + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ + + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ + + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ + + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ + + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ + + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ + + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ + + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ + + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ + + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ + + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ + + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ + + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ + + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ + + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ + + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ + + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ + + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ + + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ + + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ + + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ + + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ + + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ + + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ + + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ + + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ + + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ + + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ + + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ + + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ + + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ + + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ + + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ + + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ + + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ + + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ + + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ + + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ + + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ + + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ + + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ + + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ + + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ + + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ + + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ + + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ + + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ + + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ + + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ + + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ + + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ + + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ + + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ + + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ + + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ + + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ + + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ + + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ + + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ + + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */ + + kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */ + + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */ + + kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */ + + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */ + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ + + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ + + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ + + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ + + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ + + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ + + kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */ + + kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */ + + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ + + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ + + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ + + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ + + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ + + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ + + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ + + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ + + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ + + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ + + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ + + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ + + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ + + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ + + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ + + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ + + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ + + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ + + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ + + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ + + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ + + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ + + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ + + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ + + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + + kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */ + + kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ + + kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ + + kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ + + kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ + + kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ + + kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ + + kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ + + kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ + + kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ + + kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ + + kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ + + kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ + + kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ + + kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ + + kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ + + kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ + + kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ + + kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */ + + kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); +} +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); +/** + * @brief Initialize the I2S MCLK clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Setup rtc 1khz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value); +/** + * @brief Setup rtc 1hz clock divider. + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); + +/** + * @brief Set the flexcomm output frequency. + * @param id : flexcomm instance id + * @param freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq); + +/*! @brief Return Frequency of flexcomm input clock + * @param id : flexcomm instance id + * @return Frequency value + */ +uint32_t CLOCK_GetFlexCommInputClock(uint32_t id); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of FRO 1MHz + * @return Frequency of FRO 1MHz + */ +uint32_t CLOCK_GetFro1MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of SDIO Clock + * @return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of PLU CLKIN Clock + * @return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); +/*! @brief Return Frequency of SystickClock + * @return Frequency of Systick Clock + */ +uint32_t CLOCK_GetSystickClkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Return PLL0 output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return PLL0 output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); + +/*! @brief Enables and disables PLL0 bypass mode + * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass + * @return PLL0 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass) +{ + if (bypass) + { + SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Enables and disables PLL1 bypass mode + * @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass + * @return PLL1 output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) +{ + if (bypass) + { + SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } + else + { + SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); +} + +/*! @brief Store the current PLL0 rate + * @param rate: Current rate of the PLL0 + * @return Nothing + **/ +void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6U << SYSCON_PLL0SSCG1_MF_SHIFT), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7U << SYSCON_PLL0SSCG1_MF_SHIFT) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1 */ + kSS_MR_K1_5 = (2U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 1.5 */ + kSS_MR_K2 = (3U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 2 */ + kSS_MR_K3 = (4U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 3 */ + kSS_MR_K4 = (5U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 4 */ + kSS_MR_K6 = (6U << SYSCON_PLL0SSCG1_MR_SHIFT), /*!< k = 6 */ + kSS_MR_K8 = (7U << SYSCON_PLL0SSCG1_MR_SHIFT) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< no compensation */ + kSS_MC_RECC = (2U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< recommended setting */ + kSS_MC_MAXC = (3U << SYSCON_PLL0SSCG1_MC_SHIFT), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register PLL0CTRL */ + uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */ + uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */ + uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB FS clock source definition. */ +typedef enum _clock_usbfs_src +{ + kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */ + kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */ + kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */ + + kCLOCK_UsbfsSrcNone = + SYSCON_USB0CLKSEL_SEL(7) /*!WAKEUPINT. They are NOT restored by the + * API. + * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk + * of Dead Lock). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + * reset) + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); + +/** + * @brief + * @param + * @return + */ +static void lf_set_dcdc_power_profile_low(void) +{ +#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U) +#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U) + + uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); + uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + PMC->DCDC0 = dcdcTrimValue0 >> 1; + PMC->DCDC1 = dcdcTrimValue1; + } +} + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) +{ + lowpower_driver_interface_t *s_lowpowerDriver; + /* Judging the core and call the corresponding API base address*/ + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + /* PMC clk set to 12 MHZ */ + p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; + + /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP + * POWER DOWN) and Hardware Pin reset */ + PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | + PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); + + /* SRAM uses Voltage Scaling in all Low Power modes */ + PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); + + /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined + * parameter. */ + p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | + (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); + + /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ + SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ + lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ + + (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); + + /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = + * 0 */ + PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & + (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * @param None + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void) +{ + /* Judging the core and call the corresponding API base address*/ + lowpower_driver_interface_t *s_lowpowerDriver; + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); +}; + +/** + * brief PMC Deep Sleep function call + * return nothing + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t dcdc_voltage; + uint32_t pmc_reset_ctrl; + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ + + lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during + * deep-sleep */ + exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; + } + + /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references + * will stay powered, Shut down ROM */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & + ~(uint32_t)kPDRUNCFG_PD_BIAS) | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; + + /* Voltage control in DeepSleep Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; + + /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ + if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) + { + lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; + } + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK)) + { + /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE; + } + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) + { + /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT; + } + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC power Down function call + * return nothing + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint64_t wakeup_src_int; + uint32_t pmc_reset_ctrl; + + uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ + + /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point + * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); + + /* CPU0 retention Ctrl. + * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the + * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer, + * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area + */ + lv_low_power_mode_cfg.CPURETCTRL = + (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | + ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & + LOWPOWER_CPURETCTRL_MEMBASE_MASK); + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* CPU retention is required: store Analog Controller Registers */ + analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; + analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; + analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; + analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; + analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; + analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; + analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; + analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; + analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; + analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; + analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; + analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; + } + + /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, + * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ + wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | + WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for + instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the + stack used to call this function shall be preserved during low power ***/ + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; + + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* Restore Analog Controller Registers */ + ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; + ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; + ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; + ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; + ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; + ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; + ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; + ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; + ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; + ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; + ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; + } +} + +/** + * brief PMC Deep Sleep Power Down function call + * return nothing + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t pmc_reset_ctrl; + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ + + /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; + * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | + (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; + + /* SRAM retention control during DEEPPOWERDOWN */ + sram_retention_ctrl = + sram_retention_ctrl & + (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); + + /* SRAM retention control during DEEPPOWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); + + lv_low_power_mode_cfg.WAKEUPINT = + wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | + WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER */ + lv_low_power_mode_cfg.WAKEUPSRC = + wakeup_interrupts & + (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | + WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ + + /* Wake up I/O sources */ + lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + /* Save the configuration of the PMC RESETCTRL register */ + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Disable LDO MEM bleed current */ + // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK; + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC Sleep function call + * return nothing + */ +void POWER_EnterSleep(void) +{ + uint32_t pmsk; + pmsk = __get_PRIMASK(); + __disable_irq(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + __set_PRIMASK(pmsk); +} + +/** + * @brief Get Digital Core logic supply source to be used during Deep Sleep. + * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep + * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used + * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h + + * @return Nothing + */ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) +{ + *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */ + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode */ + PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ + *dcdc_voltage = + (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ + } +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) +{ +#define FLASH_NMPA_LDO_AO_ADDRS (0x9FCF4U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) + + uint32_t ldo_ao_trim, voltage; + uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; + + ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); + + switch (p_lp_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P900; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; + } + } + break; + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + default: + /* Should never reach this point */ + lv_v_ldo_pmu = (uint32_t)V_AO_1P100; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; + break; + } + + /* The Memories Voltage settings below are for voltage scaling */ + voltage = + (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ + (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ + ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ + ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ + ((uint32_t)V_DEEPSLEEP_0P900 + << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ + (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ + ; + + return (voltage); +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) +{ + uint32_t wake_up_type; + uint32_t misc_ctrl_reg; + uint8_t use_external_pullupdown = 0; + + /* Configure Pull up & Pull down based on the required wake-up edge */ + CLOCK_EnableClock(kCLOCK_Iocon); + + misc_ctrl_reg = 0UL; + + /* Wake-up I/O 0 */ + wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 1 */ + wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 2 */ + wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 3 */ + wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + + PMC->MISCCTRL = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg; + PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL; + + /* + * Defined according to : + * - LOWPOWER_WAKEUPIOSRC_ in fsl_power.h + * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h + */ + return (p_wakeup_io_ctrl & 0xFFFUL); +} + +/** + * @brief + * @param + * @return + */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) +{ + /* Compensate for discontinuity in the capacitor banks */ + if (u8OscCap < 64U) + { + if (u8OscCap >= u8CapBankDiscontinuity) + { + u8OscCap -= u8CapBankDiscontinuity; + } + else + { + u8OscCap = 0U; + } + } + else + { + if (u8OscCap <= (127U - u8CapBankDiscontinuity)) + { + u8OscCap += u8CapBankDiscontinuity; + } + else + { + u8OscCap = 127U; + } + } + return u8OscCap; +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_system_voltage(uint32_t system_voltage_mv) +{ + /* + * Set system voltage + */ + uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ + uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ + uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ + + if (system_voltage_mv <= 950UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P950; + lv_ldo_ao = (uint32_t)V_AO_0P960; + lv_ldo_ao_boost = (uint32_t)V_AO_1P010; + } + else if (system_voltage_mv <= 975UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P975; + lv_ldo_ao = (uint32_t)V_AO_0P980; + lv_ldo_ao_boost = (uint32_t)V_AO_1P030; + } + else if (system_voltage_mv <= 1000UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P000; + lv_ldo_ao = (uint32_t)V_AO_1P000; + lv_ldo_ao_boost = (uint32_t)V_AO_1P050; + } + else if (system_voltage_mv <= 1025UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P025; + lv_ldo_ao = (uint32_t)V_AO_1P030; + lv_ldo_ao_boost = (uint32_t)V_AO_1P080; + } + else if (system_voltage_mv <= 1050UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P050; + lv_ldo_ao = (uint32_t)V_AO_1P060; + lv_ldo_ao_boost = (uint32_t)V_AO_1P110; + } + else if (system_voltage_mv <= 1075UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P075; + lv_ldo_ao = (uint32_t)V_AO_1P080; + lv_ldo_ao_boost = (uint32_t)V_AO_1P130; + } + else if (system_voltage_mv <= 1100UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P100; + lv_ldo_ao = (uint32_t)V_AO_1P100; + lv_ldo_ao_boost = (uint32_t)V_AO_1P150; + } + else if (system_voltage_mv <= 1125UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P125; + lv_ldo_ao = (uint32_t)V_AO_1P130; + lv_ldo_ao_boost = (uint32_t)V_AO_1P160; + } + else if (system_voltage_mv <= 1150UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P150; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else if (system_voltage_mv <= 1175UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P175; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else + { + lv_dcdc = (uint32_t)V_DCDC_1P200; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + + /* Set up LDO Always-On voltages */ + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | + PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); + + /* Set up DCDC voltage */ + PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ +#define FLASH_NMPA_BASE (0x9FC00u) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU) + + const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; + const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; + + uint32_t dcdcTrimValue0; + uint32_t dcdcTrimValue1; + + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_LOW: + /* Low */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "MEDIUM" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "HIGH" + "\n"); +#endif + } + break; + + default: + /* Low */ + PMC->DCDC0 = PMC_DCDC0_DEFAULT; + PMC->DCDC1 = PMC_DCDC1_DEFAULT; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + break; + } +} + +/** + * @brief + * @param + * @return + */ +static lowpower_process_corner_enum lowpower_get_part_process_corner(void) +{ +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) + + lowpower_process_corner_enum part_process_corner; + uint32_t pvt_ringo_hz; + uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); + uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); + + /* + * Check that the PVT Monitors Trimmings in flash are valid. + */ + if (0UL != (pvt_ringo_0 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_0 = pvt_ringo_0 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_0 = PROCESS_NNN_AVG_HZ; + } + + if (0UL != (pvt_ringo_1 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_1 = pvt_ringo_1 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_1 = PROCESS_NNN_AVG_HZ; + } + + if (pvt_ringo_1 <= pvt_ringo_0) + { + pvt_ringo_hz = pvt_ringo_1; + } + else + { + pvt_ringo_hz = pvt_ringo_0; + } + + /* + * Determine the process corner based on the value of the Ring Oscillator frequency + */ + if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) + { + /* SSS Process Corner */ + part_process_corner = PROCESS_CORNER_SSS; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "SSS" + "\n"); +#endif + } + else + { + if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) + { + /* NNN Process Corner */ + part_process_corner = PROCESS_CORNER_NNN; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "NNN" + "\n"); +#endif + } + else + { + /* FFF Process Corner */ + part_process_corner = PROCESS_CORNER_FFF; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "FFF" + "\n"); +#endif + } + } + + return (part_process_corner); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ + /* Get Sample Process Corner */ + lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); + + switch (part_process_corner) + { + case PROCESS_CORNER_SSS: + /* Slow Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + case PROCESS_CORNER_FFF: + /* Fast Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + default: + /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); + break; + } // switch(dcdc_power_profile) + break; + } + } // switch(part_process_corner) +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz) +{ + if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) + { + /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); + } + else + { + if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) + { + /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); + } + else + { + /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); + } + } +} + +void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + + /* Enable and set LDO, if not already done */ + POWER_SetXtal16mhzLdo(); + /* Get Cal values from Flash */ + u32XOTrimValue = GET_16MXO_TRIM(); + /* Check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* This field is 1 bit */ + u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 20; // gain in LSB/pF + ibXin = -9; // offset in LSB + iaXout_x4 = 20; // gain in LSB/pF + ibXout = -13; // offset in LSB + u8XOSlave = 0; + } + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + + 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; + iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + /* Read register and clear fields to be written */ + u32RegVal = ANACTRL->XO32M_CTRL; + u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); + /* Configuration of 32 MHz XO output buffers */ +#if (XO_SLAVE_EN == 0) + u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); +#else + u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; +#endif + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; + /* Write back to register */ + ANACTRL->XO32M_CTRL = u32RegVal; +} + +void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + /* Get Cal values from Flash */ + u32XOTrimValue = GET_32KXO_TRIM(); + /* check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 16; // gain in LSB/pF + ibXin = 12; // offset in LSB + iaXout_x4 = 16; // gain in LSB/pF + ibXout = 11; // offset in LSB + } + + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; + iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + + /* Read register and clear fields to be written */ + u32RegVal = PMC->XTAL32K; + u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); + + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; + + /* Write back to register */ + PMC->XTAL32K = u32RegVal; +} + +void POWER_SetXtal16mhzLdo(void) +{ + uint32_t temp; + const uint32_t u32Mask = + (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); + + const uint32_t u32Value = + (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); + + /* Enable & set-up XTAL 32 MHz clock LDO */ + temp = ANACTRL->LDO_XO32M; + + if ((temp & u32Mask) != u32Value) + { + temp &= ~u32Mask; + + /* + * Enable the XTAL32M LDO + * Adjust the output voltage level, 0x5 for 1.1V + * Adjust the biasing current, 0x2 value + * Stability configuration, 0x1 default mode + */ + temp |= u32Value; + + ANACTRL->LDO_XO32M = temp; + + /* Delay for LDO to be up */ + // CLOCK_uDelay(20); + } + + /* Enable LDO XO32M */ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; +} + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause) +{ + uint32_t reset_cause_reg; + uint32_t boot_mode_reg; + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; +#else /* LPC55S69/28 */ + reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; +#endif + + /* + * Prioritize interrupts source with respect to their critical level + */ +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) + { /* Code Watchdog Reset */ + *p_reset_cause = kRESET_CAUSE_CDOGRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else +#endif + { + if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) + { /* Watchdog Timer Reset */ + *p_reset_cause = kRESET_CAUSE_WDTRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) + { /* ARM System Reset */ + *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; + + if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ + { + *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + + /* + * Prioritise Reset causes, starting from the strongest (Power On Reset) + */ + if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) + { /* Power On Reset */ + *p_reset_cause = kRESET_CAUSE_POR; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) + { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ + *p_reset_cause = kRESET_CAUSE_BODRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) + { /* Hardware Pin Reset */ + *p_reset_cause = kRESET_CAUSE_PADRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) + { /* Software triggered Reset */ + *p_reset_cause = kRESET_CAUSE_SWRRESET; + } + else + { /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + } + } + } + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ + { + /* + * 1- First, save wakeup_io_cause register ... + */ + *p_wakeupio_cause = PMC->WAKEIOCAUSE; + + if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; + + switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) + { + case 1: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; + break; + case 2: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; + break; + case 3: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; + break; + case 4: + *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; + break; + case 5: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; + break; + case 6: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; + break; + case 7: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; + break; + default: + /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + break; + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* + * 2- Next, transfer the control of the 4 wake-up pins + * to IOCON (instead of the Power Management Controller) + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP and POWER-DOWN */ + { + *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; + + /* + * The control of the 4 wake-up pins is already in IOCON, + * so there is nothing special to do. + */ + + if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; + } + else /* POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; + + } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ + + } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ + + } /* if ( boot_mode == 0 ) POWER-UP */ + + } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h new file mode 100644 index 000000000..6a9de7a9f --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_power.h @@ -0,0 +1,611 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 1.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; + +/** + * @brief Analog components power modes control during low power modes + */ +typedef enum pd_bits +{ + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), + /* + This enum member has no practical meaning,it is used to avoid MISRA issue, + user should not trying to use it. + */ + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/*! @brief BOD VBAT level */ +typedef enum _power_bod_vbat_level +{ + kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ + kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */ + kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */ + kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */ + kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */ + kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */ + kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */ + kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */ + kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */ + kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */ + kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */ + kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */ + kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */ + kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */ + kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */ + kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */ + kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */ + kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */ + kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */ + kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */ + kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */ + kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */ + kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */ + kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */ + kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */ + kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ +} power_bod_vbat_level_t; + +/*! @brief BOD Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/*! @brief BOD core level */ +typedef enum _power_bod_core_level +{ + kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ + kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */ + kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */ + kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */ + kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */ + kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */ + kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */ + kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ +} power_bod_core_level_t; + +/** + * @brief Device Reset Causes + */ +typedef enum _power_device_reset_cause +{ + kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ + kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ + kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ + kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ + kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ + kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ + kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ + /* Reset causes in DEEP-POWER-DOWN low power mode */ + kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ + kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ + kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish + which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish + which of these 3 events occured first) */ + /* Miscallenous */ + kRESET_CAUSE_NOT_RELEVANT = + 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ + kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an + application point of view. */ +} power_device_reset_cause_t; + +/** + * @brief Device Boot Modes + */ +typedef enum _power_device_boot_mode +{ + kBOOT_MODE_POWER_UP = + 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ + kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ + kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ + kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ +} power_device_boot_mode_t; + +/** + * @brief SRAM instances retention control during low power modes + */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ + (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ + (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ + (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ + (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ + (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ + (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ + (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ + (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ + (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ + (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ + (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ + (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ + (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ + (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ + (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ + (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ + +/** + * @brief Low Power Modes Wake up sources + */ +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +// reserved (1ULL << 25) +// reserved (1ULL << 26) +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +// reserved (1ULL << 39) +// reserved (1ULL << 40) +// reserved (1ULL << 41) +#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ +// reserved (1ULL << 43) +// reserved (1ULL << 44) +// reserved (1ULL << 45) +// reserved (1ULL << 46) +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) +// reserved WAKEUP_PVTVF0_RED (1ULL << 61) +// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ + +/** + * @brief Sleep Postpone + */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ + +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ +/** + * @brief Wake up I/O sources + */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ + +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ + +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ + +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ + +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ + +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ + (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ + (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ + (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ + (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + PMC->PDRUNCFGSET0 = (uint32_t)en; +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + PMC->PDRUNCFGCLR0 = (uint32_t)en; +} + +/*! + * @brief set BOD VBAT level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodVbatReset VBAT brown out detect reset + */ +static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) +{ + PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | + PMC_BODVBAT_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); +} + +#if defined(PMC_BODCORE_TRIGLVL_MASK) +/*! + * @brief set BOD core level. + * + * @param level BOD detect level + * @param hyst BoD Hysteresis control + * @param enBodCoreReset core brown out detect reset + */ +static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) +{ + PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | + PMC_BODCORE_HYST(hyst); + PMC->RESETCTRL = + (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); +} +#endif + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * This MUST BE EXECUTED outside the Flash: + * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is + * preferable to have all functions defined in this file implemented in ROM. + * + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void); + +/** + * @brief Configures and enters in DEEP-SLEEP low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param hardware_wake_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl); + +/** + * @brief Configures and enters in POWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are + RESERVED. + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance + containing the stack used to call this function WILL BE preserved during low power (via parameter + "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) + */ + +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl); + +/** + * @brief Configures and enters in DEEPPOWERDOWN low power mode + * @param exclude_from_pd: + * @param sram_retention_ctrl: + * @param wakeup_interrupts: + * @param wakeup_io_ctrl: + + * @return Nothing + * + * !!! IMPORTANT NOTES : + 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if + DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl); + +/** + * @brief Configures and enters in SLEEP low power mode + * @param : + * @return Nothing + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz); + +/** + * @brief Sets board-specific trim values for 16MHz XTAL + * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @return none + * @note Following default Values can be used: + * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 + * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100); +/** + * @brief Sets board-specific trim values for 32kHz XTAL + * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + + * @return none + * @note Following default Values can be used: + * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 + * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 + * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 + */ +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100); +/** + * @brief Enables and sets LDO for 16MHz XTAL + * + * @return none + */ +extern void POWER_SetXtal16mhzLdo(void); + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause); +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_POWER_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c new file mode 100644 index 000000000..4326e0dae --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h new file mode 100644 index 000000000..ecdf2392a --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/drivers/fsl_reset.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define AES_RSTS \ + { \ + kAES_RST_SHIFT_RSTn \ + } /* Reset bits for AES peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define OTP_RSTS \ + { \ + kOTP_RST_SHIFT_RSTn \ + } /* Reset bits for OTP peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SDIO_RST \ + { \ + kSDIO_RST_SHIFT_RSTn \ + } /* Reset bits for SDIO peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define SPIFI_RSTS \ + { \ + kSPIFI_RST_SHIFT_RSTn \ + } /* Reset bits for SPIFI peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ +#define CAPT_RSTS_N \ + { \ + kCAP0_RST_SHIFT_RSTn \ + } /* Reset bits for CAPT peripheral */ +#define PLU_RSTS_N \ + { \ + kPLULUT_RST_SHIFT_RSTn \ + } /* Reset bits for PLU peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define POWERQUAD_RSTS \ + { \ + kPOWERQUAD_RST_SHIFT_RSTn \ + } /* Reset bits for Powerquad peripheral */ +#define CASPER_RSTS \ + { \ + kCASPER_RST_SHIFT_RSTn \ + } /* Reset bits for Casper peripheral */ +#define HASHCRYPT_RSTS \ + { \ + kHASHCRYPT_RST_SHIFT_RSTn \ + } /* Reset bits for Hashcrypt peripheral */ +#define PUF_RSTS \ + { \ + kPUF_RST_SHIFT_RSTn \ + } /* Reset bits for PUF peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; +#define USB1RAM_RSTS USB1RAM_RST +#define USB1H_RSTS USB1H_RST +#define USB1D_RSTS USB1D_RST +#define USB0HSL_RSTS USB0HSL_RST +#define USB0HMR_RSTS USB0HMR_RST +#define USB0D_RSTS USB0D_RST +#define SDIO_RSTS SDIO_RST + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h new file mode 100644 index 000000000..96bfa54ec --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/fsl_device_registers.h @@ -0,0 +1,44 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || defined(CPU_LPC55S69JEV59_cm33_core0) || \ + defined(CPU_LPC55S69JEV98_cm33_core0)) + +#define LPC55S69_cm33_core0_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core0.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core0_features.h" + +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || defined(CPU_LPC55S69JEV59_cm33_core1) || \ + defined(CPU_LPC55S69JEV98_cm33_core1)) + +#define LPC55S69_cm33_core1_SERIES + +/* CMSIS-style register definitions */ +#include "LPC55S69_cm33_core1.h" +/* CPU specific feature definitions */ +#include "LPC55S69_cm33_core1_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c new file mode 100644 index 000000000..ddaa379f5 --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.c @@ -0,0 +1,378 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b231019 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.1 + * @date 2019-05-16 + * @brief Device specific configuration file for LPC55S69_cm33_core0 + * (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +/* PLL0 SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +/* Get predivider (N) from PLL0 NDEC setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDEC setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1; + + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) + { + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); + } + else + { + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get predivider (N) from PLL1 NDEC setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL1 PDEC setting */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; + } + else + { + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + return postDiv; +} + +/* Get multiplier (M) from PLL1 MDEC settings */ +static uint32_t findPll1MMult(void) +{ + uint32_t mMult = 1UL; + + mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; + + if (mMult == 0UL) + { + mMult = 1UL; + } + return mMult; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t GetFro12MFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get FRO 1M Clk */ +/*! brief Return Frequency of FRO 1MHz + * return Frequency of FRO 1MHz + */ +static uint32_t GetFro1MFreq(void) +{ + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t GetExtClkFreq(void) +{ + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t GetFroHfFreq(void) +{ + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t GetOsc32KFreq(void) +{ + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + CLK_RTC_32K_CLK : + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? + CLK_RTC_32K_CLK : + 0U; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; +#endif + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + uint64_t workRate1; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + default: /* = 0x03 = FRO 96 MHz (fro_hf) */ + clkRate = GetFroHfFreq(); + break; + } + break; + case 0x01: /* PLL0 clock (pll0_clk)*/ + switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); + } + break; + case 0x02: /* PLL1 clock (pll1_clk)*/ + switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = GetFro12MFreq(); + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = GetExtClkFreq(); + break; + case 0x02: /* Fro 1MHz (fro_1m) */ + clkRate = GetFro1MFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); + clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = GetOsc32KFreq(); + break; + default: + clkRate = 0UL; + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h new file mode 100644 index 000000000..5c7a3b21a --- /dev/null +++ b/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/system_LPC55S69_cm33_core0.h @@ -0,0 +1,112 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV59_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b231019 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2018-08-22) +** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM +** +** ################################################################### +*/ + +/*! + * @file LPC55S69_cm33_core0 + * @version 1.1 + * @date 2019-05-16 + * @brief Device specific configuration file for LPC55S69_cm33_core0 (header + * file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC55S69_cm33_core0_H_ +#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/config_tfm_target.h b/platform/ext/target/nxp/lpcxpresso55s69/config_tfm_target.h index c2c2630fd..638173658 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/config_tfm_target.h +++ b/platform/ext/target/nxp/lpcxpresso55s69/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * Copyright 2022 NXP. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -12,6 +12,7 @@ /* Using of stored NV seed to provide entropy is disabled, when CRYPTO_HW_ACCELERATOR is defined. */ #ifdef CRYPTO_HW_ACCELERATOR #define CRYPTO_NV_SEED 0 +#define CRYPTO_EXT_RNG 1 #endif /* The maximum asset size to be stored in the Protected Storage area. */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h b/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h index 8b36a96e4..3498e5afe 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h +++ b/platform/ext/target/nxp/lpcxpresso55s69/partition/region_defs.h @@ -160,5 +160,8 @@ security tier by programing corresponding registers in secure AHB controller. */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT #endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c index 9bb2f3138..a4bbf92ea 100644 --- a/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c +++ b/platform/ext/target/nxp/lpcxpresso55s69/target_cfg.c @@ -15,6 +15,8 @@ * limitations under the License. */ +#include + #include "target_cfg.h" #include "Driver_Common.h" #include "platform_description.h" @@ -64,8 +66,8 @@ int32_t mpc_init_cfg(void) /* == Flash region == */ /* The regions have to be alligned to 32 kB to cover the AHB Flash Region. */ - SPM_ASSERT((memory_regions.non_secure_partition_base % FLASH_SUBREGION_SIZE) == 0); - SPM_ASSERT(((memory_regions.non_secure_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0); + assert((memory_regions.non_secure_partition_base % FLASH_SUBREGION_SIZE) == 0); + assert(((memory_regions.non_secure_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0); /* Flash region is divided into 20 sub-regions (sector). Each flash sub-regions (sector) is 32 kbytes. */ /* 1) Set FLASH memory security access rule configuration to init value (0x3 = all regions set to secure and privileged user access) */ @@ -98,8 +100,8 @@ int32_t mpc_init_cfg(void) #ifdef BL2 /* Set secondary image region to NS, when BL2 is enabled */ /* The regions have to be alligned to 32 kB to cover the AHB Flash Region. */ - SPM_ASSERT((memory_regions.secondary_partition_base % FLASH_SUBREGION_SIZE) == 0); - SPM_ASSERT(((memory_regions.secondary_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0); + assert((memory_regions.secondary_partition_base % FLASH_SUBREGION_SIZE) == 0); + assert(((memory_regions.secondary_partition_limit+1) % FLASH_SUBREGION_SIZE) == 0); /* 2) Set FLASH memory security access rule configuration (set to non-secure and non-privileged user access allowed).*/ ns_region_start_id = memory_regions.secondary_partition_base/FLASH_SUBREGION_SIZE; @@ -143,8 +145,8 @@ int32_t mpc_init_cfg(void) /* == SRAM region == */ /* The regions have to be alligned to 4 kB to cover the AHB RAM Region */ - SPM_ASSERT((S_DATA_SIZE % DATA_SUBREGION_SIZE) == 0); - SPM_ASSERT(((S_DATA_SIZE + NS_DATA_SIZE) % DATA_SUBREGION_SIZE) == 0); + assert((S_DATA_SIZE % DATA_SUBREGION_SIZE) == 0); + assert(((S_DATA_SIZE + NS_DATA_SIZE) % DATA_SUBREGION_SIZE) == 0); /* Security access rules for RAM (0x3 = all regions set to secure and privileged user access*/ AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0]= 0x33333333U; /* 0x2000_0000 - 0x2000_7FFF */ diff --git a/platform/ext/target/rpi/pico_uf2.sh b/platform/ext/target/rpi/pico_uf2.sh new file mode 100644 index 000000000..3d90ff6a2 --- /dev/null +++ b/platform/ext/target/rpi/pico_uf2.sh @@ -0,0 +1,8 @@ +#!/bin/bash +tfm_tests_dir=$1 +build_dir=$2 +spe_bin="${tfm_tests_dir}/tests_reg/spe/${build_dir}/bin" +ns_bin="${tfm_tests_dir}/tests_reg/${build_dir}/bin" +python uf2conv.py "${spe_bin}/bl2.bin" --base 0x10000000 --convert --output "${spe_bin}/bl2.uf2" --family 0xe48bff59 +python uf2conv.py "${ns_bin}/../tfm_s_ns_signed.bin" --base 0x10011000 --convert --output "${spe_bin}/tfm_s_ns_signed.uf2" --family 0xe48bff59 +python uf2conv.py "${spe_bin}/provisioning_bundle.bin" --base 0x1019F000 --convert --output "${spe_bin}/provisioning_bundle.uf2" --family 0xe48bff59 diff --git a/platform/ext/target/rpi/rp2350/CMakeLists.txt b/platform/ext/target/rpi/rp2350/CMakeLists.txt new file mode 100644 index 000000000..0503fa63a --- /dev/null +++ b/platform/ext/target/rpi/rp2350/CMakeLists.txt @@ -0,0 +1,348 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + + +# initialize pico-sdk from GIT +set(PICO_SDK_FETCH_FROM_GIT on) +set(PICO_PLATFORM rp2350-arm-s) +set(SKIP_BOOT_STAGE2 1) + +# initialize the Raspberry Pi Pico SDK +include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) +pico_sdk_init() + +get_target_property(pico_link_options pico_standard_link INTERFACE_LINK_OPTIONS) +list(FILTER pico_link_options EXCLUDE REGEX "LINKER.*--script") +list(APPEND pico_link_options "--entry=_entry_point") +set_target_properties(pico_standard_link PROPERTIES INTERFACE_LINK_OPTIONS "${pico_link_options}") +set_target_properties(pico_runtime PROPERTIES INTERFACE_LINK_OPTIONS "") + +target_compile_options(cmsis_core + INTERFACE + ${COMPILER_CMSE_FLAG} +) + +cmake_policy(SET CMP0076 NEW) +set(CMAKE_CURRENT_SOURCE_DIR ${CMAKE_CURRENT_LIST_DIR}) + +set(STATIC_ASSERT_OVERRIDE_HEADER "${CMAKE_CURRENT_LIST_DIR}/static_assert_override.h") +add_library(static_assert_override INTERFACE) +target_compile_options(static_assert_override + INTERFACE + "$<$:SHELL:-include ${STATIC_ASSERT_OVERRIDE_HEADER}>" + "$<$:SHELL:-include ${STATIC_ASSERT_OVERRIDE_HEADER}>" + "$<$:SHELL:--preinclude ${STATIC_ASSERT_OVERRIDE_HEADER}>" +) + +#========================= Platform region defs ===============================# + +add_library(platform_s_init INTERFACE) +target_sources(platform_s_init + INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/extra_init.c +) + +target_link_libraries(platform_s_init + INTERFACE + pico_runtime_init + pico_runtime_headers + pico_bootrom_headers +) + +target_link_options(tfm_s + PUBLIC + "--entry=_entry_point" +) + +target_include_directories(platform_region_defs + INTERFACE + partition +) + +target_link_libraries(platform_region_defs + INTERFACE + tfm_fih_headers + hardware_regs_headers + static_assert_override +) + +target_compile_definitions(platform_region_defs + INTERFACE + PROVISIONING_CODE_PADDED_SIZE=${PROVISIONING_CODE_PADDED_SIZE} + PROVISIONING_VALUES_PADDED_SIZE=${PROVISIONING_VALUES_PADDED_SIZE} + PROVISIONING_DATA_PADDED_SIZE=${PROVISIONING_DATA_PADDED_SIZE} +) + +if(NOT PLATFORM_DEFAULT_PROVISIONING) + add_subdirectory(${PLATFORM_DIR}/ext/common/provisioning_bundle provisioning) + + target_include_directories(provisioning_bundle + INTERFACE + ${PLATFORM_DIR}/../interface/include + ) + + if(NOT PLATFORM_DEFAULT_PROV_LINKER_SCRIPT) + target_add_scatter_file(provisioning_bundle + linker_provisioning.ld + ) + + target_compile_definitions(provisioning_bundle_scatter + PRIVATE + # u modifier in scatter file is not valid + NO_U_MODIFIER=1 + ) + endif() +endif() + +if(TFM_PARTITION_CRYPTO) + target_include_directories(platform_crypto_keys + PRIVATE + ${CMAKE_CURRENT_LIST_DIR} + ) +endif() + +#========================= Platform common defs ===============================# + +# Specify the location of platform specific build dependencies. +target_add_scatter_file(tfm_s + $<$:${CMAKE_BINARY_DIR}/generated/platform/ext/common/armclang/tfm_common_s.sct> + linker_s.ld + $<$:${CMAKE_BINARY_DIR}/generated/platform/ext/common/iar/tfm_common_s.icf> +) +target_compile_definitions(tfm_s_scatter + PRIVATE + # u modifier in scatter file is not valid + NO_U_MODIFIER=1 +) +target_compile_options(tfm_s_scatter + PUBLIC + ${COMPILER_CMSE_FLAG} +) + +if(BL2) + # Pico startup and runtime init + target_link_libraries(bl2 + PUBLIC + pico_runtime + ) + target_add_scatter_file(bl2 + $<$:${PLATFORM_DIR}/ext/common/armclang/tfm_common_bl2.sct> + linker_bl2.ld + $<$:${PLATFORM_DIR}/ext/common/iar/tfm_common_bl2.icf> + ) + target_compile_definitions(bl2_scatter + PRIVATE + # u modifier in scatter file is not valid + NO_U_MODIFIER=1 + ) + + target_compile_options(bl2_scatter + PUBLIC + ${COMPILER_CMSE_FLAG} + ) +endif() + +#========================= Platform Secure ====================================# + +target_include_directories(platform_s + PUBLIC + . + cmsis_drivers + partition + device/config + ${PLATFORM_DIR}/.. + INTERFACE + ${PLATFORM_DIR}/../interface/include +) + +target_link_libraries(platform_s + PUBLIC + cmsis_core_headers + hardware_uart_headers + platform_s_init + PRIVATE + pico_crt0 + pico_rand + pico_multicore + hardware_regs + hardware_flash + hardware_uart + cmsis_core + tfm_sprt +) + +target_sources(platform_s + INTERFACE + $<$:${PLATFORM_DIR}/ext/common/template/tfm_fih_rng.c> + PRIVATE + cmsis_drivers/Driver_Flash_RPI.c + cmsis_drivers/Driver_USART_RPI.c + + tfm_peripherals_def.c + + rpi_trng.c + + $<$,$>:${CMAKE_CURRENT_SOURCE_DIR}/plat_test.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c> + $<$,$>:${PLATFORM_DIR}/ext/common/template/tfm_hal_its_encryption.c> + $<$>:${CMAKE_CURRENT_SOURCE_DIR}/rp2350_otp.c> + $<$>:${CMAKE_CURRENT_SOURCE_DIR}/nv_counters.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/tfm_hal_multi_core.c> + $<$:${CMAKE_CURRENT_SOURCE_DIR}/tfm_hal_mailbox.c> +) + +target_compile_options(platform_s + PUBLIC + ${COMPILER_CMSE_FLAG} +) + +target_compile_definitions(platform_s + PUBLIC + CMSIS_device_header= + PICO_UART_DEFAULT_CRLF=1 + $<$:PS_NS_NV_COUNTER_IN_ITS=1> + $<$:TEST_NS_FPU> + $<$:TEST_S_FPU> + $<$:ITS_ENCRYPTION> + $<$:TFM_MULTI_CORE_TOPOLOGY> +) + +# GNU Arm compiler version greater equal than *11.3.Rel1* +# throw warning when linker segments used as rwx +# Adding --no-warn-rwx-segments like the RPi SDK did. +if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3.1) + target_link_options(platform_s INTERFACE "LINKER:--no-warn-rwx-segments") +endif() + +#========================= Platform BL2 =======================================# + +if(BL2) + target_sources(platform_bl2 + PRIVATE + cmsis_drivers/Driver_Flash_RPI_bl2.c + cmsis_drivers/Driver_USART_RPI.c + $<$>:${CMAKE_CURRENT_SOURCE_DIR}/rp2350_otp.c> + $<$>:${CMAKE_CURRENT_SOURCE_DIR}/nv_counters.c> + ) + + target_link_libraries(platform_bl2 + PUBLIC + cmsis_core_headers + hardware_uart_headers + PRIVATE + pico_runtime_headers + pico_runtime_init + hardware_regs + hardware_flash + hardware_uart + cmsis_core + ) + + # GNU Arm compiler version greater equal than *11.3.Rel1* + # throw warning when linker segments used as rwx + # Adding --no-warn-rwx-segments like the RPi SDK did. + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3.1) + target_link_options(platform_bl2 INTERFACE "LINKER:--no-warn-rwx-segments") + endif() + + target_include_directories(platform_bl2 + PUBLIC + partition + retarget + device/config + device/include + PRIVATE + . + ) + + target_compile_definitions(platform_bl2 + PUBLIC + PICO_UART_DEFAULT_CRLF=1 + CMSIS_device_header= + ) + + target_include_directories(bl2 + PRIVATE + ${CMAKE_CURRENT_LIST_DIR} +) + +endif() + +#========================= tfm_spm ============================================# + +target_sources(tfm_spm + PRIVATE + target_cfg.c + tfm_hal_platform.c + tfm_hal_isolation_rp2350.c + $<$,$>:${PLATFORM_DIR}/ext/common/tfm_interrupts.c> +) + +target_link_libraries(tfm_spm + PRIVATE + pico_bootrom_headers +) + +#========================= Platform Crypto Keys ===============================# + +if (TFM_PARTITION_CRYPTO) + target_sources(platform_crypto_keys + PRIVATE + crypto_keys.c + ) + target_link_libraries(platform_crypto_keys + PRIVATE + platform_s + ) +endif() + +#========================= Files for building NS platform =====================# + +install(FILES ${PLATFORM_DIR}/ext/common/test_interrupt.c + ${TARGET_PLATFORM_PATH}/cmsis_drivers/Driver_USART_RPI.c + ${TARGET_PLATFORM_PATH}/pico-sdk.patch + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(DIRECTORY ${TARGET_PLATFORM_PATH}/device + ${TARGET_PLATFORM_PATH}/cmsis_drivers + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(DIRECTORY ${PLATFORM_DIR}/ext/target/arm/drivers + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/ext/target/arm) + +install(FILES ${PLATFORM_DIR}/ext/driver/Driver_USART.h + ${PLATFORM_DIR}/ext/driver/Driver_Common.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/ext/driver) + +install(FILES ${TARGET_PLATFORM_PATH}/partition/region_defs.h + ${TARGET_PLATFORM_PATH}/partition/flash_layout.h + ${TARGET_PLATFORM_PATH}/target_cfg.h + ${TARGET_PLATFORM_PATH}/tfm_peripherals_def.h + ${TARGET_PLATFORM_PATH}/platform_multicore.h + ${TARGET_PLATFORM_PATH}/tfm_builtin_key_ids.h + ${PLATFORM_DIR}/include/tfm_plat_defs.h + ${CMAKE_SOURCE_DIR}/lib/fih/inc/fih.h + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/include) + +install(FILES ${TARGET_PLATFORM_PATH}/linker_ns.ld + DESTINATION ${INSTALL_PLATFORM_NS_DIR}/linker_scripts) + +# copy all files from active platform directory +install(DIRECTORY ${TARGET_PLATFORM_PATH}/ns/ + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +install(FILES ${TARGET_PLATFORM_PATH}/cpuarch.cmake + ${TARGET_PLATFORM_PATH}/pico_sdk_import.cmake + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Copy the platform specific config +install(FILES ${TARGET_PLATFORM_PATH}/config.cmake + ${STATIC_ASSERT_OVERRIDE_HEADER} + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) + +# Install test configs +install(DIRECTORY ${TARGET_PLATFORM_PATH}/tests + DESTINATION ${INSTALL_PLATFORM_NS_DIR}) diff --git a/platform/ext/target/rpi/rp2350/check_config.cmake b/platform/ext/target/rpi/rp2350/check_config.cmake new file mode 100644 index 000000000..6a7fc73c8 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/check_config.cmake @@ -0,0 +1,8 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +## The platform specific NV counters require OTP usage +tfm_invalid_config((NOT PLATFORM_DEFAULT_OTP) EQUAL PLATFORM_DEFAULT_NV_COUNTERS) diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.c b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.c new file mode 100644 index 000000000..3bf56ccf4 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.c @@ -0,0 +1,190 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_device_header.h" +#include "Driver_Flash_RPI.h" +#include "RTE_Device.h" + +#include "armv8m_mpu.h" + +#ifdef TFM_MULTI_CORE_TOPOLOGY +#include "platform_multicore.h" +#include "hardware/structs/sio.h" +#endif + +#if (RTE_FLASH0) + +#define RP2350_FLASH_PAGE_SIZE 0x100 /* 256B */ +#define RP2350_FLASH_SECTOR_SIZE 0x1000 /* 4KB */ +#define RP2350_FLASH_SIZE PICO_FLASH_SIZE_BYTES +#define RP2350_FLASH_ERASE_VALUE 0xFF + +static ARM_FLASH_INFO RP2350_FLASH_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = RP2350_FLASH_SIZE/ RP2350_FLASH_SECTOR_SIZE, + .sector_size = RP2350_FLASH_SECTOR_SIZE, + .page_size = RP2350_FLASH_PAGE_SIZE, + .program_unit = RP2350_FLASH_PAGE_SIZE, /* page aligned, page multipled */ + .erased_value = RP2350_FLASH_ERASE_VALUE +}; + +#define MPU_REGION_NUMBER 8 +#define SEC_STATE_NUM 2 + +struct mpu_state_save { + uint32_t mpu; + uint32_t shcsr; + uint32_t mair[2]; + ARM_MPU_Region_t mpu_table[MPU_REGION_NUMBER]; +}; + +static struct mpu_state_save mpu_state[SEC_STATE_NUM]; +static uint32_t irq_state = 0; +MPU_Type* mpu_p[SEC_STATE_NUM] = {MPU, MPU_NS}; +SCB_Type* scb_p[SEC_STATE_NUM] = {SCB, SCB_NS}; + +static inline uint32_t __save_disable_irq(void) +{ + uint32_t result = 0; + + /* Claim lock of Flash */ +#ifdef TFM_MULTI_CORE_TOPOLOGY + while(!*FLASH_SPINLOCK); +#endif + __ASM volatile ("mrs %0, primask \n cpsid i" : "=r" (result) :: "memory"); +#ifdef TFM_MULTI_CORE_TOPOLOGY + /* Signal Core1 to wait for flash */ + sio_hw->doorbell_out_set = FLASH_DOORBELL_MASK; + if (CORE1_RUNNING) + { + /* Wait for Core1 to clear doorbell */ + while(sio_hw->doorbell_out_set & FLASH_DOORBELL_MASK); + } +#endif + return result; +} + +static inline void __restore_irq(uint32_t status) +{ + __ASM volatile ("msr primask, %0" :: "r" (status) : "memory"); + /* Release lock of Flash */ +#ifdef TFM_MULTI_CORE_TOPOLOGY + *FLASH_SPINLOCK = 0x1; +#endif +} + +/* This function must be placed in RAM, so when MPU configuration is saved and + flash is protected by a non-executable region MemManageFault is avoided. + Since PRIVDEFENA is set the system memory map is enabled for privileged code + and execution from RAM is available */ +static void __not_in_flash_func(mpu_state_save) + (struct rp2350_flash_dev_t* flash_dev) +{ + static const uint8_t mpu_attr_num = 0; + uint32_t memory_base = flash_dev->base; + uint32_t memory_limit = flash_dev->base + flash_dev->size -1; + + irq_state = __save_disable_irq(); + + for(int i=0; iSHCSR; + mpu_state[i].mpu = mpu_p[i]->CTRL; + + if(mpu_p[i] == MPU) { + ARM_MPU_Disable(); + } else { + ARM_MPU_Disable_NS(); + } + + for(uint8_t j = 0; j < MPU_REGION_NUMBER; j++) { + mpu_p[i]->RNR = j; + mpu_state[i].mpu_table[j].RBAR = mpu_p[i]->RBAR; + mpu_state[i].mpu_table[j].RLAR = mpu_p[i]->RLAR; + mpu_p[i]->RBAR = 0; + mpu_p[i]->RLAR = 0; + } + + mpu_state[i].mair[0] = mpu_p[i]->MAIR[0]; + mpu_state[i].mair[1] = mpu_p[i]->MAIR[1]; + + mpu_p[i]->MAIR[0] = 0; + mpu_p[i]->MAIR[1] = 0; + + /* Attr0 : Device memory, nGnRE */ + if(mpu_p[i] == MPU) { + ARM_MPU_SetMemAttr(mpu_attr_num, + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, + ARM_MPU_ATTR_DEVICE_nGnRE)); + } else { + ARM_MPU_SetMemAttr_NS(mpu_attr_num, + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, + ARM_MPU_ATTR_DEVICE_nGnRE)); + } + + mpu_p[i]->RNR = 0; + mpu_p[i]->RBAR = ARM_MPU_RBAR(memory_base, + ARM_MPU_SH_NON, + 1, + 0, + 1); + #ifdef TFM_PXN_ENABLE + mpu_p[i]->RLAR = ARM_MPU_RLAR_PXN(memory_limit, 1, mpu_attr_num); + #else + mpu_p[i]->RLAR = ARM_MPU_RLAR(memory_limit, mpu_attr_num); + #endif + + if(mpu_p[i] == MPU) { + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + } else { + ARM_MPU_Enable_NS(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + } + } +} + +static void __not_in_flash_func(mpu_state_restore)(void) +{ + for(int i=0; iRNR = j; + mpu_p[i]->RBAR = mpu_state[i].mpu_table[j].RBAR; + mpu_p[i]->RLAR = mpu_state[i].mpu_table[j].RLAR; + } + + mpu_p[i]->MAIR[0] = mpu_state[i].mair[0]; + mpu_p[i]->MAIR[1] = mpu_state[i].mair[1]; + + __DMB(); + mpu_p[i]->CTRL = mpu_state[i].mpu; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + scb_p[i]->SHCSR = mpu_state[i].shcsr; +#endif + __DSB(); + __ISB(); + + } + + __restore_irq(irq_state); +} + +static rp2350_flash_dev_t RP2350_FLASH_DEV = { + .data = &RP2350_FLASH_DEV_DATA, + .base = XIP_BASE, + .size = RP2350_FLASH_SIZE, + .save_mpu_state = mpu_state_save, + .restore_mpu_state = mpu_state_restore +}; + + +RPI_RP2350_FLASH(RP2350_FLASH_DEV, RP2350_FLASH); +#endif /* RTE_FLASH0 */ diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.h b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.h new file mode 100644 index 000000000..3664758e3 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI.h @@ -0,0 +1,209 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __DRIVER_FLASH_RPI_H__ +#define __DRIVER_FLASH_RPI_H__ + +#include "Driver_Flash.h" +#include "hardware/flash.h" +#include + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) ((void)arg) +#endif + +/* Driver version */ +#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) + +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_FLASH_API_VERSION, /* Defined in the CMSIS Flash Driver header file */ + ARM_FLASH_DRV_VERSION +}; + +/** + * Data width values for ARM_FLASH_CAPABILITIES::data_width + * \ref ARM_FLASH_CAPABILITIES + */ + enum { + DATA_WIDTH_8BIT = 0u, + DATA_WIDTH_16BIT, + DATA_WIDTH_32BIT, + DATA_WIDTH_ENUM_SIZE +}; + +/* Flash Status */ +static ARM_FLASH_STATUS FlashStatus = {0, 0, 0}; + +/** + * \brief Flash driver capability macro definitions \ref ARM_FLASH_CAPABILITIES + */ +/* Flash Ready event generation capability values */ +#define EVENT_READY_NOT_AVAILABLE (0u) +#define EVENT_READY_AVAILABLE (1u) + +/* Chip erase capability values */ +#define CHIP_ERASE_NOT_SUPPORTED (0u) +#define CHIP_ERASE_SUPPORTED (1u) + +static inline ARM_DRIVER_VERSION ARM_Flash_GetVersion(void) +{ + return DriverVersion; +} + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES DriverCapabilities = { + EVENT_READY_NOT_AVAILABLE, + DATA_WIDTH_8BIT, + CHIP_ERASE_NOT_SUPPORTED +}; + +/* + * ARM FLASH device structure + */ +typedef struct rp2350_flash_dev_t{ + ARM_FLASH_INFO* data; /* FLASH data */ + uint32_t base; /* Flash base address, used for flash + reads */ + uint32_t size; /* Flash size */ + void (*save_mpu_state)(struct rp2350_flash_dev_t* dev); + /*!< Function to save MPU settings */ + void (*restore_mpu_state)(void); + /*!< Function to restore MPU settings */ +} rp2350_flash_dev_t; + +/* Driver Capabilities */ +static const ARM_FLASH_CAPABILITIES PicoDriverCapabilities = { + 0, /* event_ready */ + 0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */ + 0, /* erase_chip */ + 0, /* reserved */ +}; + +static inline ARM_FLASH_CAPABILITIES Pico_Driver_GetCapabilities(void) +{ + return PicoDriverCapabilities; +} + +static inline int32_t ARM_Flash_Uninitialize(void) +{ + /* Nothing to be done */ + return ARM_DRIVER_OK; +} + +static inline int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + break; + + case ARM_POWER_OFF: + case ARM_POWER_LOW: + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } +} + +static inline ARM_FLASH_STATUS ARM_Flash_GetStatus(void) +{ + return FlashStatus; +} + +/* + * \brief Macro for Pico Flash Driver + * + * \param[out] FLASH_DRIVER_NAME Resulting Driver name + */ +#define RPI_RP2350_FLASH(FLASH_DEV, FLASH_DRIVER_NAME) \ + \ +static int32_t FLASH_DRIVER_NAME##_Initialize( \ + ARM_Flash_SignalEvent_t cb_event) \ +{ \ + ARG_UNUSED(cb_event); \ + return ARM_DRIVER_OK; \ +} \ + \ +static int32_t FLASH_DRIVER_NAME##_ReadData(uint32_t addr, \ + void *data, \ + uint32_t cnt) \ +{ \ + if ((addr+cnt) >= FLASH_DEV.size) { \ + return ARM_DRIVER_ERROR_PARAMETER; \ + } \ + \ + memcpy(data, (void *)(addr + FLASH_DEV.base), cnt); \ + \ + return ARM_DRIVER_OK; \ +} \ + \ +static int32_t FLASH_DRIVER_NAME##_ProgramData(uint32_t addr, \ + const void *data, \ + uint32_t cnt) \ +{ \ + if ((addr+cnt) >= FLASH_DEV.size) { \ + return ARM_DRIVER_ERROR_PARAMETER; \ + } \ + \ + if ((cnt < FLASH_DEV.data->program_unit) || \ + (cnt % FLASH_DEV.data->program_unit) || \ + (addr % FLASH_DEV.data->page_size)) { \ + return ARM_DRIVER_ERROR_PARAMETER; \ + } \ + \ + FLASH_DEV.save_mpu_state(&FLASH_DEV); \ + \ + flash_range_program(addr, data, cnt); \ + \ + FLASH_DEV.restore_mpu_state(); \ + \ + return ARM_DRIVER_OK; \ +} \ + \ +static int32_t FLASH_DRIVER_NAME##_EraseSector(uint32_t addr) \ +{ \ + if (addr >= FLASH_DEV.size) { \ + return ARM_DRIVER_ERROR_PARAMETER; \ + } \ + \ + if (addr % FLASH_DEV.data->sector_size) { \ + return ARM_DRIVER_ERROR_PARAMETER; \ + } \ + \ + FLASH_DEV.save_mpu_state(&FLASH_DEV); \ + \ + flash_range_erase(addr, FLASH_DEV.data->sector_size); \ + \ + FLASH_DEV.restore_mpu_state(); \ + \ + return ARM_DRIVER_OK; \ +} \ + \ +static int32_t FLASH_DRIVER_NAME##_EraseChip(void) \ +{ \ + return ARM_DRIVER_ERROR_UNSUPPORTED; \ +} \ + \ +static ARM_FLASH_INFO * FLASH_DRIVER_NAME##_GetInfo(void) \ +{ \ + return FLASH_DEV.data; \ +} \ + \ +ARM_DRIVER_FLASH FLASH_DRIVER_NAME = { \ + ARM_Flash_GetVersion, \ + Pico_Driver_GetCapabilities, \ + FLASH_DRIVER_NAME##_Initialize, \ + ARM_Flash_Uninitialize, \ + ARM_Flash_PowerControl, \ + FLASH_DRIVER_NAME##_ReadData, \ + FLASH_DRIVER_NAME##_ProgramData, \ + FLASH_DRIVER_NAME##_EraseSector, \ + FLASH_DRIVER_NAME##_EraseChip, \ + ARM_Flash_GetStatus, \ + FLASH_DRIVER_NAME##_GetInfo \ +}; + +#endif /* __DRIVER_FLASH_RPI_H__ */ diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI_bl2.c b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI_bl2.c new file mode 100644 index 000000000..5878a4853 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_Flash_RPI_bl2.c @@ -0,0 +1,61 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_device_header.h" +#include "Driver_Flash_RPI.h" +#include "RTE_Device.h" + +#if (RTE_FLASH0) + +#define RP2350_FLASH_PAGE_SIZE 0x100 /* 256B */ +#define RP2350_FLASH_SECTOR_SIZE 0x1000 /* 4KB */ +#define RP2350_FLASH_SIZE PICO_FLASH_SIZE_BYTES +#define RP2350_FLASH_ERASE_VALUE 0xFF + +static ARM_FLASH_INFO RP2350_FLASH_DEV_DATA = { + .sector_info = NULL, /* Uniform sector layout */ + .sector_count = RP2350_FLASH_SIZE/ RP2350_FLASH_SECTOR_SIZE, + .sector_size = RP2350_FLASH_SECTOR_SIZE, + .page_size = RP2350_FLASH_PAGE_SIZE, + .program_unit = RP2350_FLASH_PAGE_SIZE, /* page aligned, page multipled */ + .erased_value = RP2350_FLASH_ERASE_VALUE +}; + +static uint32_t irq_state = 0; + +static inline uint32_t __save_disable_irq(void) +{ + uint32_t result = 0; + + __ASM volatile ("mrs %0, primask \n cpsid i" : "=r" (result) :: "memory"); + return result; +} + +static inline void __restore_irq(uint32_t status) +{ + __ASM volatile ("msr primask, %0" :: "r" (status) : "memory"); +} + +/* No need to save and restore MPU configuration for bl2 */ +static void dummy_save(struct rp2350_flash_dev_t* flash_dev){ + ARG_UNUSED(flash_dev); + irq_state = __save_disable_irq(); +} +static void dummy_restore(void){ + __restore_irq(irq_state); +} + +static rp2350_flash_dev_t RP2350_FLASH_DEV = { + .data = &RP2350_FLASH_DEV_DATA, + .base = XIP_BASE, + .size = RP2350_FLASH_SIZE, + .save_mpu_state = dummy_save, + .restore_mpu_state = dummy_restore +}; + + +RPI_RP2350_FLASH(RP2350_FLASH_DEV, RP2350_FLASH); +#endif /* RTE_FLASH0 */ diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.c b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.c new file mode 100644 index 000000000..46360d4f1 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.c @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "Driver_USART_RPI.h" +#include "RTE_Device.h" + + +#if (defined (RTE_USART0) && (RTE_USART0 == 1)) +#define UART_TX_PIN 0 +#define UART_RX_PIN 1 + +ARM_DRIVER_USART_RP2350((uart_inst_t *)UART0_BASE, driver_usart0, UART_RX_PIN, UART_TX_PIN); +#endif /* RTE_USART0 */ diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.h b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.h new file mode 100644 index 000000000..09a591a1c --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/Driver_USART_RPI.h @@ -0,0 +1,380 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __DRIVER_USART_RPI_H__ +#define __DRIVER_USART_RPI_H__ + +#include "Driver_USART.h" +#include "hardware/gpio.h" +#include "hardware/uart.h" + +#ifdef TFM_MULTI_CORE_TOPOLOGY +#include "platform_multicore.h" +#include "hardware/structs/sio.h" +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(arg) (void)arg +#endif + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */ + +/* Driver Version */ +static const ARM_DRIVER_VERSION DriverVersion = { + ARM_USART_API_VERSION, + ARM_USART_DRV_VERSION +}; + +/* Driver Capabilities */ +static const ARM_USART_CAPABILITIES DriverCapabilities = { + 1, /* supports UART (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports UART Single-wire mode */ + 0, /* supports UART IrDA mode */ + 0, /* supports UART Smart Card mode */ + 0, /* Smart Card Clock generator available */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ + 0 /* Reserved (must be zero) */ +}; + + +typedef struct { + uart_inst_t *dev; /* UART device */ + uint32_t tx_nbr_bytes; /* Number of bytes transfered */ + uint32_t rx_nbr_bytes; /* Number of bytes recevied */ + uint32_t default_baudrate; /* UART default baudrate */ + uint8_t rx_pin_num; /* RX pin number for GPIO config */ + uint8_t tx_pin_num; /* TX pin number for GPIO config */ + ARM_USART_SignalEvent_t cb_event; /* Callback function for events */ +} UARTx_Resources; +// +// Functions +// + +#ifdef TFM_MULTI_CORE_TOPOLOGY +static inline void spinlock_claim() +{ + /* Reading a spinlock register attempts to claim it, returning nonzero + * if the claim was successful and 0 if unsuccessful */ + while(!*UART_SPINLOCK); +} + +static inline void spinlock_release() +{ + /* Writing to a spinlock register releases it */ + *UART_SPINLOCK = 0x1u; +} +#endif + +static ARM_DRIVER_VERSION ARM_USART_GetVersion(void) +{ + return DriverVersion; +} + +static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void) +{ + return DriverCapabilities; +} + +static inline int32_t ARM_USARTx_Initialize(UARTx_Resources *uart_dev) +{ + gpio_set_function(uart_dev->rx_pin_num, GPIO_FUNC_UART); + gpio_set_function(uart_dev->tx_pin_num, GPIO_FUNC_UART); + uart_init(uart_dev->dev, uart_dev->default_baudrate); + + return ARM_DRIVER_OK; +} + +static inline int32_t ARM_USARTx_Uninitialize(UARTx_Resources *uart_dev) +{ + uart_deinit(uart_dev->dev); + + return ARM_DRIVER_OK; +} + +static int32_t ARM_USARTx_PowerControl(UARTx_Resources *uart_dev, ARM_POWER_STATE state) +{ + ARG_UNUSED(uart_dev); + + switch (state) { + case ARM_POWER_OFF: + case ARM_POWER_LOW: + return ARM_DRIVER_ERROR_UNSUPPORTED; + case ARM_POWER_FULL: + /* Nothing to be done */ + return ARM_DRIVER_OK; + /* default: The default is not defined intentionally to force the + * compiler to check that all the enumeration values are + * covered in the switch.*/ + } +} + +static inline int32_t ARM_USARTx_Send(UARTx_Resources *uart_dev, + const void *data, + uint32_t num) +{ + const uint8_t *p_data; + + if ((data == NULL) || (num == 0U)) { + /* Invalid parameters */ + return ARM_DRIVER_ERROR_PARAMETER; + } + +#ifdef TFM_MULTI_CORE_TOPOLOGY + spinlock_claim(); +#endif + + p_data = (const uint8_t *)data; + + /* Resets previous TX counter */ + uart_dev->tx_nbr_bytes = 0; + + while (uart_dev->tx_nbr_bytes != num) { + /* Waits until UART is ready to transmit */ + while (!uart_is_writable(uart_dev->dev)) { + } + /* As UART is ready to transmit at this point, the write function can + * not return any transmit error */ + uart_putc(uart_dev->dev, *p_data); + + uart_dev->tx_nbr_bytes++; + p_data++; + } + uart_tx_wait_blocking(uart_dev->dev); + + if (uart_dev->cb_event != NULL) { + uart_dev->cb_event(ARM_USART_EVENT_SEND_COMPLETE); + } +#ifdef TFM_MULTI_CORE_TOPOLOGY + spinlock_release(); +#endif + + return ARM_DRIVER_OK; +} + +static inline int32_t ARM_USARTx_Receive(UARTx_Resources *uart_dev, + void *data, uint32_t num) +{ + uint8_t *p_data; + + if ((data == NULL) || (num == 0U)) { + // Invalid parameters + return ARM_DRIVER_ERROR_PARAMETER; + } +#ifdef TFM_MULTI_CORE_TOPOLOGY + spinlock_claim(); +#endif + + p_data = (uint8_t *)data; + + /* Resets previous RX counter */ + uart_dev->rx_nbr_bytes = 0; + + while (uart_dev->rx_nbr_bytes != num) { + /* Waits until one character is received */ + while (uart_is_readable(uart_dev->dev)) { + *p_data = uart_getc(uart_dev->dev); + + uart_dev->rx_nbr_bytes++; + p_data++; + } + } + + if (uart_dev->cb_event != NULL) { + uart_dev->cb_event(ARM_USART_EVENT_RECEIVE_COMPLETE); + } +#ifdef TFM_MULTI_CORE_TOPOLOGY + spinlock_release(); +#endif + return ARM_DRIVER_OK; +} + +static inline uint32_t ARM_USARTx_GetTxCount(UARTx_Resources *uart_dev) +{ + return uart_dev->tx_nbr_bytes; +} + +static inline uint32_t ARM_USARTx_GetRxCount(UARTx_Resources *uart_dev) +{ + return uart_dev->rx_nbr_bytes; +} + +static inline int32_t ARM_USARTx_Control(UARTx_Resources *uart_dev, + uint32_t control, + uint32_t arg) +{ + switch (control & ARM_USART_CONTROL_Msk) { +#ifdef UART_TX_RX_CONTROL_ENABLED + case ARM_USART_CONTROL_TX: + if (arg == 0) { + uart_get_hw(uart)->cr &= ~UART_UARTCR_TXE_BITS; + } else if (arg == 1) { + uart_get_hw(uart)->cr |= UART_UARTCR_TXE_BITS; + } else { + return ARM_DRIVER_ERROR_PARAMETER; + } + break; + case ARM_USART_CONTROL_RX: + if (arg == 0) { + uart_get_hw(uart)->cr &= ~UART_UARTCR_RXE_BITS; + } else if (arg == 1) { + uart_get_hw(uart)->cr |= UART_UARTCR_RXE_BITS; + } else { + return ARM_DRIVER_ERROR_PARAMETER; + } + break; +#endif + case ARM_USART_MODE_ASYNCHRONOUS: + uart_set_baudrate(uart_dev->dev, arg); + break; + /* Unsupported command */ + default: + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Data bits */ + if (control & ARM_USART_DATA_BITS_Msk) { + /* Data bit is not configurable */ + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + /* UART Parity */ + if (control & ARM_USART_PARITY_Msk) { + /* Parity is not configurable */ + return ARM_USART_ERROR_PARITY; + } + + /* USART Stop bits */ + if (control & ARM_USART_STOP_BITS_Msk) { + /* Stop bit is not configurable */ + return ARM_USART_ERROR_STOP_BITS; + } + + return ARM_DRIVER_OK; +} + +/* + * \brief Macro for USART Driver + * + * \param[in] USART_DEV uart_inst_t pointer + * \param[out] USART_DRIVER_NAME Resulting Driver name + */ +#define ARM_DRIVER_USART_RP2350(USART_DEV, USART_DRIVER_NAME, RX_PIN, TX_PIN) \ +static UARTx_Resources USART_DRIVER_NAME##_DEV = { \ + .dev = USART_DEV, \ + .default_baudrate = 115200, \ + .tx_nbr_bytes = 0, \ + .rx_nbr_bytes = 0, \ + .rx_pin_num = RX_PIN, \ + .tx_pin_num = TX_PIN, \ + .cb_event = NULL, \ +}; \ + \ +static int32_t USART_DRIVER_NAME##_Initialize( \ + ARM_USART_SignalEvent_t cb_event) \ +{ \ + USART_DRIVER_NAME##_DEV.cb_event = cb_event; \ + \ + return ARM_USARTx_Initialize(&USART_DRIVER_NAME##_DEV); \ +} \ + \ +static int32_t USART_DRIVER_NAME##_Uninitialize(void) \ +{ \ + return ARM_USARTx_Uninitialize(&USART_DRIVER_NAME##_DEV); \ +} \ + \ +static int32_t USART_DRIVER_NAME##_PowerControl(ARM_POWER_STATE state) \ +{ \ + return ARM_USARTx_PowerControl(&USART_DRIVER_NAME##_DEV, state); \ +} \ + \ +static int32_t USART_DRIVER_NAME##_Send(const void *data, uint32_t num) \ +{ \ + return ARM_USARTx_Send(&USART_DRIVER_NAME##_DEV, data, num); \ +} \ + \ +static int32_t USART_DRIVER_NAME##_Receive(void *data, uint32_t num) \ +{ \ + return ARM_USARTx_Receive(&USART_DRIVER_NAME##_DEV, data, num); \ +} \ + \ +static int32_t USART_DRIVER_NAME##_Transfer(const void *data_out, \ + void *data_in, \ + uint32_t num) \ +{ \ + ARG_UNUSED(data_out); \ + ARG_UNUSED(data_in); \ + ARG_UNUSED(num); \ + \ + return ARM_DRIVER_ERROR_UNSUPPORTED; \ +} \ + \ +static uint32_t USART_DRIVER_NAME##_GetTxCount(void) \ +{ \ + return ARM_USARTx_GetTxCount(&USART_DRIVER_NAME##_DEV); \ +} \ + \ +static uint32_t USART_DRIVER_NAME##_GetRxCount(void) \ +{ \ + return ARM_USARTx_GetRxCount(&USART_DRIVER_NAME##_DEV); \ +} \ +static int32_t USART_DRIVER_NAME##_Control(uint32_t control, uint32_t arg) \ +{ \ + return ARM_USARTx_Control(&USART_DRIVER_NAME##_DEV, control, arg); \ +} \ + \ +static ARM_USART_STATUS USART_DRIVER_NAME##_GetStatus(void) \ +{ \ + ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0}; \ + return status; \ +} \ + \ +static int32_t USART_DRIVER_NAME##_SetModemControl( \ + ARM_USART_MODEM_CONTROL control) \ +{ \ + ARG_UNUSED(control); \ + return ARM_DRIVER_ERROR_UNSUPPORTED; \ +} \ + \ +static ARM_USART_MODEM_STATUS USART_DRIVER_NAME##_GetModemStatus(void) \ +{ \ + ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0}; \ + return modem_status; \ +} \ + \ +extern ARM_DRIVER_USART USART_DRIVER_NAME; \ +ARM_DRIVER_USART USART_DRIVER_NAME = { \ + ARM_USART_GetVersion, \ + ARM_USART_GetCapabilities, \ + USART_DRIVER_NAME##_Initialize, \ + USART_DRIVER_NAME##_Uninitialize, \ + USART_DRIVER_NAME##_PowerControl, \ + USART_DRIVER_NAME##_Send, \ + USART_DRIVER_NAME##_Receive, \ + USART_DRIVER_NAME##_Transfer, \ + USART_DRIVER_NAME##_GetTxCount, \ + USART_DRIVER_NAME##_GetRxCount, \ + USART_DRIVER_NAME##_Control, \ + USART_DRIVER_NAME##_GetStatus, \ + USART_DRIVER_NAME##_SetModemControl, \ + USART_DRIVER_NAME##_GetModemStatus \ +} + +#endif /* __DRIVER_USART_RPI_H__ */ diff --git a/platform/ext/target/rpi/rp2350/cmsis_drivers/RTE_Device.h b/platform/ext/target/rpi/rp2350/cmsis_drivers/RTE_Device.h new file mode 100644 index 000000000..5624bbd79 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cmsis_drivers/RTE_Device.h @@ -0,0 +1,24 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_USART0 1 + +// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_USART1 0 + +// Flash device emulated in SRAM [Driver_Flash0] +// Configuration settings for Driver_Flash0 in component ::Drivers:Flash +#define RTE_FLASH0 1 + +#endif /* __RTE_DEVICE_H */ \ No newline at end of file diff --git a/platform/ext/target/rpi/rp2350/config.cmake b/platform/ext/target/rpi/rp2350/config.cmake new file mode 100644 index 000000000..379458043 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/config.cmake @@ -0,0 +1,58 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +set(PROVISIONING_KEYS_CONFIG "" CACHE FILEPATH "The config file which has the keys and seeds for provisioning") + +if(BL2) + set(BL2_TRAILER_SIZE 0x800 CACHE STRING "Trailer size") +else() + #No header if no bootloader, but keep IMAGE_CODE_SIZE the same + set(BL2_TRAILER_SIZE 0xC00 CACHE STRING "Trailer size") +endif() + +# Platform-specific configurations +set(TFM_MULTI_CORE_TOPOLOGY OFF CACHE BOOL "Enable Multicore topology") +if (TFM_MULTI_CORE_TOPOLOGY) + set(TFM_NS_MAILBOX_API ON) + set(TFM_PARTITION_NS_AGENT_MAILBOX ON) + set(TFM_NS_CUSTOM_API ON) +else() + set(TFM_NS_MAILBOX_API OFF) + set(TFM_PARTITION_NS_AGENT_MAILBOX OFF) + set(TFM_NS_CUSTOM_API OFF) +endif() + +set(CONFIG_TFM_USE_TRUSTZONE ON) +set(MCUBOOT_USE_PSA_CRYPTO ON CACHE BOOL "Enable the cryptographic abstraction layer to use PSA Crypto APIs") +set(MCUBOOT_SIGNATURE_TYPE "EC-P256" CACHE STRING "Algorithm to use for signature validation [RSA-2048, RSA-3072, EC-P256, EC-P384]") +set(MCUBOOT_HW_KEY OFF CACHE BOOL "Whether to embed the entire public key in the image metadata instead of the hash only") +set(MCUBOOT_BUILTIN_KEY ON CACHE BOOL "Use builtin key(s) for validation, no public key data is embedded into the image metadata") + +set(PROVISIONING_CODE_PADDED_SIZE "0x2000" CACHE STRING "") +set(PROVISIONING_VALUES_PADDED_SIZE "0x400" CACHE STRING "") +set(PROVISIONING_DATA_PADDED_SIZE "0x400" CACHE STRING "") + +set(PICO_SDK_FETCH_FROM_GIT_TAG "2.1.1" CACHE STRING "Use the define Pico SDK tag for the build") + +set(TFM_MBEDCRYPTO_PLATFORM_EXTRA_CONFIG_PATH ${CMAKE_CURRENT_LIST_DIR}/mbedtls_extra_config.h CACHE PATH "Config to append to standard Mbed Crypto config, used by platforms to cnfigure feature support") + +set(PLATFORM_DEFAULT_PROV_LINKER_SCRIPT OFF CACHE BOOL "Use default provisioning linker script") +set(ITS_ENCRYPTION ON CACHE BOOL "Enable authenticated encryption of ITS files using platform specific APIs") +set(PLATFORM_DEFAULT_NV_SEED OFF CACHE BOOL "Use default NV seed implementation.") +set(PLATFORM_DEFAULT_OTP OFF CACHE BOOL "Use trusted on-chip flash to implement OTP memory") +set(PLATFORM_DEFAULT_NV_COUNTERS OFF CACHE BOOL "Use default nv counter implementation.") + +set(PLATFORM_DEFAULT_CRYPTO_KEYS OFF CACHE BOOL "Use default crypto keys implementation.") + +set(PS_NS_NV_COUNTER_IN_ITS ON CACHE BOOL "Use ITS for PS and NS NV counters.") + +if (PS_NS_NV_COUNTER_IN_ITS) + # Config to append to standard TFM_SP_PLATFORM, to add dependency on ITS partition + set(TFM_RP2350_MANIFEST_LIST ${CMAKE_CURRENT_LIST_DIR}/manifest/tfm_manifest_list.yaml) +else() + set(TFM_RP2350_MANIFEST_LIST ${CMAKE_SOURCE_DIR}/tools/tfm_manifest_list.yaml) +endif() +set(TFM_MANIFEST_LIST ${TFM_RP2350_MANIFEST_LIST} CACHE PATH "Platform specific Secure Partition manifests file" FORCE) diff --git a/platform/ext/target/rpi/rp2350/config_tfm_target.h b/platform/ext/target/rpi/rp2350/config_tfm_target.h new file mode 100644 index 000000000..ebbe22d29 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/config_tfm_target.h @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __CONFIG_TFM_TARGET_H__ +#define __CONFIG_TFM_TARGET_H__ + +/* Use stored NV seed to provide entropy */ +#define CRYPTO_NV_SEED 0 + +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + +/* Run the scheduler after handling a secure interrupt if the NSPE was pre-empted */ +#define CONFIG_TFM_SCHEDULE_WHEN_NS_INTERRUPTED 1 + +/* Use ITS for PS and NS NV counters */ +#define NV_COUNTER_IN_ITS 1 + +#endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/rpi/rp2350/cpuarch.cmake b/platform/ext/target/rpi/rp2350/cpuarch.cmake new file mode 100644 index 000000000..d049ea299 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/cpuarch.cmake @@ -0,0 +1,13 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +# Set architecture and CPU +set(TFM_SYSTEM_PROCESSOR cortex-m33) +set(TFM_SYSTEM_ARCHITECTURE armv8-m.main) + +set(TFM_SYSTEM_DSP OFF) +set(CONFIG_TFM_FP_ARCH "fpv5-d16") +set(CONFIG_TFM_FP_ARCH_ASM "FPv5_D16") diff --git a/platform/ext/target/rpi/rp2350/crypto_keys.c b/platform/ext/target/rpi/rp2350/crypto_keys.c new file mode 100644 index 000000000..4ea25beb9 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/crypto_keys.c @@ -0,0 +1,155 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include +#include "tfm_plat_crypto_keys.h" +#include "tfm_builtin_key_ids.h" +#include "tfm_plat_otp.h" +#include "psa_manifest/pid.h" +#include "tfm_builtin_key_loader.h" + +#define NUMBER_OF_ELEMENTS_OF(x) sizeof(x)/sizeof(*x) +#define MAPPED_TZ_NS_AGENT_DEFAULT_CLIENT_ID -0x3c000000 +#define TFM_NS_PARTITION_ID MAPPED_TZ_NS_AGENT_DEFAULT_CLIENT_ID +#define MAPPED_RSE_MBOX_NS_AGENT_DEFAULT_CLIENT_ID -0x04000000 +#define TFM_NS_MAILBOX_PARTITION_ID MAPPED_RSE_MBOX_NS_AGENT_DEFAULT_CLIENT_ID + +static enum tfm_plat_err_t tfm_plat_get_huk(uint8_t *buf, size_t buf_len, + size_t *key_len, + psa_key_bits_t *key_bits, + psa_algorithm_t *algorithm, + psa_key_type_t *type) +{ + enum tfm_plat_err_t err; + + err = tfm_plat_otp_read(PLAT_OTP_ID_HUK, buf_len, buf); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + err = tfm_plat_otp_get_size(PLAT_OTP_ID_HUK, key_len); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + *key_bits = *key_len * 8; + *algorithm = PSA_ALG_HKDF(PSA_ALG_SHA_256); + *type = PSA_KEY_TYPE_DERIVE; + + return TFM_PLAT_ERR_SUCCESS; +} + +#ifdef TFM_PARTITION_INITIAL_ATTESTATION +static enum tfm_plat_err_t tfm_plat_get_iak(uint8_t *buf, size_t buf_len, + size_t *key_len, + psa_key_bits_t *key_bits, + psa_algorithm_t *algorithm, + psa_key_type_t *type) +{ + enum tfm_plat_err_t err; +#ifndef SYMMETRIC_INITIAL_ATTESTATION + psa_ecc_family_t curve_type; +#endif /* SYMMETRIC_INITIAL_ATTESTATION */ + + err = tfm_plat_otp_read(PLAT_OTP_ID_IAK_LEN, + sizeof(size_t), (uint8_t*)key_len); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + *key_bits = *key_len * 8; + + if (buf_len < *key_len) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + +#ifdef SYMMETRIC_INITIAL_ATTESTATION + err = tfm_plat_otp_read(PLAT_OTP_ID_IAK_TYPE, + sizeof(psa_algorithm_t), (uint8_t*)algorithm); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + *type = PSA_KEY_TYPE_HMAC; +#else /* SYMMETRIC_INITIAL_ATTESTATION */ + err = tfm_plat_otp_read(PLAT_OTP_ID_IAK_TYPE, sizeof(psa_ecc_family_t), + &curve_type); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + *algorithm = PSA_ALG_ECDSA(PSA_ALG_SHA_256); + *type = PSA_KEY_TYPE_ECC_KEY_PAIR(curve_type); +#endif /* SYMMETRIC_INITIAL_ATTESTATION */ + + return tfm_plat_otp_read(PLAT_OTP_ID_IAK, *key_len, buf); +} +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ + +#ifdef TFM_PARTITION_INITIAL_ATTESTATION +/** + * @brief Table describing per-user key policy for the IAK + * + */ +static const tfm_plat_builtin_key_per_user_policy_t g_iak_per_user_policy[] = { + {.user = TFM_SP_INITIAL_ATTESTATION, +#ifdef SYMMETRIC_INITIAL_ATTESTATION + .usage = PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_EXPORT, +#else + .usage = PSA_KEY_USAGE_SIGN_HASH, +#endif /* SYMMETRIC_INITIAL_ATTESTATION */ + }, +#ifdef TEST_S_ATTESTATION + {.user = TFM_SP_SECURE_TEST_PARTITION, .usage = PSA_KEY_USAGE_VERIFY_HASH}, +#endif /* TEST_S_ATTESTATION */ +#ifdef TEST_NS_ATTESTATION + {.user = TFM_NS_PARTITION_ID, .usage = PSA_KEY_USAGE_VERIFY_HASH}, + {.user = TFM_NS_MAILBOX_PARTITION_ID, .usage = PSA_KEY_USAGE_VERIFY_HASH}, +#endif /* TEST_NS_ATTESTATION */ +}; +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ + +/** + * @brief Table describing per-key user policies + * + */ +static const tfm_plat_builtin_key_policy_t g_builtin_keys_policy[] = { + {.key_id = TFM_BUILTIN_KEY_ID_HUK, .per_user_policy = 0, .usage = PSA_KEY_USAGE_DERIVE}, +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + {.key_id = TFM_BUILTIN_KEY_ID_IAK, + .per_user_policy = NUMBER_OF_ELEMENTS_OF(g_iak_per_user_policy), + .policy_ptr = g_iak_per_user_policy}, +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ +}; + +/** + * @brief Table describing the builtin-in keys (plaform keys) available in the platform. Note + * that to bind the keys to the tfm_builtin_key_loader driver, the lifetime must be + * explicitly set to the one associated to the driver, i.e. TFM_BUILTIN_KEY_LOADER_LIFETIME + */ +static const tfm_plat_builtin_key_descriptor_t g_builtin_keys_desc[] = { + {.key_id = TFM_BUILTIN_KEY_ID_HUK, + .slot_number = TFM_BUILTIN_KEY_SLOT_HUK, + .lifetime = TFM_BUILTIN_KEY_LOADER_LIFETIME, + .loader_key_func = tfm_plat_get_huk}, +#ifdef TFM_PARTITION_INITIAL_ATTESTATION + {.key_id = TFM_BUILTIN_KEY_ID_IAK, + .slot_number = TFM_BUILTIN_KEY_SLOT_IAK, + .lifetime = TFM_BUILTIN_KEY_LOADER_LIFETIME, + .loader_key_func = tfm_plat_get_iak}, +#endif /* TFM_PARTITION_INITIAL_ATTESTATION */ +}; + +size_t tfm_plat_builtin_key_get_policy_table_ptr(const tfm_plat_builtin_key_policy_t *desc_ptr[]) +{ + *desc_ptr = &g_builtin_keys_policy[0]; + return NUMBER_OF_ELEMENTS_OF(g_builtin_keys_policy); +} + +size_t tfm_plat_builtin_key_get_desc_table_ptr(const tfm_plat_builtin_key_descriptor_t *desc_ptr[]) +{ + *desc_ptr = &g_builtin_keys_desc[0]; + return NUMBER_OF_ELEMENTS_OF(g_builtin_keys_desc); +} diff --git a/platform/ext/target/rpi/rp2350/device/config/device_cfg.h b/platform/ext/target/rpi/rp2350/device/config/device_cfg.h new file mode 100644 index 000000000..f83e8d503 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/device/config/device_cfg.h @@ -0,0 +1,19 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configurations for peripherals defined in + * platform's device definition + */ + +#define DEFAULT_UART_CONTROL 0 +#define DEFAULT_UART_BAUDRATE 115200 + +#endif /* __DEVICE_CFG_H__ */ diff --git a/platform/ext/target/rpi/rp2350/extra_init.c b/platform/ext/target/rpi/rp2350/extra_init.c new file mode 100644 index 000000000..bda0fbca5 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/extra_init.c @@ -0,0 +1,117 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "pico/runtime.h" +#include "pico/runtime_init.h" +#include "hardware/structs/scb.h" +#ifdef PSA_API_TEST_CRYPTO +#include "hardware/ticks.h" +#include "hardware/clocks.h" +#endif + +#include "stdint.h" + +/* Do not use __cmsis_start */ +#define __PROGRAM_START +#include "tfm_hal_device_header.h" + +void copy_zero_tables(void) { + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } +} + +void hard_assertion_failure(void) { + SPM_ASSERT(0); +} + +static void runtime_run_initializers_from(uintptr_t *from) { + + /* Start and end points of the constructor list, defined by the linker script. */ + extern uintptr_t __preinit_array_end; + + /* Call each function in the list, based on the mask + We have to take the address of the symbols, as __preinit_array_start *is* + the first function value, not the address of it. */ + for (uintptr_t *p = from; p < &__preinit_array_end; p++) { + uintptr_t val = *p; + ((void (*)(void))val)(); + } +} + +void runtime_run_initializers(void) { + extern uintptr_t __preinit_array_start; + runtime_run_initializers_from(&__preinit_array_start); +} + +/* We keep the per-core initializers in the standard __preinit_array so a standard C library + initialization will fo the core 0 initialization, however we also want to be able to find + them after the fact so that we can run them on core 1. Per core initializers have sections + __preinit_array.ZZZZZ.nnnnn i.e. the ZZZZZ sorts below all the standard __preinit_array.nnnnn + values, and then we sort within the ZZZZZ. + + We create a dummy initializer in __preinit_array.YYYYY (between the standard initializers + and the per core initializers), so we find the first per core initializer. Whilst we could + have done this via an entry in the linker script, we want to preserve backwards compatibility + with RP2040 custom linker scripts. */ +static void first_per_core_initializer(void) {} +PICO_RUNTIME_INIT_FUNC(first_per_core_initializer, "YYYYY"); + +void runtime_run_per_core_initializers(void) { + runtime_run_initializers_from(&__pre_init_first_per_core_initializer); +} + +extern uint32_t __vectors_start__; +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +extern uint64_t __STACK_SEAL; + +void runtime_init(void) { + scb_hw->vtor = (uintptr_t) &__vectors_start__; + copy_zero_tables(); + + __disable_irq(); + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); + + runtime_run_initializers(); + +#ifdef PSA_API_TEST_CRYPTO + /* RSA Key generation test takes very long. Use 4 times slower WD + reference tick when it is enabled. */ + tick_start(TICK_WATCHDOG, 4 * clock_get_hz(clk_ref) / MHZ); +#endif + + SystemInit(); +} diff --git a/platform/ext/target/rpi/rp2350/linker_bl2.ld b/platform/ext/target/rpi/rp2350/linker_bl2.ld new file mode 100644 index 000000000..5dfd04ce9 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/linker_bl2.ld @@ -0,0 +1,284 @@ +;/* +; * SPDX-License-Identifier: BSD-3-Clause +; * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +; * +; */ +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ +#include "region_defs.h" +MEMORY +{ + FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE + RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE +#ifdef __ENABLE_SCRATCH__ + SCRATCH_X(rwx) : ORIGIN = SCRATCH_X_START, LENGTH = SCRATCH_X_SIZE + SCRATCH_Y(rwx) : ORIGIN = SCRATCH_Y_START, LENGTH = SCRATCH_Y_SIZE +#endif +} +__heap_size__ = BL2_HEAP_SIZE; +__msp_stack_size__ = BL2_MSP_STACK_SIZE; +ENTRY(Reset_Handler) +SECTIONS +{ + .flash_begin : { + __flash_binary_start = .; + } > FLASH + .text (READONLY) : + { + __logical_binary_start = .; + __Vectors_Start = .; + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors_Start; + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + __end__ = .; + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + /* .copy.table */ + . = ALIGN(4); + __copy_table_start__ = .; +#ifdef CODE_SHARING + LONG (LOADADDR(.tfm_shared_symbols)) + LONG (ADDR(.tfm_shared_symbols)) + LONG (SIZEOF(.tfm_shared_symbols) / 4) +#endif + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + __copy_table_end__ = .; + /* .zero.table */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) + __zero_table_end__ = .; + KEEP(*(.init)) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*) + KEEP(*(.fini)) + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*) + *(.srodata*) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + . = ALIGN(4); + KEEP(*(.eh_frame*)) + . = ALIGN(4); + } > FLASH + /* Note the boot2 section is optional, and should be discarded if there is + no reference to it *inside* the binary, as it is not called by the + bootrom. (The bootrom performs a simple best-effort XIP setup and + leaves it to the binary to do anything more sophisticated.) However + there is still a size limit of 256 bytes, to ensure the boot2 can be + stored in boot RAM. + Really this is a "XIP setup function" -- the name boot2 is historic and + refers to its dual-purpose on RP2040, where it also handled vectoring + from the bootrom into the user image. + */ + .boot2 : { + __boot2_start__ = .; + *(.boot2) + __boot2_end__ = .; + } > FLASH + ASSERT(__boot2_end__ - __boot2_start__ <= 256, + "ERROR: Pico second stage bootloader must be no more than 256 bytes in size") + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; +#ifdef CODE_SHARING + /* The code sharing between bootloader and runtime firmware requires to + * share the global variables. Section size must be equal with + * SHARED_SYMBOL_AREA_SIZE defined in region_defs.h + */ + .tfm_shared_symbols : ALIGN(4) + { + *(.data.mbedtls_calloc_func) + *(.data.mbedtls_free_func) + *(.data.mbedtls_exit) + *(.data.memset_func) + . = ALIGN(SHARED_SYMBOL_AREA_SIZE); + } > RAM AT > FLASH + ASSERT(SHARED_SYMBOL_AREA_SIZE % 4 == 0, "SHARED_SYMBOL_AREA_SIZE must be divisible by 4") +#endif + .tfm_bl2_shared_data : ALIGN(32) + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data); + Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data); + . = ALIGN(4); + .ram_vector_table (NOLOAD): { + *(.ram_vector_table) + } > RAM + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.time_critical*) + /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */ + *(.text*) + . = ALIGN(4); + *(.rodata*) + . = ALIGN(4); + *(.data*) + *(.sdata*) + . = ALIGN(4); + *(.after_data.*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + } > RAM AT > FLASH + __etext = LOADADDR(.data); + Image$$ER_DATA$$Base = ADDR(.data); + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM + .bss : ALIGN(4) + { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*))) + *(COMMON) + PROVIDE(__global_pointer$ = . + 2K); + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .msp_stack ALIGN(32) : + { + . += __msp_stack_size__ - 0x8; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + .msp_stack_seal_res : + { + . += 0x8; + } > RAM + __StackSeal = ADDR(.msp_stack_seal_res); +#else + .msp_stack ALIGN(32) : + { + . += __msp_stack_size__; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#ifdef __ENABLE_SCRATCH__ + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); +#endif + .heap (NOLOAD): ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + KEEP(*(.heap*)) + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + /* .stack*_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later + * + * stack1 section may be empty/missing if platform_launch_core1 is not used */ + /* by default we put core 0 stack at the end of scratch Y, so that if core 1 + * stack is not used then all of SCRATCH_X is free. + */ +#ifdef __ENABLE_SCRATCH__ + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y +#endif + .flash_end : { + PROVIDE(__flash_binary_end = .); + } > FLASH =0xaa + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); +#ifdef __ENABLE_SCRATCH__ + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") +#endif + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") + /* todo assert on extra code */ +} diff --git a/platform/ext/target/rpi/rp2350/linker_ns.ld b/platform/ext/target/rpi/rp2350/linker_ns.ld new file mode 100644 index 000000000..3e2744352 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/linker_ns.ld @@ -0,0 +1,242 @@ +;/* +; * SPDX-License-Identifier: BSD-3-Clause +; * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +; * +; */ +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ +#include "region_defs.h" +/* Include file with definitions for section alignments. + * Note: it should be included after region_defs.h to let platform define + * default values if needed. */ +MEMORY +{ + FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE + RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE +#ifdef __ENABLE_SCRATCH__ + SCRATCH_X(rwx) : ORIGIN = SRAM_SCRATCH_X_BASE, LENGTH = SCRATCH_X_SIZE + SCRATCH_Y(rwx) : ORIGIN = SRAM_SCRATCH_Y_BASE, LENGTH = SCRATCH_Y_SIZE +#endif +} + +__heap_size__ = NS_HEAP_SIZE; +__stack_size__ = NS_STACK_SIZE; +ENTRY(_entry_point) +SECTIONS +{ + .vectors : + { + __logical_binary_start = .; + __Vectors_Start__ = .; + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors_Start__; + __end__ = .; + } > FLASH + +#if defined(NS_VECTOR_ALLOCATED_SIZE) + ASSERT(. <= ADDR(.vectors) + NS_VECTOR_ALLOCATED_SIZE, ".vectors section size overflow.") + . = ADDR(.vectors) + NS_VECTOR_ALLOCATED_SIZE; +#endif + + .CORE1_ENTRY : ALIGN(4) + { + KEEP (*(.core1_ns_entry*)) + } + + .PICO_RESET : ALIGN(4) + { + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + } > FLASH + + .text (READONLY) : + { + *(.text*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .copy.table */ + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) + __copy_table_end__ = .; + + /* .zero.table */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__) / 4) + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) + __zero_table_end__ = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + + __etext2 = ALIGN(4); + + .data : AT (__etext2) + { + __data2_start__ = .; + *(vtable) + *(.data*) + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data2_end__ = .; + } > RAM + + /* Pico crt0.S copies the __data_start__-__data_end__ region, but we handle + * that in our runtime_init */ + __etext = 0; + __data_start__ = 0; + __data_end__ = 0; + + .ram_vector_table (NOLOAD): ALIGN(256) { + *(.ram_vector_table) + } > RAM + + .bss : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM + + /* Pico crt0.S zeros the __bss_start__-__bss_end__ region, but we handle + * that in our runtime_init */ + __bss_start__ = 0; + __bss_end__ = 0; + + bss_size = __bss2_end__ - __bss2_start__; + + .heap : ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > RAM + + #ifdef __ENABLE_SCRATCH__ + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + /* stack limit is poorly named, but historically is maximum heap ptr */ + __StackLimit = ORIGIN(RAM) + LENGTH(RAM); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); + __StackBottom = __StackTop - SIZEOF(.stack_dummy); + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed") + PROVIDE(__stack = __StackTop); +#endif + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") +} diff --git a/platform/ext/target/rpi/rp2350/linker_provisioning.ld b/platform/ext/target/rpi/rp2350/linker_provisioning.ld new file mode 100644 index 000000000..a613940bd --- /dev/null +++ b/platform/ext/target/rpi/rp2350/linker_provisioning.ld @@ -0,0 +1,50 @@ +;/* +; * SPDX-License-Identifier: BSD-3-Clause +; * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +; * +; */ + +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ + +#include "region_defs.h" + +MEMORY +{ + CODE (rx) : ORIGIN = PROVISIONING_BUNDLE_CODE_START, LENGTH = PROVISIONING_BUNDLE_CODE_SIZE + DATA (rw) : ORIGIN = PROVISIONING_BUNDLE_DATA_START, LENGTH = PROVISIONING_BUNDLE_DATA_SIZE + VALUES (r) : ORIGIN = PROVISIONING_BUNDLE_VALUES_START, LENGTH = PROVISIONING_BUNDLE_VALUES_SIZE +} + +ENTRY(do_provisioning) + +SECTIONS +{ + CODE : + { + *provisioning_code.o(DO_PROVISION) + *(.text*) + *(.time_critical*) + } > CODE + + RW_DATA : + { + *(COMMON .data*) + } > DATA + + RO_DATA : + { + *(EXCLUDE_FILE (*provisioning_data.o) .rodata*) + } > DATA + + BSS_DATA : + { + *(.bss*) + } > DATA + + VALUES : + { + *provisioning_data.o(.rodata.data) + } > VALUES + +} diff --git a/platform/ext/target/rpi/rp2350/linker_s.ld b/platform/ext/target/rpi/rp2350/linker_s.ld new file mode 100644 index 000000000..084b1fc67 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/linker_s.ld @@ -0,0 +1,576 @@ +;/* +; * SPDX-License-Identifier: BSD-3-Clause +; * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +; * +; */ +/* Linker script to configure memory regions. */ +/* This file will be run trough the pre-processor. */ +#include "region_defs.h" +/* Include file with definitions for section alignments. + * Note: it should be included after region_defs.h to let platform define + * default values if needed. */ +#include "tfm_s_linker_alignments.h" +MEMORY +{ + FLASH (rx) : ORIGIN = S_CODE_START, LENGTH = S_CODE_SIZE + RAM (rw) : ORIGIN = S_DATA_START, LENGTH = S_DATA_SIZE +#if defined(S_RAM_CODE_START) + CODE_RAM (rwx) : ORIGIN = S_RAM_CODE_START, LENGTH = S_RAM_CODE_SIZE +#endif +#ifdef __ENABLE_SCRATCH__ + SCRATCH_X(rwx) : ORIGIN = SCRATCH_X_START, LENGTH = SCRATCH_X_SIZE + SCRATCH_Y(rwx) : ORIGIN = SCRATCH_Y_START, LENGTH = SCRATCH_Y_SIZE +#endif +} + +#ifndef TFM_LINKER_VENEERS_START +#define TFM_LINKER_VENEERS_START ALIGN(TFM_LINKER_VENEERS_ALIGNMENT) +#endif + +#ifndef TFM_LINKER_VENEERS_END +#define TFM_LINKER_VENEERS_END ALIGN(TFM_LINKER_VENEERS_ALIGNMENT) +#endif + +#define VENEERS() \ +/* \ + * Place the CMSE Veneers (containing the SG instruction) after the code, in \ + * a separate at least 32 bytes aligned region so that the SAU can \ + * programmed to just set this region as Non-Secure Callable. \ + */ \ +.gnu.sgstubs TFM_LINKER_VENEERS_START : \ +{ \ + *(.gnu.sgstubs*) \ +} > FLASH \ +/* GCC always places veneers at the end of .gnu.sgstubs section, so the only \ + * way to align the end of .gnu.sgstubs section is to align start of the \ + * next section */ \ +.sgstubs_end : TFM_LINKER_VENEERS_END \ +{ \ +} > FLASH + +__msp_stack_size__ = S_MSP_STACK_SIZE; + +ENTRY(_entry_point) + +SECTIONS +{ + /* Start address of the code. */ + Image$$PT_RO_START$$Base = ADDR(.TFM_VECTORS); + + .TFM_VECTORS : ALIGN(4) + { + __logical_binary_start = .; + __vectors_start__ = .; + KEEP(*(.vectors)) + . = ALIGN(4); + __vectors_end__ = .; + } > FLASH + + ASSERT(__vectors_start__ != __vectors_end__, ".vectors should not be empty") + +#if defined(S_CODE_VECTOR_TABLE_SIZE) + ASSERT(. <= ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE, ".TFM_VECTORS section size overflow.") + . = ADDR(.TFM_VECTORS) + S_CODE_VECTOR_TABLE_SIZE; +#endif + + .PICO_RESET : ALIGN(4) + { + KEEP (*(.binary_info_header)) + __binary_info_header_end = .; + KEEP (*(.embedded_block)) + __embedded_block_end = .; + KEEP (*(.reset)) + } > FLASH + +#if defined(CONFIG_TFM_USE_TRUSTZONE) && !defined(TFM_LINKER_VENEERS_LOCATION_END) + VENEERS() +#endif + + /**** Section for holding partition RO load data */ + /* + * Sort the partition info by priority to guarantee the initing order. + * The first loaded partition will be inited at last in SFN model. + */ + .TFM_SP_LOAD_LIST ALIGN(4) : + { + KEEP(*(.part_load_priority_00)) + KEEP(*(.part_load_priority_01)) + KEEP(*(.part_load_priority_02)) + KEEP(*(.part_load_priority_03)) + } > FLASH + Image$$TFM_SP_LOAD_LIST$$RO$$Base = ADDR(.TFM_SP_LOAD_LIST); + Image$$TFM_SP_LOAD_LIST$$RO$$Limit = ADDR(.TFM_SP_LOAD_LIST) + SIZEOF(.TFM_SP_LOAD_LIST); + + /**** PSA RoT RO part (CODE + RODATA) start here */ + . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT); + Image$$TFM_PSA_CODE_START$$Base = .; + + .TFM_PSA_ROT_LINKER ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT) : + { + *tfm_psa_rot_partition*:(SORT_BY_ALIGNMENT(.text*)) + *tfm_psa_rot_partition*:(SORT_BY_ALIGNMENT(.rodata*)) + *(TFM_*_PSA-ROT_ATTR_FN) + . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_CODE_ALIGNMENT); + } > FLASH + + Image$$TFM_PSA_ROT_LINKER$$RO$$Base = ADDR(.TFM_PSA_ROT_LINKER); + Image$$TFM_PSA_ROT_LINKER$$RO$$Limit = ADDR(.TFM_PSA_ROT_LINKER) + SIZEOF(.TFM_PSA_ROT_LINKER); + Image$$TFM_PSA_ROT_LINKER$$Base = ADDR(.TFM_PSA_ROT_LINKER); + Image$$TFM_PSA_ROT_LINKER$$Limit = ADDR(.TFM_PSA_ROT_LINKER) + SIZEOF(.TFM_PSA_ROT_LINKER); + + /**** PSA RoT RO part (CODE + RODATA) end here */ + Image$$TFM_PSA_CODE_END$$Base = .; + + /**** APPLICATION RoT RO part (CODE + RODATA) start here */ + Image$$TFM_APP_CODE_START$$Base = .; + + .TFM_APP_ROT_LINKER ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT) : + { + *tfm_app_rot_partition*:(SORT_BY_ALIGNMENT(.text*)) + *tfm_app_rot_partition*:(SORT_BY_ALIGNMENT(.rodata*)) + *(TFM_*_APP-ROT_ATTR_FN) + . = ALIGN(TFM_LINKER_APP_ROT_LINKER_CODE_ALIGNMENT); + } > FLASH + + Image$$TFM_APP_ROT_LINKER$$RO$$Base = ADDR(.TFM_APP_ROT_LINKER); + Image$$TFM_APP_ROT_LINKER$$RO$$Limit = ADDR(.TFM_APP_ROT_LINKER) + SIZEOF(.TFM_APP_ROT_LINKER); + Image$$TFM_APP_ROT_LINKER$$Base = ADDR(.TFM_APP_ROT_LINKER); + Image$$TFM_APP_ROT_LINKER$$Limit = ADDR(.TFM_APP_ROT_LINKER) + SIZEOF(.TFM_APP_ROT_LINKER); + + /**** APPLICATION RoT RO part (CODE + RODATA) end here */ + Image$$TFM_APP_CODE_END$$Base = .; + +#if defined(S_RAM_CODE_START) + /* Flash drivers code that gets copied from Flash */ + .ER_CODE_SRAM ALIGN(S_RAM_CODE_START, 4) : + { + *libflash_drivers*:(SORT_BY_ALIGNMENT(.text*)) + *libflash_drivers*:(SORT_BY_ALIGNMENT(.rodata*)) + KEEP(*(.ramfunc)) + . = ALIGN(4); /* This alignment is needed to make the section size 4 bytes aligned */ + } > CODE_RAM AT > FLASH + + ASSERT(S_RAM_CODE_START % 4 == 0, "S_RAM_CODE_START must be divisible by 4") + + Image$$ER_CODE_SRAM$$RO$$Base = ADDR(.ER_CODE_SRAM); + Image$$ER_CODE_SRAM$$RO$$Limit = ADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM); + Image$$ER_CODE_SRAM$$Base = ADDR(.ER_CODE_SRAM); + Image$$ER_CODE_SRAM$$Limit = ADDR(.ER_CODE_SRAM) + SIZEOF(.ER_CODE_SRAM); +#endif + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* Machine inspectable binary information */ + . = ALIGN(4); + __binary_info_start = .; + .binary_info : + { + KEEP(*(.binary_info.keep.*)) + *(.binary_info.*) + } > FLASH + __binary_info_end = .; + + /* Data copy is done by extra_init */ + __etext = 0; + __data_start__ = 0; + __data_end__ = 0; + + .ER_TFM_CODE ALIGN(4) (READONLY) : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__mutex_array_start = .); + KEEP(*(SORT(.mutex_array.*))) + KEEP(*(.mutex_array)) + PROVIDE_HIDDEN (__mutex_array_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(SORT(.preinit_array.*))) + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .copy.table */ + . = ALIGN(4); + __copy_table_start__ = .; +#ifdef RAM_VECTORS_SUPPORT + /* Copy interrupt vectors from flash to RAM */ + LONG (__vectors_start__) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG ((__vectors_end__ - __vectors_start__) / 4) /* Size */ +#endif + LONG (LOADADDR(.TFM_DATA)) + LONG (ADDR(.TFM_DATA)) + LONG (SIZEOF(.TFM_DATA) / 4) + + LONG (LOADADDR(.TFM_PSA_ROT_LINKER_DATA)) + LONG (ADDR(.TFM_PSA_ROT_LINKER_DATA)) + LONG (SIZEOF(.TFM_PSA_ROT_LINKER_DATA) / 4) + + LONG (LOADADDR(.TFM_APP_ROT_LINKER_DATA)) + LONG (ADDR(.TFM_APP_ROT_LINKER_DATA)) + LONG (SIZEOF(.TFM_APP_ROT_LINKER_DATA) / 4) + +#if defined (S_RAM_CODE_START) + LONG (LOADADDR(.ER_CODE_SRAM)) + LONG (ADDR(.ER_CODE_SRAM)) + LONG (SIZEOF(.ER_CODE_SRAM) / 4) +#endif + __copy_table_end__ = .; + + /* .zero.table */ + . = ALIGN(4); + __zero_table_start__ = .; + LONG (ADDR(.TFM_BSS)) + LONG (SIZEOF(.TFM_BSS) / 4) + LONG (ADDR(.TFM_PSA_ROT_LINKER_BSS)) + LONG (SIZEOF(.TFM_PSA_ROT_LINKER_BSS) / 4) + + LONG (ADDR(.TFM_APP_ROT_LINKER_BSS)) + LONG (SIZEOF(.TFM_APP_ROT_LINKER_BSS) / 4) +#if defined(CONFIG_TFM_PARTITION_META) + LONG (ADDR(.TFM_SP_META_PTR)) + LONG (SIZEOF(.TFM_SP_META_PTR) / 4) +#endif + __zero_table_end__ = .; + + *startup*(.text*) + /* Remove flash driver related files */ + EXCLUDE_FILE (*libplatform_s*:*Flash_RPI*) *libplatform_s*:(SORT_BY_ALIGNMENT(.text*)) + *libtfm_spm*:(SORT_BY_ALIGNMENT(.text*)) + + EXCLUDE_FILE (*libplatform_s*:*Flash_RPI*) *libplatform_s*:*(.rodata*) + *libtfm_spm*:*(.rodata*) + } > FLASH + + .TFM_UNPRIV_CODE ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT) : + { + /* Remove flash driver related files */ + EXCLUDE_FILE (*libplatform_s*:*Flash_RPI*) *(SORT_BY_ALIGNMENT(.text*)) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(SORT_BY_ALIGNMENT(.rodata*)) + . = ALIGN(4); + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*))) + + KEEP(*(.eh_frame*)) + . = ALIGN(TFM_LINKER_UNPRIV_CODE_ALIGNMENT); + } > FLASH + Image$$TFM_UNPRIV_CODE_START$$RO$$Base = ADDR(.TFM_UNPRIV_CODE); + Image$$TFM_UNPRIV_CODE_END$$RO$$Limit = ADDR(.TFM_UNPRIV_CODE) + SIZEOF(.TFM_UNPRIV_CODE); + +#if defined(CONFIG_TFM_USE_TRUSTZONE) && defined(TFM_LINKER_VENEERS_LOCATION_END) + VENEERS() +#endif + + /* Position tag */ + . = ALIGN(TFM_LINKER_PT_RO_ALIGNMENT); + Image$$PT_RO_END$$Base = .; + + /**** Base address of secure data area */ + .tfm_secure_data_start : + { + /* Relocate current position to RAM */ + . = ALIGN(4); + } > RAM + + /* + * MPU on Armv6-M/v7-M core in multi-core topology may require more strict + * alignment that MPU region base address must align with the MPU region + * size. + * As a result, on Armv6-M/v7-M cores, to save memory resource and MPU + * regions, unprivileged data sections and privileged data sections are + * separated and gathered in unprivileged/privileged data area respectively. + * Keep BL2 shared data and MSP stack at the beginning of the secure data + * area on Armv8-M cores, while move the two areas to the beginning of + * privileged data region on Armv6-M/v7-M cores. + */ +#if defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \ + defined(__ARM_ARCH_8_1M_MAIN__) +#ifdef CODE_SHARING + /* The code sharing between bootloader and runtime requires to share the + * global variables. + */ + .TFM_SHARED_SYMBOLS ALIGN(TFM_LINKER_SHARED_SYMBOLS_ALIGNMENT) : + { + . += SHARED_SYMBOL_AREA_SIZE; + } > RAM +#endif + + /* shared_data and msp_stack are overlapping on purpose when + * msp_stack is extended until the beginning of RAM, when shared_date + * was read out by partitions + */ + .tfm_bl2_shared_data ALIGN(TFM_LINKER_BL2_SHARED_DATA_ALIGNMENT) : + { + . += BOOT_TFM_SHARED_DATA_SIZE; + } > RAM + + .msp_stack ALIGN(TFM_LINKER_MSP_STACK_ALIGNMENT) : + { + . += __msp_stack_size__ - 0x8; + } > RAM + Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack); + Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack); + + .msp_stack_seal_res : + { + . += 0x8; + } > RAM + __StackSeal = ADDR(.msp_stack_seal_res); + +#endif /* defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__) || \ + * defined(__ARM_ARCH_8_1M_MAIN__) */ + + .ram_vector_table (NOLOAD): ALIGN(256) { + *(.ram_vector_table) + } > RAM + +#if defined(ENABLE_HEAP) + __heap_size__ = S_HEAP_SIZE; + .heap (NOLOAD): ALIGN(8) + { + . = ALIGN(8); + __end__ = .; + end = __end__; + PROVIDE(end = .); + __HeapBase = .; + KEEP(*(.heap*)) + . += __heap_size__; + __HeapLimit = .; + __heap_limit = .; + } > RAM +#else + end = 0; +#endif + +#if defined(CONFIG_TFM_PARTITION_META) + .TFM_SP_META_PTR ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT) (NOLOAD): + { + *(.bss.SP_META_PTR_SPRTL_INST) + . = ALIGN(TFM_LINKER_SP_META_PTR_ALIGNMENT); + } > RAM + Image$$TFM_SP_META_PTR$$ZI$$Base = ADDR(.TFM_SP_META_PTR); + Image$$TFM_SP_META_PTR$$ZI$$Limit = ADDR(.TFM_SP_META_PTR) + SIZEOF(.TFM_SP_META_PTR); + /* This is needed for the uniform configuration of MPU region. */ + Image$$TFM_SP_META_PTR_END$$ZI$$Limit = Image$$TFM_SP_META_PTR$$ZI$$Limit; +#endif + + /**** APPLICATION RoT DATA start here */ + . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT); + Image$$TFM_APP_RW_STACK_START$$Base = .; + + .TFM_APP_ROT_LINKER_DATA ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT) : + { + *tfm_app_rot_partition*:(SORT_BY_ALIGNMENT(.data*)) + *(TFM_*_APP-ROT_ATTR_RW) + . = ALIGN(4); + } > RAM AT> FLASH + Image$$TFM_APP_ROT_LINKER_DATA$$RW$$Base = ADDR(.TFM_APP_ROT_LINKER_DATA); + Image$$TFM_APP_ROT_LINKER_DATA$$RW$$Limit = ADDR(.TFM_APP_ROT_LINKER_DATA) + SIZEOF(.TFM_APP_ROT_LINKER_DATA); + + .TFM_APP_ROT_LINKER_BSS ALIGN(4) (NOLOAD) : + { + start_of_TFM_APP_ROT_LINKER = .; + *tfm_app_rot_partition*:(SORT_BY_ALIGNMENT(.bss*)) + *tfm_app_rot_partition*:*(COMMON) + *(TFM_*_APP-ROT_ATTR_ZI) + . += (. - start_of_TFM_APP_ROT_LINKER) ? 0 : 4; + . = ALIGN(TFM_LINKER_APP_ROT_LINKER_DATA_ALIGNMENT); + } > RAM AT> RAM + Image$$TFM_APP_ROT_LINKER_DATA$$ZI$$Base = ADDR(.TFM_APP_ROT_LINKER_BSS); + Image$$TFM_APP_ROT_LINKER_DATA$$ZI$$Limit = ADDR(.TFM_APP_ROT_LINKER_BSS) + SIZEOF(.TFM_APP_ROT_LINKER_BSS); + + /**** APPLICATION RoT DATA end here */ + Image$$TFM_APP_RW_STACK_END$$Base = .; + + /**** PSA RoT DATA start here */ + + Image$$TFM_PSA_RW_STACK_START$$Base = .; + + .TFM_PSA_ROT_LINKER_DATA ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT) : + { + *tfm_psa_rot_partition*:(SORT_BY_ALIGNMENT(.data*)) + *(TFM_*_PSA-ROT_ATTR_RW) + . = ALIGN(4); + } > RAM AT> FLASH + Image$$TFM_PSA_ROT_LINKER_DATA$$RW$$Base = ADDR(.TFM_PSA_ROT_LINKER_DATA); + Image$$TFM_PSA_ROT_LINKER_DATA$$RW$$Limit = ADDR(.TFM_PSA_ROT_LINKER_DATA) + SIZEOF(.TFM_PSA_ROT_LINKER_DATA); + + .TFM_PSA_ROT_LINKER_BSS ALIGN(4) (NOLOAD) : + { + start_of_TFM_PSA_ROT_LINKER = .; + *tfm_psa_rot_partition*:(SORT_BY_ALIGNMENT(.bss*)) + *tfm_psa_rot_partition*:*(COMMON) + *(TFM_*_PSA-ROT_ATTR_ZI) + . += (. - start_of_TFM_PSA_ROT_LINKER) ? 0 : 4; + . = ALIGN(TFM_LINKER_PSA_ROT_LINKER_DATA_ALIGNMENT); + } > RAM AT> RAM + Image$$TFM_PSA_ROT_LINKER_DATA$$ZI$$Base = ADDR(.TFM_PSA_ROT_LINKER_BSS); + Image$$TFM_PSA_ROT_LINKER_DATA$$ZI$$Limit = ADDR(.TFM_PSA_ROT_LINKER_BSS) + SIZEOF(.TFM_PSA_ROT_LINKER_BSS); + + /**** PSA RoT DATA end here */ + Image$$TFM_PSA_RW_STACK_END$$Base = .; + +#ifdef RAM_VECTORS_SUPPORT + .ramVectors ALIGN(TFM_LINKER_RAM_VECTORS_ALIGNMENT) (NOLOAD) : + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > RAM + .TFM_DATA __ram_vectors_end__ : +#else + + .TFM_DATA ALIGN(4) : +#endif + { + *(vtable) + *(.time_critical*) + *(*libplatform_s*:*Flash_RPI* .text*) + *(*libplatform_s*:*Flash_RPI* .rodata*) + *(SORT_BY_ALIGNMENT(.data*)) + *(.sdata*) + . = ALIGN(4); + *(.after_data.*) + + KEEP(*(.jcr*)) + . = ALIGN(4); + + } > RAM AT> FLASH + Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA); + + .uninitialized_data (NOLOAD): { + . = ALIGN(4); + *(.uninitialized_data*) + } > RAM AT> RAM + + .TFM_BSS ALIGN(4) (NOLOAD) : + { + __bss_start__ = .; + + /* The runtime partition placed order is same as load partition */ + __partition_runtime_start__ = .; + KEEP(*(.bss.part_runtime_priority_00)) + KEEP(*(.bss.part_runtime_priority_01)) + KEEP(*(.bss.part_runtime_priority_02)) + KEEP(*(.bss.part_runtime_priority_03)) + __partition_runtime_end__ = .; + . = ALIGN(4); + + /* The runtime service placed order is same as load partition */ + __service_runtime_start__ = .; + KEEP(*(.bss.serv_runtime_priority_00)) + KEEP(*(.bss.serv_runtime_priority_01)) + KEEP(*(.bss.serv_runtime_priority_02)) + KEEP(*(.bss.serv_runtime_priority_03)) + __service_runtime_end__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + *(.sbss*) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT> RAM + Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS); + Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS); + Image$$ER_PART_RT_POOL$$ZI$$Base = __partition_runtime_start__; + Image$$ER_PART_RT_POOL$$ZI$$Limit = __partition_runtime_end__; + Image$$ER_SERV_RT_POOL$$ZI$$Base = __service_runtime_start__; + Image$$ER_SERV_RT_POOL$$ZI$$Limit = __service_runtime_end__; + + Image$$ER_TFM_DATA$$Base = ADDR(.TFM_DATA); + Image$$ER_TFM_DATA$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA) + SIZEOF(.TFM_BSS); + +#if defined(CONFIG_TFM_USE_TRUSTZONE) + Image$$ER_VENEER$$Base = ADDR(.gnu.sgstubs); + Image$$VENEER_ALIGN$$Limit = ADDR(.sgstubs_end); + +#if defined(TFM_LINKER_VENEERS_SIZE) + ASSERT ((Image$$VENEER_ALIGN$$Limit - Image$$ER_VENEER$$Base) <= TFM_LINKER_VENEERS_SIZE, "Veneer region overflowed") +#endif +#endif + + Load$$LR$$LR_NS_PARTITION$$Base = NS_PARTITION_START; + +#ifdef BL2 + Load$$LR$$LR_SECONDARY_PARTITION$$Base = SECONDARY_PARTITION_START; +#endif /* BL2 */ + + PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit); + +#ifdef __ENABLE_SCRATCH__ + /* Start and end symbols must be word-aligned */ + .scratch_x : { + __scratch_x_start__ = .; + *(.scratch_x.*) + . = ALIGN(4); + __scratch_x_end__ = .; + } > SCRATCH_X AT > FLASH + __scratch_x_source__ = LOADADDR(.scratch_x); + .scratch_y : { + __scratch_y_start__ = .; + *(.scratch_y.*) + . = ALIGN(4); + __scratch_y_end__ = .; + } > SCRATCH_Y AT > FLASH + __scratch_y_source__ = LOADADDR(.scratch_y); + + .stack1_dummy (NOLOAD): + { + *(.stack1*) + } > SCRATCH_X + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > SCRATCH_Y + + PROVIDE(__StackBottom = Image$$ARM_LIB_STACK$$ZI$$Base); + PROVIDE(__StackTop = Image$$ARM_LIB_STACK$$ZI$$Limit); + __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X); + __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy); +#endif + + ASSERT( __binary_info_header_end - __logical_binary_start <= 1024, "Binary info must be in first 1024 bytes of the binary") +} diff --git a/platform/ext/target/rpi/rp2350/manifest/tfm_manifest_list.yaml b/platform/ext/target/rpi/rp2350/manifest/tfm_manifest_list.yaml new file mode 100644 index 000000000..0800e595b --- /dev/null +++ b/platform/ext/target/rpi/rp2350/manifest/tfm_manifest_list.yaml @@ -0,0 +1,125 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +# The "manifest" field must be a path relative to this file, a path relative to +# the directory that tfm_parse_manifest_list.py is run in (which by default is +# the TF-M root directory), or an absolute path. +# +# Files per Secure Partition are generated to: +# - "output_path", if it is a absolute path - not recommended +# - generated_file_root/"output_path", if "output_path" is relative path +# - generated_file_root/, if "output_path" is not specified +# * generated_file_root is the path passed to tfm_parse_manifest_list.py +# by -o/--outdir + +{ + "description": "TF-M secure partition manifests", + "type": "manifest_list", + "version_major": 0, + "version_minor": 1, + "manifest_list": [ + { + "description": "Non-Secure Mailbox Agent", + "manifest": "secure_fw/partitions/ns_agent_mailbox/ns_agent_mailbox.yaml", + "output_path": "secure_fw/partitions/ns_agent_mailbox", + "conditional": "TFM_PARTITION_NS_AGENT_MAILBOX", + "version_major": 0, + "version_minor": 1, + "pid": 262, + "linker_pattern": { + "library_list": [ + "*tfm_*ns_agent_mailbox.*" + ], + }, + "non_ffm_attributes": ['ns_agent'] + }, + { + "description": "Protected Storage Partition", + "manifest": "secure_fw/partitions/protected_storage/tfm_protected_storage.yaml", + "output_path": "secure_fw/partitions/protected_storage", + "conditional": "TFM_PARTITION_PROTECTED_STORAGE", + "version_major": 0, + "version_minor": 1, + "pid": 256, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_ps.*" + ], + } + }, + { + "description": "TF-M Internal Trusted Storage Partition", + "manifest": "secure_fw/partitions/internal_trusted_storage/tfm_internal_trusted_storage.yaml", + "output_path": "secure_fw/partitions/internal_trusted_storage", + "conditional": "TFM_PARTITION_INTERNAL_TRUSTED_STORAGE", + "version_major": 0, + "version_minor": 1, + "pid": 257, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_its.*" + ] + } + }, + { + "description": "TFM Crypto Partition", + "manifest": "secure_fw/partitions/crypto/tfm_crypto.yaml", + "output_path": "secure_fw/partitions/crypto", + "conditional": "TFM_PARTITION_CRYPTO", + "version_major": 0, + "version_minor": 1, + "pid": 259, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_crypto.*", + "*mbedcrypto.*", + ] + } + }, + { + "description": "TFM Platform Partition", + "manifest": "platform/ext/target/rpi/rp2350/manifest/tfm_platform.yaml", + "output_path": "secure_fw/partitions/platform", + "conditional": "TFM_PARTITION_PLATFORM", + "version_major": 0, + "version_minor": 1, + "pid": 260, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_platform.*" + ] + } + }, + { + "description": "TFM Initial Attestation Partition", + "manifest": "secure_fw/partitions/initial_attestation/tfm_initial_attestation.yaml", + "output_path": "secure_fw/partitions/initial_attestation", + "conditional": "TFM_PARTITION_INITIAL_ATTESTATION", + "version_major": 0, + "version_minor": 1, + "pid": 261, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_attestation.*" + ] + } + }, + { + "description": "TFM Firmware Update Partition", + "manifest": "secure_fw/partitions/firmware_update/tfm_firmware_update.yaml", + "output_path": "secure_fw/partitions/firmware_update", + "conditional": "TFM_PARTITION_FIRMWARE_UPDATE", + "version_major": 0, + "version_minor": 1, + "pid": 271, + "linker_pattern": { + "library_list": [ + "*tfm_*partition_fwu*" + ] + } + }, + ] +} diff --git a/platform/ext/target/rpi/rp2350/manifest/tfm_platform.yaml b/platform/ext/target/rpi/rp2350/manifest/tfm_platform.yaml new file mode 100644 index 000000000..6558830e5 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/manifest/tfm_platform.yaml @@ -0,0 +1,29 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +{ + "psa_framework_version": 1.1, + "name": "TFM_SP_PLATFORM", + "type": "PSA-ROT", + "priority": "NORMAL", + "model": "SFN", + "entry_init": "platform_sp_init", + "stack_size": "PLATFORM_SP_STACK_SIZE", + "services": [ + { + "name": "TFM_PLATFORM_SERVICE", + "sid": "0x00000040", + "non_secure_clients": true, + "connection_based": false, + "stateless_handle": 6, + "version": 1, + "version_policy": "STRICT" + }, + ], + "dependencies": [ + "TFM_INTERNAL_TRUSTED_STORAGE_SERVICE" + ] +} diff --git a/platform/ext/target/rpi/rp2350/mbedtls_extra_config.h b/platform/ext/target/rpi/rp2350/mbedtls_extra_config.h new file mode 100644 index 000000000..0d295419f --- /dev/null +++ b/platform/ext/target/rpi/rp2350/mbedtls_extra_config.h @@ -0,0 +1,11 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#undef MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 1 + +#define PSA_WANT_ALG_GCM 1 + diff --git a/platform/ext/target/rpi/rp2350/ns/CMakeLists.txt b/platform/ext/target/rpi/rp2350/ns/CMakeLists.txt new file mode 100644 index 000000000..28d0db08b --- /dev/null +++ b/platform/ext/target/rpi/rp2350/ns/CMakeLists.txt @@ -0,0 +1,185 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +# initialize pico-sdk from GIT +set(PICO_SDK_FETCH_FROM_GIT on) +set(PICO_PLATFORM rp2350-arm-s) +set(SKIP_BOOT_STAGE2 1) + +# initialize the Raspberry Pi Pico SDK +include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) +pico_sdk_init() + +get_target_property(pico_link_options pico_standard_link INTERFACE_LINK_OPTIONS) +list(FILTER pico_link_options EXCLUDE REGEX "LINKER.*--script") +list(APPEND pico_link_options "--entry=_entry_point") +set_target_properties(pico_standard_link PROPERTIES INTERFACE_LINK_OPTIONS "${pico_link_options}") +set_target_properties(pico_runtime PROPERTIES INTERFACE_LINK_OPTIONS "") + + +cmake_policy(SET CMP0076 NEW) + +set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR}) +set(STATIC_ASSERT_OVERRIDE_HEADER "${PLATFORM_DIR}/static_assert_override.h") + +add_library(static_assert_override INTERFACE) +add_library(device_definition INTERFACE) +add_library(platform_ns STATIC) + +# GNU Arm compiler version greater equal than *11.3.Rel1* +# throw warning when linker segments used as rwx +# Adding --no-warn-rwx-segments like the RPi SDK did. +if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3.1) + target_link_options(tfm_ns PRIVATE "LINKER:--no-warn-rwx-segments") +endif() + +target_link_options(tfm_ns PRIVATE "LINKER:--entry=_entry_point") + +add_library(platform_ns_init INTERFACE) +target_sources(platform_ns_init + INTERFACE + extra_init_ns.c +) + +target_link_libraries(platform_ns_init + INTERFACE + cmsis_core_headers + pico_runtime_init + pico_runtime_headers + static_assert_override + pico_bootrom_headers + hardware_clocks +) + +target_compile_definitions(platform_ns_init + INTERFACE + $<$:TFM_MULTI_CORE_TOPOLOGY> +) + +# Note: This should be Private and in tfm_ns_scatter +target_compile_definitions(platform_region_defs + INTERFACE + # u modifier in scatter file is not valid + NO_U_MODIFIER=1 +) +#========================= Platform region defs ===============================# + +target_include_directories(platform_region_defs + INTERFACE + partition + ${CMAKE_CURRENT_SOURCE_DIR} + ${PLATFORM_DIR}/include + ${PLATFORM_DIR}/device/config +) + +target_link_libraries(platform_region_defs + INTERFACE + hardware_regs_headers + static_assert_override +) + +target_compile_options(static_assert_override + INTERFACE + "$<$:SHELL:-include ${STATIC_ASSERT_OVERRIDE_HEADER}>" + "$<$:SHELL:-include ${STATIC_ASSERT_OVERRIDE_HEADER}>" + "$<$:SHELL:--preinclude ${STATIC_ASSERT_OVERRIDE_HEADER}>" +) + +#========================= Device definition lib ===============================# + +target_include_directories(device_definition + INTERFACE + . + device/include + native_drivers + partition + libraries + native_drivers + ${PLATFORM_DIR}/ext/target/arm/drivers/flash/common + ${PLATFORM_DIR}/ext/target/arm/drivers/usart/cmsdk + ${PLATFORM_DIR}/ext/target/arm/drivers/usart/common + ${PLATFORM_DIR}/ext/target/arm/drivers/mpc_sie + ${PLATFORM_DIR}/ext/target/arm/drivers/mpu/armv8m + ${PLATFORM_DIR}/ext/target/arm/drivers/counter/armv8m + ${PLATFORM_DIR}/ext/target/arm/drivers/timer/armv8m + ${ETHOS_DRIVER_PATH}/src + ${ETHOS_DRIVER_PATH}/include + ${CMAKE_CURRENT_SOURCE_DIR}/device/config +) + +#========================= Platform Non-Secure ================================# + +target_sources(platform_ns + PRIVATE + $<$:platform_ns_mailbox.c> + cmsis_drivers/Driver_USART_RPI.c + ${PLATFORM_DIR}/ext/target/arm/drivers/usart/cmsdk/uart_cmsdk_drv.c +) + +target_include_directories(platform_ns + PUBLIC + cmsis_drivers + ${PLATFORM_DIR}/ext/cmsis/Include + ${PLATFORM_DIR}/ext/cmsis/Include/m-profile + ${PLATFORM_DIR}/include + ${PLATFORM_DIR}/ext/common + ${PLATFORM_DIR}/ext/driver +) + +target_link_libraries(platform_ns + PUBLIC + cmsis_core_headers + platform_ns_init + PRIVATE + device_definition + pico_crt0 + $<$:pico_multicore> + hardware_regs + hardware_flash + hardware_uart + cmsis_core +) + +target_compile_definitions(platform_ns + PUBLIC + PICO_UART_DEFAULT_CRLF=1 + CMSIS_device_header= + PICO_DEFAULT_TIMER=1 + $<$:TFM_MULTI_CORE_TOPOLOGY> +) + +if (TFM_NS_CUSTOM_API) + target_sources(tfm_api_ns PRIVATE + ${INTERFACE_SRC_DIR}/os_wrapper/tfm_ns_interface_rtos.c + ) + + add_library(tfm_api_ns_custom INTERFACE) + + target_sources(tfm_api_ns_custom + INTERFACE + tfm_custom_psa_ns_api.c + ) + + target_link_libraries(tfm_api_ns_custom + INTERFACE + ${INTERFACE_SRC_DIR}/../lib/s_veneers.o + ) + + target_link_libraries(tfm_api_ns + PRIVATE + tfm_api_ns_custom + os_wrapper + ) + + # lib parth + set(APP_LIB_DIR ${CMAKE_CURRENT_LIST_DIR}/../../../../../lib) + + target_sources(RTX_OS + INTERFACE + # Provide TZ context management stub to RTOS if protected by Trustzone + ${APP_LIB_DIR}/nsid_manager/tz_shim_layer.c + ) +endif() diff --git a/platform/ext/target/rpi/rp2350/ns/extra_init_ns.c b/platform/ext/target/rpi/rp2350/ns/extra_init_ns.c new file mode 100644 index 000000000..0941eced8 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/ns/extra_init_ns.c @@ -0,0 +1,84 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "hardware/clocks.h" + +#ifdef TFM_MULTI_CORE_TOPOLOGY +#include "hardware/structs/sio.h" +#include "hardware/structs/scb.h" +#include "tfm_multi_core_api.h" +#endif + +#include "stdint.h" + +/* Do not use __cmsis_start */ +#define __PROGRAM_START +#include "tfm_hal_device_header.h" + +void copy_zero_tables(void) { + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } +} + +void __weak hard_assertion_failure(void) { + panic("Hard assert"); +} + +extern void runtime_init_install_ram_vector_table(void); +extern uint32_t ram_vector_table[PICO_RAM_VECTOR_TABLE_SIZE]; + +void runtime_init(void) { +#ifdef TFM_MULTI_CORE_TOPOLOGY + if(sio_hw->cpuid == 0) { + scb_hw->vtor = (uintptr_t) ram_vector_table; + return; + } +#endif + copy_zero_tables(); + runtime_init_install_ram_vector_table(); + + /* These are already configured by the Secure side, just fill the array */ + clock_set_reported_hz(clk_ref, XOSC_KHZ * KHZ); + clock_set_reported_hz(clk_sys, SYS_CLK_KHZ * KHZ); + clock_set_reported_hz(clk_peri, SYS_CLK_KHZ * KHZ); + clock_set_reported_hz(clk_hstx, SYS_CLK_KHZ * KHZ); + clock_set_reported_hz(clk_usb, USB_CLK_KHZ * KHZ); + clock_set_reported_hz(clk_adc, USB_CLK_KHZ * KHZ); + + SystemInit(); +} + +#ifdef TFM_MULTI_CORE_TOPOLOGY +int32_t tfm_ns_wait_for_s_cpu_ready(void) +{ + return tfm_platform_ns_wait_for_s_cpu_ready(); +} +#endif diff --git a/platform/ext/target/rpi/rp2350/ns/platform_ns_mailbox.c b/platform/ext/target/rpi/rp2350/ns/platform_ns_mailbox.c new file mode 100644 index 000000000..469eacf4d --- /dev/null +++ b/platform/ext/target/rpi/rp2350/ns/platform_ns_mailbox.c @@ -0,0 +1,154 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +/* FIXME: This shouldn't be required when TFM_PLAT_SPECIFIC_MULTI_CORE_COMM is + * enabled. + */ + +#include "tfm_ns_mailbox.h" +#include "platform_multicore.h" +#include "region.h" + +#include "pico/multicore.h" +#include "hardware/irq.h" +#include "hardware/structs/scb.h" +#include "hardware/structs/sio.h" + +#include "tfm_hal_device_header.h" +#include "uart_stdout.h" +#include "Driver_Common.h" + +int32_t tfm_ns_platform_init(void) +{ + if(sio_hw->cpuid == 0) { + __enable_irq(); + } else { + /* Core1 */ + __enable_irq(); + stdio_init(); + } + + return ARM_DRIVER_OK; +} + +/* Platform specific inter-processor communication interrupt handler. */ +void SIO_IRQ_FIFO_NS_IRQHandler(void) +{ + uint32_t msg; + if(multicore_fifo_rvalid()) + { + msg = multicore_fifo_pop_blocking(); + if (msg == NOTIFY_FROM_CORE0) { + /* Handle all the pending replies */ + tfm_ns_mailbox_wake_reply_owner_isr(); + } + } +} + +int32_t tfm_ns_mailbox_hal_init(struct ns_mailbox_queue_t *queue) +{ + uint32_t stage; + + if(sio_hw->cpuid == 0) { + return MAILBOX_SUCCESS; + } + + if (!queue) { + return MAILBOX_INVAL_PARAMS; + } + + NVIC_SetVector(SIO_IRQ_FIFO_NS_IRQn, (uint32_t) SIO_IRQ_FIFO_NS_IRQHandler); + + /* + * Wait until SPE mailbox library is ready to receive NSPE mailbox queue + * address. + */ + while (1) { + stage = multicore_fifo_pop_blocking(); + if (stage == NS_MAILBOX_INIT) { + break; + } + } + + /* Send out the address */ + struct mailbox_init_t ns_init; + ns_init.status = &queue->status; + ns_init.slot_count = NUM_MAILBOX_QUEUE_SLOT; + ns_init.slots = &queue->slots[0]; + multicore_fifo_push_blocking((uint32_t) &ns_init); + + /* Wait until SPE mailbox service is ready */ + while (1) { + stage = multicore_fifo_pop_blocking(); + if (stage == S_MAILBOX_READY) { + break; + } + } + + NVIC_EnableIRQ(SIO_IRQ_FIFO_NS_IRQn); + + return MAILBOX_SUCCESS; +} + +int32_t tfm_ns_mailbox_hal_notify_peer(void) +{ + multicore_fifo_push_blocking(NOTIFY_FROM_CORE1); + return 0; +} + +void tfm_ns_mailbox_hal_enter_critical(void) +{ + /* Reading a spinlock register attempts to claim it, returning nonzero + * if the claim was successful and 0 if unsuccessful */ + while(!*MAILBOX_SPINLOCK); + return; +} + +void tfm_ns_mailbox_hal_exit_critical(void) +{ + /* Writing to a spinlock register releases it */ + *MAILBOX_SPINLOCK = 0x1u; + return; +} + +void tfm_ns_mailbox_hal_enter_critical_isr(void) +{ + /* Reading a spinlock register attempts to claim it, returning nonzero + * if the claim was successful and 0 if unsuccessful */ + while(!*MAILBOX_SPINLOCK); + return; +} + +void tfm_ns_mailbox_hal_exit_critical_isr(void) +{ + /* Writing to a spinlock register releases it */ + *MAILBOX_SPINLOCK = 0x1u; + return; +} + +extern void runtime_init(void); +extern int main(void); +extern uint32_t __StackOneTop; +extern uint32_t __Vectors_Start__; + +void __attribute__((section(".core1_ns_entry"), used, naked)) core1_ns_entry(void) +{ + scb_hw->vtor = (uintptr_t) &__Vectors_Start__; + __set_MSP((uint32_t)(&__StackOneTop)); + __set_PSP((uint32_t)(&__StackOneTop)); + runtime_init(); + main(); +} + +#include "stdio.h" +int32_t tfm_platform_ns_wait_for_s_cpu_ready(void) +{ + if(sio_hw->cpuid == 1) { + /* Core1 */ + multicore_fifo_push_blocking(CORE1_NS_READY); + } + return 0; +} diff --git a/platform/ext/target/rpi/rp2350/ns/tfm_custom_psa_ns_api.c b/platform/ext/target/rpi/rp2350/ns/tfm_custom_psa_ns_api.c new file mode 100644 index 000000000..3d45f5a9a --- /dev/null +++ b/platform/ext/target/rpi/rp2350/ns/tfm_custom_psa_ns_api.c @@ -0,0 +1,234 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + + +#include +#include + +#include "psa/client.h" +#include "tfm_ns_interface.h" +#include "tfm_psa_call_pack.h" +#include "tfm_mailbox.h" +#include "tfm_ns_mailbox.h" + +#include "hardware/structs/sio.h" + +/* + * TODO + * Currently, force all the non-secure client to share the same ID. + * + * It requires a more clear mechanism to synchronize the non-secure client + * ID with SPE in dual core scenario. + * In current design, the value is transferred to SPE via mailbox message. + * A dedicated routine to receive the non-secure client information in + * TF-M core/SPM in dual core scenario should be added besides current + * implementation for single Armv8-M. + * The non-secure client identification is shared with SPE in + * single Armv8-M scenario via CMSIS TrustZone context management API, + * which may not work in dual core scenario. + */ +#define NON_SECURE_CLIENT_ID (-1) + +/* + * TODO + * Require a formal definition of errors related to mailbox in PSA client call. + */ +#define PSA_INTER_CORE_COMM_ERR (INT32_MIN + 0xFF) + +/**** TZ API functions ****/ + +uint32_t tz_psa_framework_version(void) +{ + return tfm_ns_interface_dispatch( + (veneer_fn)tfm_psa_framework_version_veneer, + 0, + 0, + 0, + 0); +} + +uint32_t tz_psa_version(uint32_t sid) +{ + return tfm_ns_interface_dispatch( + (veneer_fn)tfm_psa_version_veneer, + sid, + 0, + 0, + 0); +} + +psa_status_t tz_psa_call(psa_handle_t handle, int32_t type, + const psa_invec *in_vec, + size_t in_len, + psa_outvec *out_vec, + size_t out_len) +{ + if ((type > PSA_CALL_TYPE_MAX) || + (type < PSA_CALL_TYPE_MIN) || + (in_len > PSA_MAX_IOVEC) || + (out_len > PSA_MAX_IOVEC)) { + return PSA_ERROR_PROGRAMMER_ERROR; + } + + return tfm_ns_interface_dispatch( + (veneer_fn)tfm_psa_call_veneer, + (uint32_t)handle, + PARAM_PACK(type, in_len, out_len), + (uint32_t)in_vec, + (uint32_t)out_vec); +} + +psa_handle_t tz_psa_connect(uint32_t sid, uint32_t version) +{ + return tfm_ns_interface_dispatch((veneer_fn)tfm_psa_connect_veneer, sid, version, 0, 0); +} + +void tz_psa_close(psa_handle_t handle) +{ + (void)tfm_ns_interface_dispatch((veneer_fn)tfm_psa_close_veneer, (uint32_t)handle, 0, 0, 0); +} + +/**** Mailbox API functions ****/ + +uint32_t mb_psa_framework_version(void) +{ + struct psa_client_params_t params; + uint32_t version; + int32_t ret; + + ret = tfm_ns_mailbox_client_call(MAILBOX_PSA_FRAMEWORK_VERSION, + ¶ms, NON_SECURE_CLIENT_ID, + (int32_t *)&version); + if (ret != MAILBOX_SUCCESS) { + version = PSA_VERSION_NONE; + } + + return version; +} + +uint32_t mb_psa_version(uint32_t sid) +{ + struct psa_client_params_t params; + uint32_t version; + int32_t ret; + + params.psa_version_params.sid = sid; + + ret = tfm_ns_mailbox_client_call(MAILBOX_PSA_VERSION, ¶ms, + NON_SECURE_CLIENT_ID, + (int32_t *)&version); + if (ret != MAILBOX_SUCCESS) { + version = PSA_VERSION_NONE; + } + + return version; +} + +psa_handle_t mb_psa_connect(uint32_t sid, uint32_t version) +{ + struct psa_client_params_t params; + psa_handle_t psa_handle; + int32_t ret; + + params.psa_connect_params.sid = sid; + params.psa_connect_params.version = version; + + ret = tfm_ns_mailbox_client_call(MAILBOX_PSA_CONNECT, ¶ms, + NON_SECURE_CLIENT_ID, + (int32_t *)&psa_handle); + if (ret != MAILBOX_SUCCESS) { + psa_handle = PSA_NULL_HANDLE; + } + + return psa_handle; +} + +psa_status_t mb_psa_call(psa_handle_t handle, int32_t type, + const psa_invec *in_vec, size_t in_len, + psa_outvec *out_vec, size_t out_len) +{ + struct psa_client_params_t params; + int32_t ret; + psa_status_t status; + + params.psa_call_params.handle = handle; + params.psa_call_params.type = type; + params.psa_call_params.in_vec = in_vec; + params.psa_call_params.in_len = in_len; + params.psa_call_params.out_vec = out_vec; + params.psa_call_params.out_len = out_len; + + ret = tfm_ns_mailbox_client_call(MAILBOX_PSA_CALL, ¶ms, + NON_SECURE_CLIENT_ID, + (int32_t *)&status); + if (ret != MAILBOX_SUCCESS) { + status = PSA_INTER_CORE_COMM_ERR; + } + + return status; +} + +void mb_psa_close(psa_handle_t handle) +{ + struct psa_client_params_t params; + int32_t reply; + + params.psa_close_params.handle = handle; + + (void)tfm_ns_mailbox_client_call(MAILBOX_PSA_CLOSE, ¶ms, + NON_SECURE_CLIENT_ID, &reply); +} + +/**** API functions ****/ + +uint32_t psa_framework_version(void) +{ + if(sio_hw->cpuid == 0) { + return tz_psa_framework_version(); + } else { + return mb_psa_framework_version(); + } +} + +uint32_t psa_version(uint32_t sid) +{ + if(sio_hw->cpuid == 0) { + return tz_psa_version(sid); + } else { + return mb_psa_version(sid); + } +} + +psa_status_t psa_call(psa_handle_t handle, int32_t type, + const psa_invec *in_vec, + size_t in_len, + psa_outvec *out_vec, + size_t out_len) +{ + if(sio_hw->cpuid == 0) { + return tz_psa_call(handle, type, in_vec, in_len, out_vec, out_len); + } else { + return mb_psa_call(handle, type, in_vec, in_len, out_vec, out_len); + } +} + +psa_handle_t psa_connect(uint32_t sid, uint32_t version) +{ + if(sio_hw->cpuid == 0) { + return tz_psa_connect(sid, version); + } else { + return mb_psa_connect(sid, version); + } +} + +void psa_close(psa_handle_t handle) +{ + if(sio_hw->cpuid == 0) { + return tz_psa_close(handle); + } else { + return mb_psa_close(handle); + } +} diff --git a/platform/ext/target/rpi/rp2350/nv_counters.c b/platform/ext/target/rpi/rp2350/nv_counters.c new file mode 100644 index 000000000..99943a498 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/nv_counters.c @@ -0,0 +1,243 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_plat_nv_counters.h" +#include "tfm_plat_otp.h" + +#if (PS_NS_NV_COUNTER_IN_ITS == 1) +#include "psa/internal_trusted_storage.h" +#endif + +#include +#include + +#define OTP_COUNTER_MAX_SIZE 64 +#define NV_COUNTER_SIZE 4 +#define OTP_COUNTER_MAGIC 0xAEC7 +#define ITS_NV_COUNTER_UID_BASE 0xFFFFFFFFFFFFA000 + +enum tfm_plat_err_t tfm_plat_init_nv_counter(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +static enum tfm_plat_err_t read_otp_counter(enum tfm_otp_element_id_t id, + uint8_t *val) +{ + size_t counter_size; + enum tfm_plat_err_t err; + size_t idx; + uint16_t counter_value[OTP_COUNTER_MAX_SIZE / sizeof(uint16_t)] = {0}; + uint32_t count; + + err = tfm_plat_otp_get_size(id, &counter_size); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + counter_size = counter_size > OTP_COUNTER_MAX_SIZE ? OTP_COUNTER_MAX_SIZE + : counter_size; + + err = tfm_plat_otp_read(id, counter_size, (uint8_t *)counter_value); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + count = 0; + for (idx = 0; idx < counter_size / sizeof(uint16_t); idx++) { + if (counter_value[idx] == OTP_COUNTER_MAGIC) { + count += 1; + } else if (counter_value[idx] == 0) { + break; + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + memcpy(val, &count, NV_COUNTER_SIZE); + + return TFM_PLAT_ERR_SUCCESS; +} + +#if (PS_NS_NV_COUNTER_IN_ITS == 1) +static enum tfm_plat_err_t read_its_nv_counter(enum tfm_otp_element_id_t id, + uint8_t *val) +{ + psa_storage_uid_t uid = (ITS_NV_COUNTER_UID_BASE + id); + psa_status_t status; + size_t data_length = 0; + + status = psa_its_get(uid, 0, NV_COUNTER_SIZE, val, &data_length); + + if (status == PSA_ERROR_DOES_NOT_EXIST) { + memset(val, 0, NV_COUNTER_SIZE); + } + + if (((status == PSA_SUCCESS) && (data_length == NV_COUNTER_SIZE)) || + (status == PSA_ERROR_DOES_NOT_EXIST)) { + return TFM_PLAT_ERR_SUCCESS; + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +} +#endif /* (PS_NS_NV_COUNTER_IN_ITS == 1) */ + +enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id, + uint32_t size, uint8_t *val) +{ + if (size != NV_COUNTER_SIZE) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + /* Assumes Platform nv counters are contiguous*/ + if (counter_id >= PLAT_NV_COUNTER_BL2_0 && + counter_id < (PLAT_NV_COUNTER_BL2_0 + MCUBOOT_IMAGE_NUMBER)) { + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_BL2_0 + + (counter_id - PLAT_NV_COUNTER_BL2_0), + val); + } + + switch (counter_id) { +#if (PS_NS_NV_COUNTER_IN_ITS == 0) + case (PLAT_NV_COUNTER_NS_0): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_0, val); + case (PLAT_NV_COUNTER_NS_1): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_1, val); + case (PLAT_NV_COUNTER_NS_2): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_2, val); + case (PLAT_NV_COUNTER_PS_0): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_0, val); + case (PLAT_NV_COUNTER_PS_1): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_1, val); + case (PLAT_NV_COUNTER_PS_2): + return read_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_2, val); +#else + case (PLAT_NV_COUNTER_NS_0): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_0, val); + case (PLAT_NV_COUNTER_NS_1): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_1, val); + case (PLAT_NV_COUNTER_NS_2): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_2, val); + case (PLAT_NV_COUNTER_PS_0): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_0, val); + case (PLAT_NV_COUNTER_PS_1): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_1, val); + case (PLAT_NV_COUNTER_PS_2): + return read_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_2, val); +#endif /* (PS_NS_NV_COUNTER_IN_ITS == 0) */ + + default: + return TFM_PLAT_ERR_UNSUPPORTED; + } +} + +static enum tfm_plat_err_t set_otp_counter(enum tfm_otp_element_id_t id, + uint32_t val) +{ + size_t counter_size; + enum tfm_plat_err_t err; + size_t idx; + uint16_t counter_value[OTP_COUNTER_MAX_SIZE / sizeof(uint16_t)] = {0}; + + err = tfm_plat_otp_get_size(id, &counter_size); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + counter_size = counter_size > OTP_COUNTER_MAX_SIZE ? OTP_COUNTER_MAX_SIZE + : counter_size; + + if (val > (counter_size / sizeof(uint16_t))) { + return TFM_PLAT_ERR_INVALID_INPUT; + } + + for (idx = 0; idx < val; idx++) { + counter_value[idx] = OTP_COUNTER_MAGIC; + } + + err = tfm_plat_otp_write(id, counter_size, + (uint8_t *)counter_value); + + return err; +} + +#if (PS_NS_NV_COUNTER_IN_ITS == 1) +static enum tfm_plat_err_t set_its_nv_counter(enum tfm_otp_element_id_t id, + uint32_t val) +{ + psa_storage_uid_t uid = (ITS_NV_COUNTER_UID_BASE + id); + psa_status_t status; + + status = psa_its_set(uid, NV_COUNTER_SIZE, &val, PSA_STORAGE_FLAG_NONE); + + if (status == PSA_SUCCESS) { + return TFM_PLAT_ERR_SUCCESS; + } else { + return TFM_PLAT_ERR_SYSTEM_ERR; + } +} +#endif /* (PS_NS_NV_COUNTER_IN_ITS == 1) */ + +enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id, + uint32_t value) +{ + /* Assumes Platform nv counters are contiguous*/ + if (counter_id >= PLAT_NV_COUNTER_BL2_0 && + counter_id < (PLAT_NV_COUNTER_BL2_0 + MCUBOOT_IMAGE_NUMBER)) { + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_BL2_0 + + (counter_id - PLAT_NV_COUNTER_BL2_0), + value); + } + + switch (counter_id) { +#if (PS_NS_NV_COUNTER_IN_ITS == 0) + case (PLAT_NV_COUNTER_NS_0): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_0, value); + case (PLAT_NV_COUNTER_NS_1): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_1, value); + case (PLAT_NV_COUNTER_NS_2): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_NS_2, value); + case (PLAT_NV_COUNTER_PS_0): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_0, value); + case (PLAT_NV_COUNTER_PS_1): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_1, value); + case (PLAT_NV_COUNTER_PS_2): + return set_otp_counter(PLAT_OTP_ID_NV_COUNTER_PS_2, value); +#else + case (PLAT_NV_COUNTER_NS_0): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_0, value); + case (PLAT_NV_COUNTER_NS_1): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_1, value); + case (PLAT_NV_COUNTER_NS_2): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_NS_2, value); + case (PLAT_NV_COUNTER_PS_0): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_0, value); + case (PLAT_NV_COUNTER_PS_1): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_1, value); + case (PLAT_NV_COUNTER_PS_2): + return set_its_nv_counter(PLAT_OTP_ID_NV_COUNTER_PS_2, value); +#endif /* (PS_NS_NV_COUNTER_IN_ITS == 0) */ + + default: + return TFM_PLAT_ERR_UNSUPPORTED; + } +} + +enum tfm_plat_err_t tfm_plat_increment_nv_counter( + enum tfm_nv_counter_t counter_id) +{ + uint32_t security_cnt; + enum tfm_plat_err_t err; + + err = tfm_plat_read_nv_counter(counter_id, + sizeof(security_cnt), + (uint8_t *)&security_cnt); + if (err != TFM_PLAT_ERR_SUCCESS) { + return err; + } + + return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u); +} diff --git a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/flash_layout.h b/platform/ext/target/rpi/rp2350/partition/flash_layout.h similarity index 55% rename from platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/flash_layout.h rename to platform/ext/target/rpi/rp2350/partition/flash_layout.h index ca15bdaba..48045a184 100644 --- a/platform/ext/target/nordic_nrf/nrf9161dk_nrf9161/partition/flash_layout.h +++ b/platform/ext/target/rpi/rp2350/partition/flash_layout.h @@ -1,81 +1,35 @@ /* - * Copyright (c) 2018-2022 Arm Limited. All rights reserved. - * Copyright (c) 2020 Nordic Semiconductor ASA. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. */ #ifndef __FLASH_LAYOUT_H__ #define __FLASH_LAYOUT_H__ -/* Flash layout on nRF91 with BL2: - * - * 0x0000_0000 BL2 - MCUBoot (64 KB) - * 0x0001_0000 Primary image area (448 KB): - * 0x0001_0000 Secure image primary (256 KB) - * 0x0005_0000 Non-secure image primary (192 KB) - * 0x0008_0000 Secondary image area (448 KB): - * 0x0008_0000 Secure image secondary (256 KB) - * 0x000c_0000 Non-secure image secondary (192 KB) - * 0x000f_0000 Protected Storage Area (16 KB) - * 0x000f_4000 Internal Trusted Storage Area (8 KB) - * 0x000f_6000 OTP / NV counters area (8 KB) - * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, - * otherwise unused (32 KB) - * - * Flash layout on nRF91 without BL2: - * - * 0x0000_0000 Primary image area (960 KB): - * 0x0000_0000 Secure image primary (480 KB) - * 0x0007_8000 Non-secure image primary (480 KB) - * 0x000f_0000 Protected Storage Area (16 KB) - * 0x000f_4000 Internal Trusted Storage Area (8 KB) - * 0x000f_6000 OTP / NV counters area (8 KB) - * 0x000f_8000 Non-secure storage, used when built with NRF_NS_STORAGE=ON, - * otherwise unused (32 KB) - */ +#include "hardware/regs/addressmap.h" /* Coming from SDK */ -/* This header file is included from linker scatter file as well, where only a - * limited C constructs are allowed. Therefore it is not possible to include - * here the platform_base_address.h to access flash related defines. To resolve - * this some of the values are redefined here with different names, these are - * marked with comment. - */ -/* Size of a Secure and of a Non-secure image */ -#ifdef PSA_API_TEST_IPC -/* Firmware Framework test suites */ -#define FLASH_S_PARTITION_SIZE (0x48000) /* S partition: 288 kB*/ -#define FLASH_NS_PARTITION_SIZE (0x28000) /* NS partition: 160 kB*/ -#else -#define FLASH_S_PARTITION_SIZE (0x40000) /* S partition: 256 kB*/ -#define FLASH_NS_PARTITION_SIZE (0x30000) /* NS partition: 192 kB*/ -#endif +#define FLASH_S_PARTITION_SIZE (0x60000) /* 384 kB */ +#define FLASH_NS_PARTITION_SIZE (0x60000) /* 384 kB */ -#if (FLASH_S_PARTITION_SIZE > FLASH_NS_PARTITION_SIZE) #define FLASH_MAX_PARTITION_SIZE FLASH_S_PARTITION_SIZE -#else -#define FLASH_MAX_PARTITION_SIZE FLASH_NS_PARTITION_SIZE + +/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 kB */ +/* Same as FLASH0_SIZE */ +#define FLASH_TOTAL_SIZE (0x200000) /* 2MB */ + +#if ((FLASH_S_PARTITION_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0) +#error "Secure image size should be a multiple of flash sector size!" #endif -/* Sector size of the embedded flash hardware (erase/program) */ -#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB. Flash memory program/erase operations have a page granularity. */ -/* FLASH size */ -#define FLASH_TOTAL_SIZE (0x100000) /* 1024 kB. */ +#if ((FLASH_NS_PARTITION_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0) +#error "Non-secure image size should be a multiple of flash sector size!" +#endif /* Flash layout info for BL2 bootloader */ -#define FLASH_BASE_ADDRESS (0x00000000) - +#define FLASH_BASE_ADDRESS (XIP_BASE) /* Offset and size definitions of the flash partitions that are handled by the * bootloader. The image swapping is done between IMAGE_PRIMARY and @@ -83,7 +37,7 @@ * swapping. */ #define FLASH_AREA_BL2_OFFSET (0x0) -#define FLASH_AREA_BL2_SIZE (0x10000) /* 64 KB */ +#define FLASH_AREA_BL2_SIZE (0x11000) /* 68 kB */ #if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) /* Secure + Non-secure image primary slot */ @@ -96,12 +50,14 @@ #define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE) #define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \ FLASH_NS_PARTITION_SIZE) -/* Not used, only the Non-swapping firmware upgrade operation - * is supported on nRF91. - */ +/* Scratch area */ #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0) +#define FLASH_AREA_SCRATCH_SIZE (0x8000) /* 32 kB */ +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_SCRATCH_SIZE) /* Maximum number of image sectors supported by the bootloader. */ #define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ FLASH_NS_PARTITION_SIZE) / \ @@ -123,12 +79,13 @@ #define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1) #define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) #define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE) -/* Not used, only the Non-swapping firmware upgrade operation - * is supported on nRF91. - */ +/* Scratch area */ #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0) +#define FLASH_AREA_SCRATCH_SIZE (0x8000) /* 32 kB */ +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES (FLASH_MAX_PARTITION_SIZE / \ + FLASH_AREA_SCRATCH_SIZE) /* Maximum number of image sectors supported by the bootloader. */ #define MCUBOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \ FLASH_AREA_IMAGE_SECTOR_SIZE) @@ -136,33 +93,32 @@ #error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!" #endif /* MCUBOOT_IMAGE_NUMBER */ -/* Not used, only the Non-swapping firmware upgrade operation - * is supported on nRF91. The maximum number of status entries - * supported by the bootloader. - */ -#define MCUBOOT_STATUS_MAX_ENTRIES (0) - - /* Protected Storage (PS) Service definitions */ #define FLASH_PS_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \ FLASH_AREA_SCRATCH_SIZE) -#define FLASH_PS_AREA_SIZE (0x4000) /* 16 KB */ +#define FLASH_PS_AREA_SIZE (2 * FLASH_AREA_IMAGE_SECTOR_SIZE) /* 8 kB */ /* Internal Trusted Storage (ITS) Service definitions */ #define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \ FLASH_PS_AREA_SIZE) -#define FLASH_ITS_AREA_SIZE (0x2000) /* 8 KB */ +#define FLASH_ITS_AREA_SIZE (2 * FLASH_AREA_IMAGE_SECTOR_SIZE) /* 8 kB */ /* OTP_definitions */ #define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ FLASH_ITS_AREA_SIZE) -#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE * 2) +#define FLASH_OTP_NV_COUNTERS_AREA_SIZE (2 * FLASH_AREA_IMAGE_SECTOR_SIZE) /* 8 kB */ #define FLASH_OTP_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE -/* Non-secure storage region */ -#define NRF_FLASH_NS_STORAGE_AREA_OFFSET (FLASH_TOTAL_SIZE - \ - NRF_FLASH_NS_STORAGE_AREA_SIZE) -#define NRF_FLASH_NS_STORAGE_AREA_SIZE (0x8000) /* 32 KB */ +#if (((FLASH_OTP_NV_COUNTERS_AREA_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0) || \ + (FLASH_OTP_NV_COUNTERS_AREA_SIZE < (2 * FLASH_OTP_NV_COUNTERS_SECTOR_SIZE)) || \ + (((FLASH_OTP_NV_COUNTERS_AREA_SIZE / FLASH_OTP_NV_COUNTERS_SECTOR_SIZE) % 2) != 0) \ + ) +#error "NV_COUNTERS should be a multiple of block size and total number of blocks should be more greater than or equal to 2 and even." +#endif + +#if ( FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE > FLASH_TOTAL_SIZE) +#error "Out of flash memory!" +#endif /* Offset and size definition in flash area used by assemble.py */ #define SECURE_IMAGE_OFFSET (0x0) @@ -173,17 +129,17 @@ #define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE /* Flash device name used by BL2 - * Name is defined in flash driver file: Driver_Flash.c + * Name is defined in flash driver file: Driver_Flash_RPI.c */ -#define FLASH_DEV_NAME Driver_FLASH0 +#define FLASH_DEV_NAME RP2350_FLASH /* Smallest flash programmable unit in bytes */ -#define TFM_HAL_FLASH_PROGRAM_UNIT (0x4) +#define TFM_HAL_FLASH_PROGRAM_UNIT (0x100) /* Protected Storage (PS) Service definitions * Note: Further documentation of these definitions can be found in the * TF-M PS Integration Guide. */ -#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 +#define TFM_HAL_PS_FLASH_DRIVER RP2350_FLASH /* In this target the CMSIS driver requires only the offset from the base * address instead of the full memory address. @@ -196,7 +152,16 @@ /* Number of physical erase sectors per logical FS block */ #define TFM_HAL_PS_SECTORS_PER_BLOCK (1) /* Smallest flash programmable unit in bytes */ -#define TFM_HAL_PS_PROGRAM_UNIT (0x4) +#define TFM_HAL_PS_PROGRAM_UNIT TFM_HAL_FLASH_PROGRAM_UNIT +#define PS_FLASH_NAND_BUF_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) + +#if (((TFM_HAL_PS_FLASH_AREA_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0) || \ + ((TFM_HAL_PS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 0) || \ + ((TFM_HAL_PS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 1) || \ + ((TFM_HAL_PS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 3) \ + ) +#error "PS area size should be a multiple of block size and total number of blocks can not be 0, 1 or 3." +#endif /* Internal Trusted Storage (ITS) Service definitions * Note: Further documentation of these definitions can be found in the @@ -204,7 +169,7 @@ * allocated in the external flash just for development platforms that don't * have internal flash available. */ -#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 +#define TFM_HAL_ITS_FLASH_DRIVER RP2350_FLASH /* In this target the CMSIS driver requires only the offset from the base * address instead of the full memory address. @@ -217,7 +182,16 @@ /* Number of physical erase sectors per logical FS block */ #define TFM_HAL_ITS_SECTORS_PER_BLOCK (1) /* Smallest flash programmable unit in bytes */ -#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) +#define TFM_HAL_ITS_PROGRAM_UNIT TFM_HAL_FLASH_PROGRAM_UNIT +#define ITS_FLASH_NAND_BUF_SIZE (2 * FLASH_AREA_IMAGE_SECTOR_SIZE) + +#if (((TFM_HAL_ITS_FLASH_AREA_SIZE % FLASH_AREA_IMAGE_SECTOR_SIZE) != 0) || \ + ((TFM_HAL_ITS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 0) || \ + ((TFM_HAL_ITS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 1) || \ + ((TFM_HAL_ITS_FLASH_AREA_SIZE / FLASH_AREA_IMAGE_SECTOR_SIZE) == 3) \ + ) +#error "ITS area size should be a multiple of block size and total number of blocks can not be 0, 1 or 3." +#endif /* OTP / NV counter definitions */ #define TFM_OTP_NV_COUNTERS_AREA_SIZE (FLASH_OTP_NV_COUNTERS_AREA_SIZE / 2) @@ -226,17 +200,4 @@ #define TFM_OTP_NV_COUNTERS_BACKUP_AREA_ADDR (TFM_OTP_NV_COUNTERS_AREA_ADDR + \ TFM_OTP_NV_COUNTERS_AREA_SIZE) -/* Use Flash memory to store Code data */ -#define FLASH_BASE_ADDRESS (0x00000000) -#define S_ROM_ALIAS_BASE FLASH_BASE_ADDRESS -#define NS_ROM_ALIAS_BASE FLASH_BASE_ADDRESS - -/* Use SRAM memory to store RW data */ -#define SRAM_BASE_ADDRESS (0x20000000) -#define S_RAM_ALIAS_BASE SRAM_BASE_ADDRESS -#define NS_RAM_ALIAS_BASE SRAM_BASE_ADDRESS - -#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE -#define TOTAL_RAM_SIZE (0x00040000) /* 256 kB */ - #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/rpi/rp2350/partition/region_defs.h b/platform/ext/target/rpi/rp2350/partition/region_defs.h new file mode 100644 index 000000000..fdb422512 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/partition/region_defs.h @@ -0,0 +1,173 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#ifdef NO_U_MODIFIER +#define _u(x) x +#endif + +#include "flash_layout.h" +#include "hardware/regs/addressmap.h" /* Coming from SDK */ + +#define BL2_HEAP_SIZE (0x0001000) +#define BL2_MSP_STACK_SIZE (0x0001800) + +#ifdef ENABLE_HEAP +#define S_HEAP_SIZE (0x0000200) +#endif + +#define S_MSP_STACK_SIZE (0x0000800) +#define S_PSP_STACK_SIZE (0x0000800) + +#define NS_HEAP_SIZE (0x0001000) +#define NS_STACK_SIZE (0x0001000) + +#ifdef BL2 +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) +#endif /* BL2 */ + +#ifndef LINK_TO_SECONDARY_PARTITION +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#else +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET \ + + FLASH_S_PARTITION_SIZE) +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ +#if (!defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)) && \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET > S_IMAGE_PRIMARY_PARTITION_OFFSET) +/* If secure image and nonsecure image are concatenated, and nonsecure image + * locates at the higher memory range, then the secure image does not need + * the trailer area. + */ +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE) +#else +#define IMAGE_S_CODE_SIZE \ + (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#endif + +#define IMAGE_NS_CODE_SIZE \ + (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET \ + (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +/* Secure Code stored in Flash */ +#define S_CODE_START ((XIP_BASE) + (S_IMAGE_PRIMARY_AREA_OFFSET)) +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_OVERALL_SIZE (0x30000) /* 192 KB */ + +/* Secure Data stored in SRAM0-3 */ +#define S_DATA_START (SRAM0_BASE) +#define S_DATA_SIZE (S_DATA_OVERALL_SIZE) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* Size of vector table: 52 + 16 entry -> 0x110 bytes */ +/* Not defined, reason: TFM_VECTORS contain default handler implementations as + well, which increases the standard size, resulting a failed check in linker + script */ +//#define S_CODE_VECTOR_TABLE_SIZE (0x110) +/* This is used instead of the above */ +#define NS_VECTOR_ALLOCATED_SIZE 0x124 + +/* Non-secure regions */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +/* Non-Secure Code stored in Code SRAM memory */ +#define NS_CODE_START ((XIP_BASE) + (NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +/* Entry point of Core1 */ +#define NS_CODE_CORE1_START (NS_CODE_START + NS_VECTOR_ALLOCATED_SIZE) + +#define NS_DATA_OVERALL_SIZE (0x40000) + +/* Non-Secure Data stored in ISRAM0+ISRAM1 */ +#define NS_DATA_START (SRAM4_BASE) +#define NS_DATA_SIZE (NS_DATA_OVERALL_SIZE) +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for SAU configuration */ +#define NS_PARTITION_START \ + ((XIP_BASE) + (NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START \ + ((XIP_BASE) + (S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (XIP_BASE) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +/* Bootloader uses same memory as for secure image */ +#define BL2_DATA_START (S_DATA_START) +#define BL2_DATA_SIZE (S_DATA_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_DATA_START +#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \ + BOOT_TFM_SHARED_DATA_SIZE - 1) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE +#define SHARED_BOOT_MEASUREMENT_LIMIT BOOT_TFM_SHARED_DATA_LIMIT + +#define PROVISIONING_BUNDLE_CODE_START (NS_DATA_START) +#define PROVISIONING_BUNDLE_CODE_SIZE (PROVISIONING_CODE_PADDED_SIZE) +/* The max size of the values(keys, seeds) that are going to be provisioned + * into the OTP. */ +#define PROVISIONING_BUNDLE_VALUES_START (PROVISIONING_BUNDLE_CODE_START + PROVISIONING_BUNDLE_CODE_SIZE) +#define PROVISIONING_BUNDLE_VALUES_SIZE (PROVISIONING_VALUES_PADDED_SIZE) +#define PROVISIONING_BUNDLE_DATA_START (PROVISIONING_BUNDLE_VALUES_START + \ + PROVISIONING_BUNDLE_VALUES_SIZE) +#define PROVISIONING_BUNDLE_DATA_SIZE (PROVISIONING_DATA_PADDED_SIZE) + +#define PROVISIONING_BUNDLE_START (XIP_BASE + FLASH_OTP_NV_COUNTERS_AREA_OFFSET + FLASH_OTP_NV_COUNTERS_AREA_SIZE) +#define PROVISIONING_BUNDLE_MAGIC (0x18) + +#if ((PROVISIONING_BUNDLE_START + PROVISIONING_BUNDLE_CODE_SIZE + PROVISIONING_BUNDLE_VALUES_SIZE + \ + PROVISIONING_BUNDLE_DATA_SIZE + PROVISIONING_BUNDLE_MAGIC) > XIP_BASE + FLASH_TOTAL_SIZE) +#error "Out of flash memory!" +#endif + +/* Enable scratch regions for pico-rp2350 */ +#define __ENABLE_SCRATCH__ + +#define SCRATCH_X_START (BL2_DATA_START + BL2_DATA_SIZE) +#define SCRATCH_X_SIZE 0x1000 +#define SCRATCH_Y_START (SCRATCH_X_START + SCRATCH_X_SIZE) +#define SCRATCH_Y_SIZE 0x1000 + +#endif /* __REGION_DEFS_H__ */ diff --git a/platform/ext/target/rpi/rp2350/pico-sdk.patch b/platform/ext/target/rpi/rp2350/pico-sdk.patch new file mode 100644 index 000000000..8d9179838 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/pico-sdk.patch @@ -0,0 +1,41 @@ +diff --git a/src/common/pico_sync/sem.c b/src/common/pico_sync/sem.c +index 9044817..8fc4458 100644 +--- a/src/common/pico_sync/sem.c ++++ b/src/common/pico_sync/sem.c +@@ -15,7 +15,7 @@ void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits) { + } + + int __time_critical_func(sem_available)(semaphore_t *sem) { +-#ifdef __GNUC__ ++#if defined(__GNUC__) && !defined(__STRICT_ANSI__) + return *(volatile typeof(sem->permits) *) &sem->permits; + #else + static_assert(sizeof(sem->permits) == 2, ""); +diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c +index adae078..8a0f857 100644 +--- a/src/rp2_common/hardware_flash/flash.c ++++ b/src/rp2_common/hardware_flash/flash.c +@@ -299,7 +299,7 @@ static void flash_devinfo_update_field(uint16_t wdata, uint16_t mask) { + // Boot RAM does not support exclusives, but does support RWTYPE SET/CLR/XOR (with byte + // strobes). Can't use hw_write_masked because it performs a 32-bit write. + io_rw_16 *devinfo = flash_devinfo_ptr(); +- *hw_xor_alias(devinfo) = (*devinfo ^ wdata) & mask; ++ *(io_rw_32 *)hw_xor_alias_untyped(devinfo) = (*devinfo ^ wdata) & mask; + } + + // This is a RAM function because may be called during flash programming to enable save/restore of +diff --git a/src/rp2_common/pico_multicore/multicore.c b/src/rp2_common/pico_multicore/multicore.c +index f8f5660..725e313 100644 +--- a/src/rp2_common/pico_multicore/multicore.c ++++ b/src/rp2_common/pico_multicore/multicore.c +@@ -101,8 +101,8 @@ int core1_wrapper(int (*entry)(void), void *stack_base) { + void multicore_reset_core1(void) { + // Use atomic aliases just in case core 1 is also manipulating some PSM state + io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET); +- io_rw_32 *power_off_set = hw_set_alias(power_off); +- io_rw_32 *power_off_clr = hw_clear_alias(power_off); ++ io_rw_32 *power_off_set = hw_set_alias_untyped(power_off); ++ io_rw_32 *power_off_clr = hw_clear_alias_untyped(power_off); + + // Hard-reset core 1. + // Reading back confirms the core 1 reset is in the correct state, but also diff --git a/platform/ext/target/rpi/rp2350/pico_sdk_import.cmake b/platform/ext/target/rpi/rp2350/pico_sdk_import.cmake new file mode 100644 index 000000000..9644ea2bb --- /dev/null +++ b/platform/ext/target/rpi/rp2350/pico_sdk_import.cmake @@ -0,0 +1,88 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") +find_package(Git) +set(PICO_SDK_PATCH_COMMAND ${GIT_EXECUTABLE} reset --hard --quiet && ${GIT_EXECUTABLE} apply "${CMAKE_CURRENT_LIST_DIR}/pico-sdk.patch") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + PATCH_COMMAND ${PICO_SDK_PATCH_COMMAND} + ) + else () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + PATCH_COMMAND ${PICO_SDK_PATCH_COMMAND} + ) + endif () + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + FetchContent_Populate(pico_sdk) + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/platform/ext/target/rpi/rp2350/plat_test.c b/platform/ext/target/rpi/rp2350/plat_test.c new file mode 100644 index 000000000..fef65b89d --- /dev/null +++ b/platform/ext/target/rpi/rp2350/plat_test.c @@ -0,0 +1,63 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + + +#include "tfm_plat_test.h" +#include "hardware/timer.h" +#include "hardware/irq.h" + +#define TIMER0_IRQ0_NUM 0 +#define TIMER_MS 1000 +#define TIMER_DELAY_US (500 * TIMER_MS) + +extern void TFM_TIMER0_IRQ_Handler(void); + +#ifdef TFM_PARTITION_SLIH_TEST +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") +#elif defined(TFM_PARTITION_FLIH_TEST) +TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_FLIH_TEST", "APP-ROT") +#endif +void tfm_plat_test_secure_timer_set_alarm_in_us(uint32_t delay_us) +{ + /* Load timer */ + uint64_t target = timer0_hw->timerawl + delay_us; + + /* Write the lower 32 bits of the target time to the alarm which will + arm it */ + timer0_hw->alarm[TIMER0_IRQ0_NUM] = (uint32_t) target; +} + +void tfm_plat_test_secure_timer_irq_handler(void) +{ + TFM_TIMER0_IRQ_Handler(); + tfm_plat_test_secure_timer_set_alarm_in_us(TIMER_DELAY_US); +} + +void tfm_plat_test_secure_timer_start(void) +{ + /* Enable Timer0_0 interrupt */ + hw_set_bits(&timer0_hw->inte, 1u << TIMER0_IRQ0_NUM); + tfm_plat_test_secure_timer_set_alarm_in_us(TIMER_DELAY_US); +} + +void tfm_plat_test_secure_timer_clear_intr(void) +{ + hw_clear_bits(&timer0_hw->intr, 1u << TIMER0_IRQ0_NUM); +} + +void tfm_plat_test_secure_timer_stop(void) +{ + /* Disable Timer0_0 interrupt */ + hw_clear_bits(&timer0_hw->inte, 1u << TIMER0_IRQ0_NUM); +} + +void tfm_plat_test_non_secure_timer_start(void) +{ +} + +void tfm_plat_test_non_secure_timer_stop(void) +{ +} diff --git a/platform/ext/target/rpi/rp2350/platform_builtin_key_loader_ids.h b/platform/ext/target/rpi/rp2350/platform_builtin_key_loader_ids.h new file mode 100644 index 000000000..b76d67ce6 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/platform_builtin_key_loader_ids.h @@ -0,0 +1,26 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __PLATFORM_BUILTIN_KEY_LOADER_IDS_H__ +#define __PLATFORM_BUILTIN_KEY_LOADER_IDS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TFM_BUILTIN_MAX_KEY_LEN 96 + +enum psa_drv_slot_number_t { + TFM_BUILTIN_KEY_SLOT_HUK = 0, + TFM_BUILTIN_KEY_SLOT_IAK, + TFM_BUILTIN_KEY_SLOT_MAX, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __PLATFORM_BUILTIN_KEY_LOADER_IDS_H__ */ diff --git a/platform/ext/target/rpi/rp2350/platform_multicore.h b/platform/ext/target/rpi/rp2350/platform_multicore.h new file mode 100644 index 000000000..3054886ea --- /dev/null +++ b/platform/ext/target/rpi/rp2350/platform_multicore.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __PLATFORM_MULTICORE_H__ +#define __PLATFORM_MULTICORE_H__ + +#include + +#include "hardware/structs/sio.h" + +#define CORE1_S_READY 0x10 +#define CORE1_NS_READY 0x20 +#define CORE0_NS_READY 0x30 + +#define NS_MAILBOX_INIT 0x100 +#define S_MAILBOX_READY 0x110 + +#define NOTIFY_FROM_CORE0 0x200 +#define NOTIFY_FROM_CORE1 0x300 + +#define HALT_DOORBELL_MASK (0x1UL << 0) +#define FLASH_DOORBELL_MASK (0x1UL << 1) + +#define UART_SPINLOCK_NUM 0 +#define FLASH_SPINLOCK_NUM 1 +#define MAILBOX_SPINLOCK_NUM 2 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define UART_SPINLOCK (&sio_ns_hw->spinlock[UART_SPINLOCK_NUM]) +#define FLASH_SPINLOCK (&sio_hw->spinlock[FLASH_SPINLOCK_NUM]) +#define MAILBOX_SPINLOCK (&sio_ns_hw->spinlock[MAILBOX_SPINLOCK_NUM]) +#else +#define UART_SPINLOCK (&sio_hw->spinlock[UART_SPINLOCK_NUM]) +#define MAILBOX_SPINLOCK (&sio_hw->spinlock[MAILBOX_SPINLOCK_NUM]) +#endif + + +bool multicore_ns_fifo_rvalid(void); +bool multicore_ns_fifo_wready(void); +void multicore_ns_fifo_push_blocking_inline(uint32_t data); +uint32_t multicore_ns_fifo_pop_blocking_inline(void); +extern volatile uint32_t CORE1_RUNNING; + + +#endif /* __PLATFORM_MULTICORE_H__ */ diff --git a/platform/ext/target/rpi/rp2350/platform_nv_counters_ids.h b/platform/ext/target/rpi/rp2350/platform_nv_counters_ids.h new file mode 100644 index 000000000..1112e2efd --- /dev/null +++ b/platform/ext/target/rpi/rp2350/platform_nv_counters_ids.h @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __PLATFORM_NV_COUNTERS_IDS_H__ +#define __PLATFORM_NV_COUNTERS_IDS_H__ + +#include + +enum tfm_nv_counter_t { + PLAT_NV_COUNTER_PS_0 = 0, /* Used by PS service */ + PLAT_NV_COUNTER_PS_1, /* Used by PS service */ + PLAT_NV_COUNTER_PS_2, /* Used by PS service */ + + /* BL2 NV counters must be contiguous */ + PLAT_NV_COUNTER_BL2_0, /* Used by bootloader */ + PLAT_NV_COUNTER_BL2_1, /* Used by bootloader */ + PLAT_NV_COUNTER_BL2_2, /* Used by bootloader */ + PLAT_NV_COUNTER_BL2_3, /* Used by bootloader */ + + /* NS counters must be contiguous */ + PLAT_NV_COUNTER_NS_0, /* Used by NS */ + PLAT_NV_COUNTER_NS_1, /* Used by NS */ + PLAT_NV_COUNTER_NS_2, /* Used by NS */ + + PLAT_NV_COUNTER_MAX, + PLAT_NV_COUNTER_BOUNDARY = UINT32_MAX /* Fix tfm_nv_counter_t size + to 4 bytes */ +}; + +#endif /* __PLATFORM_NV_COUNTERS_IDS_H__ */ diff --git a/platform/ext/target/rpi/rp2350/platform_otp_ids.h b/platform/ext/target/rpi/rp2350/platform_otp_ids.h new file mode 100644 index 000000000..cad3f0735 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/platform_otp_ids.h @@ -0,0 +1,62 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __PLATFORM_OTP_IDS_H__ +#define __PLATFORM_OTP_IDS_H__ + +#include + +enum tfm_otp_element_id_t { + PLAT_OTP_ID_HUK = 0, + PLAT_OTP_ID_GUK, + PLAT_OTP_ID_IAK, + PLAT_OTP_ID_IAK_LEN, + PLAT_OTP_ID_IAK_TYPE, + PLAT_OTP_ID_IAK_ID, + + PLAT_OTP_ID_BOOT_SEED, + PLAT_OTP_ID_LCS, + PLAT_OTP_ID_IMPLEMENTATION_ID, + PLAT_OTP_ID_CERT_REF, + PLAT_OTP_ID_VERIFICATION_SERVICE_URL, + PLAT_OTP_ID_PROFILE_DEFINITION, + + /* BL2 ROTPK must be contiguous */ + PLAT_OTP_ID_BL2_ROTPK_0, + PLAT_OTP_ID_BL2_ROTPK_1, + PLAT_OTP_ID_BL2_ROTPK_2, + PLAT_OTP_ID_BL2_ROTPK_3, + + /* BL2 NV counters must be contiguous */ + PLAT_OTP_ID_NV_COUNTER_BL2_0, + PLAT_OTP_ID_NV_COUNTER_BL2_1, + PLAT_OTP_ID_NV_COUNTER_BL2_2, + PLAT_OTP_ID_NV_COUNTER_BL2_3, + + PLAT_OTP_ID_NV_COUNTER_NS_0, + PLAT_OTP_ID_NV_COUNTER_NS_1, + PLAT_OTP_ID_NV_COUNTER_NS_2, + + PLAT_OTP_ID_KEY_BL2_ENCRYPTION, + PLAT_OTP_ID_BL1_2_IMAGE, + PLAT_OTP_ID_BL1_2_IMAGE_HASH, + PLAT_OTP_ID_BL2_IMAGE_HASH, + PLAT_OTP_ID_BL1_ROTPK_0, + + PLAT_OTP_ID_NV_COUNTER_BL1_0, + + PLAT_OTP_ID_ENTROPY_SEED, + + PLAT_OTP_ID_SECURE_DEBUG_PK, + + PLAT_OTP_ID_NV_COUNTER_PS_0, + PLAT_OTP_ID_NV_COUNTER_PS_1, + PLAT_OTP_ID_NV_COUNTER_PS_2, + + PLAT_OTP_ID_MAX = UINT32_MAX, +}; + +#endif /* __PLATFORM_OTP_IDS_H__ */ diff --git a/platform/ext/target/rpi/rp2350/rp2350_otp.c b/platform/ext/target/rpi/rp2350/rp2350_otp.c new file mode 100644 index 000000000..c2f1499d4 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/rp2350_otp.c @@ -0,0 +1,257 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_plat_otp.h" +#include "pico/bootrom.h" +#include "hardware/regs/otp_data.h" +#include + +#define OTP_BUFFER_MASK 0x0000FFFF +#define OTP_IS_WRITE_MASK 0x00010000 +#define OTP_IS_ECC_MASK 0x00020000 +#define OTP_ROW_PER_PAGE 0x40 + +struct rp2350_otp_element_t { + uint16_t row_offset; /* OTP row offset, used in otp_access() bootrom api */ + uint8_t byte_len; /* Length of the element in bytes, should be aligned(2) or + aligned(4) depending usage mode */ +}; + +/* RP2350 OTP is accessable through the bootrom api: otp_access. This OTP is + organized into pages and rows, it has 64 pages, each 64 rows in size, 4096 + rows altogether. Each row has 24 bits (16 bit data, 8bit ECC). Because of its + structure accesses have to be aligned to 2 bytes. The default OTP elements + need to be placed here. This sturct serves as a map between rows and + tfm_otp_element_id_t ids. + The first 3 pages are occupied. +*/ +static const struct rp2350_otp_element_t otp_map[] = { + [PLAT_OTP_ID_HUK] = {.row_offset = 0xC0 + 0x00 , .byte_len = 32 }, + [PLAT_OTP_ID_GUK] = {.row_offset = 0xC0 + 0x10 , .byte_len = 32 }, + [PLAT_OTP_ID_IAK] = {.row_offset = 0xC0 + 0x20 , .byte_len = 32 }, + [PLAT_OTP_ID_IAK_LEN] = {.row_offset = 0xC0 + 0x30 , .byte_len = 4 }, + [PLAT_OTP_ID_IAK_TYPE] = {.row_offset = 0xC0 + 0x32 , .byte_len = 4 }, + [PLAT_OTP_ID_IAK_ID] = {.row_offset = 0xC0 + 0x34 , .byte_len = 32 }, + [PLAT_OTP_ID_BOOT_SEED] = {.row_offset = 0xC0 + 0x44 , .byte_len = 32 }, + [PLAT_OTP_ID_LCS] = {.row_offset = 0xC0 + 0x54 , .byte_len = 4 }, + [PLAT_OTP_ID_IMPLEMENTATION_ID] = {.row_offset = 0xC0 + 0x56 , .byte_len = 32 }, + [PLAT_OTP_ID_CERT_REF] = {.row_offset = 0xC0 + 0x66 , .byte_len = 32 }, + [PLAT_OTP_ID_VERIFICATION_SERVICE_URL] = {.row_offset = 0xC0 + 0x76 , .byte_len = 32 }, + [PLAT_OTP_ID_PROFILE_DEFINITION] = {.row_offset = 0xC0 + 0x86 , .byte_len = 32 }, + [PLAT_OTP_ID_BL2_ROTPK_0] = {.row_offset = 0xC0 + 0x96 , .byte_len = 100}, + [PLAT_OTP_ID_BL2_ROTPK_1] = {.row_offset = 0xC0 + 0xC8 , .byte_len = 100}, + [PLAT_OTP_ID_BL2_ROTPK_2] = {.row_offset = 0xC0 + 0xFA , .byte_len = 100}, + [PLAT_OTP_ID_BL2_ROTPK_3] = {.row_offset = 0xC0 + 0x12C, .byte_len = 100}, + [PLAT_OTP_ID_NV_COUNTER_BL2_0] = {.row_offset = 0xC0 + 0x15E, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_BL2_1] = {.row_offset = 0xC0 + 0x17E, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_BL2_2] = {.row_offset = 0xC0 + 0x19E, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_BL2_3] = {.row_offset = 0xC0 + 0x1BE, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_NS_0] = {.row_offset = 0xC0 + 0x1DE, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_NS_1] = {.row_offset = 0xC0 + 0x1FE, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_NS_2] = {.row_offset = 0xC0 + 0x21E, .byte_len = 64 }, + [PLAT_OTP_ID_KEY_BL2_ENCRYPTION] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_BL1_2_IMAGE] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_BL1_2_IMAGE_HASH] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_BL2_IMAGE_HASH] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_BL1_ROTPK_0] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_NV_COUNTER_BL1_0] = {.row_offset = 0xC0 + 0x23E, .byte_len = 0 }, + [PLAT_OTP_ID_ENTROPY_SEED] = {.row_offset = 0xC0 + 0x23E, .byte_len = 64 }, + [PLAT_OTP_ID_SECURE_DEBUG_PK] = {.row_offset = 0xC0 + 0x25E, .byte_len = 32 }, + [PLAT_OTP_ID_NV_COUNTER_PS_0] = {.row_offset = 0xC0 + 0x26E, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_PS_1] = {.row_offset = 0xC0 + 0x28E, .byte_len = 64 }, + [PLAT_OTP_ID_NV_COUNTER_PS_2] = {.row_offset = 0xC0 + 0x2AE, .byte_len = 64 }, +}; + +enum tfm_plat_err_t tfm_plat_otp_init(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_read(enum tfm_otp_element_id_t id, + size_t out_len, uint8_t *out) +{ + otp_cmd_t row_and_flags; + otp_cmd_t odd_byte_row_and_flags; + int rc = 0; + size_t out_len_checked; + uint8_t odd_byte_buff[2] = {0}; + uint8_t *odd_byte_p; + + + if ((out_len == 0) || (otp_map[id].byte_len == 0)) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Output buffer can be bigger than the OTP element */ + out_len_checked = (out_len < otp_map[id].byte_len) ? out_len : otp_map[id].byte_len; + + /* Assemble command */ + row_and_flags.flags = (OTP_BUFFER_MASK & otp_map[id].row_offset); + /* For LCS ECC is not used so it can be updated */ + if (id != PLAT_OTP_ID_LCS) { + row_and_flags.flags |= OTP_IS_ECC_MASK; + } + + /* Read OTP through API */ + /* Bootrom API requires 2 byte alignment with ECC mode ON, handle odd byte separately */ + if (out_len_checked % 2) { + /* Update len to be even */ + out_len_checked -= 1; + /* Assemble the command for the odd byte, row number is incremented by (len in byte)/2 */ + odd_byte_row_and_flags.flags = row_and_flags.flags + (out_len_checked / 2); + /* Set pointer to the last byte of the output (not the buffer) */ + odd_byte_p = out + out_len_checked; + + rc = rom_func_otp_access(&odd_byte_buff[0], 2, odd_byte_row_and_flags); + if (rc) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + memcpy(odd_byte_p, &odd_byte_buff[0], 1); + } + if (out_len_checked) { + rc = rom_func_otp_access(out, out_len_checked, row_and_flags); + if (rc) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + return TFM_PLAT_ERR_SUCCESS; + +} + +enum tfm_plat_err_t tfm_plat_otp_write(enum tfm_otp_element_id_t id, + size_t in_len, const uint8_t *in) +{ + otp_cmd_t row_and_flags; + otp_cmd_t odd_byte_row_and_flags; + int rc = 0; + size_t in_len_checked; + uint8_t odd_byte_buff[2] = {0}; + uint8_t *odd_byte_p; + + if ((in_len == 0) || (otp_map[id].byte_len == 0)) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + in_len_checked = (in_len < otp_map[id].byte_len) ? in_len : otp_map[id].byte_len; + + /* Assemble command */ + row_and_flags.flags = OTP_IS_WRITE_MASK | + (OTP_BUFFER_MASK & otp_map[id].row_offset); + /* For LCS ECC is not used so it can be updated */ + if (id != PLAT_OTP_ID_LCS) { + row_and_flags.flags |= OTP_IS_ECC_MASK; + } + + /* Write OTP through API */ + /* Bootrom API requires 2 byte alignment with ECC mode ON, handle odd byte separately */ + if (in_len_checked % 2) { + /* Update len to be even */ + in_len_checked -= 1; + /* Assemble the command for the odd byte, row number is incremented by (len in byte)/2 */ + odd_byte_row_and_flags.flags = row_and_flags.flags + (in_len_checked / 2); + /* Set pointer to the last byte of the input (not the buffer) */ + odd_byte_p = in + in_len_checked; + memcpy(&odd_byte_buff[0], odd_byte_p, 1); + + rc = rom_func_otp_access(&odd_byte_buff[0], 2, odd_byte_row_and_flags); + if (rc) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + if (in_len_checked) { + rc = rom_func_otp_access(in, in_len_checked, row_and_flags); + if (rc) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_get_size(enum tfm_otp_element_id_t id, + size_t *size) +{ + if (id >= PLAT_OTP_ID_MAX) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + *size = otp_map[id].byte_len; + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_start(void) +{ + return TFM_PLAT_ERR_SUCCESS; +} + +enum tfm_plat_err_t tfm_plat_otp_secure_provisioning_finish(void) +{ + + uint32_t row_count = 0; + uint8_t first_page_to_lock; + uint8_t last_page_to_lock; + uint8_t num_pages_to_lock; + otp_cmd_t row_and_flags; + uint8_t msg_buff[4] = {0}; + uint32_t lock_config; + int rc = 0; + + /* Count the number of allocated OTP rows, assuming continious usage */ + for (int i = 0; i <= PLAT_OTP_ID_SECURE_DEBUG_PK; i++) { + row_count += otp_map[i].byte_len; + } + + /* Get the pages to be locked */ + first_page_to_lock = otp_map[0].row_offset / OTP_ROW_PER_PAGE; + + last_page_to_lock = (otp_map[PLAT_OTP_ID_SECURE_DEBUG_PK].row_offset + + (otp_map[PLAT_OTP_ID_SECURE_DEBUG_PK].byte_len / 2)) / + 0x40; + num_pages_to_lock = last_page_to_lock - first_page_to_lock + 1; + + /* First and last 3 pages are already in use */ + if ((first_page_to_lock < 3) || (last_page_to_lock > 60)) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + + /* Assmble message */ + /* Lock information encoded to the first 8 bits of lock register 1 */ + lock_config = (OTP_DATA_PAGE0_LOCK1_LOCK_NS_BITS & + (OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_INACCESSIBLE << + OTP_DATA_PAGE0_LOCK1_LOCK_NS_LSB)) | + (OTP_DATA_PAGE0_LOCK1_LOCK_BL_BITS & + (OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_INACCESSIBLE << + OTP_DATA_PAGE0_LOCK1_LOCK_BL_LSB)); + /* Triple majority vote */ + msg_buff[0] = lock_config; + msg_buff[1] = lock_config; + msg_buff[2] = lock_config; + + /* Lock pages, NS and BL code should not be able to access them */ + for (int i = 0; i < num_pages_to_lock; i++) { + /* Assemble command */ + row_and_flags.flags = OTP_IS_WRITE_MASK | + (OTP_BUFFER_MASK & (OTP_DATA_PAGE0_LOCK1_ROW + + ((i + first_page_to_lock) * 2))); + + /* Write lock register PAGExx_LOCK1 */ + rc = rom_func_otp_access(&msg_buff[0], 4, row_and_flags); + if (rc) { + return TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + return TFM_PLAT_ERR_SUCCESS; +} diff --git a/platform/ext/target/rpi/rp2350/rpi_trng.c b/platform/ext/target/rpi/rp2350/rpi_trng.c new file mode 100644 index 000000000..dad35cde0 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/rpi_trng.c @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "psa/crypto.h" +#include "pico/rand.h" +#include + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +psa_status_t mbedtls_psa_external_get_random(mbedtls_psa_external_random_context_t *context, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + size_t i = 0; + size_t copy_size = 0; + size_t remaining_size = 0; + + uint64_t tmp_trn; + + (void) context; + + while (i < output_size) { + remaining_size = output_size - i; + copy_size = (remaining_size > 8) ? 8 : remaining_size; + + tmp_trn = get_rand_64(); + memcpy(output + i, (uint8_t *)(&tmp_trn), copy_size); + i += copy_size; + } + + *output_length = output_size; + + return PSA_SUCCESS; +} +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ diff --git a/platform/ext/target/rpi/rp2350/services/src/tfm_platform_system.c b/platform/ext/target/rpi/rp2350/services/src/tfm_platform_system.c new file mode 100644 index 000000000..12c1835a8 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/services/src/tfm_platform_system.c @@ -0,0 +1,28 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_platform_system.h" +#include "tfm_hal_device_header.h" +#include "tfm_hal_platform.h" + +void tfm_platform_hal_system_reset(void) +{ + __disable_irq(); + tfm_hal_system_reset(); +} + +enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request, + psa_invec *in_vec, + psa_outvec *out_vec) +{ + (void)request; + (void)in_vec; + (void)out_vec; + + /* Not needed for this platform */ + return TFM_PLATFORM_ERR_NOT_SUPPORTED; +} + diff --git a/platform/ext/target/rpi/rp2350/static_assert_override.h b/platform/ext/target/rpi/rp2350/static_assert_override.h new file mode 100644 index 000000000..300cc43a1 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/static_assert_override.h @@ -0,0 +1,8 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#define static_assert(cond, message) +#define asm __asm diff --git a/platform/ext/target/rpi/rp2350/target_cfg.c b/platform/ext/target/rpi/rp2350/target_cfg.c new file mode 100644 index 000000000..a61049368 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/target_cfg.c @@ -0,0 +1,320 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_device_header.h" +#include "region_defs.h" +#include "target_cfg.h" +#include "tfm_plat_defs.h" +#include "tfm_peripherals_def.h" +#include "hardware/uart.h" +#include "region.h" +#include "hardware/regs/addressmap.h" +#include "hardware/structs/accessctrl.h" +#include "hardware/structs/dma.h" + +#define REG_RW(addr) (*(volatile uint32_t *)(addr)) + +#define ACCESSCTRL_DBG (1U << 7) +#define ACCESSCTRL_DMA (1U << 6) +#define ACCESSCTRL_CORE1 (1U << 5) +#define ACCESSCTRL_CORE0 (1U << 4) +#define ACCESSCTRL_SP (1U << 3) +#define ACCESSCTRL_SU (1U << 2) +#define ACCESSCTRL_NSP (1U << 1) +#define ACCESSCTRL_NSU (1U << 0) + +#define ACCESSCTRL_NS_PRIV (ACCESSCTRL_DBG | ACCESSCTRL_DMA | \ + ACCESSCTRL_CORE1 | ACCESSCTRL_CORE0 |\ + ACCESSCTRL_SP | ACCESSCTRL_SU | \ + ACCESSCTRL_NSP) +#define ACCESSCTRL_S_UNPRIV_C0 (ACCESSCTRL_DBG | ACCESSCTRL_CORE0 |\ + ACCESSCTRL_SP | ACCESSCTRL_SU) +/* Only grant access to Core0 when Multi-core topology is not in use */ +#ifdef TFM_MULTI_CORE_TOPOLOGY +#define ACCESSCTRL_S_UNPRIV_C0_C1 (ACCESSCTRL_DBG | ACCESSCTRL_CORE0 |\ + ACCESSCTRL_CORE1 | ACCESSCTRL_SP |\ + ACCESSCTRL_SU) +#else +#define ACCESSCTRL_S_UNPRIV_C0_C1 ACCESSCTRL_S_UNPRIV_C0 +#endif +#define ACCESSCTRL_S_PRIV_C0 (ACCESSCTRL_DBG | ACCESSCTRL_CORE0 |\ + ACCESSCTRL_SP) + + +#ifdef CONFIG_TFM_USE_TRUSTZONE +REGION_DECLARE(Image$$, ER_VENEER, $$Base); +REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); +#endif /* CONFIG_TFM_USE_TRUSTZONE */ +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE_START, $$RO$$Base); +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE_END, $$RO$$Limit); +REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); +#ifdef CONFIG_TFM_PARTITION_META +REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$ZI$$Base); +REGION_DECLARE(Image$$, TFM_SP_META_PTR_END, $$ZI$$Limit); +#endif /* CONFIG_TFM_PARTITION_META */ + +#define FF_TEST_NVMEM_REGION_START 0x2005E000 +#define FF_TEST_NVMEM_REGION_END 0x2005E3FF +#define FF_TEST_SERVER_PARTITION_MMIO_START 0x2005E400 +#define FF_TEST_SERVER_PARTITION_MMIO_END 0x2005E4FF +#define FF_TEST_DRIVER_PARTITION_MMIO_START 0x2005E600 +#define FF_TEST_DRIVER_PARTITION_MMIO_END 0x2005E6FF + +extern const struct memory_region_limits memory_regions; + +struct platform_data_t tfm_peripheral_std_uart = { + .periph_start = UART0_BASE, + .periph_limit = UART0_BASE + 0x3FFF, + /* Based on platform_data_t definition TF-M expects PPC to control + security and privilege settings. There is no PPC on this platform. + Using periph_ppc_mask to store accessctrl register index. */ + .periph_ppc_mask = AC_DO_NOT_CONFIGURE, +}; + +struct platform_data_t tfm_peripheral_timer0 = { + .periph_start = TIMER0_BASE, + .periph_limit = TIMER0_BASE + 0x3FFF, + /* Based on platform_data_t definition TF-M expects PPC to control + security and privilege settings. There is no PPC on this platform. + Using periph_ppc_mask to store accessctrl register index. */ + .periph_ppc_mask = AC_TIMER0, +}; + +#ifdef PSA_API_TEST_IPC + +/* Below data structure are only used for PSA FF tests, and this pattern is + * definitely not to be followed for real life use cases, as it can break + * security. + */ + +struct platform_data_t + tfm_peripheral_FF_TEST_UART_REGION = { + .periph_start = UART1_BASE, + .periph_limit = UART1_BASE + 0x3FFF, + .periph_ppc_mask = AC_UART1, +}; + +struct platform_data_t + tfm_peripheral_FF_TEST_WATCHDOG_REGION = { + .periph_start = WATCHDOG_BASE, + .periph_limit = WATCHDOG_BASE + 0x3FFF, + .periph_ppc_mask = AC_DO_NOT_CONFIGURE, +}; + +struct platform_data_t + tfm_peripheral_FF_TEST_NVMEM_REGION = { + .periph_start = FF_TEST_NVMEM_REGION_START, + .periph_limit = FF_TEST_NVMEM_REGION_END, + .periph_ppc_mask = AC_DO_NOT_CONFIGURE +}; + +struct platform_data_t + tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO = { + .periph_start = FF_TEST_SERVER_PARTITION_MMIO_START, + .periph_limit = FF_TEST_SERVER_PARTITION_MMIO_END, + .periph_ppc_mask = AC_DO_NOT_CONFIGURE +}; + +struct platform_data_t + tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO = { + .periph_start = FF_TEST_DRIVER_PARTITION_MMIO_START, + .periph_limit = FF_TEST_DRIVER_PARTITION_MMIO_END, + .periph_ppc_mask = AC_DO_NOT_CONFIGURE +}; +#endif + +/*------------------- SAU/IDAU configuration functions -----------------------*/ +void sau_and_idau_cfg(void) +{ + /* Ensure all memory accesses are completed */ + __DMB(); + #if 0 /* Bootrom set to be secure temporary */ + /* Configures SAU regions to be non-secure */ + /* Configure Bootrom */ + SAU->RNR = 0; + SAU->RBAR = (ROM_BASE & SAU_RBAR_BADDR_Msk); + SAU->RLAR = ((ROM_BASE + 0x7E00 - 1) & SAU_RLAR_LADDR_Msk) + | SAU_RLAR_ENABLE_Msk; + + /* Configure Bootrom SGs */ + SAU->RNR = 1; + SAU->RBAR = ((ROM_BASE + 0x7E00) & SAU_RBAR_BADDR_Msk); + SAU->RLAR = ((ROM_BASE + 0x7FFF) & SAU_RLAR_LADDR_Msk) + | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk; + #endif + + /* Configures veneers region to be non-secure callable */ + SAU->RNR = 2; + SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk) + | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk; + + /* Configure Non-Secure partition in flash */ + SAU->RNR = 3; + SAU->RBAR = (memory_regions.non_secure_partition_base + & SAU_RBAR_BADDR_Msk); + SAU->RLAR = (memory_regions.non_secure_partition_limit + & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk; + + /* Configure the rest of the address map up to PPB */ + SAU->RNR = 4; + SAU->RBAR = (SRAM4_BASE & SAU_RBAR_BADDR_Msk); + SAU->RLAR = ((PPB_BASE - 1) & SAU_RLAR_LADDR_Msk) + | SAU_RLAR_ENABLE_Msk; + + /* Turn off unused bootrom region */ + SAU->RNR = 7; + SAU->RBAR = 0; + SAU->RLAR = 0; + + /* Enables SAU */ + TZ_SAU_Enable(); + /* Add barriers to assure the SAU configuration is done before continue + * the execution. + */ + __DSB(); + __ISB(); +} + +enum tfm_plat_err_t bus_filter_cfg(void) +{ + enum tfm_plat_err_t err = TFM_PLAT_ERR_SUCCESS; + uint32_t c0_c1_unpriv_periph_offsets[] = {AC_SRAM0, + AC_SRAM1, AC_SRAM2, AC_SRAM3}; + uint8_t nbr_of_c0_c1_unpriv_periphs; + uint32_t c0_unpriv_periph_offsets[] = {AC_SYSCFG, AC_CLOCKS_BANK_DEFAULT, + AC_RSM, AC_BUSCTRL, AC_OTP, AC_POWMAN, AC_TRNG, AC_XOSC, + AC_ROSC, AC_PLL_SYS, AC_PLL_USB, AC_TICKS, AC_XIP_CTRL, + AC_XIP_QMI}; + uint8_t nbr_of_c0_unpriv_periphs; + uint32_t ns_priv_periph_offsets[] = {AC_ROM, AC_XIP_MAIN, AC_SRAM4, + AC_SRAM5, AC_SRAM6, AC_SRAM7, AC_SRAM8, AC_SRAM9, AC_DMA, + AC_USBCTRL, AC_PIO0, AC_PIO1, AC_PIO2, AC_CORESIGHT_TRACE, + AC_CORESIGHT_PERIPH, AC_SYSINFO, AC_RESETS, AC_IO_BANK0, + AC_IO_BANK1, AC_PADS_BANK0, AC_PADS_QSPI, AC_ADC0, AC_HSTX, + AC_I2C0, AC_I2C1, AC_PWM, AC_SPI0, AC_SPI1, AC_TIMER0, + AC_TIMER1, AC_UART0, AC_UART1, AC_TBMAN, AC_SHA256, AC_WATCHDOG, + AC_XIP_AUX}; + uint8_t nbr_of_ns_periphs; + uint32_t temp_addr; + + nbr_of_c0_c1_unpriv_periphs = sizeof(c0_c1_unpriv_periph_offsets) / + sizeof(c0_c1_unpriv_periph_offsets[0]); + nbr_of_c0_unpriv_periphs = sizeof(c0_unpriv_periph_offsets) / + sizeof(c0_unpriv_periph_offsets[0]); + nbr_of_ns_periphs = sizeof(ns_priv_periph_offsets) / + sizeof(ns_priv_periph_offsets[0]); + + /* Probably worth doing a software reset of access ctrl before setup */ + accessctrl_hw->cfgreset = ACCESSCTRL_PASSWORD_BITS | 0x1; + + accessctrl_hw->gpio_nsmask[0] = 0xFFFFFFFC; + accessctrl_hw->gpio_nsmask[1] = 0xFF00FFFF; + + /* Peripherals controlled by Secure Core0 and Core1 */ + for (uint8_t i = 0; i < nbr_of_c0_c1_unpriv_periphs; i++){ + temp_addr = ACCESSCTRL_BASE + c0_c1_unpriv_periph_offsets[i]; + REG_RW(temp_addr) = ACCESSCTRL_S_UNPRIV_C0_C1 | + ACCESSCTRL_PASSWORD_BITS; + if (REG_RW(temp_addr) != ACCESSCTRL_S_UNPRIV_C0_C1) { + err = TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + /* Peripherals controlled by Secure Core0 */ + for (uint8_t i = 0; i < nbr_of_c0_unpriv_periphs; i++){ + temp_addr = ACCESSCTRL_BASE + c0_unpriv_periph_offsets[i]; + REG_RW(temp_addr) = ACCESSCTRL_S_UNPRIV_C0 | + ACCESSCTRL_PASSWORD_BITS; + if (REG_RW(temp_addr) != ACCESSCTRL_S_UNPRIV_C0) { + err = TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + /* Peripherals accessable to all bus actors */ + for (uint8_t i = 0; i < nbr_of_ns_periphs; i++){ + temp_addr = ACCESSCTRL_BASE + ns_priv_periph_offsets[i]; + REG_RW(temp_addr) = ACCESSCTRL_NS_PRIV | + ACCESSCTRL_PASSWORD_BITS; + if (REG_RW(temp_addr) != ACCESSCTRL_NS_PRIV) { + err = TFM_PLAT_ERR_SYSTEM_ERR; + } + } + + /* Lock setings for every actor except Core0, only hard reset can clear + this. Core0 must retain control for mmio control. */ + accessctrl_hw->lock = ACCESSCTRL_PASSWORD_BITS | 0x6; + + return err; +} + +void access_ctrl_configure_to_secure_privileged(access_ctrl_reg_offset offset) +{ + if (offset != AC_DO_NOT_CONFIGURE){ + REG_RW(ACCESSCTRL_BASE + offset) = + ACCESSCTRL_S_PRIV_C0 | ACCESSCTRL_PASSWORD_BITS; + } +} + +void access_ctrl_configure_to_secure_unprivileged(access_ctrl_reg_offset offset) +{ + if (offset != AC_DO_NOT_CONFIGURE){ + REG_RW(ACCESSCTRL_BASE + offset) = + ACCESSCTRL_S_UNPRIV_C0 | ACCESSCTRL_PASSWORD_BITS; + } +} + +enum tfm_plat_err_t dma_security_config(void) +{ + /* Configure every DMA channel as Nonsecure Privileged since TF-M uses no DMA */ + for (int i=0; i<16; i++){ + REG_RW(DMA_BASE + DMA_SECCFG_CH0_OFFSET + (i * 4)) = + DMA_SECCFG_CH0_P_BITS; + } + + /* Configure DMA MPU to mirror SAU settings */ + /* Unmapped address regions default to SP */ + dma_hw->mpu_ctrl = DMA_MPU_CTRL_NS_HIDE_ADDR_BITS | DMA_MPU_CTRL_S_BITS | + DMA_MPU_CTRL_P_BITS; + + /* Configure MPU regions */ + dma_hw->mpu_region[0].bar = (memory_regions.veneer_base & + DMA_MPU_BAR0_BITS); + dma_hw->mpu_region[0].lar = (memory_regions.veneer_limit & + DMA_MPU_LAR0_ADDR_BITS) | + DMA_MPU_LAR0_P_BITS | DMA_MPU_LAR0_EN_BITS; + + dma_hw->mpu_region[1].bar = (memory_regions.non_secure_partition_base & + DMA_MPU_BAR0_BITS); + dma_hw->mpu_region[1].lar = (memory_regions.veneer_limit & + DMA_MPU_LAR0_ADDR_BITS) | + DMA_MPU_LAR0_P_BITS | DMA_MPU_LAR0_EN_BITS; + + dma_hw->mpu_region[2].bar = (SRAM4_BASE & DMA_MPU_BAR0_BITS); + dma_hw->mpu_region[2].lar = ((PPB_BASE - 1) & DMA_MPU_LAR0_ADDR_BITS) | + DMA_MPU_LAR0_P_BITS | DMA_MPU_LAR0_EN_BITS; + + dma_hw->mpu_region[3].bar = 0; + dma_hw->mpu_region[3].lar = 0; + + dma_hw->mpu_region[4].bar = 0; + dma_hw->mpu_region[4].lar = 0; + + dma_hw->mpu_region[5].bar = 0; + dma_hw->mpu_region[5].lar = 0; + + dma_hw->mpu_region[6].bar = 0; + dma_hw->mpu_region[6].lar = 0; + + dma_hw->mpu_region[7].bar = 0; + dma_hw->mpu_region[7].lar = 0; + + return TFM_PLAT_ERR_SUCCESS; +} + diff --git a/platform/ext/target/rpi/rp2350/target_cfg.h b/platform/ext/target/rpi/rp2350/target_cfg.h new file mode 100644 index 000000000..3719df605 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/target_cfg.h @@ -0,0 +1,114 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __TARGET_CFG_H__ +#define __TARGET_CFG_H__ + +#include + +#define TFM_DRIVER_STDIO driver_usart0 +#define NS_DRIVER_STDIO driver_usart0 + +/** + * \brief Defines the word offsets of Slave Peripheral Protection Controller + * Registers + */ +typedef enum +{ + PPC_SP_DO_NOT_CONFIGURE = -1, +} ppc_bank_t; + +typedef enum +{ + AC_LOCK = 0x0, + AC_FORCE_CORE_NS = 0x4, + AC_CFGRESET = 0x8, + AC_GPIO_NSMASK0 = 0xC, + AC_GPIO_NSMASK1 = 0x10, + AC_ROM = 0x14, + AC_XIP_MAIN = 0x18, + AC_SRAM0 = 0x1C, + AC_SRAM1 = 0x20, + AC_SRAM2 = 0x24, + AC_SRAM3 = 0x28, + AC_SRAM4 = 0x2C, + AC_SRAM5 = 0x30, + AC_SRAM6 = 0x34, + AC_SRAM7 = 0x38, + AC_SRAM8 = 0x3C, + AC_SRAM9 = 0x40, + AC_DMA = 0x44, + AC_USBCTRL = 0x48, + AC_PIO0 = 0x4C, + AC_PIO1 = 0x50, + AC_PIO2 = 0x54, + AC_CORESIGHT_TRACE = 0x58, + AC_CORESIGHT_PERIPH = 0x5C, + AC_SYSINFO = 0x60, + AC_RESETS = 0x64, + AC_IO_BANK0 = 0x68, + AC_IO_BANK1 = 0x6C, + AC_PADS_BANK0 = 0x70, + AC_PADS_QSPI = 0x74, + AC_BUSCTRL = 0x78, + AC_ADC0 = 0x7C, + AC_HSTX = 0x80, + AC_I2C0 = 0x84, + AC_I2C1 = 0x88, + AC_PWM = 0x8C, + AC_SPI0 = 0x90, + AC_SPI1 = 0x94, + AC_TIMER0 = 0x98, + AC_TIMER1 = 0x9C, + AC_UART0 = 0xA0, + AC_UART1 = 0xA4, + AC_OTP = 0xA8, + AC_TBMAN = 0xAC, + AC_POWMAN = 0xB0, + AC_TRNG = 0xB4, + AC_SHA256 = 0xB8, + AC_SYSCFG = 0xBC, + AC_CLOCKS_BANK_DEFAULT = 0xC0, + AC_XOSC = 0xC4, + AC_ROSC = 0xC8, + AC_PLL_SYS = 0xCC, + AC_PLL_USB = 0xD0, + AC_TICKS = 0xD4, + AC_WATCHDOG = 0xD8, + AC_RSM = 0xDC, + AC_XIP_CTRL = 0xE0, + AC_XIP_QMI = 0xE4, + AC_XIP_AUX = 0xE8, + AC_DO_NOT_CONFIGURE = 0xFFFF, +} access_ctrl_reg_offset; + +/** + * \brief Initialize SAU. + */ +void sau_and_idau_cfg(void); + +/** + * \brief Configure access control for bus endpoints. + */ +enum tfm_plat_err_t bus_filter_cfg(void); + +/** + * \brief Configure DMA channels' security + */ +enum tfm_plat_err_t dma_security_config(void); + +/** + * \brief Configure bus endpoint to be secure privileged accessible for core0 + */ +void access_ctrl_configure_to_secure_privileged(access_ctrl_reg_offset offset); + + +/** + * \brief Configure bus endpoint to be secure unprivileged accessible for core0 + */ +void access_ctrl_configure_to_secure_unprivileged(access_ctrl_reg_offset offset); + +#endif /* __TARGET_CFG_H__ */ diff --git a/platform/ext/target/rpi/rp2350/tests/psa_arch_tests_config.cmake b/platform/ext/target/rpi/rp2350/tests/psa_arch_tests_config.cmake new file mode 100644 index 000000000..6ae2b7bac --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tests/psa_arch_tests_config.cmake @@ -0,0 +1,9 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- + +# Paramters for PSA API tests + +set(PSA_API_TEST_TARGET rp2350 CACHE STRING "PSA_API_TARGET name") diff --git a/platform/ext/target/rpi/rp2350/tests/tfm_tests_config.cmake b/platform/ext/target/rpi/rp2350/tests/tfm_tests_config.cmake new file mode 100644 index 000000000..3fff55dff --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tests/tfm_tests_config.cmake @@ -0,0 +1,10 @@ +#------------------------------------------------------------------------------- +# SPDX-License-Identifier: BSD-3-Clause +# SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors +# +#------------------------------------------------------------------------------- +# Make FLIH IRQ test as the default IRQ test on RP2350 +set(TEST_NS_SLIH_IRQ OFF CACHE BOOL "Whether to build NS regression Second-Level Interrupt Handling tests") + +set(PLATFORM_SLIH_IRQ_TEST_SUPPORT ON) +set(PLATFORM_FLIH_IRQ_TEST_SUPPORT ON) diff --git a/platform/ext/target/rpi/rp2350/tfm_builtin_key_ids.h b/platform/ext/target/rpi/rp2350/tfm_builtin_key_ids.h new file mode 100644 index 000000000..ec842aef6 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_builtin_key_ids.h @@ -0,0 +1,31 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __TFM_BUILTIN_KEY_IDS_H__ +#define __TFM_BUILTIN_KEY_IDS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief The persistent key identifiers for TF-M builtin keys. + * + * The value of TFM_BUILTIN_KEY_ID_MIN (and therefore of the whole range) is + * completely arbitrary except for being inside the PSA builtin keys range. + * + */ +enum tfm_key_id_builtin_t { + TFM_BUILTIN_KEY_ID_MIN = 0x7FFF815Bu, + TFM_BUILTIN_KEY_ID_HUK, + TFM_BUILTIN_KEY_ID_IAK, + TFM_BUILTIN_KEY_ID_MAX = 0x7FFF817Bu, +}; + +#ifdef __cplusplus +} +#endif +#endif /* __TFM_BUILTIN_KEY_IDS_H__ */ diff --git a/platform/ext/target/rpi/rp2350/tfm_hal_isolation_rp2350.c b/platform/ext/target/rpi/rp2350/tfm_hal_isolation_rp2350.c new file mode 100644 index 000000000..eda91faec --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_hal_isolation_rp2350.c @@ -0,0 +1,469 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include +#include +#include +#include +#include +#include "array.h" +#include "tfm_hal_device_header.h" +#include "region.h" +#include "armv8m_mpu.h" +#include "target_cfg.h" +#include "tfm_hal_defs.h" +#include "tfm_hal_isolation.h" +#include "tfm_peripherals_def.h" +#include "load/spm_load_api.h" + +#define PROT_BOUNDARY_VAL \ + ((1U << HANDLE_ATTR_PRIV_POS) & HANDLE_ATTR_PRIV_MASK) +/* Boundary handle binding macros. */ +#define HANDLE_ATTR_PRIV_POS 1U +#define HANDLE_ATTR_PRIV_MASK (0x1UL << HANDLE_ATTR_PRIV_POS) +#define HANDLE_ATTR_NS_POS 0U +#define HANDLE_ATTR_NS_MASK (0x1UL << HANDLE_ATTR_NS_POS) + +#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT +static uint32_t n_configured_regions = 0; + +#ifdef CONFIG_TFM_USE_TRUSTZONE +REGION_DECLARE(Image$$, ER_VENEER, $$Base); +REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); +#endif /* CONFIG_TFM_USE_TRUSTZONE */ +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE_START, $$RO$$Base); +REGION_DECLARE(Image$$, TFM_UNPRIV_CODE_END, $$RO$$Limit); +REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base); +REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base); +#ifdef CONFIG_TFM_PARTITION_META +REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$ZI$$Base); +REGION_DECLARE(Image$$, TFM_SP_META_PTR_END, $$ZI$$Limit); +#endif /* CONFIG_TFM_PARTITION_META */ + +#define ARM_MPU_NON_TRANSIENT ( 1U ) +#define ARM_MPU_TRANSIENT ( 0U ) +#define ARM_MPU_WRITE_BACK ( 1U ) +#define ARM_MPU_WRITE_THROUGH ( 0U ) +#define ARM_MPU_READ_ALLOCATE ( 1U ) +#define ARM_MPU_NON_READ_ALLOCATE ( 0U ) +#define ARM_MPU_WRITE_ALLOCATE ( 1U ) +#define ARM_MPU_NON_WRITE_ALLOCATE ( 0U ) +#define ARM_MPU_READ_ONLY ( 1U ) +#define ARM_MPU_READ_WRITE ( 0U ) +#define ARM_MPU_UNPRIVILEGED ( 1U ) +#define ARM_MPU_PRIVILEGED ( 0U ) +#define ARM_MPU_EXECUTE_NEVER ( 1U ) +#define ARM_MPU_EXECUTE_OK ( 0U ) +#define ARM_MPU_PRIVILEGE_EXECUTE_NEVER ( 1U ) +#define ARM_MPU_PRIVILEGE_EXECUTE_OK ( 0U ) +#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + +enum tfm_hal_status_t tfm_hal_set_up_static_boundaries( + uintptr_t *p_spm_boundary) +{ +#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT +const ARM_MPU_Region_t mpu_region_attributes[] = { +#ifdef CONFIG_TFM_USE_TRUSTZONE + /* TFM Veneer region (Bootrom SGs are not included) + * Region Number 0, Non-shareable, Read-Only, Non-Privileged, Executable, + * Privilege Executable - if PXN available, Attribute set: 0 + */ + { + ARM_MPU_RBAR((uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + ARM_MPU_SH_NON, + ARM_MPU_READ_ONLY, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_OK), + #ifdef TFM_PXN_ENABLE + ARM_MPU_RLAR_PXN((uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1, + ARM_MPU_PRIVILEGE_EXECUTE_OK, + 0) + #else + ARM_MPU_RLAR((uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1, + 0) + #endif + }, +#endif /* CONFIG_TFM_USE_TRUSTZONE */ + /* TFM Core unprivileged code region + * Region Number 1, Non-shareable, Read-Only, Non-Privileged, Executable, + * Privilege Executable - if PXN available, Attribute set: 0 + */ + { + ARM_MPU_RBAR((uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE_START, $$RO$$Base), + ARM_MPU_SH_NON, + ARM_MPU_READ_ONLY, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_OK), + #ifdef TFM_PXN_ENABLE + ARM_MPU_RLAR_PXN((uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE_END, $$RO$$Limit) - 1, + ARM_MPU_PRIVILEGE_EXECUTE_OK, + 0) + #else + ARM_MPU_RLAR((uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE_END, $$RO$$Limit) - 1, + 0) + #endif + }, + /* RO region + * Region Number 2, Non-shareable, Read-Only, Non-Privileged, Executable, + * PXN depends on isolation level, Attribute set: 0 + */ + { + ARM_MPU_RBAR((uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_START, $$Base), + ARM_MPU_SH_NON, + ARM_MPU_READ_ONLY, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_OK), + #ifdef TFM_PXN_ENABLE + ARM_MPU_RLAR_PXN((uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_END, $$Base) - 1, + #if TFM_ISOLATION_LEVEL == 1 + ARM_MPU_PRIVILEGE_EXECUTE_OK, + #else + ARM_MPU_PRIVILEGE_EXECUTE_NEVER, + #endif + 0) + #else + ARM_MPU_RLAR((uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_END, $$Base) - 1, + 0) + #endif + }, + /* RW, ZI and stack as one region + * Region Number 3, Non-shareable, Read-Write, Non-Privileged, Execute Never + * Attribute set: 1, Privilege Execute Never - if PXN available + */ + { + ARM_MPU_RBAR((uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_START, $$Base), + ARM_MPU_SH_NON, + ARM_MPU_READ_WRITE, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_NEVER), + #ifdef TFM_PXN_ENABLE + ARM_MPU_RLAR_PXN((uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_END, $$Base) - 1, + ARM_MPU_PRIVILEGE_EXECUTE_NEVER, + 1) + #else + ARM_MPU_RLAR((uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_END, $$Base) - 1, + 1) + #endif + }, +#ifdef CONFIG_TFM_PARTITION_META + /* TFM partition metadata pointer region + * Region Number 4, Non-shareable, Read-Write, Non-Privileged, Execute Never + * Attribute set: 1, Privilege Execute Never - if PXN available + */ + { + ARM_MPU_RBAR((uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$ZI$$Base), + ARM_MPU_SH_NON, + ARM_MPU_READ_WRITE, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_NEVER), + #ifdef TFM_PXN_ENABLE + ARM_MPU_RLAR_PXN((uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR_END, $$ZI$$Limit) - 1, + ARM_MPU_PRIVILEGE_EXECUTE_NEVER, + 1) + #else + ARM_MPU_RLAR((uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR_END, $$ZI$$Limit) - 1, + 1) + #endif + }, +#endif +}; + ARM_MPU_Region_t localcfg; +#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + + /* Set up isolation boundaries between SPE and NSPE */ + sau_and_idau_cfg(); + if (bus_filter_cfg() != TFM_PLAT_ERR_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + if (dma_security_config() != TFM_PLAT_ERR_SUCCESS) { + return TFM_HAL_ERROR_GENERIC; + } + + /* Set up static isolation boundaries inside SPE */ +#ifdef CONFIG_TFM_ENABLE_MEMORY_PROTECT + int32_t i; + + uint32_t mpu_region_num = + (MPU ->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + if (mpu_region_num < ARRAY_SIZE(mpu_region_attributes)) { + return TFM_HAL_ERROR_GENERIC; + } + + /* Turn off MPU during configuration */ + if ((MPU->CTRL & MPU_CTRL_ENABLE_Msk)) { + ARM_MPU_Disable(); + } + /* Disable all regions */ + for (i = 0; i < mpu_region_num; i++) { + ARM_MPU_ClrRegion(i); + } + + /* Configure attribute registers + * Attr0 : Normal memory, Inner/Outer Cacheable, Write-Trough Read-Allocate + */ + ARM_MPU_SetMemAttr(0, + ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(ARM_MPU_NON_TRANSIENT, + ARM_MPU_WRITE_THROUGH, + ARM_MPU_READ_ALLOCATE, + ARM_MPU_NON_WRITE_ALLOCATE), + ARM_MPU_ATTR_MEMORY_(ARM_MPU_NON_TRANSIENT, + ARM_MPU_WRITE_THROUGH, + ARM_MPU_READ_ALLOCATE, + ARM_MPU_NON_WRITE_ALLOCATE))); + /* Attr1 : Normal memory, Inner/Outer Cacheable, Write-Back R-W Allocate */ + ARM_MPU_SetMemAttr(1, + ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(ARM_MPU_NON_TRANSIENT, + ARM_MPU_WRITE_BACK, + ARM_MPU_READ_ALLOCATE, + ARM_MPU_WRITE_ALLOCATE), + ARM_MPU_ATTR_MEMORY_(ARM_MPU_NON_TRANSIENT, + ARM_MPU_WRITE_BACK, + ARM_MPU_READ_ALLOCATE, + ARM_MPU_WRITE_ALLOCATE))); + /* Attr2 : Device memory, nGnRE */ + ARM_MPU_SetMemAttr(2, + ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, + ARM_MPU_ATTR_DEVICE_nGnRE)); + + /* Configure regions */ + /* Note: CMSIS MPU API clears the lower 5 address bits without check */ + for (i = 0; i < ARRAY_SIZE(mpu_region_attributes); i++) { + localcfg.RBAR = mpu_region_attributes[i].RBAR; + localcfg.RLAR = mpu_region_attributes[i].RLAR; + ARM_MPU_SetRegion(i, localcfg.RBAR, localcfg.RLAR); + } + n_configured_regions = i; + + /* Enable MPU with the above configurations. Allow default memory map for + * privileged software and enable MPU during HardFault and NMI handlers. + */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); +#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */ + + *p_spm_boundary = (uintptr_t)PROT_BOUNDARY_VAL; + + return TFM_HAL_SUCCESS; +} + +/* + * Implementation of tfm_hal_bind_boundary(): + * + * The API encodes some attributes into a handle and returns it to SPM. + * The attributes include isolation boundaries, privilege, and MMIO information. + * When scheduler switches running partitions, SPM compares the handle between + * partitions to know if boundary update is necessary. If update is required, + * SPM passes the handle to platform to do platform settings and update + * isolation boundaries. + */ +enum tfm_hal_status_t tfm_hal_bind_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t *p_boundary) +{ + uint32_t i, j; + bool privileged; + bool ns_agent_tz; + uint32_t partition_attrs = 0; + const struct asset_desc_t *p_asset; + struct platform_data_t *plat_data_ptr; + const uintptr_t* mmio_list; + size_t mmio_list_length; + +#if TFM_ISOLATION_LEVEL == 2 + ARM_MPU_Region_t local_mpu_region; + uint32_t mpu_region_num; +#endif + if (!p_ldinf || !p_boundary) { + return TFM_HAL_ERROR_GENERIC; + } + +#if TFM_ISOLATION_LEVEL == 1 + privileged = true; +#else + privileged = IS_PSA_ROT(p_ldinf); +#endif + + ns_agent_tz = IS_NS_AGENT_TZ(p_ldinf); + p_asset = LOAD_INFO_ASSET(p_ldinf); + + get_partition_named_mmio_list(&mmio_list, &mmio_list_length); + + /* + * Validate if the named MMIO of partition is allowed by the platform. + * Otherwise, skip validation. + * + * NOTE: Need to add validation of numbered MMIO if platform requires. + */ + for (i = 0; i < p_ldinf->nassets; i++) { + if (!(p_asset[i].attr & ASSET_ATTR_NAMED_MMIO)) { + continue; + } + for (j = 0; j < mmio_list_length; j++) { + if (p_asset[i].dev.dev_ref == mmio_list[j]) { + break; + } + } + + if (j == mmio_list_length) { + /* The MMIO asset is not in the allowed list of platform. */ + return TFM_HAL_ERROR_GENERIC; + } + /* Assume sec and priv settings are required even under level 1 */ + plat_data_ptr = REFERENCE_TO_PTR(p_asset[i].dev.dev_ref, + struct platform_data_t *); + + if (plat_data_ptr->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) { + if (privileged) { + access_ctrl_configure_to_secure_privileged( + (access_ctrl_reg_offset)plat_data_ptr->periph_ppc_mask); + } else { + access_ctrl_configure_to_secure_unprivileged( + (access_ctrl_reg_offset)plat_data_ptr->periph_ppc_mask); + } + } +#if TFM_ISOLATION_LEVEL == 2 + /* + * Static boundaries are set. Set up MPU region for MMIO. + * Setup regions for unprivileged assets only. + */ + if (!privileged) { + mpu_region_num = + (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos; + + /* There is a limited number of available MPU regions in v8M */ + if (mpu_region_num <= n_configured_regions) { + return TFM_HAL_ERROR_GENERIC; + } + if ((plat_data_ptr->periph_start & ~MPU_RBAR_BASE_Msk) != 0) { + return TFM_HAL_ERROR_GENERIC; + } + if ((plat_data_ptr->periph_limit & ~MPU_RLAR_LIMIT_Msk) != 0x1F) { + return TFM_HAL_ERROR_GENERIC; + } + + /* Turn off MPU during configuration */ + if (MPU->CTRL & MPU_CTRL_ENABLE_Msk) { + ARM_MPU_Disable(); + } + + /* Assemble region base and limit address register contents. */ + local_mpu_region.RBAR = ARM_MPU_RBAR(plat_data_ptr->periph_start, + ARM_MPU_SH_NON, + ARM_MPU_READ_WRITE, + ARM_MPU_UNPRIVILEGED, + ARM_MPU_EXECUTE_NEVER); + /* Attr2 contains required attribute set for device regions */ + #ifdef TFM_PXN_ENABLE + local_mpu_region.RLAR = ARM_MPU_RLAR_PXN(plat_data_ptr->periph_limit, + ARM_MPU_PRIVILEGE_EXECUTE_NEVER, + 2); + #else + local_mpu_region.RLAR = ARM_MPU_RLAR(plat_data_ptr->periph_limit, + 2); + #endif + + /* Configure device mpu region */ + ARM_MPU_SetRegion(n_configured_regions, + local_mpu_region.RBAR, + local_mpu_region.RLAR); + + n_configured_regions++; + + /* Enable MPU with the new region added */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + } +#endif + } + + partition_attrs = ((uint32_t)privileged << HANDLE_ATTR_PRIV_POS) & + HANDLE_ATTR_PRIV_MASK; + partition_attrs |= ((uint32_t)ns_agent_tz << HANDLE_ATTR_NS_POS) & + HANDLE_ATTR_NS_MASK; + *p_boundary = (uintptr_t)partition_attrs; + + return TFM_HAL_SUCCESS; +} + +enum tfm_hal_status_t tfm_hal_activate_boundary( + const struct partition_load_info_t *p_ldinf, + uintptr_t boundary) +{ + CONTROL_Type ctrl; + bool privileged = !!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK); + + /* Privileged level is required to be set always */ + ctrl.w = __get_CONTROL(); + ctrl.b.nPRIV = privileged ? 0 : 1; + __set_CONTROL(ctrl.w); + + return TFM_HAL_SUCCESS; +} + +enum tfm_hal_status_t tfm_hal_memory_check(uintptr_t boundary, uintptr_t base, + size_t size, uint32_t access_type) +{ + int flags = 0; + + /* If size is zero, this indicates an empty buffer and base is ignored */ + if (size == 0) { + return TFM_HAL_SUCCESS; + } + + if (!base) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if ((access_type & TFM_HAL_ACCESS_READWRITE) == TFM_HAL_ACCESS_READWRITE) { + flags |= CMSE_MPU_READWRITE; + } else if (access_type & TFM_HAL_ACCESS_READABLE) { + flags |= CMSE_MPU_READ; + } else { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + if (access_type & TFM_HAL_ACCESS_NS) { + flags |= CMSE_NONSECURE; + } + + if (!((uint32_t)boundary & HANDLE_ATTR_PRIV_MASK)) { + flags |= CMSE_MPU_UNPRIV; + } + + /* This check is only done for ns_agent_tz */ + if ((uint32_t)boundary & HANDLE_ATTR_NS_MASK) { + CONTROL_Type ctrl; + ctrl.w = __TZ_get_CONTROL_NS(); + if (ctrl.b.nPRIV == 1) { + flags |= CMSE_MPU_UNPRIV; + } else { + flags &= ~CMSE_MPU_UNPRIV; + } + flags |= CMSE_NONSECURE; + } + + if (cmse_check_address_range((void *)base, size, flags) != NULL) { + return TFM_HAL_SUCCESS; + } else { + return TFM_HAL_ERROR_MEM_FAULT; + } +} + +bool tfm_hal_boundary_need_switch(uintptr_t boundary_from, + uintptr_t boundary_to) +{ + if (boundary_from == boundary_to) { + return false; + } + + if (((uint32_t)boundary_from & HANDLE_ATTR_PRIV_MASK) && + ((uint32_t)boundary_to & HANDLE_ATTR_PRIV_MASK)) { + return false; + } + return true; +} diff --git a/platform/ext/target/rpi/rp2350/tfm_hal_mailbox.c b/platform/ext/target/rpi/rp2350/tfm_hal_mailbox.c new file mode 100644 index 000000000..41b93ebf6 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_hal_mailbox.c @@ -0,0 +1,101 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_mailbox.h" +#include "tfm_multi_core.h" +#include "tfm_hal_interrupt.h" +#include "tfm_peripherals_def.h" +#include "hardware/irq.h" +#include "interrupt.h" + +#include "platform_multicore.h" + +#include "pico/multicore.h" + +static struct irq_t mbox_irq_info = {0}; + +int32_t tfm_mailbox_hal_init(struct secure_mailbox_queue_t *s_queue) +{ + struct mailbox_init_t *ns_init = NULL; + + multicore_ns_fifo_push_blocking_inline(NS_MAILBOX_INIT); + + ns_init = (struct mailbox_init_t *) multicore_ns_fifo_pop_blocking_inline(); + + /* + * FIXME + * Necessary sanity check of the address of NPSE mailbox queue should + * be implemented there. + */ + if (ns_init->slot_count > NUM_MAILBOX_QUEUE_SLOT) { + return MAILBOX_INIT_ERROR; + } + + s_queue->ns_status = ns_init->status; + s_queue->ns_slot_count = ns_init->slot_count; + s_queue->ns_slots = ns_init->slots; + + multicore_ns_fifo_push_blocking_inline(S_MAILBOX_READY); + + return MAILBOX_SUCCESS; +} + +int32_t tfm_mailbox_hal_notify_peer(void) +{ + multicore_ns_fifo_push_blocking_inline(NOTIFY_FROM_CORE0); + return MAILBOX_SUCCESS; +} + +void tfm_mailbox_hal_enter_critical(void) +{ + /* Reading a spinlock register attempts to claim it, returning nonzero + * if the claim was successful and 0 if unsuccessful */ + while(!*MAILBOX_SPINLOCK); + return; +} + +void tfm_mailbox_hal_exit_critical(void) +{ + /* Writing to a spinlock register releases it */ + *MAILBOX_SPINLOCK = 0x1u; + return; +} + +/* Platform specific inter-processor communication interrupt handler. */ +void SIO_IRQ_FIFO_NS_IRQHandler(void) +{ + /* + * SPM will send a MAILBOX_SIGNAL to the corresponding partition + * indicating that a message has arrived and can be processed. + */ + uint32_t msg; + if (multicore_ns_fifo_rvalid()) + { + msg = multicore_ns_fifo_pop_blocking_inline(); + if (msg == NOTIFY_FROM_CORE1) { + spm_handle_interrupt(mbox_irq_info.p_pt, mbox_irq_info.p_ildi); + } + } +} + +enum tfm_hal_status_t mailbox_irq_init(void *p_pt, + const struct irq_load_info_t *p_ildi) +{ + mbox_irq_info.p_pt = p_pt; + mbox_irq_info.p_ildi = p_ildi; + + + NVIC_SetPriority(SIO_IRQ_FIFO_NS_IRQn, DEFAULT_IRQ_PRIORITY-1); + irq_set_exclusive_handler(SIO_IRQ_FIFO_NS, SIO_IRQ_FIFO_NS_IRQHandler); + + if (tfm_multi_core_register_client_id_range(CLIENT_ID_OWNER_MAGIC, + p_ildi->client_id_base, + p_ildi->client_id_limit) != 0) { + return TFM_HAL_ERROR_INVALID_INPUT; + } + + return TFM_HAL_SUCCESS; +} \ No newline at end of file diff --git a/platform/ext/target/rpi/rp2350/tfm_hal_multi_core.c b/platform/ext/target/rpi/rp2350/tfm_hal_multi_core.c new file mode 100644 index 000000000..ccf8c1cba --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_hal_multi_core.c @@ -0,0 +1,147 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_multi_core.h" +#include "platform_multicore.h" +#include "target_cfg.h" +#include "region_defs.h" + +#include "interrupt.h" +#include "pico/multicore.h" +#include "hardware/structs/sio.h" + +/* Entrypoint function declaration */ +extern void ns_agent_tz_main(uint32_t c_entry); + +volatile uint32_t CORE1_RUNNING; + +bool multicore_ns_fifo_rvalid(void) { + return !!(sio_ns_hw->fifo_st & SIO_FIFO_ST_VLD_BITS); +} + +bool multicore_ns_fifo_wready(void) { + return !!(sio_ns_hw->fifo_st & SIO_FIFO_ST_RDY_BITS); +} + +void multicore_ns_fifo_push_blocking_inline(uint32_t data) { + /* We wait for the fifo to have some space */ + while (!multicore_ns_fifo_wready()) + tight_loop_contents(); + + sio_ns_hw->fifo_wr = data; + + /* Fire off an event to the other core */ + __sev(); +} + +uint32_t multicore_ns_fifo_pop_blocking_inline(void) { + /* If nothing there yet, we wait for an event first, + to try and avoid too much busy waiting */ + while (!multicore_ns_fifo_rvalid()) + __wfe(); + + return sio_ns_hw->fifo_rd; +} + +static void wait_for_core1_ready(void) +{ + uint32_t stage; + while (1) { + stage = multicore_fifo_pop_blocking(); + if (stage == CORE1_S_READY) { + break; + } + } +} + +/* If Core0 wants to write Flash, Core1 must not use it. + * As Core1 partly runs from Flash, it must be stopped while Core0 is writing. + * The simplest solution is for Core0 to ring Core1's doorbell where we wait out + * the flash operation, using spinlock. */ +static void __not_in_flash_func(Core1Doorbell_Handler)() { + uint32_t status = 0; + /* Prevent IRQs to fire, as their handlers might be in Flash */ + __ASM volatile ("mrs %0, primask \n cpsid i" : "=r" (status) :: "memory"); + /* Check if this is the "flash-in-use" doorbell */ + if (sio_hw->doorbell_in_set & FLASH_DOORBELL_MASK) + { + /* Clear doorbell */ + sio_hw->doorbell_in_clr = FLASH_DOORBELL_MASK; + /* Wait for Flash to be available, then release it immediately */ + while(!*FLASH_SPINLOCK); + *FLASH_SPINLOCK = 0x1; + /* Check if this is the "halt" doorbell */ + } else if (sio_hw->doorbell_in_set & HALT_DOORBELL_MASK) + { + /* Clear doorbell */ + sio_hw->doorbell_in_clr = HALT_DOORBELL_MASK; + while (1) { + __WFE(); + } + } + /* Restore IRQ status */ + __ASM volatile ("msr primask, %0" :: "r" (status) : "memory"); +} + +static void core1_entry(void) +{ + __TZ_set_STACKSEAL_S((uint32_t *)__get_MSP()); + /* Set up isolation boundaries between SPE and NSPE */ + sau_and_idau_cfg(); + + NVIC_SetVector(SIO_IRQ_BELL_IRQn, (uint32_t) Core1Doorbell_Handler); + /* Set it to highest priority */ + NVIC_SetPriority(SIO_IRQ_BELL_IRQn, 0x0); + NVIC_EnableIRQ(SIO_IRQ_BELL_IRQn); + __enable_irq(); + + NVIC_SetTargetState(SIO_IRQ_FIFO_NS_IRQn); + multicore_fifo_push_blocking(CORE1_S_READY); + + ns_agent_tz_main(NS_CODE_CORE1_START); +} + +static void boot_s_core(void) +{ + CORE1_RUNNING = 0x1; + multicore_launch_core1(core1_entry); + wait_for_core1_ready(); +} + +void tfm_hal_boot_ns_cpu(uintptr_t start_addr) +{ + boot_s_core(); + return; +} + +void tfm_hal_wait_for_ns_cpu_ready(void) +{ + uint32_t stage; + while (1) { + stage = multicore_ns_fifo_pop_blocking_inline(); + if (stage == CORE1_NS_READY) { + break; + } + } + return; +} + +void tfm_hal_get_secure_access_attr(const void *p, size_t s, + struct mem_attr_info_t *p_attr) +{ + /* Check static memory layout to get memory attributes */ + tfm_get_secure_mem_region_attr(p, s, p_attr); +#if TFM_ISOLATION_LEVEL >= 2 + p_attr->is_mpu_enabled = true; +#endif +} + +void tfm_hal_get_ns_access_attr(const void *p, size_t s, + struct mem_attr_info_t *p_attr) +{ + /* Check static memory layout to get memory attributes */ + tfm_get_ns_mem_region_attr(p, s, p_attr); +} diff --git a/platform/ext/target/rpi/rp2350/tfm_hal_platform.c b/platform/ext/target/rpi/rp2350/tfm_hal_platform.c new file mode 100644 index 000000000..01d9fc169 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_hal_platform.c @@ -0,0 +1,127 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_hal_device_header.h" +#include "tfm_peripherals_def.h" +#include "common_target_cfg.h" +#include "tfm_hal_platform.h" +#include "uart_stdout.h" +#include "region.h" +#include "region_defs.h" +#include "pico/bootrom.h" + +#include "hardware/structs/psm.h" +#ifdef TFM_MULTI_CORE_TOPOLOGY +#include "platform_multicore.h" +#include "hardware/structs/sio.h" +#endif + +#if defined(TFM_PARTITION_SLIH_TEST) || defined(TFM_PARTITION_FLIH_TEST) +#include "hardware/irq.h" +extern void tfm_plat_test_secure_timer_irq_handler(void); +#endif + +/* The section names come from the scatter file */ +REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base); +REGION_DECLARE(Image$$, ER_VENEER, $$Base); +REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit); +#ifdef BL2 +REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base); +#endif /* BL2 */ + +const struct memory_region_limits memory_regions = { + .non_secure_code_start = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + BL2_HEADER_SIZE, + + .non_secure_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base), + + .non_secure_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) + + NS_PARTITION_SIZE - 1, + + .veneer_base = + (uint32_t)®ION_NAME(Image$$, ER_VENEER, $$Base), + + .veneer_limit = + (uint32_t)®ION_NAME(Image$$, VENEER_ALIGN, $$Limit) - 1, + +#ifdef BL2 + .secondary_partition_base = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base), + + .secondary_partition_limit = + (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) + + SECONDARY_PARTITION_SIZE - 1, +#endif /* BL2 */ +}; + +extern __NO_RETURN void MemManage_Handler(void); +extern __NO_RETURN void BusFault_Handler(void); +extern __NO_RETURN void UsageFault_Handler(void); +extern __NO_RETURN void SecureFault_Handler(void); + +enum tfm_hal_status_t tfm_hal_platform_init(void) +{ + NVIC_SetVector(MemoryManagement_IRQn, (uint32_t) MemManage_Handler); + NVIC_SetVector(BusFault_IRQn, (uint32_t) BusFault_Handler); + NVIC_SetVector(UsageFault_IRQn, (uint32_t) UsageFault_Handler); + NVIC_SetVector(SecureFault_IRQn, (uint32_t) SecureFault_Handler); + + stdio_init(); + +#if defined(TFM_PARTITION_SLIH_TEST) || defined(TFM_PARTITION_FLIH_TEST) + irq_set_exclusive_handler(TFM_TIMER0_IRQ, tfm_plat_test_secure_timer_irq_handler); +#endif + +#ifdef PSA_API_TEST_IPC + irq_set_exclusive_handler(FF_TEST_UART_IRQ, FF_TEST_UART_IRQ_Handler); +#endif + + /* Reset everything apart from ROSC and XOSC */ + hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS)); + + __enable_irq(); + return TFM_HAL_SUCCESS; +} + +uint32_t tfm_hal_get_ns_VTOR(void) +{ + return memory_regions.non_secure_code_start; +} + +uint32_t tfm_hal_get_ns_MSP(void) +{ + return *((uint32_t *)memory_regions.non_secure_code_start); +} + +uint32_t tfm_hal_get_ns_entry_point(void) +{ + return *((uint32_t *)(memory_regions.non_secure_code_start + 4)); +} + +void tfm_hal_system_reset(void) +{ + __disable_irq(); + + NVIC_SystemReset(); +} + +void tfm_hal_system_halt(void) +{ + __disable_irq(); + +#ifdef TFM_MULTI_CORE_TOPOLOGY + /* Signal Core1 to wait for flash */ + sio_hw->doorbell_out_set = HALT_DOORBELL_MASK; +#endif + + while (1) { + __WFE(); + } + +} diff --git a/platform/ext/target/rpi/rp2350/tfm_peripherals_def.c b/platform/ext/target/rpi/rp2350/tfm_peripherals_def.c new file mode 100644 index 000000000..8a32c4369 --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_peripherals_def.c @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#include "tfm_peripherals_def.h" +#include "array.h" +#include "tfm_hal_device_header.h" + +/* Allowed named MMIO of this platform */ +const uintptr_t partition_named_mmio_list[] = { + (uintptr_t)TFM_PERIPHERAL_TIMER0, + (uintptr_t)TFM_PERIPHERAL_STD_UART, +#ifdef PSA_API_TEST_IPC + (uintptr_t)FF_TEST_UART_REGION, + (uintptr_t)FF_TEST_WATCHDOG_REGION, + (uintptr_t)FF_TEST_NVMEM_REGION, + (uintptr_t)FF_TEST_SERVER_PARTITION_MMIO, + (uintptr_t)FF_TEST_DRIVER_PARTITION_MMIO, +#endif +}; + +void get_partition_named_mmio_list(const uintptr_t** list, size_t* length) { + *list = partition_named_mmio_list; + *length = ARRAY_SIZE(partition_named_mmio_list); +} diff --git a/platform/ext/target/rpi/rp2350/tfm_peripherals_def.h b/platform/ext/target/rpi/rp2350/tfm_peripherals_def.h new file mode 100644 index 000000000..a758cdb5c --- /dev/null +++ b/platform/ext/target/rpi/rp2350/tfm_peripherals_def.h @@ -0,0 +1,54 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors + * + */ + +#ifndef __TFM_PERIPHERALS_DEF_H__ +#define __TFM_PERIPHERALS_DEF_H__ + +#include "hardware/irq.h" +#include "common_target_cfg.h" +#include "tfm_hal_device_header.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Quantized default IRQ priority, the value is: + * (Number of configurable priority) / 2: (1UL << __NVIC_PRIO_BITS) / 4 + */ + +#define DEFAULT_IRQ_PRIORITY (1UL << (__NVIC_PRIO_BITS - 2)) + +#define TFM_TIMER0_IRQ (TIMER0_IRQ_0_IRQn) +#define MAILBOX_IRQ SIO_IRQ_FIFO_NS_IRQn + +#define FF_TEST_UART_IRQ (UART0_IRQ) +extern void FF_TEST_UART_IRQ_Handler(void); + +extern struct platform_data_t tfm_peripheral_std_uart; +extern struct platform_data_t tfm_peripheral_timer0; + +#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart) +#define TFM_PERIPHERAL_TIMER0 (&tfm_peripheral_timer0) + +#ifdef PSA_API_TEST_IPC +extern struct platform_data_t tfm_peripheral_FF_TEST_UART_REGION; +extern struct platform_data_t tfm_peripheral_FF_TEST_WATCHDOG_REGION; +extern struct platform_data_t tfm_peripheral_FF_TEST_NVMEM_REGION; +extern struct platform_data_t tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO; +extern struct platform_data_t tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO; +#define FF_TEST_UART_REGION (&tfm_peripheral_FF_TEST_UART_REGION) +#define FF_TEST_WATCHDOG_REGION (&tfm_peripheral_FF_TEST_WATCHDOG_REGION) +#define FF_TEST_NVMEM_REGION (&tfm_peripheral_FF_TEST_NVMEM_REGION) +#define FF_TEST_SERVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_SERVER_PARTITION_MMIO) +#define FF_TEST_DRIVER_PARTITION_MMIO (&tfm_peripheral_FF_TEST_DRIVER_PARTITION_MMIO) +#endif /* PSA_API_TEST_IPC */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TFM_PERIPHERALS_DEF_H__ */ diff --git a/platform/ext/target/stm/b_u585i_iot02a/config.cmake b/platform/ext/target/stm/b_u585i_iot02a/config.cmake index 04cbb0797..301bad25f 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/config.cmake +++ b/platform/ext/target/stm/b_u585i_iot02a/config.cmake @@ -32,5 +32,5 @@ set(MCUBOOT_FIH_PROFILE LOW CACHE STRING "Fault injec set(CONFIG_TFM_USE_TRUSTZONE ON) set(TFM_MULTI_CORE_TOPOLOGY OFF) set(PLATFORM_HAS_FIRMWARE_UPDATE_SUPPORT ON) -set(STSAFEA ON CACHE BOOL "Activate ST SAFE SUPPORT") +set(STSAFEA OFF CACHE BOOL "Activate ST SAFE SUPPORT") set(MCUBOOT_DATA_SHARING ON) diff --git a/platform/ext/target/stm/b_u585i_iot02a/config_tfm_target.h b/platform/ext/target/stm/b_u585i_iot02a/config_tfm_target.h index 665653776..6a5535cc1 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/config_tfm_target.h +++ b/platform/ext/target/stm/b_u585i_iot02a/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #define ITS_NUM_ASSETS 32 #endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h index 0974e0616..76de906bd 100644 --- a/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h +++ b/platform/ext/target/stm/b_u585i_iot02a/partition/flash_layout.h @@ -283,4 +283,6 @@ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_BASE (0x3003fc00) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/stm/common/build_stm/ReBuildTFM_NS.bat b/platform/ext/target/stm/common/build_stm/ReBuildTFM_NS.bat new file mode 100644 index 000000000..fc868238b --- /dev/null +++ b/platform/ext/target/stm/common/build_stm/ReBuildTFM_NS.bat @@ -0,0 +1,19 @@ +set WORK_DIR=%CD% +set BUILD_DIR=%WORK_DIR%\iar +set BUILD_TFM=build_ns + +cd %BUILD_DIR% +del /s/q %BUILD_TFM% + +set WORK_DIR=%WORK_DIR:\=/% +set BUILD_S=%WORK_DIR%/iar/build_s + +set TFM_SOURCE=%WORK_DIR%/trusted-firmware-m +set QCBOR=-DQCBOR_PATH=%WORK_DIR%/QCBOR +set TFMTEST_SRC=%WORK_DIR%/tf-m-tests/tests_reg + +set TOOL_CHAIN=-DTFM_TOOLCHAIN_FILE=%BUILD_S%/api_ns/cmake/toolchain_ns_IARARM.cmake + +cmake -S %TFM_SOURCE% %TFMTEST_SRC% -B %BUILD_TFM% -GNinja -DCONFIG_SPE_PATH=%BUILD_S%/api_ns %TOOL_CHAIN% +ninja -C %BUILD_TFM% -j12 +pause \ No newline at end of file diff --git a/platform/ext/target/stm/common/build_stm/ReBuildTFM_S.bat b/platform/ext/target/stm/common/build_stm/ReBuildTFM_S.bat new file mode 100644 index 000000000..0bc96622b --- /dev/null +++ b/platform/ext/target/stm/common/build_stm/ReBuildTFM_S.bat @@ -0,0 +1,32 @@ +set WORK_DIR=%CD% +set BUILD_DIR=%WORK_DIR%\iar +set BUILD_TFM=build_s +mkdir %BUILD_DIR% +cd %BUILD_DIR% +del /S/Q %BUILD_TFM% + +set WORK_DIR=%WORK_DIR:\=/% +set TFM_SOURCE=%WORK_DIR%/trusted-firmware-m +set TOOL_CHAIN=-DTFM_TOOLCHAIN_FILE=%TFM_SOURCE%/toolchain_IARARM.cmake +::platform +set TARGET=-DTFM_PLATFORM=stm/b_u585i_iot02a +::set TARGET=-DTFM_PLATFORM=stm/stm32h573i_dk +::set TARGET=-DTFM_PLATFORM=stm/stm32l562e_dk +::profile +set PROFILE=-DTFM_PROFILE=profile_medium +::library +set MCUBOOT_SRC=-DMCUBOOT_PATH=%WORK_DIR%/mcuboot-src +set MBEDCRYPTO_SRC=-DMBEDCRYPTO_PATH=%WORK_DIR%/mbedtls +set TFMTEST_SRC=%WORK_DIR%/tf-m-tests/tests_reg/spe +set QCBOR=-DQCBOR_PATH=%WORK_DIR%/QCBOR +set BUILD_TYPE=RelWithDebInfo +::set BUILD_TYPE=Debug +set MBED_BUILD_TYPE=RelWithDebInfo +::set MBED_BUILD_TYPE=Debug +set BUILD_NS_TESTS=-DTEST_NS=ON +set BUILD_S_TESTS=-DTEST_S=ON + + +cmake -S %TFMTEST_SRC% -B %BUILD_TFM% -GNinja %TARGET% %TOOL_CHAIN% -DCONFIG_TFM_SOURCE_PATH=%TFM_SOURCE% -DCMAKE_BUILD_TYPE=%BUILD_TYPE% %PROFILE% -DTFM_PSA_API=OFF -DTFM_ISOLATION_LEVEL=2 -DTEST_S=OFF -DTEST_NS=OFF -DTEST_S_CRYPTO=OFF -DTEST_NS_CRYPTO=OFF +ninja -C %BUILD_TFM% -j12 install +pause \ No newline at end of file diff --git a/platform/ext/target/stm/common/build_stm/image.png b/platform/ext/target/stm/common/build_stm/image.png new file mode 100644 index 000000000..cfdb585ab Binary files /dev/null and b/platform/ext/target/stm/common/build_stm/image.png differ diff --git a/platform/ext/target/stm/common/build_stm/readme.txt b/platform/ext/target/stm/common/build_stm/readme.txt new file mode 100644 index 000000000..9bd2d161b --- /dev/null +++ b/platform/ext/target/stm/common/build_stm/readme.txt @@ -0,0 +1,33 @@ +STM_PLATFORM +^^^^^^^^^^^^ + +Configuration and Build +""""""""""""""""""""""" + +GNUARM/ARMCLANG/IARARM compilation is available for this target. +and build the selected configuration as follow. + +The build configuration for TF-M is provided to the build system using command +line arguments. Required arguments are noted below. + +The following instructions build multi-core TF-M with regression test suites +in Isolation Level 1. + + +Getting_started +""""""""""""""" + +1- Should install TF-M repo and all library in the same directory (trusted-firmware-m, mbedtls, mcuboot, QCBOR, tf-m-tests). +2- Configure the script as you nedd for your project. +3- Launch the script ReBuildTFM_S.bat and ReBuildTFM_NS.bat +4- In iar/build_s/api_ns laucn the scripts (postbuild.sh, regressions.sh, TFM_UPDATE.sh). +5- Reset the board. + +Example +""""""" +There's image example to the environment what should you have to use these scripts + +------------- + +*Copyright (c) 2021, STMicroelectronics. All rights reserved.* +*SPDX-License-Identifier: BSD-3-Clause* diff --git a/platform/ext/target/stm/common/scripts/TFM_UPDATE.sh b/platform/ext/target/stm/common/scripts/TFM_UPDATE.sh index 2513b7594..5577c85af 100644 --- a/platform/ext/target/stm/common/scripts/TFM_UPDATE.sh +++ b/platform/ext/target/stm/common/scripts/TFM_UPDATE.sh @@ -19,8 +19,11 @@ sn_option="sn=$1" fi # Absolute path to this script SCRIPT=$(readlink -f $0) -# Absolute path this script SCRIPTPATH=`dirname $SCRIPT` +#copy tfm_ns_signed to the true path +cp $SCRIPTPATH/../../build_ns/bin/tfm_ns_signed.bin image_signing/scripts + +# Absolute path this script BINPATH_SPE="$SCRIPTPATH/bin" BINPATH_BL2="$SCRIPTPATH/bin" BINPATH_NSPE="$SCRIPTPATH/image_signing/scripts" @@ -60,7 +63,7 @@ if [ "$slot2" == $l5 ]; then external_loader="-el $cubedir/ExternalLoader/MX25LM51245G_STM32L562E-DK.stldr" fi connect_no_reset="-c port=SWD "$sn_option" mode=UR $external_loader" -connect="-c port=SWD "$sn_option" mode=UR --hardRst $external_loader" +connect="-c port=SWD "$sn_option" mode=UR $external_loader" echo "Write TFM_Appli Secure" # part ot be updated according to flash_layout.h diff --git a/platform/ext/target/stm/common/scripts/regression.sh b/platform/ext/target/stm/common/scripts/regression.sh index 35e0b84fe..fc7ee06a4 100644 --- a/platform/ext/target/stm/common/scripts/regression.sh +++ b/platform/ext/target/stm/common/scripts/regression.sh @@ -21,7 +21,7 @@ PATH="/C/Program Files/STMicroelectronics/STM32Cube/STM32CubeProgrammer/bin/":$P stm32programmercli="STM32_Programmer_CLI" # remove write protection secbootadd0=0x180030 -connect="-c port=SWD "$sn_option" mode=UR --hardRst" +connect="-c port=SWD "$sn_option" mode=UR" connect_no_reset="-c port=SWD "$sn_option" mode=HotPlug" rdp_0="-ob RDP=0xAA TZEN=1" remove_bank1_protect="-ob SECWM1_PSTRT=127 SECWM1_PEND=0 WRP1A_PSTRT=127 WRP1A_PEND=0 WRP1B_PSTRT=127 WRP1B_PEND=0" diff --git a/platform/ext/target/stm/common/stm32l5xx/bl2/tfm_low_level_security.c b/platform/ext/target/stm/common/stm32l5xx/bl2/tfm_low_level_security.c index 0d04540b5..6ad256812 100644 --- a/platform/ext/target/stm/common/stm32l5xx/bl2/tfm_low_level_security.c +++ b/platform/ext/target/stm/common/stm32l5xx/bl2/tfm_low_level_security.c @@ -104,7 +104,7 @@ __attribute__((section(".BL2_NoHdp_Code"))) void TFM_LL_SECU_UpdateRunTimeProtections(void) { /* Write Protect SRAM2 */ - apply_wrp_sram2(BOOT_TFM_SHARED_DATA_BASE, BOOT_TFM_SHARED_DATA_SIZE); + apply_wrp_sram2(SHARED_BOOT_MEASUREMENT_BASE, SHARED_BOOT_MEASUREMENT_SIZE); /* Enable HDP protection to hide sensible boot material */ enable_hdp_protection(); @@ -755,8 +755,8 @@ static void lock_bl2_shared_area(void) /* assumption shared area in SRAM2 in the last 8 Kbytes super block */ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ if ( - (BOOT_TFM_SHARED_DATA_BASE >= S_RAM_ALIAS(_SRAM2_TOP - GTZC_MPCBB_SUPERBLOCK_SIZE)) - && (BOOT_TFM_SHARED_DATA_SIZE <= GTZC_MPCBB_SUPERBLOCK_SIZE)) + (SHARED_BOOT_MEASUREMENT_BASE >= S_RAM_ALIAS(_SRAM2_TOP - GTZC_MPCBB_SUPERBLOCK_SIZE)) + && (SHARED_BOOT_MEASUREMENT_SIZE <= GTZC_MPCBB_SUPERBLOCK_SIZE)) { __HAL_RCC_GTZC_CLK_ENABLE(); diff --git a/platform/ext/target/stm/common/stm32u5xx/bl2/low_level_security.c b/platform/ext/target/stm/common/stm32u5xx/bl2/low_level_security.c index e17733332..7dbd7321a 100644 --- a/platform/ext/target/stm/common/stm32u5xx/bl2/low_level_security.c +++ b/platform/ext/target/stm/common/stm32u5xx/bl2/low_level_security.c @@ -552,7 +552,7 @@ __attribute__((section(".BL2_NoHdp_Code"))) void LL_SECU_UpdateRunTimeProtections(void) { /* Write Protect SRAM2 */ - apply_wrp_sram2(BOOT_TFM_SHARED_DATA_BASE, BOOT_TFM_SHARED_DATA_SIZE); + apply_wrp_sram2(SHARED_BOOT_MEASUREMENT_BASE, SHARED_BOOT_MEASUREMENT_SIZE); /* Enable HDP protection to hide sensible boot material */ enable_hdp_protection(); @@ -1584,8 +1584,8 @@ static void lock_bl2_shared_area(void) /* assumption shared area in SRAM2 in the last 8 Kbytes super block */ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ if ( - (BOOT_TFM_SHARED_DATA_BASE >= S_RAM_ALIAS(_SRAM2_TOP - GTZC_MPCBB_SUPERBLOCK_SIZE)) - && (BOOT_TFM_SHARED_DATA_SIZE <= GTZC_MPCBB_SUPERBLOCK_SIZE)) + (SHARED_BOOT_MEASUREMENT_BASE >= S_RAM_ALIAS(_SRAM2_TOP - GTZC_MPCBB_SUPERBLOCK_SIZE)) + && (SHARED_BOOT_MEASUREMENT_SIZE <= GTZC_MPCBB_SUPERBLOCK_SIZE)) { __HAL_RCC_GTZC1_CLK_ENABLE(); HAL_GTZC_MPCBB_LockConfig(S_RAM_ALIAS(_SRAM2_TOP - GTZC_MPCBB_SUPERBLOCK_SIZE), diff --git a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c index c427aaf57..fe9a01944 100644 --- a/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c +++ b/platform/ext/target/stm/common/stm32u5xx/hal/Src/stm32u5xx_hal_dma_ex.c @@ -535,7 +535,11 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, DMA_NodeTypeDef *const pNode); static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, DMA_NodeTypeDef const *const pNode); +#if (__GNUC__ == 11) || (__GNUC__ == 12) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#endif DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3, DMA_NodeTypeDef const *const pNode4); @@ -4074,7 +4078,11 @@ static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, * @param pNode4 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 4 registers configurations. * @retval Return 0 when nodes addresses are compatible, 1 otherwise. */ +#if (__GNUC__ == 11) || (__GNUC__ == 12) +static __attribute__((noinline)) uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#else static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, +#endif DMA_NodeTypeDef const *const pNode2, DMA_NodeTypeDef const *const pNode3, DMA_NodeTypeDef const *const pNode4) diff --git a/platform/ext/target/stm/nucleo_l552ze_q/config_tfm_target.h b/platform/ext/target/stm/nucleo_l552ze_q/config_tfm_target.h index 599db967d..f34850c96 100644 --- a/platform/ext/target/stm/nucleo_l552ze_q/config_tfm_target.h +++ b/platform/ext/target/stm/nucleo_l552ze_q/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,4 +11,7 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/stm/nucleo_l552ze_q/partition/flash_layout.h b/platform/ext/target/stm/nucleo_l552ze_q/partition/flash_layout.h index bc4c87853..634f42b37 100644 --- a/platform/ext/target/stm/nucleo_l552ze_q/partition/flash_layout.h +++ b/platform/ext/target/stm/nucleo_l552ze_q/partition/flash_layout.h @@ -211,5 +211,7 @@ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_BASE (0x3003fc00) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE #endif /* __FLASH_LAYOUT_H__ */ diff --git a/platform/ext/target/stm/stm32h573i_dk/config.cmake b/platform/ext/target/stm/stm32h573i_dk/config.cmake index d6176fa8f..87469b62f 100644 --- a/platform/ext/target/stm/stm32h573i_dk/config.cmake +++ b/platform/ext/target/stm/stm32h573i_dk/config.cmake @@ -11,7 +11,7 @@ set(MCUBOOT_IMAGE_NUMBER 2 CACHE STRING "Whether to set(BL2_HEADER_SIZE 0x400 CACHE STRING "Header size") set(BL2_TRAILER_SIZE 0x2000 CACHE STRING "Trailer size") set(MCUBOOT_ALIGN_VAL 16 CACHE STRING "Align option to build image with imgtool") -set(MCUBOOT_UPGRADE_STRATEGY "SWAP_USING_SCRATCH" CACHE STRING "Upgrade strategy for images") +set(MCUBOOT_UPGRADE_STRATEGY "OVERWRITE_ONLY" CACHE STRING "Upgrade strategy for images") set(TFM_PARTITION_FIRMWARE_UPDATE OFF CACHE BOOL "Enable firmware update partition") set(TFM_PARTITION_PLATFORM ON CACHE BOOL "Enable platform partition") set(MCUBOOT_DATA_SHARING ON CACHE BOOL "Enable Data Sharing") diff --git a/platform/ext/target/stm/stm32h573i_dk/config_tfm_target.h b/platform/ext/target/stm/stm32h573i_dk/config_tfm_target.h index f90984a08..3ce4d7d7b 100644 --- a/platform/ext/target/stm/stm32h573i_dk/config_tfm_target.h +++ b/platform/ext/target/stm/stm32h573i_dk/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,4 +12,7 @@ #undef CRYPTO_NV_SEED #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/stm/stm32h573i_dk/include/flash_layout.h b/platform/ext/target/stm/stm32h573i_dk/include/flash_layout.h index e33d40213..a9d972337 100644 --- a/platform/ext/target/stm/stm32h573i_dk/include/flash_layout.h +++ b/platform/ext/target/stm/stm32h573i_dk/include/flash_layout.h @@ -57,7 +57,11 @@ /* Flash layout configuration : begin */ #define MCUBOOT_OVERWRITE_ONLY /* Defined: the FW installation uses ovewrite method. - UnDefined: The FW installation uses swap mode. */ + UnDefined: The FW installation uses whatever mode + is configured through the MCUBOOT_UPGRADE_STRATEGY + config item in config.cmake. FixMe: MCUboot should + be configured in a single place, i.e. config.cmake + to avoid clashes */ /*#define MCUBOOT_PRIMARY_ONLY*/ /* Defined: No secondary (download) slot(s), only primary slot(s) for each image. @@ -245,7 +249,7 @@ /* BL2 flash areas */ #define FLASH_AREA_BEGIN_OFFSET (FLASH_ITS_AREA_OFFSET + FLASH_ITS_AREA_SIZE) -#define FLASH_AREAS_DEVICE_ID (FLASH_DEVICE_ID - FLASH_DEVICE_ID) +#define FLASH_AREAS_DEVICE_ID (FLASH_DEVICE_ID - FLASH_DEVICE_ID) /* Secure data image primary slot */ #if defined (FLASH_AREA_4_ID) @@ -503,6 +507,8 @@ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_BASE (0x3004fc00) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE /* OBK */ #define OBK_HDPL0_OFFSET (0x00U) /* First OBkey Hdpl 0 */ diff --git a/platform/ext/target/stm/stm32l562e_dk/config_tfm_target.h b/platform/ext/target/stm/stm32l562e_dk/config_tfm_target.h index 599db967d..f34850c96 100644 --- a/platform/ext/target/stm/stm32l562e_dk/config_tfm_target.h +++ b/platform/ext/target/stm/stm32l562e_dk/config_tfm_target.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,4 +11,7 @@ /* Use stored NV seed to provide entropy */ #define CRYPTO_NV_SEED 0 +/* Use external RNG to provide entropy */ +#define CRYPTO_EXT_RNG 1 + #endif /* __CONFIG_TFM_TARGET_H__ */ diff --git a/platform/ext/target/stm/stm32l562e_dk/partition/flash_layout.h b/platform/ext/target/stm/stm32l562e_dk/partition/flash_layout.h index a072172c5..63ae11684 100644 --- a/platform/ext/target/stm/stm32l562e_dk/partition/flash_layout.h +++ b/platform/ext/target/stm/stm32l562e_dk/partition/flash_layout.h @@ -281,6 +281,8 @@ /* This area in SRAM 2 is updated BL2 and can be lock to avoid any changes */ #define BOOT_TFM_SHARED_DATA_SIZE (0x400) #define BOOT_TFM_SHARED_DATA_BASE (0x3003fc00) +#define SHARED_BOOT_MEASUREMENT_BASE BOOT_TFM_SHARED_DATA_BASE +#define SHARED_BOOT_MEASUREMENT_SIZE BOOT_TFM_SHARED_DATA_SIZE #if defined(EXTERNAL_FLASH) #define FLASH_DRIVER_LIST {&TFM_Driver_OSPI_FLASH0, &TFM_Driver_FLASH0} diff --git a/platform/include/tfm_hal_its_encryption.h b/platform/include/tfm_hal_its_encryption.h index 02293826b..4522e631a 100644 --- a/platform/include/tfm_hal_its_encryption.h +++ b/platform/include/tfm_hal_its_encryption.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -25,7 +25,7 @@ struct tfm_hal_its_auth_crypt_ctx { uint8_t *deriv_label; /* The derivation label for AEAD */ size_t deriv_label_size; /* Size of the deriv_label in bytes */ uint8_t *aad; /* The additional authenticated data for AEAD */ - size_t add_size; /* Size of the add in bytes */ + size_t aad_size; /* Size of the aad in bytes */ uint8_t *nonce; /* The nonce for AEAD */ size_t nonce_size; /* Size of the nonce in bytes */ }; diff --git a/platform/include/tfm_plat_provisioning.h b/platform/include/tfm_plat_provisioning.h index 2f3b16972..237095230 100644 --- a/platform/include/tfm_plat_provisioning.h +++ b/platform/include/tfm_plat_provisioning.h @@ -9,6 +9,7 @@ #define __TFM_PLAT_PROVISIONING_H__ #include "tfm_plat_defs.h" +#include #ifdef __cplusplus extern "C" { @@ -26,14 +27,13 @@ extern "C" { void tfm_plat_provisioning_check_for_dummy_keys(void); /** - * \brief Check if a provisioning operation is - * required. + * \brief Check if a provisioning operation is required. * - * \retval 1 A provisioning operation is required. - * \retval 0 A provisioning operation is not - * required. + * \param[out] provisioning_required Whether or not provisioning is required. + * + * \return TFM_PLAT_ERR_SUCCESS on success, non-zero on error. */ -int tfm_plat_provisioning_is_required(void); +enum tfm_plat_err_t tfm_plat_provisioning_is_required(bool *provisioning_required); /** * \brief Performs a provisioning operation. diff --git a/secure_fw/partitions/crypto/CMakeLists.txt b/secure_fw/partitions/crypto/CMakeLists.txt index 1ee4d1e08..e4a8d5702 100644 --- a/secure_fw/partitions/crypto/CMakeLists.txt +++ b/secure_fw/partitions/crypto/CMakeLists.txt @@ -7,30 +7,41 @@ ############################### PSA CRYPTO CONFIG ############################## # Make sure these are available even if the TFM_PARTITION_CRYPTO is not defined +add_library(psa_crypto_config INTERFACE) -# This defines the configuration files for the users of the client interface -set(TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH ${TFM_MBEDCRYPTO_CONFIG_PATH}) -cmake_path(REMOVE_EXTENSION TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH) -cmake_path(APPEND_STRING TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH "_client.h") -add_library(psa_crypto_config INTERFACE) -target_compile_definitions(psa_crypto_config - INTERFACE - MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${TFM_MBEDCRYPTO_PSA_CRYPTO_CONFIG_PATH}" - MBEDTLS_CONFIG_FILE="${TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH}" -) # The following is required for tfm_plat_crypto_nv_seed.h target_include_directories(psa_crypto_config INTERFACE $ ) -# This defines the configuration files for the users of the library directly -add_library(psa_crypto_library_config INTERFACE) -target_compile_definitions(psa_crypto_library_config + +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + #This defines the configuration files for the users of the client interface + set(TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH ${TFM_MBEDCRYPTO_CONFIG_PATH}) + cmake_path(REMOVE_EXTENSION TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH) + cmake_path(APPEND_STRING TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH "_client.h") + + target_compile_definitions(psa_crypto_config INTERFACE MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${TFM_MBEDCRYPTO_PSA_CRYPTO_CONFIG_PATH}" - MBEDTLS_CONFIG_FILE="${TFM_MBEDCRYPTO_CONFIG_PATH}" -) + MBEDTLS_CONFIG_FILE="${TFM_MBEDCRYPTO_CONFIG_CLIENT_PATH}" + ) +endif() + +# This defines the configuration files for the users of the library directly +add_library(psa_crypto_library_config INTERFACE) +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_compile_definitions(psa_crypto_library_config + INTERFACE + MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${TFM_MBEDCRYPTO_PSA_CRYPTO_CONFIG_PATH}" + MBEDTLS_CONFIG_FILE="${TFM_MBEDCRYPTO_CONFIG_PATH}" + ) +endif() if (NOT TFM_PARTITION_CRYPTO) return() @@ -57,6 +68,7 @@ target_sources(tfm_psa_rot_partition_crypto crypto_key_management.c crypto_rng.c crypto_library.c + crypto_pake.c $<$:psa_driver_api/tfm_builtin_key_loader.c> ) @@ -70,13 +82,24 @@ target_sources(tfm_partitions ${CMAKE_BINARY_DIR}/generated/secure_fw/partitions/crypto/auto_generated/load_info_tfm_crypto.c ) + # Set include directory target_include_directories(tfm_psa_rot_partition_crypto PRIVATE - $ + #$ + ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_BINARY_DIR}/generated/secure_fw/partitions/crypto - $ ) + +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_include_directories(tfm_psa_rot_partition_crypto + PRIVATE + $ + ) +endif() + target_include_directories(tfm_partitions INTERFACE ${CMAKE_BINARY_DIR}/generated/secure_fw/partitions/crypto @@ -91,6 +114,9 @@ target_link_libraries(tfm_psa_rot_partition_crypto tfm_sp_log ) target_compile_definitions(tfm_psa_rot_partition_crypto + PUBLIC + MBEDTLS_PSA_CRYPTO_DRIVERS + $<$:MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS PSA_CRYPTO_DRIVER_TFM_BUILTIN_KEY> PRIVATE $<$:CRYPTO_HW_ACCELERATOR_CC312> ) @@ -107,12 +133,25 @@ target_compile_definitions(tfm_config TFM_PARTITION_CRYPTO ) +target_link_libraries(tfm_config + INTERFACE + psa_crypto_config +) + ############################### MBEDCRYPTO ##################################### add_library(crypto_service_mbedcrypto_config INTERFACE) +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_compile_definitions(crypto_service_mbedcrypto_config + INTERFACE + MBEDTLS_CONFIG_FILE="${TFM_MBEDCRYPTO_CONFIG_PATH}" + $<$:MBEDTLS_USER_CONFIG_FILE="${TFM_MBEDCRYPTO_PLATFORM_EXTRA_CONFIG_PATH}"> + ) +endif() target_compile_definitions(crypto_service_mbedcrypto_config INTERFACE - $<$:MBEDTLS_USER_CONFIG_FILE="${TFM_MBEDCRYPTO_PLATFORM_EXTRA_CONFIG_PATH}"> # Workaround for https://github.com/ARMmbed/mbedtls/issues/1077 $<$,$>:MULADDC_CANNOT_USE_R7> $<$:PLATFORM_DEFAULT_NV_SEED> @@ -139,20 +178,8 @@ set(GEN_FILES OFF) # Set the prefix to be used by mbedTLS targets set(MBEDTLS_TARGET_PREFIX crypto_service_) -# Check if the p256m driver is enabled in the config file, as that will require a -# dedicated target to be linked in. Note that 0 means SUCCESS here, 1 means FAILURE -set(MBEDTLS_P256M_NOT_FOUND 1) -execute_process(COMMAND - ${Python3_EXECUTABLE} - ${MBEDCRYPTO_PATH}/scripts/config.py -f "${TFM_MBEDCRYPTO_CONFIG_PATH}" get MBEDTLS_PSA_P256M_DRIVER_ENABLED - RESULT_VARIABLE MBEDTLS_P256M_NOT_FOUND) - -if (${MBEDTLS_P256M_NOT_FOUND} EQUAL 0) - message(STATUS "[Crypto service] Using P256M software driver in PSA Crypto backend") - set(MBEDTLS_P256M_ENABLED true) -else() - set(MBEDTLS_P256M_ENABLED false) -endif() +# We use hardware acceleration or ocrypto so disable the P256M module by default +set(MBEDTLS_P256M_ENABLED false) # If the project is configured with CMAKE_BUILD_TYPE="Debug", the value of # MBEDCRYPTO_BUILD_TYPE will be set "RelWithDebInfo" to optimize the space @@ -168,14 +195,23 @@ if(NOT TARGET ${MBEDTLS_TARGET_PREFIX}mbedcrypto) Hint: The command might be `cd ${MBEDCRYPTO_PATH} && git apply ${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/*.patch`") endif() -target_include_directories(${MBEDTLS_TARGET_PREFIX}mbedcrypto - PUBLIC +target_include_directories(psa_crypto_library_config + INTERFACE ${CMAKE_CURRENT_SOURCE_DIR} ${CMAKE_CURRENT_SOURCE_DIR}/psa_driver_api - # The following is required for psa/error.h - $ ) +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +else() + target_include_directories(${MBEDTLS_TARGET_PREFIX}mbedcrypto + PUBLIC + # The following is required for psa/error.h + $ + ) +endif() + + # Fix platform_s and crypto_service_mbedcrypto libraries cyclic linking set_target_properties(${MBEDTLS_TARGET_PREFIX}mbedcrypto PROPERTIES LINK_INTERFACE_MULTIPLICITY 3) diff --git a/secure_fw/partitions/crypto/Kconfig.comp b/secure_fw/partitions/crypto/Kconfig.comp index 4ea7d66e7..0d07de65f 100644 --- a/secure_fw/partitions/crypto/Kconfig.comp +++ b/secure_fw/partitions/crypto/Kconfig.comp @@ -8,6 +8,16 @@ menu "Crypto component options" depends on TFM_PARTITION_CRYPTO +config CRYPTO_LIBRARY_ABI_COMPAT + bool "The interfaces towards PSA Crypto in the service and towards the service are the same" + default n + help + The crypto service acts as a layer between a client and towards a library that provides + PSA Crypto APIs through the implementation of a PSA Crypto core component. With this option + set, the crypto service assumes that the ABI of the internal interface is the same as the + client interface. This is not the default case when using the headers provided by the Mbed + TLS reference implementation + config CRYPTO_STACK_SIZE hex "Stack size" default 0x1B00 @@ -71,6 +81,10 @@ config CRYPTO_KEY_DERIVATION_MODULE_ENABLED bool "PSA Crypto key derivation module" default y +config CRYPTO_PAKE_MODULE_ENABLED + bool "PSA Crypto PAKE module" + default y + config CRYPTO_NV_SEED bool default n if CRYPTO_HW_ACCELERATOR diff --git a/secure_fw/partitions/crypto/config_crypto_check.h b/secure_fw/partitions/crypto/config_crypto_check.h index 9dbcd3458..d833cd939 100644 --- a/secure_fw/partitions/crypto/config_crypto_check.h +++ b/secure_fw/partitions/crypto/config_crypto_check.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,12 +11,12 @@ #include "config_tfm.h" /* Check invalid configs. */ -#if CRYPTO_NV_SEED && defined(CRYPTO_HW_ACCELERATOR) -#error "Invalid config: CRYPTO_NV_SEED AND CRYPTO_HW_ACCELERATOR!" +#if CRYPTO_NV_SEED && CRYPTO_EXT_RNG +// #error "Invalid config: CRYPTO_NV_SEED AND CRYPTO_EXT_RNG!" #endif -#if (!CRYPTO_NV_SEED) && (!defined(CRYPTO_HW_ACCELERATOR)) -#error "Invalid config: NOT CRYPTO_NV_SEED AND NOT CRYPTO_HW_ACCELERATOR!" +#if (!CRYPTO_NV_SEED) && (!CRYPTO_EXT_RNG) +#error "Invalid config: NOT CRYPTO_NV_SEED AND NOT CRYPTO_EXT_RNG!" #endif #endif /* __CONFIG_PARTITION_CRYPTO_H__ */ diff --git a/secure_fw/partitions/crypto/crypto_aead.c b/secure_fw/partitions/crypto/crypto_aead.c index 7681bb5ef..db57d1906 100644 --- a/secure_fw/partitions/crypto/crypto_aead.c +++ b/secure_fw/partitions/crypto/crypto_aead.c @@ -94,6 +94,9 @@ psa_status_t tfm_crypto_aead_interface(psa_invec in_vec[], if ((sid == TFM_CRYPTO_AEAD_ENCRYPT_SETUP_SID) || (sid == TFM_CRYPTO_AEAD_DECRYPT_SETUP_SID)) { p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; status = tfm_crypto_operation_alloc(TFM_CRYPTO_AEAD_OPERATION, out_vec[0].base, @@ -113,6 +116,9 @@ psa_status_t tfm_crypto_aead_interface(psa_invec in_vec[], * if lookup fails. */ p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; } } diff --git a/secure_fw/partitions/crypto/crypto_check_config.h b/secure_fw/partitions/crypto/crypto_check_config.h index 364912257..19d04b77b 100644 --- a/secure_fw/partitions/crypto/crypto_check_config.h +++ b/secure_fw/partitions/crypto/crypto_check_config.h @@ -118,4 +118,14 @@ #error "CRYPTO_KEY_DERIVATION_MODULE_ENABLED enabled, but not all prerequisites (missing key derivation algorithms)!" #endif +#if CRYPTO_PAKE_MODULE_ENABLED && \ + (!defined(PSA_WANT_ALG_JPAKE) && \ + !defined(PSA_WANT_ALG_SPAKE2P_HMAC) && \ + !defined(PSA_WANT_ALG_SPAKE2P_CMAC) && \ + !defined(PSA_WANT_ALG_SPAKE2P_MATTER) && \ + !defined(PSA_WANT_ALG_SRP_6) && \ + !defined(PSA_WANT_ALG_SRP_PASSWORD_HASH)) +#error "CRYPTO_PAKE_MODULE_ENABLED enabled, but not all prerequisites (missing PAKE algorithms)!" +#endif + #endif /* __CRYPTO_CHECK_CONFIG_H__ */ diff --git a/secure_fw/partitions/crypto/crypto_cipher.c b/secure_fw/partitions/crypto/crypto_cipher.c index 2af4fccd6..bca6d89c9 100644 --- a/secure_fw/partitions/crypto/crypto_cipher.c +++ b/secure_fw/partitions/crypto/crypto_cipher.c @@ -75,6 +75,9 @@ psa_status_t tfm_crypto_cipher_interface(psa_invec in_vec[], if ((sid == TFM_CRYPTO_CIPHER_ENCRYPT_SETUP_SID) || (sid == TFM_CRYPTO_CIPHER_DECRYPT_SETUP_SID)) { p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; status = tfm_crypto_operation_alloc(TFM_CRYPTO_CIPHER_OPERATION, out_vec[0].base, @@ -92,6 +95,9 @@ psa_status_t tfm_crypto_cipher_interface(psa_invec in_vec[], * override the original handle value in client, after lookup fails. */ p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; } } diff --git a/secure_fw/partitions/crypto/crypto_hash.c b/secure_fw/partitions/crypto/crypto_hash.c index d993fefea..e494c561a 100644 --- a/secure_fw/partitions/crypto/crypto_hash.c +++ b/secure_fw/partitions/crypto/crypto_hash.c @@ -64,6 +64,9 @@ psa_status_t tfm_crypto_hash_interface(psa_invec in_vec[], if (sid == TFM_CRYPTO_HASH_SETUP_SID) { p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; status = tfm_crypto_operation_alloc(TFM_CRYPTO_HASH_OPERATION, out_vec[0].base, @@ -82,6 +85,9 @@ psa_status_t tfm_crypto_hash_interface(psa_invec in_vec[], * override the original handle value in client, after lookup fails. */ p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; } } @@ -150,6 +156,10 @@ psa_status_t tfm_crypto_hash_interface(psa_invec in_vec[], { psa_hash_operation_t *target_operation = NULL; p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t)) || + (in_vec[1].base == NULL) || (in_vec[1].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = *((uint32_t *)in_vec[1].base); /* Allocate the target operation context in the secure world */ diff --git a/secure_fw/partitions/crypto/crypto_init.c b/secure_fw/partitions/crypto/crypto_init.c index 1854b8faf..cd77ef8ab 100644 --- a/secure_fw/partitions/crypto/crypto_init.c +++ b/secure_fw/partitions/crypto/crypto_init.c @@ -112,6 +112,11 @@ static psa_status_t tfm_crypto_get_scratch_owner(int32_t *id) static psa_status_t tfm_crypto_alloc_scratch(size_t requested_size, void **buf) { + /* Prevent ALIGN() from overflowing */ + if (requested_size > SIZE_MAX - (TFM_CRYPTO_IOVEC_ALIGNMENT - 1)) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + /* Ensure alloc_index remains aligned to the required iovec alignment */ requested_size = ALIGN(requested_size, TFM_CRYPTO_IOVEC_ALIGNMENT); @@ -234,6 +239,16 @@ static psa_status_t tfm_crypto_call_srv(const psa_msg_t *msg) psa_unmap_outvec(msg->handle, i, out_vec[i].len); } } + + /* + * Unmap from the second element because the first element is read when + * parsing the message, hence it is never mapped. + */ + for (i = 1; i < in_len; i++) { + if (in_vec[i].base != NULL) { + psa_unmap_invec(msg->handle, i); + } + } #else /* Write into the IPC framework outputs from the scratch */ for (i = 0; i < out_len; i++) { @@ -387,6 +402,8 @@ psa_status_t tfm_crypto_api_dispatcher(psa_invec in_vec[], &encoded_key); case TFM_CRYPTO_GROUP_ID_RANDOM: return tfm_crypto_random_interface(in_vec, out_vec); + case TFM_CRYPTO_GROUP_ID_PAKE: + return tfm_crypto_pake_interface(in_vec, out_vec, &encoded_key); default: LOG_ERRFMT("[ERR][Crypto] Unsupported request!\r\n"); return PSA_ERROR_NOT_SUPPORTED; diff --git a/secure_fw/partitions/crypto/crypto_key_derivation.c b/secure_fw/partitions/crypto/crypto_key_derivation.c index 2dc29ecb9..747d596a8 100644 --- a/secure_fw/partitions/crypto/crypto_key_derivation.c +++ b/secure_fw/partitions/crypto/crypto_key_derivation.c @@ -51,6 +51,11 @@ psa_status_t tfm_crypto_key_derivation_interface(psa_invec in_vec[], if (sid == TFM_CRYPTO_KEY_DERIVATION_SETUP_SID) { p_handle = out_vec[0].base; + + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(*p_handle))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } + *p_handle = iov->op_handle; status = tfm_crypto_operation_alloc(TFM_CRYPTO_KEY_DERIVATION_OPERATION, out_vec[0].base, @@ -80,6 +85,10 @@ psa_status_t tfm_crypto_key_derivation_interface(psa_invec in_vec[], { size_t *capacity = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len != sizeof(*capacity))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } + return psa_key_derivation_get_capacity(operation, capacity); } case TFM_CRYPTO_KEY_DERIVATION_SET_CAPACITY_SID: @@ -115,7 +124,14 @@ psa_status_t tfm_crypto_key_derivation_interface(psa_invec in_vec[], { psa_key_id_t *key_handle = out_vec[0].base; psa_key_attributes_t srv_key_attr; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(psa_key_id_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } + if ((in_vec[1].base == NULL) || + (in_vec[1].len != (sizeof(srv_key_attr) - TFM_CRYPTO_KEY_ATTR_OFFSET_CLIENT_SERVER))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } memcpy(&srv_key_attr, in_vec[1].base, in_vec[1].len); tfm_crypto_library_get_library_key_id_set_owner(encoded_key->owner, &srv_key_attr); @@ -128,7 +144,11 @@ psa_status_t tfm_crypto_key_derivation_interface(psa_invec in_vec[], case TFM_CRYPTO_KEY_DERIVATION_ABORT_SID: { p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(iov->op_handle))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; + if (status != PSA_SUCCESS) { /* * If lookup() failed to find out a valid operation, it is not diff --git a/secure_fw/partitions/crypto/crypto_key_management.c b/secure_fw/partitions/crypto/crypto_key_management.c index d9bfafc15..ed733e99d 100644 --- a/secure_fw/partitions/crypto/crypto_key_management.c +++ b/secure_fw/partitions/crypto/crypto_key_management.c @@ -39,6 +39,10 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], case TFM_CRYPTO_IMPORT_KEY_SID: case TFM_CRYPTO_COPY_KEY_SID: case TFM_CRYPTO_GENERATE_KEY_SID: + if ((in_vec[1].base == NULL) || + (in_vec[1].len != (sizeof(srv_key_attr) - TFM_CRYPTO_KEY_ATTR_OFFSET_CLIENT_SERVER))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } memcpy(&srv_key_attr, in_vec[1].base, in_vec[1].len); tfm_crypto_library_get_library_key_id_set_owner(encoded_key->owner, &srv_key_attr); break; @@ -52,6 +56,9 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], const uint8_t *data = in_vec[2].base; size_t data_length = in_vec[2].len; psa_key_id_t *key_id = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(psa_key_id_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } status = psa_import_key(&srv_key_attr, data, data_length, &library_key); @@ -62,6 +69,9 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], case TFM_CRYPTO_OPEN_KEY_SID: { psa_key_id_t *key_id = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(psa_key_id_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } status = psa_open_key(library_key, &library_key); *key_id = CRYPTO_LIBRARY_GET_KEY_ID(library_key); @@ -89,6 +99,9 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], * only the client view of it, i.e. without the owner field at the * end of the structure */ + if ((out_vec[0].base == NULL) || (out_vec[0].len > sizeof(psa_key_attributes_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } memcpy(key_attributes, &srv_key_attr, out_vec[0].len); } break; @@ -125,6 +138,9 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], { psa_key_id_t *target_key_id = out_vec[0].base; tfm_crypto_library_key_id_t target_key = tfm_crypto_library_key_id_init_default(); + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(psa_key_id_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } status = psa_copy_key(library_key, &srv_key_attr, @@ -139,6 +155,9 @@ psa_status_t tfm_crypto_key_management_interface(psa_invec in_vec[], case TFM_CRYPTO_GENERATE_KEY_SID: { psa_key_id_t *key_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(psa_key_id_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } status = psa_generate_key(&srv_key_attr, &library_key); if (status != PSA_SUCCESS) { diff --git a/secure_fw/partitions/crypto/crypto_library.c b/secure_fw/partitions/crypto/crypto_library.c index f840f9019..5aa9bb06b 100644 --- a/secure_fw/partitions/crypto/crypto_library.c +++ b/secure_fw/partitions/crypto/crypto_library.c @@ -98,6 +98,7 @@ void tfm_crypto_library_get_library_key_id_set_owner(int32_t owner, psa_key_attr attr->MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = owner; } +#ifdef PSA_CRYPTO_DRIVER_TFM_BUILTIN_KEY_LOADER /** * \brief This function is required by mbed TLS to enable support for * platform builtin keys in the PSA Crypto core layer implemented @@ -126,4 +127,5 @@ psa_status_t mbedtls_psa_platform_get_builtin_key( return PSA_ERROR_DOES_NOT_EXIST; } +#endif /*!@}*/ diff --git a/secure_fw/partitions/crypto/crypto_library.h b/secure_fw/partitions/crypto/crypto_library.h index 69704811d..e3058210f 100644 --- a/secure_fw/partitions/crypto/crypto_library.h +++ b/secure_fw/partitions/crypto/crypto_library.h @@ -24,6 +24,19 @@ extern "C" { #include "psa/crypto.h" +/** + * @brief Some integration might decide to enforce the same ABI on client and + * service interfaces to PSA Crypto defining the \a CRYPTO_LIBRARY_ABI_COMPAT + * In this case the size of the structure describing the key attributes + * is the same both in client and server views. The semantics remain + * unchanged + */ +#if defined(CRYPTO_LIBRARY_ABI_COMPAT) && (CRYPTO_LIBRARY_ABI_COMPAT == 1) +#define TFM_CRYPTO_KEY_ATTR_OFFSET_CLIENT_SERVER (0) +#else +#define TFM_CRYPTO_KEY_ATTR_OFFSET_CLIENT_SERVER (sizeof(mbedtls_key_owner_id_t)) +#endif /* CRYPTO_LIBRARY_ABI_COMPAT */ + /** * @brief This macro extracts the key ID from the library encoded key passed as parameter * diff --git a/secure_fw/partitions/crypto/crypto_mac.c b/secure_fw/partitions/crypto/crypto_mac.c index 4fe85a15f..bb8571de8 100644 --- a/secure_fw/partitions/crypto/crypto_mac.c +++ b/secure_fw/partitions/crypto/crypto_mac.c @@ -71,6 +71,9 @@ psa_status_t tfm_crypto_mac_interface(psa_invec in_vec[], if ((sid == TFM_CRYPTO_MAC_SIGN_SETUP_SID) || (sid == TFM_CRYPTO_MAC_VERIFY_SETUP_SID)) { p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; status = tfm_crypto_operation_alloc(TFM_CRYPTO_MAC_OPERATION, out_vec[0].base, @@ -89,6 +92,9 @@ psa_status_t tfm_crypto_mac_interface(psa_invec in_vec[], * override the original handle value in client, after lookup fails. */ p_handle = out_vec[0].base; + if ((out_vec[0].base == NULL) || (out_vec[0].len < sizeof(uint32_t))) { + return PSA_ERROR_PROGRAMMER_ERROR; + } *p_handle = iov->op_handle; } } diff --git a/secure_fw/partitions/crypto/crypto_pake.c b/secure_fw/partitions/crypto/crypto_pake.c new file mode 100644 index 000000000..3cb37dd77 --- /dev/null +++ b/secure_fw/partitions/crypto/crypto_pake.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2024, Nordic Semiconductor ASA. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "config_tfm.h" +#include "tfm_mbedcrypto_include.h" + +#include "tfm_crypto_api.h" +#include "tfm_crypto_key.h" +#include "tfm_crypto_defs.h" + +#include "crypto_library.h" + +/*! + * \addtogroup tfm_crypto_api_shim_layer + * + */ + +/*!@{*/ +#if CRYPTO_PAKE_MODULE_ENABLED +psa_status_t tfm_crypto_pake_interface(psa_invec in_vec[], + psa_outvec out_vec[], + struct tfm_crypto_key_id_s *encoded_key) +{ + const struct tfm_crypto_pack_iovec *iov = in_vec[0].base; + psa_status_t status = PSA_ERROR_NOT_SUPPORTED; + psa_pake_operation_t *operation = NULL; + uint32_t *p_handle = NULL; + uint16_t sid = iov->function_id; + + tfm_crypto_library_key_id_t library_key = tfm_crypto_library_key_id_init( + encoded_key->owner, encoded_key->key_id); + if(sid == TFM_CRYPTO_PAKE_SETUP_SID) { + p_handle = out_vec[0].base; + *p_handle = iov->op_handle; + status = tfm_crypto_operation_alloc(TFM_CRYPTO_PAKE_OPERATION, + out_vec[0].base, + (void **)&operation); + } else { + status = tfm_crypto_operation_lookup(TFM_CRYPTO_PAKE_OPERATION, + iov->op_handle, + (void **)&operation); + if ((sid == TFM_CRYPTO_PAKE_ABORT_SID) || sid == TFM_CRYPTO_PAKE_GET_SHARED_KEY_SID){ + /* + * finish()/abort() interface put handle in out_vec[0]. + * Therefore, out_vec[0] shall be specially set to original handle + * value. Otherwise, the garbage data in message out_vec[0] may + * override the original handle value in client, after lookup fails. + */ + p_handle = out_vec[0].base; + *p_handle = iov->op_handle; + } + } + if (status != PSA_SUCCESS) { + if (sid == TFM_CRYPTO_PAKE_ABORT_SID) { + /* + * Mbed TLS psa_pake_abort() will return a misleading error code + * if it is called with invalid operation content, since it + * doesn't validate the operation handle. + * It is neither necessary to call tfm_crypto_operation_release() + * with an invalid handle. + * Therefore return PSA_SUCCESS directly as psa_cipher_abort() can + * be called multiple times. + */ + return PSA_SUCCESS; + } + return status; + } + + switch (sid) + { + case TFM_CRYPTO_PAKE_SETUP_SID: + { + status = psa_pake_setup(operation, library_key, in_vec[1].base); + if (status != PSA_SUCCESS) { + goto release_operation_and_return; + } + } + break; + case TFM_CRYPTO_PAKE_SET_ROLE_SID: + { + status = psa_pake_set_role(operation, iov->role); + } + break; + case TFM_CRYPTO_PAKE_SET_USER_SID: + { + status = psa_pake_set_user(operation, in_vec[1].base, in_vec[1].len); + } + break; + case TFM_CRYPTO_PAKE_SET_PEER_SID: + { + status = psa_pake_set_peer(operation, in_vec[1].base, in_vec[1].len); + } + break; + case TFM_CRYPTO_PAKE_SET_CONTEXT_SID: + { + status = psa_pake_set_context(operation, in_vec[1].base, in_vec[1].len); + } + break; + case TFM_CRYPTO_PAKE_OUTPUT_SID: + { + psa_pake_step_t step = (psa_pake_step_t)iov->step; + uint8_t *output = (uint8_t *)out_vec[0].base; + size_t output_size = out_vec[0].len; + size_t *output_length = &out_vec[0].len; + status = psa_pake_output(operation, step, output, output_size, output_length); + if (status != PSA_SUCCESS) { + out_vec[0].len = 0; + } + } + break; + case TFM_CRYPTO_PAKE_INPUT_SID: + { + status = psa_pake_input(operation, (psa_pake_step_t)iov->step, in_vec[1].base, in_vec[1].len); + } + break; + case TFM_CRYPTO_PAKE_GET_SHARED_KEY_SID: + { + psa_key_attributes_t key_attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_key_id_t *key_handle = out_vec[1].base; + + memcpy(&key_attributes, in_vec[1].base, in_vec[1].len); + tfm_crypto_library_get_library_key_id_set_owner(encoded_key->owner, &key_attributes); + + if (status != PSA_SUCCESS) { + break; + } + + status = psa_pake_get_shared_key(operation, &key_attributes, &library_key); + if (status == PSA_SUCCESS) { + *key_handle = CRYPTO_LIBRARY_GET_KEY_ID(library_key); + /* In case of success automatically release the operation */ + goto release_operation_and_return; + } + } + break; + case TFM_CRYPTO_PAKE_ABORT_SID: + { + status = psa_pake_abort(operation); + goto release_operation_and_return; + } + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return status; + +release_operation_and_return: + /* Release the operation context, ignore if the operation fails. */ + (void)tfm_crypto_operation_release(p_handle); + return status; +} +#else /* CRYPTO_PAKE_MODULE_ENABLED */ +psa_status_t tfm_crypto_pake_interface(psa_invec in_vec[], + psa_outvec out_vec[], + struct tfm_crypto_key_id_s *encoded_key) +{ + (void)in_vec; + (void)out_vec; + (void)encoded_key; + + return PSA_ERROR_NOT_SUPPORTED; +} +#endif /* CRYPTO_PAKE_MODULE_ENABLED */ +/*!@}*/ diff --git a/secure_fw/partitions/crypto/crypto_spe.h b/secure_fw/partitions/crypto/crypto_spe.h index 61e85488b..f49f58b50 100644 --- a/secure_fw/partitions/crypto/crypto_spe.h +++ b/secure_fw/partitions/crypto/crypto_spe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,6 +24,10 @@ #define psa_crypto_init \ PSA_FUNCTION_NAME(psa_crypto_init) +#define psa_can_do_hash \ + PSA_FUNCTION_NAME(psa_can_do_hash) +#define psa_can_do_cipher \ + PSA_FUNCTION_NAME(psa_can_do_cipher) #define psa_key_derivation_get_capacity \ PSA_FUNCTION_NAME(psa_key_derivation_get_capacity) #define psa_key_derivation_set_capacity \ @@ -162,5 +166,27 @@ PSA_FUNCTION_NAME(psa_asymmetric_decrypt) #define psa_generate_key \ PSA_FUNCTION_NAME(psa_generate_key) +#define psa_pake_setup \ + PSA_FUNCTION_NAME(psa_pake_setup) +#define psa_pake_set_role \ + PSA_FUNCTION_NAME(psa_pake_set_role) +#define psa_pake_set_user \ + PSA_FUNCTION_NAME(psa_pake_set_user) +#define psa_pake_set_peer \ + PSA_FUNCTION_NAME(psa_pake_set_peer) +#define psa_pake_set_context \ + PSA_FUNCTION_NAME(psa_pake_set_context) +#define psa_pake_output \ + PSA_FUNCTION_NAME(psa_pake_output) +#define psa_pake_input \ + PSA_FUNCTION_NAME(psa_pake_input) +#define psa_pake_get_shared_key \ + PSA_FUNCTION_NAME(psa_pake_get_shared_key) +#define psa_pake_abort \ + PSA_FUNCTION_NAME(psa_pake_abort) +#define psa_key_derivation_verify_key \ + PSA_FUNCTION_NAME(psa_key_derivation_verify_key) +#define psa_key_derivation_verify_bytes \ + PSA_FUNCTION_NAME(psa_key_derivation_verify_bytes) #endif /* CRYPTO_SPE_H */ diff --git a/secure_fw/partitions/crypto/tfm_crypto_api.h b/secure_fw/partitions/crypto/tfm_crypto_api.h index 8fff29dce..2dc8473fd 100644 --- a/secure_fw/partitions/crypto/tfm_crypto_api.h +++ b/secure_fw/partitions/crypto/tfm_crypto_api.h @@ -31,6 +31,7 @@ enum tfm_crypto_operation_type { TFM_CRYPTO_HASH_OPERATION = 3, TFM_CRYPTO_KEY_DERIVATION_OPERATION = 4, TFM_CRYPTO_AEAD_OPERATION = 5, + TFM_CRYPTO_PAKE_OPERATION = 6, /* Used to force the enum size */ TFM_CRYPTO_OPERATION_TYPE_MAX = INT_MAX @@ -217,6 +218,19 @@ psa_status_t tfm_crypto_random_interface(psa_invec in_vec[], psa_status_t tfm_crypto_hash_interface(psa_invec in_vec[], psa_outvec out_vec[]); +/** + * \brief This function acts as interface for the PAKE module + * + * \param[in] in_vec Array of invec parameters + * \param[out] out_vec Array of outvec parameters + * \param[in] encoded_key Key encoded with partition_id and key_id + * + * \return Return values as described in \ref psa_status_t + */ +psa_status_t tfm_crypto_pake_interface(psa_invec in_vec[], + psa_outvec out_vec[], + struct tfm_crypto_key_id_s *encoded_key); + #ifdef __cplusplus } #endif diff --git a/secure_fw/partitions/initial_attestation/attest_core.c b/secure_fw/partitions/initial_attestation/attest_core.c index f58715ac7..8262dec18 100644 --- a/secure_fw/partitions/initial_attestation/attest_core.c +++ b/secure_fw/partitions/initial_attestation/attest_core.c @@ -23,7 +23,9 @@ #include "tfm_crypto_defs.h" #include "tfm_sp_log.h" +#ifndef ARRAY_LENGTH #define ARRAY_LENGTH(array) (sizeof(array) / sizeof(*(array))) +#endif /*! * \brief Static function to map return values between \ref psa_attest_err_t diff --git a/secure_fw/partitions/initial_attestation/tfm_attest_req_mngr.c b/secure_fw/partitions/initial_attestation/tfm_attest_req_mngr.c index 023246cd3..cd1e2b2fb 100644 --- a/secure_fw/partitions/initial_attestation/tfm_attest_req_mngr.c +++ b/secure_fw/partitions/initial_attestation/tfm_attest_req_mngr.c @@ -53,6 +53,7 @@ static psa_status_t psa_attest_get_token(const psa_msg_t *msg) token_buff, token_buff_size, &token_size); if (status == PSA_SUCCESS) { psa_unmap_outvec(msg->handle, 0, token_size); + psa_unmap_invec(msg->handle, 0); } return status; diff --git a/secure_fw/partitions/internal_trusted_storage/CMakeLists.txt b/secure_fw/partitions/internal_trusted_storage/CMakeLists.txt index 6c139d515..4f30c6242 100644 --- a/secure_fw/partitions/internal_trusted_storage/CMakeLists.txt +++ b/secure_fw/partitions/internal_trusted_storage/CMakeLists.txt @@ -63,6 +63,7 @@ target_link_libraries(tfm_psa_rot_partition_its target_compile_definitions(tfm_psa_rot_partition_its PUBLIC PS_CRYPTO_AEAD_ALG=${PS_CRYPTO_AEAD_ALG} + PS_CRYPTO_KDF_ALG=${PS_CRYPTO_KDF_ALG} ) ################ Display the configuration being applied ####################### diff --git a/secure_fw/partitions/internal_trusted_storage/flash_fs/its_flash_fs.h b/secure_fw/partitions/internal_trusted_storage/flash_fs/its_flash_fs.h index 281d48e6b..4132d2b89 100644 --- a/secure_fw/partitions/internal_trusted_storage/flash_fs/its_flash_fs.h +++ b/secure_fw/partitions/internal_trusted_storage/flash_fs/its_flash_fs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, Arm Limited. All rights reserved. + * Copyright (c) 2018-2024, Arm Limited. All rights reserved. * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -181,9 +181,9 @@ struct its_flash_fs_file_info_t { uint32_t flags; /*!< Flags set when the file was created */ #ifdef ITS_ENCRYPTION /*!< Additional authenticated data */ - uint8_t add[ITS_FILE_ID_SIZE + ITS_DATA_SIZE_FIELD_SIZE + ITS_FLAG_SIZE]; - uint8_t nonce[12];/*!< Nonce/IV for encrypted files */ - uint8_t tag[16]; /*!< Authentication tag */ + uint8_t aad[ITS_FILE_ID_SIZE + ITS_DATA_SIZE_FIELD_SIZE + ITS_FLAG_SIZE]; + uint8_t nonce[TFM_ITS_ENC_NONCE_LENGTH]; /*!< Nonce/IV for encrypted files */ + uint8_t tag[TFM_ITS_AUTH_TAG_LENGTH]; /*!< Authentication tag */ #endif }; diff --git a/secure_fw/partitions/internal_trusted_storage/its_crypto_interface.c b/secure_fw/partitions/internal_trusted_storage/its_crypto_interface.c index f2f721d5c..52c75c07a 100644 --- a/secure_fw/partitions/internal_trusted_storage/its_crypto_interface.c +++ b/secure_fw/partitions/internal_trusted_storage/its_crypto_interface.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * @@ -20,25 +20,25 @@ /** * \brief Fills the AEAD additional data used for the encryption/decryption * - * \details The additional data are not encypted their integrity is checked. + * \details The additional data is not encrypted but its integrity is checked. * For the ITS encryption we use the file id, the file flags and the * data size of the file as addditional data. * - * \param[out] add Additional data - * \param[in] add_size Additional data size in bytes + * \param[out] aad Additional authenticated data + * \param[in] aad_size Additional authenticated data size in bytes * \param[in] fid Identifier of the file * \param[in] fid_size Identifier of the file size in bytes * \param[in] flags Flags of the file * \param[in] data_size Data size in bytes * * \retval PSA_SUCCESS On success - * \retval PSA_ERROR_INVALID_ARGUMENT When the addditional data buffer does not - * have the correct size of the add/fid + * \retval PSA_ERROR_INVALID_ARGUMENT When the additional data buffer does not + * have the correct size or the aad/fid * buffers are NULL * */ -static psa_status_t tfm_its_fill_enc_add(uint8_t *add, - const size_t add_size, +static psa_status_t tfm_its_fill_enc_add(uint8_t *aad, + const size_t aad_size, const uint8_t *fid, const size_t fid_size, const uint32_t flags, @@ -49,22 +49,21 @@ static psa_status_t tfm_its_fill_enc_add(uint8_t *add, * gets the file info from ITS (see its_flash_fs_file_get_info). * We use the same flags for conformity. */ - uint32_t user_flags = flags & ITS_FLASH_FS_USER_FLAGS_MASK; + const uint32_t user_flags = flags & ITS_FLASH_FS_USER_FLAGS_MASK; /* The additional data consist of the file id, the flags and the * data size of the file. */ - size_t add_expected_size = ITS_FILE_ID_SIZE + - sizeof(user_flags) + - sizeof(data_size); + const size_t aad_expected_size = + ITS_FILE_ID_SIZE + sizeof(user_flags) + sizeof(data_size); - if (add_size != add_expected_size || add == NULL || fid == NULL) { + if ((aad_size != aad_expected_size) || (aad == NULL) || (fid == NULL)) { return PSA_ERROR_INVALID_ARGUMENT; } - memcpy(add, fid, fid_size); - memcpy(add + fid_size, &user_flags, sizeof(user_flags)); - memcpy(add + fid_size + sizeof(user_flags), + memcpy(aad, fid, fid_size); + memcpy(aad + fid_size, &user_flags, sizeof(user_flags)); + memcpy(aad + fid_size + sizeof(user_flags), &data_size, sizeof(data_size)); @@ -107,8 +106,8 @@ psa_status_t tfm_its_crypt_file(struct its_flash_fs_file_info_t *finfo, file_size = finfo->size_current; } - err = tfm_its_fill_enc_add(finfo->add, - sizeof(finfo->add), + err = tfm_its_fill_enc_add(finfo->aad, + sizeof(finfo->aad), fid, fid_size, finfo->flags, @@ -131,8 +130,8 @@ psa_status_t tfm_its_crypt_file(struct its_flash_fs_file_info_t *finfo, aead_ctx.nonce_size = sizeof(finfo->nonce); aead_ctx.deriv_label = fid; aead_ctx.deriv_label_size = fid_size; - aead_ctx.aad = finfo->add; - aead_ctx.add_size = sizeof(finfo->add); + aead_ctx.aad = finfo->aad; + aead_ctx.aad_size = sizeof(finfo->aad); if (is_encrypt) { @@ -163,4 +162,3 @@ psa_status_t tfm_its_crypt_file(struct its_flash_fs_file_info_t *finfo, return PSA_SUCCESS; } - diff --git a/secure_fw/partitions/internal_trusted_storage/tfm_internal_trusted_storage.c b/secure_fw/partitions/internal_trusted_storage/tfm_internal_trusted_storage.c index 691db5305..515743bf2 100644 --- a/secure_fw/partitions/internal_trusted_storage/tfm_internal_trusted_storage.c +++ b/secure_fw/partitions/internal_trusted_storage/tfm_internal_trusted_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2019-2024, Arm Limited. All rights reserved. * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) * or an affiliate of Cypress Semiconductor Corporation. All rights reserved. * @@ -45,8 +45,13 @@ static struct its_flash_fs_file_info_t g_file_info; * Note: size must be aligned to the max flash program unit to meet the * alignment requirement of the filesystem. */ +#ifndef ITS_ENCRYPTION static uint8_t __ALIGNED(4) asset_data[ITS_UTILS_ALIGN(ITS_BUF_SIZE, ITS_FLASH_MAX_ALIGNMENT)]; +#else +static uint8_t __ALIGNED(4) asset_data[ITS_UTILS_ALIGN(ITS_MAX_ASSET_SIZE, + ITS_FLASH_MAX_ALIGNMENT)]; +#endif #endif #ifdef TFM_PARTITION_INTERNAL_TRUSTED_STORAGE @@ -85,11 +90,12 @@ static its_flash_fs_ctx_t *get_fs_ctx(int32_t client_id) } #ifdef ITS_ENCRYPTION -/* Buffer to store the encrypted asset data before it is stored in the - * filesystem. +/* Buffer to store the encrypted asset data and the authentication tag before it + * is stored in the filesystem. */ -static uint8_t enc_asset_data[ITS_UTILS_ALIGN(ITS_BUF_SIZE, - ITS_FLASH_MAX_ALIGNMENT)]; +static uint8_t __ALIGNED(4) enc_asset_data[ITS_UTILS_ALIGN(ITS_MAX_ASSET_SIZE + + TFM_ITS_AUTH_TAG_LENGTH, + ITS_FLASH_MAX_ALIGNMENT)]; static psa_status_t buffer_size_check(int32_t client_id, size_t buffer_size) { @@ -102,8 +108,8 @@ static psa_status_t buffer_size_check(int32_t client_id, size_t buffer_size) /* When encryption is enabled the whole file needs to fit in the * global buffer. */ - if (buffer_size > sizeof(enc_asset_data)) { - return PSA_ERROR_BUFFER_TOO_SMALL; + if (buffer_size > ITS_MAX_ASSET_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; } } return PSA_SUCCESS; @@ -111,7 +117,8 @@ static psa_status_t buffer_size_check(int32_t client_id, size_t buffer_size) static psa_status_t tfm_its_crypt_data(int32_t client_id, uint8_t **input, - size_t input_size) + size_t input_size, + size_t offset) { psa_status_t status; #ifdef TFM_PARTITION_PROTECTED_STORAGE @@ -119,6 +126,11 @@ static psa_status_t tfm_its_crypt_data(int32_t client_id, #else { #endif /* TFM_PARTITION_PROTECTED_STORAGE */ + if (offset != 0) { + /* If the data will be encrypted the whole file needs to be written */ + return PSA_ERROR_INVALID_ARGUMENT; + } + status = tfm_its_crypt_file(&g_file_info, g_fid, sizeof(g_fid), @@ -392,11 +404,7 @@ static psa_status_t tfm_its_write_data_to_fs(const int32_t client_id, psa_status_t status; uint8_t *buffer_ptr = data; #ifdef ITS_ENCRYPTION /* ITS_ENCRYPTION */ - /* If the data will be encrypted the whole file needs to be written */ - if (offset != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - status = tfm_its_crypt_data(client_id, &buffer_ptr, data_size); + status = tfm_its_crypt_data(client_id, &buffer_ptr, data_size, offset); if (status != PSA_SUCCESS) { return status; } diff --git a/secure_fw/partitions/lib/runtime/CMakeLists.txt b/secure_fw/partitions/lib/runtime/CMakeLists.txt index 7a626b961..c29561764 100644 --- a/secure_fw/partitions/lib/runtime/CMakeLists.txt +++ b/secure_fw/partitions/lib/runtime/CMakeLists.txt @@ -16,6 +16,10 @@ target_include_directories(tfm_sprt ${CMAKE_SOURCE_DIR}/secure_fw/include ) +if(PSA_CRYPTO_EXTERNAL_CORE) + include(${TARGET_PLATFORM_PATH}/../external_core.cmake) +endif() + target_sources(tfm_sprt PUBLIC $<$:${CMAKE_SOURCE_DIR}/platform/ext/common/syscalls_stub.c> diff --git a/secure_fw/partitions/ns_agent_mailbox/tfm_spe_mailbox.c b/secure_fw/partitions/ns_agent_mailbox/tfm_spe_mailbox.c index 7fda47700..c15286eb4 100644 --- a/secure_fw/partitions/ns_agent_mailbox/tfm_spe_mailbox.c +++ b/secure_fw/partitions/ns_agent_mailbox/tfm_spe_mailbox.c @@ -17,6 +17,7 @@ #include "internal_status_code.h" #include "psa/error.h" #include "utilities.h" +#include "private/assert.h" #include "tfm_arch.h" #include "thread.h" #include "tfm_psa_call_pack.h" @@ -143,13 +144,14 @@ static void mailbox_direct_reply(uint8_t idx, uint32_t result) uint32_t ret_result = result; /* Copy outvec lengths back if necessary */ - if (vectors[idx].in_use) { + if ((vectors[idx].in_use) && (result == PSA_SUCCESS)) { for (int i = 0; i < vectors[idx].out_len; i++) { vectors[idx].original_out_vec[i].len = vectors[idx].out_vec[i].len; } - vectors[idx].in_use = false; } + vectors[idx].in_use = false; + /* Get reply address */ reply_ptr = get_nspe_reply_addr(idx); spm_memcpy(&reply_ptr->return_val, &ret_result, @@ -173,6 +175,54 @@ __STATIC_INLINE int32_t check_mailbox_msg(const struct mailbox_msg_t *msg) return MAILBOX_SUCCESS; } +static int local_copy_vects(const struct psa_client_params_t *params, + uint32_t idx, + uint32_t *control) +{ + size_t in_len, out_len; + + in_len = params->psa_call_params.in_len; + out_len = params->psa_call_params.out_len; + + if (((params->psa_call_params.out_vec == NULL) && (out_len != 0)) || + ((params->psa_call_params.in_vec == NULL) && (in_len != 0))) { + return MAILBOX_INVAL_PARAMS; + } + + if ((in_len > PSA_MAX_IOVEC) || + (out_len > PSA_MAX_IOVEC) || + ((in_len + out_len) > PSA_MAX_IOVEC)) { + return MAILBOX_INVAL_PARAMS; + } + + for (unsigned int i = 0; i < PSA_MAX_IOVEC; i++) { + if (i < in_len) { + vectors[idx].in_vec[i] = params->psa_call_params.in_vec[i]; + } else { + vectors[idx].in_vec[i].base = 0; + vectors[idx].in_vec[i].len = 0; + } + } + + for (unsigned int i = 0; i < PSA_MAX_IOVEC; i++) { + if (i < out_len) { + vectors[idx].out_vec[i] = params->psa_call_params.out_vec[i]; + } else { + vectors[idx].out_vec[i].base = 0; + vectors[idx].out_vec[i].len = 0; + } + } + + *control = PARAM_SET_NS_INVEC(*control); + *control = PARAM_SET_NS_OUTVEC(*control); + + vectors[idx].out_len = out_len; + vectors[idx].original_out_vec = params->psa_call_params.out_vec; + + vectors[idx].in_use = true; + return MAILBOX_SUCCESS; +} + /* Passes the request from the mailbox message into SPM. * idx indicates the slot used to use for any immediate reply. * If it queues the reply immediately, updates reply_slots accordingly. @@ -190,6 +240,7 @@ static int32_t tfm_mailbox_dispatch(const struct mailbox_msg_t *msg_ptr, psa_status_t psa_ret = PSA_ERROR_GENERIC_ERROR; mailbox_msg_handle_t *mb_msg_handle = &spe_mailbox_queue.queue[idx].msg_handle; + int ret; #if CONFIG_TFM_SPM_BACKEND_IPC == 1 /* Assume asynchronous. Set to synchronous when an error happens. */ @@ -213,33 +264,13 @@ static int32_t tfm_mailbox_dispatch(const struct mailbox_msg_t *msg_ptr, break; case MAILBOX_PSA_CALL: - /* TODO check vector validity before use */ - /* Make local copy of invecs and outvecs */ - vectors[idx].in_use = true; - vectors[idx].out_len = params->psa_call_params.out_len; - vectors[idx].original_out_vec = params->psa_call_params.out_vec; - for (int i = 0; i < PSA_MAX_IOVEC; i++) { - if (i < params->psa_call_params.in_len) { - vectors[idx].in_vec[i] = params->psa_call_params.in_vec[i]; - } else { - vectors[idx].in_vec[i].base = 0; - vectors[idx].in_vec[i].len = 0; - } - } - - control = PARAM_SET_NS_INVEC(control); - - for (int i = 0; i < PSA_MAX_IOVEC; i++) { - if (i < params->psa_call_params.out_len) { - vectors[idx].out_vec[i] = params->psa_call_params.out_vec[i]; - } else { - vectors[idx].out_vec[i].base = 0; - vectors[idx].out_vec[i].len = 0; - } + ret = local_copy_vects(params, idx, &control); + if (ret != MAILBOX_SUCCESS) { + sync = true; + psa_ret = PSA_ERROR_INVALID_ARGUMENT; + break; } - control = PARAM_SET_NS_OUTVEC(control); - if (tfm_multi_core_hal_client_id_translate(CLIENT_ID_OWNER_MAGIC, msg_ptr->client_id, &client_id) != SPM_SUCCESS) { diff --git a/secure_fw/partitions/protected_storage/CMakeLists.txt b/secure_fw/partitions/protected_storage/CMakeLists.txt index 0cfedac08..bb6e5fcfe 100644 --- a/secure_fw/partitions/protected_storage/CMakeLists.txt +++ b/secure_fw/partitions/protected_storage/CMakeLists.txt @@ -75,11 +75,11 @@ target_sources(tfm_partitions target_link_libraries(tfm_app_rot_partition_ps PRIVATE + psa_crypto_config secure_fw platform_s tfm_config tfm_sprt - psa_crypto_config ) target_compile_definitions(tfm_app_rot_partition_ps diff --git a/secure_fw/partitions/protected_storage/crypto/ps_crypto_interface.c b/secure_fw/partitions/protected_storage/crypto/ps_crypto_interface.c index 20e9adfed..f508ff455 100644 --- a/secure_fw/partitions/protected_storage/crypto/ps_crypto_interface.c +++ b/secure_fw/partitions/protected_storage/crypto/ps_crypto_interface.c @@ -18,6 +18,14 @@ #define PS_CRYPTO_AEAD_ALG PSA_ALG_GCM #endif +/* CMake can't handle round brackets for compile defines so PSA_ALG_HKDF(PSA_ALG_SHA_256) doesn't + * work, therefore we have to use a own defined for the C code where + * PSA_ALG_HKDF_PSA_ALG_SHA_256 gets translated to PSA_ALG_HKDF_PSA_ALG_SHA_256 + */ +#if !defined(PS_CRYPTO_KDF_ALG) +#define PS_CRYPTO_KDF_ALG PSA_ALG_HKDF(PSA_ALG_SHA_256) +#endif + /* The PSA key type used by this implementation */ #define PS_KEY_TYPE PSA_KEY_TYPE_AES /* The PSA key usage required by this implementation */ @@ -73,7 +81,7 @@ psa_status_t ps_crypto_setkey(const uint8_t *key_label, size_t key_label_len) psa_set_key_type(&attributes, PS_KEY_TYPE); psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(PS_KEY_LEN_BYTES)); - status = psa_key_derivation_setup(&op, PSA_ALG_HKDF(PSA_ALG_SHA_256)); + status = psa_key_derivation_setup(&op, PS_CRYPTO_KDF_ALG); if (status != PSA_SUCCESS) { return status; } @@ -86,7 +94,8 @@ psa_status_t ps_crypto_setkey(const uint8_t *key_label, size_t key_label_len) } /* Supply the PS key label as an input to the key derivation */ - status = psa_key_derivation_input_bytes(&op, PSA_KEY_DERIVATION_INPUT_INFO, + status = psa_key_derivation_input_bytes(&op, PS_CRYPTO_KDF_ALG == PSA_ALG_SP800_108_COUNTER_CMAC ? + PSA_KEY_DERIVATION_INPUT_LABEL : PSA_KEY_DERIVATION_INPUT_INFO, key_label, key_label_len); if (status != PSA_SUCCESS) { diff --git a/secure_fw/partitions/protected_storage/ps_object_system.c b/secure_fw/partitions/protected_storage/ps_object_system.c index 8584c60f3..733096999 100644 --- a/secure_fw/partitions/protected_storage/ps_object_system.c +++ b/secure_fw/partitions/protected_storage/ps_object_system.c @@ -480,6 +480,7 @@ psa_status_t ps_object_get_info(psa_storage_uid_t uid, int32_t client_id, /* Copy PS object info to the PSA PS info struct */ info->size = g_ps_object.header.info.current_size; + info->capacity = g_ps_object.header.info.max_size; info->flags = g_ps_object.header.info.create_flags; clear_data_and_return: diff --git a/secure_fw/partitions/protected_storage/ps_object_table.c b/secure_fw/partitions/protected_storage/ps_object_table.c index eb8f7a1f7..f293d0b87 100644 --- a/secure_fw/partitions/protected_storage/ps_object_table.c +++ b/secure_fw/partitions/protected_storage/ps_object_table.c @@ -902,14 +902,6 @@ psa_status_t ps_object_table_init(uint8_t *obj_data) return err; } -#if PS_ROLLBACK_PROTECTION - /* Align PS NV counters */ - err = ps_object_table_align_nv_counters(init_ctx.nvc_1); - if (err != PSA_SUCCESS) { - return err; - } -#endif /* PS_ROLLBACK_PROTECTION */ - #ifdef PS_ENCRYPTION ps_crypto_set_iv(&ps_obj_table_ctx.obj_table.crypto); #endif diff --git a/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.h b/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.h index 67c658f47..f5fc7ee8c 100644 --- a/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.h +++ b/secure_fw/spm/core/arch/tfm_arch_v6m_v7m.h @@ -11,6 +11,7 @@ #include #include "cmsis_compiler.h" #include "utilities.h" +#include "private/assert.h" #if !TFM_MULTI_CORE_TOPOLOGY #error "Armv6-M/Armv7-M can only support multi-core TF-M now." diff --git a/secure_fw/spm/core/backend_ipc.c b/secure_fw/spm/core/backend_ipc.c index e29aa3dd7..e0f3efd8d 100644 --- a/secure_fw/spm/core/backend_ipc.c +++ b/secure_fw/spm/core/backend_ipc.c @@ -14,6 +14,7 @@ #include "config_spm.h" #include "critical_section.h" #include "compiler_ext_defs.h" +#include "config_spm.h" #include "ffm/psa_api.h" #include "fih.h" #include "runtime_defs.h" @@ -22,8 +23,10 @@ #include "tfm_hal_isolation.h" #include "tfm_hal_platform.h" #include "tfm_nspm.h" +#include "tfm_rpc.h" #include "ffm/backend.h" #include "utilities.h" +#include "private/assert.h" #include "memory_symbols.h" #include "load/partition_defs.h" #include "load/service_defs.h" @@ -94,7 +97,20 @@ static uint32_t query_state(struct thread_t *p_thrd, uint32_t *p_retval) if ((retval_signals == ASYNC_MSG_REPLY) && ((p_pt->signals_allowed & ASYNC_MSG_REPLY) != ASYNC_MSG_REPLY)) { p_pt->signals_asserted &= ~ASYNC_MSG_REPLY; - *p_retval = (uint32_t)p_pt->reply_value; +#ifndef NDEBUG + SPM_ASSERT(p_pt->p_replied->status < TFM_HANDLE_STATUS_MAX); +#endif + + /* + * For FF-M Secure Partition, the reply is synchronous and only one + * replied handle node should be mounted. Take the reply value from + * the node and delete it then. + */ + *p_retval = (uint32_t)p_pt->p_replied->replied_value; + if (p_pt->p_replied->status == TFM_HANDLE_STATUS_TO_FREE) { + spm_free_connection(p_pt->p_replied); + } + p_pt->p_replied = NULL; } else { *p_retval = retval_signals; } @@ -125,7 +141,9 @@ static void prv_process_metadata(struct partition_t *p_pt) struct runtime_metadata_t *p_rt_meta; service_fn_t *p_sfn_table; uint32_t allocate_size; +#if TFM_ISOLATION_LEVEL != 1 FIH_RET_TYPE(bool) fih_rc; +#endif p_pt_ldi = p_pt->p_ldinf; p_srv_ldi = LOAD_INFO_SERVICE(p_pt_ldi); @@ -189,16 +207,16 @@ psa_status_t backend_messaging(struct connection_t *p_connection) p_owner = p_connection->service->partition; signal = p_connection->service->p_ldinf->signal; - UNI_LIST_INSERT_AFTER(p_owner, p_connection, p_handles); + UNI_LIST_INSERT_AFTER(p_owner, p_connection, p_reqs); /* Messages put. Update signals */ ret = backend_assert_signal(p_owner, signal); /* - * If it is a NS request via RPC, it is unnecessary to block current - * thread. + * If it is a request from NS Mailbox Agent, it is NOT necessary to block + * the current thread. */ - if (tfm_spm_is_rpc_msg(p_connection)) { + if (IS_NS_AGENT_MAILBOX(p_connection->p_client->p_ldinf)) { ret = PSA_SUCCESS; } else { signal = backend_wait_signals(p_connection->p_client, ASYNC_MSG_REPLY); @@ -207,8 +225,6 @@ psa_status_t backend_messaging(struct connection_t *p_connection) } } - p_connection->status = TFM_HANDLE_STATUS_ACTIVE; - return ret; } @@ -216,21 +232,19 @@ psa_status_t backend_replying(struct connection_t *handle, int32_t status) { struct partition_t *client = handle->p_client; - if (tfm_spm_is_rpc_msg(handle)) { - /* - * Add to the list of outstanding responses. - * Note that we use the partition's p_handles pointer. - * This assumes that partitions using the agent API will process all requests - * asynchronously and will not also provide services of their own. - */ - handle->reply_value = (uintptr_t)status; - handle->msg.rhandle = handle; - UNI_LIST_INSERT_AFTER(client, handle, p_handles); - return backend_assert_signal(handle->p_client, ASYNC_MSG_REPLY); - } else { - handle->p_client->reply_value = (uintptr_t)status; - return backend_assert_signal(handle->p_client, ASYNC_MSG_REPLY); - } + /* Prepare the replied handle. */ + handle->replied_value = (uintptr_t)status; + + /* Mount the replied handle. There are two mode for replying. + * + * - For synchronous reply, only one node is mounted. + * - For asynchronous reply, the first moundted is at the tail of the list + * and will be first replied. + * - Currently, this is used for mailbox multi-core technology. + */ + UNI_LIST_INSERT_AFTER(client, handle, p_replied); + + return backend_assert_signal(handle->p_client, ASYNC_MSG_REPLY); } extern void common_sfn_thread(void *param); @@ -254,7 +268,8 @@ static thrd_fn_t partition_init(struct partition_t *p_pt, p_pt->signals_allowed |= ASYNC_MSG_REPLY; } - UNI_LISI_INIT_NODE(p_pt, p_handles); + UNI_LIST_INIT_NODE(p_pt, p_reqs); + UNI_LIST_INIT_NODE(p_pt, p_replied); if (IS_IPC_MODEL(p_pt->p_ldinf)) { /* IPC Partition */ @@ -295,6 +310,8 @@ static thrd_fn_t ns_agent_tz_init(struct partition_t *p_pt, (void)p_pt; (void)service_setting; (void)param; + + return POSITION_TO_ENTRY(NULL, thrd_fn_t); } #endif @@ -545,6 +562,31 @@ uint64_t ipc_schedule(uint32_t exc_return) } p_partition_metadata = (uintptr_t)(p_part_next->p_metadata); + /* + * ctx_ctrl is set from struct thread_t's p_context_ctrl, and p_part_curr + * and p_part_next are calculated from the thread pointer. + * struct partition_t's ctx_ctrl is pointed to by struct thread_t's p_context_ctrl, + * but the optimiser doesn't know that when building this code. + * Use that information to check that the context, thread, and partition + * are all consistent + */ + if (ctx_ctrls.u32_regs.r0 != (uint32_t)&p_part_curr->ctx_ctrl) { + tfm_core_panic(); + } + + if (ctx_ctrls.u32_regs.r1 != (uint32_t)&p_part_next->ctx_ctrl) { + tfm_core_panic(); + } + + if (&p_part_next->thrd != CURRENT_THREAD) { + tfm_core_panic(); + } + + /* also double-check the metadata */ + if ((uintptr_t)GET_CTX_OWNER(ctx_ctrls.u32_regs.r1)->p_metadata != p_partition_metadata) { + tfm_core_panic(); + } + CRITICAL_SECTION_LEAVE(cs); return AAPCS_DUAL_U32_AS_U64(ctx_ctrls); diff --git a/secure_fw/spm/core/backend_sfn.c b/secure_fw/spm/core/backend_sfn.c index 1b7919d0a..30233f091 100644 --- a/secure_fw/spm/core/backend_sfn.c +++ b/secure_fw/spm/core/backend_sfn.c @@ -23,6 +23,7 @@ #include "psa/service.h" #include "spm.h" #include "memory_symbols.h" +#include "private/assert.h" /* SFN Partition state */ #define SFN_PARTITION_STATE_NOT_INITED 0 @@ -50,7 +51,7 @@ psa_status_t backend_messaging(struct connection_t *p_connection) } p_target = p_connection->service->partition; - p_target->p_handles = p_connection; + p_target->p_reqs = p_connection; SET_CURRENT_COMPONENT(p_target); @@ -67,8 +68,6 @@ psa_status_t backend_messaging(struct connection_t *p_connection) status = ((service_fn_t)p_connection->service->p_ldinf->sfn)(&p_connection->msg); - p_connection->status = TFM_HANDLE_STATUS_ACTIVE; - return status; } @@ -128,7 +127,7 @@ void backend_init_comp_assuredly(struct partition_t *p_pt, { const struct partition_load_info_t *p_pldi = p_pt->p_ldinf; - p_pt->p_handles = NULL; + p_pt->p_reqs = NULL; p_pt->state = SFN_PARTITION_STATE_NOT_INITED; watermark_stack(p_pt); diff --git a/secure_fw/spm/core/interrupt.c b/secure_fw/spm/core/interrupt.c index c0d7c9da1..132da6d2d 100644 --- a/secure_fw/spm/core/interrupt.c +++ b/secure_fw/spm/core/interrupt.c @@ -71,6 +71,9 @@ uint32_t tfm_flih_prepare_depriv_flih(struct partition_t *p_owner_sp, if (fih_not_eq(fih_bool, fih_int_encode(false))) { FIH_CALL(tfm_hal_activate_boundary, fih_rc, p_owner_sp->p_ldinf, p_owner_sp->boundary); + if (fih_not_eq(fih_rc, fih_int_encode(TFM_HAL_SUCCESS))) { + tfm_core_panic(); + } } /* @@ -107,6 +110,9 @@ uint32_t tfm_flih_return_to_isr(psa_flih_result_t result, if (fih_not_eq(fih_bool, fih_int_encode(false))) { FIH_CALL(tfm_hal_activate_boundary, fih_rc, p_prev_sp->p_ldinf, p_prev_sp->boundary); + if (fih_not_eq(fih_rc, fih_int_encode(TFM_HAL_SUCCESS))) { + tfm_core_panic(); + } } /* diff --git a/secure_fw/spm/core/mailbox_agent_api.c b/secure_fw/spm/core/mailbox_agent_api.c index 20238e730..33f5177eb 100644 --- a/secure_fw/spm/core/mailbox_agent_api.c +++ b/secure_fw/spm/core/mailbox_agent_api.c @@ -43,13 +43,19 @@ psa_status_t tfm_spm_agent_psa_call(psa_handle_t handle, status = spm_associate_call_params(p_connection, control, params->p_invecs, params->p_outvecs); if (status != PSA_SUCCESS) { + if (IS_STATIC_HANDLE(handle)) { + spm_free_connection(p_connection); + } return status; } /* Set Mailbox client data in connection handle for message reply. */ p_connection->client_data = client_data_stateless; - return backend_messaging(p_connection); + status = backend_messaging(p_connection); + + p_connection->status = TFM_HANDLE_STATUS_ACTIVE; + return status; } #if CONFIG_TFM_CONNECTION_BASED_SERVICE_API == 1 @@ -77,7 +83,10 @@ psa_handle_t tfm_spm_agent_psa_connect(uint32_t sid, uint32_t version, /* Set Mailbox client data in connection handle for message reply. */ p_connection->client_data = client_data; - return backend_messaging(p_connection); + status = backend_messaging(p_connection); + + p_connection->status = TFM_HANDLE_STATUS_ACTIVE; + return status; } psa_status_t tfm_spm_agent_psa_close(psa_handle_t handle, diff --git a/secure_fw/spm/core/main.c b/secure_fw/spm/core/main.c index 377a32f92..de04d1bb0 100644 --- a/secure_fw/spm/core/main.c +++ b/secure_fw/spm/core/main.c @@ -29,6 +29,7 @@ static fih_int tfm_core_init(void) { enum tfm_plat_err_t plat_err = TFM_PLAT_ERR_SYSTEM_ERR; fih_int fih_rc = FIH_FAILURE; + bool provisioning_required; /* * Access to any peripheral should be performed after programming @@ -62,7 +63,12 @@ static fih_int tfm_core_init(void) } /* Perform provisioning. */ - if (tfm_plat_provisioning_is_required()) { + plat_err = tfm_plat_provisioning_is_required(&provisioning_required); + if (plat_err != TFM_PLAT_ERR_SUCCESS) { + FIH_RET(fih_int_encode(SPM_ERROR_GENERIC)); + } + + if (provisioning_required) { plat_err = tfm_plat_provisioning_perform(); if (plat_err != TFM_PLAT_ERR_SUCCESS) { FIH_RET(fih_int_encode(SPM_ERROR_GENERIC)); diff --git a/secure_fw/spm/core/psa_api.c b/secure_fw/spm/core/psa_api.c index ee3621055..1ddbf1c62 100644 --- a/secure_fw/spm/core/psa_api.c +++ b/secure_fw/spm/core/psa_api.c @@ -158,26 +158,9 @@ psa_status_t tfm_spm_partition_psa_get(psa_signal_t signal, psa_msg_t *msg) } if (signal == ASYNC_MSG_REPLY) { - struct connection_t **pr_handle_iter, **prev = NULL; - struct critical_section_t cs_assert = CRITICAL_SECTION_STATIC_INIT; - - /* Remove tail of the list, which is the first item added */ - CRITICAL_SECTION_ENTER(cs_assert); - if (!partition->p_handles) { - tfm_core_panic(); - } - UNI_LIST_FOREACH_NODE_PNODE(pr_handle_iter, handle, - partition, p_handles) { - prev = pr_handle_iter; - } - handle = *prev; - UNI_LIST_REMOVE_NODE_BY_PNODE(prev, p_handles); - ret = handle->reply_value; - /* Clear the signal if there are no more asynchronous responses waiting */ - if (!partition->p_handles) { - partition->signals_asserted &= ~ASYNC_MSG_REPLY; - } - CRITICAL_SECTION_LEAVE(cs_assert); + handle = spm_get_async_replied_handle(partition); + ret = handle->replied_value; + msg->rhandle = handle; } else { /* * Get message by signal from partition. It is a fatal error if getting @@ -189,14 +172,62 @@ psa_status_t tfm_spm_partition_psa_get(psa_signal_t signal, psa_msg_t *msg) } else { return PSA_ERROR_DOES_NOT_EXIST; } - } - spm_memcpy(msg, &handle->msg, sizeof(psa_msg_t)); + spm_memcpy(msg, &handle->msg, sizeof(psa_msg_t)); + } return ret; } #endif +static void update_caller_outvec_len(struct connection_t *handle) +{ + uint32_t i; + +#if PSA_FRAMEWORK_HAS_MM_IOVEC + /* + * If no unmapping call was made, output vectors will report that no data + * has been written. + */ + for (i = OUTVEC_IDX_BASE; i < (PSA_MAX_IOVEC * 2); i++) { + if (!IOVEC_IS_UNMAPPED(handle, i) && !IOVEC_IS_ACCESSED(handle, i)) { + handle->outvec_written[i - OUTVEC_IDX_BASE] = 0; + } + } +#endif + + /* + * The total number of bytes written to a single parameter must be reported + * to the client by updating the len member of the psa_outvec structure for + * the parameter before returning from psa_call(). + */ + for (i = 0; i < PSA_MAX_IOVEC; i++) { + if (handle->msg.out_size[i] == 0) { + continue; + } + + SPM_ASSERT(handle->caller_outvec[i].base == handle->outvec_base[i]); + + handle->caller_outvec[i].len = handle->outvec_written[i]; + } +} + +static inline psa_status_t psa_reply_error_connection( + struct connection_t *handle, + psa_status_t status, + bool *del_conn) +{ +#if CONFIG_TFM_SPM_BACKEND_SFN == 1 + *del_conn = true; +#else + (void)del_conn; +#endif + + handle->status = TFM_HANDLE_STATUS_TO_FREE; + + return status; +} + psa_status_t tfm_spm_partition_psa_reply(psa_handle_t msg_handle, psa_status_t status) { @@ -204,6 +235,7 @@ psa_status_t tfm_spm_partition_psa_reply(psa_handle_t msg_handle, struct connection_t *handle; psa_status_t ret = PSA_SUCCESS; struct critical_section_t cs_assert = CRITICAL_SECTION_STATIC_INIT; + bool delete_connection = false; /* It is a fatal error if message handle is invalid */ handle = spm_msg_handle_to_connection(msg_handle); @@ -232,18 +264,22 @@ psa_status_t tfm_spm_partition_psa_reply(psa_handle_t msg_handle, ret = msg_handle; } else if (status == PSA_ERROR_CONNECTION_REFUSED) { /* Refuse the client connection, indicating a permanent error. */ - ret = PSA_ERROR_CONNECTION_REFUSED; - handle->status = TFM_HANDLE_STATUS_TO_FREE; + ret = psa_reply_error_connection(handle, status, &delete_connection); } else if (status == PSA_ERROR_CONNECTION_BUSY) { /* Fail the client connection, indicating a transient error. */ - ret = PSA_ERROR_CONNECTION_BUSY; + ret = psa_reply_error_connection(handle, status, &delete_connection); } else { tfm_core_panic(); } break; case PSA_IPC_DISCONNECT: - /* Service handle is not used anymore */ +#if CONFIG_TFM_SPM_BACKEND_IPC == 1 + /* Service handle will be freed in the backend */ handle->status = TFM_HANDLE_STATUS_TO_FREE; +#else + /* Service handle is not used anymore */ + delete_connection = true; +#endif /* * If the message type is PSA_IPC_DISCONNECT, then the status code is @@ -252,29 +288,15 @@ psa_status_t tfm_spm_partition_psa_reply(psa_handle_t msg_handle, break; default: if (handle->msg.type >= PSA_IPC_CALL) { - -#if PSA_FRAMEWORK_HAS_MM_IOVEC - /* - * Any output vectors that are still mapped will report that - * zero bytes have been written. - */ - for (int i = OUTVEC_IDX_BASE; i < PSA_MAX_IOVEC * 2; i++) { - if (IOVEC_IS_MAPPED(handle, i) && (!IOVEC_IS_UNMAPPED(handle, i))) { - handle->outvec_written[i - OUTVEC_IDX_BASE] = 0; - } - } -#endif /* Reply to a request message. Return values are based on status */ ret = status; - /* - * The total number of bytes written to a single parameter must be - * reported to the client by updating the len member of the - * psa_outvec structure for the parameter before returning from - * psa_call(). - */ + update_caller_outvec_len(handle); if (SERVICE_IS_STATELESS(service->p_ldinf->flags)) { handle->status = TFM_HANDLE_STATUS_TO_FREE; +#if CONFIG_TFM_SPM_BACKEND_SFN == 1 + delete_connection = true; +#endif /* CONFIG_TFM_SPM_BACKEND_SFN == 1 */ } } else { tfm_core_panic(); @@ -305,19 +327,22 @@ psa_status_t tfm_spm_partition_psa_reply(psa_handle_t msg_handle, * until the response has been collected by the agent. */ #if CONFIG_TFM_SPM_BACKEND_IPC == 1 - if (tfm_spm_is_rpc_msg(handle)) { + if (IS_NS_AGENT_MAILBOX(handle->p_client->p_ldinf)) { return ret; } #endif + if (handle->status != TFM_HANDLE_STATUS_TO_FREE) { + handle->status = TFM_HANDLE_STATUS_IDLE; + } /* * When the asynchronous agent API is not used or when in SFN model, free * the connection handle immediately. */ - if (handle->status == TFM_HANDLE_STATUS_TO_FREE) { - spm_free_connection(handle); - } else { + if (delete_connection) { handle->status = TFM_HANDLE_STATUS_IDLE; + + spm_free_connection(handle); } return ret; diff --git a/secure_fw/spm/core/psa_call_api.c b/secure_fw/spm/core/psa_call_api.c index f6b70229d..52891bc9c 100644 --- a/secure_fw/spm/core/psa_call_api.c +++ b/secure_fw/spm/core/psa_call_api.c @@ -178,5 +178,8 @@ psa_status_t tfm_spm_client_psa_call(psa_handle_t handle, return status; } - return backend_messaging(p_connection); + status = backend_messaging(p_connection); + + p_connection->status = TFM_HANDLE_STATUS_ACTIVE; + return status; } diff --git a/secure_fw/spm/core/psa_connection_api.c b/secure_fw/spm/core/psa_connection_api.c index 170b29d66..90f5a7bef 100644 --- a/secure_fw/spm/core/psa_connection_api.c +++ b/secure_fw/spm/core/psa_connection_api.c @@ -31,7 +31,10 @@ psa_status_t tfm_spm_client_psa_connect(uint32_t sid, uint32_t version) return status; } - return backend_messaging(p_connection); + status = backend_messaging(p_connection); + + p_connection->status = TFM_HANDLE_STATUS_ACTIVE; + return status; } psa_status_t spm_psa_connect_client_id_associated(struct connection_t **p_connection, @@ -123,7 +126,11 @@ psa_status_t spm_psa_close_client_id_associated(psa_handle_t handle, int32_t cli p_connection->msg.type = PSA_IPC_DISCONNECT; - return backend_messaging(p_connection); + status = backend_messaging(p_connection); + + p_connection->status = TFM_HANDLE_STATUS_TO_FREE; + + return status; } psa_status_t tfm_spm_partition_psa_set_rhandle(psa_handle_t msg_handle, void *rhandle) diff --git a/secure_fw/spm/core/psa_interface_sfn.c b/secure_fw/spm/core/psa_interface_sfn.c index 81096c21a..59d90c85a 100644 --- a/secure_fw/spm/core/psa_interface_sfn.c +++ b/secure_fw/spm/core/psa_interface_sfn.c @@ -52,7 +52,7 @@ psa_status_t tfm_psa_call_pack(psa_handle_t handle, uint32_t ctrl_param, p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, stat); } else { /* Execution is returned from SPM */ @@ -126,7 +126,7 @@ psa_handle_t psa_connect(uint32_t sid, uint32_t version) p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, stat); } else { /* Execution is returned from SPM */ @@ -153,7 +153,7 @@ void psa_close(psa_handle_t handle) p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, PSA_SUCCESS); } else { /* Execution is returned from SPM */ @@ -283,7 +283,7 @@ psa_status_t agent_psa_call(psa_handle_t handle, p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, stat); } else { /* Execution is returned from SPM */ @@ -312,7 +312,7 @@ psa_handle_t agent_psa_connect(uint32_t sid, uint32_t version, p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, stat); } else { /* Execution is returned from SPM */ @@ -339,7 +339,7 @@ psa_status_t agent_psa_close(psa_handle_t handle, int32_t ns_client_id) p_target = GET_CURRENT_COMPONENT(); if (p_client != p_target) { /* Execution is returned from RoT Service */ - stat = tfm_spm_partition_psa_reply(p_target->p_handles->msg.handle, + stat = tfm_spm_partition_psa_reply(p_target->p_reqs->msg.handle, PSA_SUCCESS); } else { /* Execution is returned from SPM */ diff --git a/secure_fw/spm/core/psa_interface_thread_fn_call.c b/secure_fw/spm/core/psa_interface_thread_fn_call.c index 1dfa0a2e8..9d21db52b 100644 --- a/secure_fw/spm/core/psa_interface_thread_fn_call.c +++ b/secure_fw/spm/core/psa_interface_thread_fn_call.c @@ -36,21 +36,18 @@ ) __naked -__section(".psa_interface_thread_fn_call") uint32_t psa_framework_version_thread_fn_call(void) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_client_psa_framework_version); } __naked -__section(".psa_interface_thread_fn_call") uint32_t psa_version_thread_fn_call(uint32_t sid) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_client_psa_version); } __naked -__section(".psa_interface_thread_fn_call") psa_status_t tfm_psa_call_pack_thread_fn_call(psa_handle_t handle, uint32_t ctrl_param, const psa_invec *in_vec, @@ -60,21 +57,18 @@ psa_status_t tfm_psa_call_pack_thread_fn_call(psa_handle_t handle, } __naked -__section(".psa_interface_thread_fn_call") psa_signal_t psa_wait_thread_fn_call(psa_signal_t signal_mask, uint32_t timeout) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_wait); } __naked -__section(".psa_interface_thread_fn_call") psa_status_t psa_get_thread_fn_call(psa_signal_t signal, psa_msg_t *msg) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_get); } __naked -__section(".psa_interface_thread_fn_call") size_t psa_read_thread_fn_call(psa_handle_t msg_handle, uint32_t invec_idx, void *buffer, size_t num_bytes) { @@ -82,7 +76,6 @@ size_t psa_read_thread_fn_call(psa_handle_t msg_handle, uint32_t invec_idx, } __naked -__section(".psa_interface_thread_fn_call") size_t psa_skip_thread_fn_call(psa_handle_t msg_handle, uint32_t invec_idx, size_t num_bytes) { @@ -90,7 +83,6 @@ size_t psa_skip_thread_fn_call(psa_handle_t msg_handle, } __naked -__section(".psa_interface_thread_fn_call") void psa_write_thread_fn_call(psa_handle_t msg_handle, uint32_t outvec_idx, const void *buffer, size_t num_bytes) { @@ -98,7 +90,6 @@ void psa_write_thread_fn_call(psa_handle_t msg_handle, uint32_t outvec_idx, } __naked -__section(".psa_interface_thread_fn_call") void psa_reply_thread_fn_call(psa_handle_t msg_handle, psa_status_t status) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_reply); @@ -106,14 +97,12 @@ void psa_reply_thread_fn_call(psa_handle_t msg_handle, psa_status_t status) #if CONFIG_TFM_DOORBELL_API == 1 __naked -__section(".psa_interface_thread_fn_call") void psa_notify_thread_fn_call(int32_t partition_id) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_notify); } __naked -__section(".psa_interface_thread_fn_call") void psa_clear_thread_fn_call(void) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_clear); @@ -121,14 +110,12 @@ void psa_clear_thread_fn_call(void) #endif /* CONFIG_TFM_DOORBELL_API == 1 */ __naked -__section(".psa_interface_thread_fn_call") void psa_panic_thread_fn_call(void) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_panic); } __naked -__section(".psa_interface_thread_fn_call") uint32_t psa_rot_lifecycle_state_thread_fn_call(void) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_get_lifecycle_state); @@ -138,21 +125,18 @@ uint32_t psa_rot_lifecycle_state_thread_fn_call(void) #if CONFIG_TFM_CONNECTION_BASED_SERVICE_API == 1 __naked -__section(".psa_interface_thread_fn_call") psa_handle_t psa_connect_thread_fn_call(uint32_t sid, uint32_t version) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_client_psa_connect); } __naked -__section(".psa_interface_thread_fn_call") void psa_close_thread_fn_call(psa_handle_t handle) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_client_psa_close); } __naked -__section(".psa_interface_thread_fn_call") void psa_set_rhandle_thread_fn_call(psa_handle_t msg_handle, void *rhandle) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_set_rhandle); @@ -162,14 +146,12 @@ void psa_set_rhandle_thread_fn_call(psa_handle_t msg_handle, void *rhandle) #if CONFIG_TFM_FLIH_API == 1 || CONFIG_TFM_SLIH_API == 1 __naked -__section(".psa_interface_thread_fn_call") void psa_irq_enable_thread_fn_call(psa_signal_t irq_signal) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_irq_enable); } __naked -__section(".psa_interface_thread_fn_call") psa_irq_status_t psa_irq_disable_thread_fn_call(psa_signal_t irq_signal) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_irq_disable); @@ -178,7 +160,6 @@ psa_irq_status_t psa_irq_disable_thread_fn_call(psa_signal_t irq_signal) /* This API is only used for FLIH. */ #if CONFIG_TFM_FLIH_API == 1 __naked -__section(".psa_interface_thread_fn_call") void psa_reset_signal_thread_fn_call(psa_signal_t irq_signal) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_reset_signal); @@ -188,7 +169,6 @@ void psa_reset_signal_thread_fn_call(psa_signal_t irq_signal) /* This API is only used for SLIH. */ #if CONFIG_TFM_SLIH_API == 1 __naked -__section(".psa_interface_thread_fn_call") void psa_eoi_thread_fn_call(psa_signal_t irq_signal) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_eoi); @@ -199,28 +179,24 @@ void psa_eoi_thread_fn_call(psa_signal_t irq_signal) #if PSA_FRAMEWORK_HAS_MM_IOVEC __naked -__section(".psa_interface_thread_fn_call") const void *psa_map_invec_thread_fn_call(psa_handle_t msg_handle, uint32_t invec_idx) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_map_invec); } __naked -__section(".psa_interface_thread_fn_call") void psa_unmap_invec_thread_fn_call(psa_handle_t msg_handle, uint32_t invec_idx) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_unmap_invec); } __naked -__section(".psa_interface_thread_fn_call") void *psa_map_outvec_thread_fn_call(psa_handle_t msg_handle, uint32_t outvec_idx) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_partition_psa_map_outvec); } __naked -__section(".psa_interface_thread_fn_call") void psa_unmap_outvec_thread_fn_call(psa_handle_t msg_handle, uint32_t outvec_idx, size_t len) { @@ -231,7 +207,6 @@ void psa_unmap_outvec_thread_fn_call(psa_handle_t msg_handle, uint32_t outvec_id #ifdef TFM_PARTITION_NS_AGENT_MAILBOX __naked -__section(".psa_interface_thread_fn_call") psa_status_t agent_psa_call_thread_fn_call(psa_handle_t handle, uint32_t control, const struct client_params_t *params, @@ -242,7 +217,6 @@ psa_status_t agent_psa_call_thread_fn_call(psa_handle_t handle, #if CONFIG_TFM_CONNECTION_BASED_SERVICE_API == 1 __naked -__section(".psa_interface_thread_fn_call") psa_handle_t agent_psa_connect_thread_fn_call(uint32_t sid, uint32_t version, int32_t ns_client_id, const void *client_data) @@ -251,7 +225,6 @@ psa_handle_t agent_psa_connect_thread_fn_call(uint32_t sid, uint32_t version, } __naked -__section(".psa_interface_thread_fn_call") psa_status_t agent_psa_close_thread_fn_call(psa_handle_t handle, int32_t ns_client_id) { TFM_THREAD_FN_CALL_ENTRY(tfm_spm_agent_psa_close); diff --git a/secure_fw/spm/core/psa_read_write_skip_api.c b/secure_fw/spm/core/psa_read_write_skip_api.c index b5e84f096..252a234c0 100644 --- a/secure_fw/spm/core/psa_read_write_skip_api.c +++ b/secure_fw/spm/core/psa_read_write_skip_api.c @@ -47,7 +47,8 @@ size_t tfm_spm_partition_psa_read(psa_handle_t msg_handle, uint32_t invec_idx, * It is a fatal error if the input vector has already been mapped using * psa_map_invec(). */ - if (IOVEC_IS_MAPPED(handle, (invec_idx + INVEC_IDX_BASE))) { + if (IOVEC_IS_MAPPED(handle, (invec_idx + INVEC_IDX_BASE)) || + IOVEC_IS_UNMAPPED(handle, (invec_idx + INVEC_IDX_BASE))) { tfm_core_panic(); } @@ -115,7 +116,8 @@ size_t tfm_spm_partition_psa_skip(psa_handle_t msg_handle, uint32_t invec_idx, * It is a fatal error if the input vector has already been mapped using * psa_map_invec(). */ - if (IOVEC_IS_MAPPED(handle, (invec_idx + INVEC_IDX_BASE))) { + if (IOVEC_IS_MAPPED(handle, (invec_idx + INVEC_IDX_BASE)) || + IOVEC_IS_UNMAPPED(handle, (invec_idx + INVEC_IDX_BASE))) { tfm_core_panic(); } @@ -184,7 +186,8 @@ psa_status_t tfm_spm_partition_psa_write(psa_handle_t msg_handle, uint32_t outve * It is a fatal error if the output vector has already been mapped using * psa_map_outvec(). */ - if (IOVEC_IS_MAPPED(handle, (outvec_idx + OUTVEC_IDX_BASE))) { + if (IOVEC_IS_MAPPED(handle, (outvec_idx + OUTVEC_IDX_BASE)) || + IOVEC_IS_UNMAPPED(handle, (outvec_idx + OUTVEC_IDX_BASE))) { tfm_core_panic(); } diff --git a/secure_fw/spm/core/spm.h b/secure_fw/spm/core/spm.h index d023b3442..da0bf42ba 100644 --- a/secure_fw/spm/core/spm.h +++ b/secure_fw/spm/core/spm.h @@ -24,9 +24,14 @@ #include "load/partition_defs.h" #include "load/interrupt_defs.h" -#define TFM_HANDLE_STATUS_IDLE 0 /* Handle created */ -#define TFM_HANDLE_STATUS_ACTIVE 1 /* Handle in use */ -#define TFM_HANDLE_STATUS_TO_FREE 2 /* Free the handle */ +enum connection_status { + TFM_HANDLE_STATUS_IDLE = 0, /* Handle created, idle */ + TFM_HANDLE_STATUS_ACTIVE = 1, /* Handle in use */ + TFM_HANDLE_STATUS_TO_FREE = 2, /* Handle to be freed */ + TFM_HANDLE_STATUS_MAX = 3, + + _TFM_HANDLE_STATUS_PAD = UINT32_MAX, +}; /* The mask used for timeout values */ #define PSA_TIMEOUT_MASK PSA_BLOCK @@ -71,13 +76,7 @@ /* RoT connection handle list */ struct connection_t { - uint32_t status; /* - * Status of handle, three valid - * options: - * TFM_HANDLE_STATUS_ACTIVE, - * TFM_HANDLE_STATUS_IDLE and - * TFM_HANDLE_STATUS_TO_FREE - */ + enum connection_status status; struct partition_t *p_client; /* Caller partition */ const struct service_t *service; /* RoT service pointer */ psa_msg_t msg; /* PSA message body */ @@ -97,8 +96,9 @@ struct connection_t { uint32_t iovec_status; /* MM-IOVEC status */ #endif #if CONFIG_TFM_SPM_BACKEND_IPC == 1 - struct connection_t *p_handles; /* Handle(s) link */ - uintptr_t reply_value; /* Result of this operation, if aynchronous */ + struct connection_t *p_reqs; /* Request handle(s) link */ + struct connection_t *p_replied; /* Replied Handle(s) link */ + uintptr_t replied_value; /* Result of this operation */ #endif }; @@ -112,12 +112,12 @@ struct partition_t { #if CONFIG_TFM_SPM_BACKEND_IPC == 1 const struct runtime_metadata_t *p_metadata; struct context_ctrl_t ctx_ctrl; - struct thread_t thrd; /* IPC model */ - uintptr_t reply_value; + struct thread_t thrd; /* IPC model */ + struct connection_t *p_replied; /* Handle(s) to record replied connections */ #else - uint32_t state; /* SFN model */ + uint32_t state; /* SFN model */ #endif - struct connection_t *p_handles; + struct connection_t *p_reqs; /* Handle(s) to record request connections to service. */ struct partition_t *next; }; @@ -148,6 +148,14 @@ void spm_free_connection(struct connection_t *p_connection); /******************** Partition management functions *************************/ #if CONFIG_TFM_SPM_BACKEND_IPC == 1 + +/* + * Get the replied handles in the asynchnorous reply mode. The first handle to + * be replied is at the tail of list. Take the handle one by one and clean the + * asynchronous signal after all handles are operated. + */ +struct connection_t *spm_get_async_replied_handle(struct partition_t *partition); + /* * Lookup and grab the last spotted handles containing the message * by the given signal. Only ONE signal bit can be accepted in 'signal', @@ -333,8 +341,6 @@ psa_handle_t connection_to_handle(struct connection_t *p_connection); */ struct connection_t *handle_to_connection(psa_handle_t handle); -void update_caller_outvec_len(struct connection_t *handle); - /* Following PSA APIs are only needed by connection-based services */ #if CONFIG_TFM_CONNECTION_BASED_SERVICE_API == 1 diff --git a/secure_fw/spm/core/spm_connection_pool.c b/secure_fw/spm/core/spm_connection_pool.c index 5ba540eb8..8eb453c4d 100644 --- a/secure_fw/spm/core/spm_connection_pool.c +++ b/secure_fw/spm/core/spm_connection_pool.c @@ -10,6 +10,7 @@ #include "spm.h" #include "tfm_pools.h" #include "load/service_defs.h" +#include "private/assert.h" #if !(defined CONFIG_TFM_CONN_HANDLE_MAX_NUM) || (CONFIG_TFM_CONN_HANDLE_MAX_NUM == 0) #error "CONFIG_TFM_CONN_HANDLE_MAX_NUM must be defined and not zero." diff --git a/secure_fw/spm/core/spm_ipc.c b/secure_fw/spm/core/spm_ipc.c index 810cebd08..ea1c8ea97 100644 --- a/secure_fw/spm/core/spm_ipc.c +++ b/secure_fw/spm/core/spm_ipc.c @@ -11,6 +11,7 @@ #include #include #include +#include "async.h" #include "bitops.h" #include "config_impl.h" #include "config_spm.h" @@ -39,6 +40,8 @@ #include "load/asset_defs.h" #include "load/spm_load_api.h" #include "tfm_nspm.h" +#include "private/assert.h" +#include "uart_stdout.h" /* Partition and service runtime data list head/runtime data table */ static struct service_head_t services_listhead; @@ -48,6 +51,32 @@ struct service_t *stateless_services_ref_tbl[STATIC_HANDLE_NUM_LIMIT]; /* This API is only used in IPC backend. */ #if CONFIG_TFM_SPM_BACKEND_IPC == 1 +struct connection_t *spm_get_async_replied_handle(struct partition_t *partition) +{ + struct connection_t **pr_handle_iter, **prev = NULL, *handle = NULL; + struct critical_section_t cs_assert = CRITICAL_SECTION_STATIC_INIT; + + /* Remove tail of the list, which is the first item added */ + CRITICAL_SECTION_ENTER(cs_assert); + if (!partition->p_replied) { + tfm_core_panic(); + } + UNI_LIST_FOREACH_NODE_PNODE(pr_handle_iter, handle, + partition, p_replied) { + prev = pr_handle_iter; + } + handle = *prev; + UNI_LIST_REMOVE_NODE_BY_PNODE(prev, p_replied); + + /* Clear the signal if there are no more asynchronous responses waiting */ + if (!partition->p_replied) { + partition->signals_asserted &= ~ASYNC_MSG_REPLY; + } + CRITICAL_SECTION_LEAVE(cs_assert); + + return handle; +} + struct connection_t *spm_get_handle_by_signal(struct partition_t *p_ptn, psa_signal_t signal) { @@ -60,7 +89,7 @@ struct connection_t *spm_get_handle_by_signal(struct partition_t *p_ptn, /* Return the last found message which applies a FIFO mechanism. */ UNI_LIST_FOREACH_NODE_PNODE(pr_handle_iter, p_handle_iter, - p_ptn, p_handles) { + p_ptn, p_reqs) { if (p_handle_iter->service->p_ldinf->signal == signal) { last_found_handle_holder = pr_handle_iter; nr_found_msgs++; @@ -69,7 +98,7 @@ struct connection_t *spm_get_handle_by_signal(struct partition_t *p_ptn, if (last_found_handle_holder) { p_handle_iter = *last_found_handle_holder; - UNI_LIST_REMOVE_NODE_BY_PNODE(last_found_handle_holder, p_handles); + UNI_LIST_REMOVE_NODE_BY_PNODE(last_found_handle_holder, p_reqs); if (nr_found_msgs == 1) { p_ptn->signals_asserted &= ~signal; @@ -367,8 +396,8 @@ uint32_t tfm_spm_init(void) spm_init_connection_space(); - UNI_LISI_INIT_NODE(PARTITION_LIST_ADDR, next); - UNI_LISI_INIT_NODE(&services_listhead, next); + UNI_LIST_INIT_NODE(PARTITION_LIST_ADDR, next); + UNI_LIST_INIT_NODE(&services_listhead, next); /* Init the nonsecure context. */ tfm_nspm_ctx_init(); @@ -397,20 +426,9 @@ uint32_t tfm_spm_init(void) backend_init_comp_assuredly(partition, service_setting); } - return backend_system_run(); -} - -void update_caller_outvec_len(struct connection_t *handle) -{ - uint32_t i; + #if defined(CONFIG_TFM_LOG_SHARE_UART) + stdio_uninit(); + #endif - for (i = 0; i < PSA_MAX_IOVEC; i++) { - if (handle->msg.out_size[i] == 0) { - continue; - } - - SPM_ASSERT(handle->caller_outvec[i].base == handle->outvec_base[i]); - - handle->caller_outvec[i].len = handle->outvec_written[i]; - } + return backend_system_run(); } diff --git a/secure_fw/spm/core/spm_local_connection.c b/secure_fw/spm/core/spm_local_connection.c index 6657d6294..6475771b7 100644 --- a/secure_fw/spm/core/spm_local_connection.c +++ b/secure_fw/spm/core/spm_local_connection.c @@ -92,7 +92,14 @@ psa_status_t spm_validate_connection(const struct connection_t *p_connection) void spm_free_connection(struct connection_t *p_connection) { + /* In debug builds, overwrite the status to catch use-after-free bugs */ +#ifndef NDEBUG + SPM_ASSERT(p_connection != NULL); + + p_connection->status = TFM_HANDLE_STATUS_MAX; +#else (void)p_connection; +#endif free_conn_from_stack_top(); } diff --git a/secure_fw/spm/core/tfm_boot_data.c b/secure_fw/spm/core/tfm_boot_data.c index d1ad7edaf..e78ae5bb4 100644 --- a/secure_fw/spm/core/tfm_boot_data.c +++ b/secure_fw/spm/core/tfm_boot_data.c @@ -130,7 +130,7 @@ void tfm_core_validate_boot_data(void) #ifdef BOOT_DATA_AVAILABLE struct tfm_boot_data *boot_data; - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; if (boot_data->header.tlv_magic == SHARED_DATA_TLV_INFO_MAGIC) { is_boot_data_valid = BOOT_DATA_VALID; @@ -176,9 +176,9 @@ void tfm_core_get_boot_data_handler(uint32_t args[]) #ifdef BOOT_DATA_AVAILABLE /* Get the boundaries of TLV section */ - boot_data = (struct tfm_boot_data *)BOOT_TFM_SHARED_DATA_BASE; - tlv_end = BOOT_TFM_SHARED_DATA_BASE + boot_data->header.tlv_tot_len; - offset = BOOT_TFM_SHARED_DATA_BASE + SHARED_DATA_HEADER_SIZE; + boot_data = (struct tfm_boot_data *)SHARED_BOOT_MEASUREMENT_BASE; + tlv_end = SHARED_BOOT_MEASUREMENT_BASE + boot_data->header.tlv_tot_len; + offset = SHARED_BOOT_MEASUREMENT_BASE + SHARED_DATA_HEADER_SIZE; #endif /* BOOT_DATA_AVAILABLE */ /* Add header to output buffer as well */ diff --git a/secure_fw/spm/core/tfm_pools.c b/secure_fw/spm/core/tfm_pools.c index 7d8a30587..3cbf42c4d 100644 --- a/secure_fw/spm/core/tfm_pools.c +++ b/secure_fw/spm/core/tfm_pools.c @@ -14,6 +14,7 @@ #include "internal_status_code.h" #include "cmsis_compiler.h" #include "utilities.h" +#include "private/assert.h" #include "lists.h" #include "tfm_pools.h" @@ -40,7 +41,7 @@ psa_status_t tfm_pool_init(struct tfm_pool_instance_t *pool, size_t poolsz, spm_memset(pool, 0, poolsz); /* Chain pool chunks */ - UNI_LISI_INIT_NODE(pool, next); + UNI_LIST_INIT_NODE(pool, next); pchunk = (struct tfm_pool_chunk_t *)pool->chunks; for (i = 0; i < num; i++) { diff --git a/secure_fw/spm/core/tfm_rpc.c b/secure_fw/spm/core/tfm_rpc.c index cdea72192..0ebb5adab 100644 --- a/secure_fw/spm/core/tfm_rpc.c +++ b/secure_fw/spm/core/tfm_rpc.c @@ -14,6 +14,7 @@ #include "ffm/psa_api.h" #include "tfm_rpc.h" #include "utilities.h" +#include "private/assert.h" #include "load/partition_defs.h" #include "tfm_psa_call_pack.h" diff --git a/secure_fw/spm/core/tfm_rpc.h b/secure_fw/spm/core/tfm_rpc.h index 18f784dcc..5cabc658f 100644 --- a/secure_fw/spm/core/tfm_rpc.h +++ b/secure_fw/spm/core/tfm_rpc.h @@ -161,6 +161,5 @@ void tfm_rpc_client_call_handler(void); */ void tfm_rpc_client_call_reply(void); #endif /* CONFIG_TFM_SPM_BACKEND_IPC == 1 */ - #endif /* TFM_PARTITION_NS_AGENT_MAILBOX */ #endif /* __TFM_RPC_H__ */ diff --git a/secure_fw/spm/core/tfm_svcalls.c b/secure_fw/spm/core/tfm_svcalls.c index c43b98e60..e6a99754f 100644 --- a/secure_fw/spm/core/tfm_svcalls.c +++ b/secure_fw/spm/core/tfm_svcalls.c @@ -204,6 +204,7 @@ static uint32_t handle_spm_svc_requests(uint32_t svc_number, uint32_t exc_return case TFM_SVC_SPM_INIT: exc_return = tfm_spm_init(); tfm_arch_check_msp_sealing(); + /* The following call does not return */ tfm_arch_free_msp_and_exc_ret(SPM_BOOT_STACK_BOTTOM, exc_return); break; diff --git a/secure_fw/spm/core/thread.c b/secure_fw/spm/core/thread.c index e83f0ae0d..aaf87e4cc 100644 --- a/secure_fw/spm/core/thread.c +++ b/secure_fw/spm/core/thread.c @@ -12,6 +12,7 @@ #include "thread.h" #include "tfm_arch.h" #include "utilities.h" +#include "private/assert.h" #include "critical_section.h" /* Declaration of current thread pointer. */ @@ -84,6 +85,7 @@ static void insert_by_prior(struct thread_t **head, struct thread_t *node) void thrd_start(struct thread_t *p_thrd, thrd_fn_t fn, thrd_fn_t exit_fn, void *param) { SPM_ASSERT(p_thrd != NULL); + SPM_ASSERT(fn != NULL); /* Insert a new thread with priority */ insert_by_prior(&LIST_HEAD, p_thrd); diff --git a/secure_fw/spm/include/ffm/psa_api.h b/secure_fw/spm/include/ffm/psa_api.h index 9f28e190e..d6e2e0951 100644 --- a/secure_fw/spm/include/ffm/psa_api.h +++ b/secure_fw/spm/include/ffm/psa_api.h @@ -61,15 +61,19 @@ #define IOVEC_IS_ACCESSED(handle, iovec_idx) \ ((((handle)->iovec_status) >> ((iovec_idx) * IOVEC_STATUS_BITS)) & \ IOVEC_ACCESSED_BIT) -#define SET_IOVEC_MAPPED(handle, iovec_idx) \ - (((handle)->iovec_status) |= (IOVEC_MAPPED_BIT << \ - ((iovec_idx) * IOVEC_STATUS_BITS))) -#define SET_IOVEC_UNMAPPED(handle, iovec_idx) \ - (((handle)->iovec_status) |= (IOVEC_UNMAPPED_BIT << \ - ((iovec_idx) * IOVEC_STATUS_BITS))) #define SET_IOVEC_ACCESSED(handle, iovec_idx) \ (((handle)->iovec_status) |= (IOVEC_ACCESSED_BIT << \ ((iovec_idx) * IOVEC_STATUS_BITS))) +#define SET_IOVEC_MAPPED(handle, iovec_idx) \ + do { \ + ((handle)->iovec_status) |= (IOVEC_MAPPED_BIT << ((iovec_idx) * IOVEC_STATUS_BITS)); \ + ((handle)->iovec_status) &= ~(IOVEC_UNMAPPED_BIT << ((iovec_idx) * IOVEC_STATUS_BITS)); \ + } while (0) +#define SET_IOVEC_UNMAPPED(handle, iovec_idx) \ + do { \ + ((handle)->iovec_status) |= (IOVEC_UNMAPPED_BIT << ((iovec_idx) * IOVEC_STATUS_BITS)); \ + ((handle)->iovec_status) &= ~(IOVEC_MAPPED_BIT << ((iovec_idx) * IOVEC_STATUS_BITS)); \ + } while (0) #endif /* PSA_FRAMEWORK_HAS_MM_IOVEC */ diff --git a/secure_fw/spm/include/lists.h b/secure_fw/spm/include/lists.h index 68a53faa2..181d3d731 100644 --- a/secure_fw/spm/include/lists.h +++ b/secure_fw/spm/include/lists.h @@ -54,7 +54,7 @@ struct bi_list_node_t { /********* Uni-directional list operations ********/ /* Initialize the head node. */ -#define UNI_LISI_INIT_NODE(head, link) do { \ +#define UNI_LIST_INIT_NODE(head, link) do { \ if ((head) != NULL) { \ (head)->link = NULL; \ } \ diff --git a/secure_fw/spm/include/private/assert.h b/secure_fw/spm/include/private/assert.h new file mode 100644 index 000000000..5f5174c99 --- /dev/null +++ b/secure_fw/spm/include/private/assert.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#ifndef __TFM_PRIV_ASSERT_H__ +#define __TFM_PRIV_ASSERT_H__ + +#include +#include "tfm_spm_log.h" + +#ifndef NDEBUG +#define SPM_ASSERT(cond) \ + do { \ + if (!(cond)) { \ + SPMLOG_INFMSG("Assert:"); \ + SPMLOG_INFMSG(__func__); \ + SPMLOG_INFMSGVAL(",", __LINE__); \ + while (1) { \ + ; \ + } \ + } \ + } while (0) +#else +#define SPM_ASSERT(cond) +#endif + +#define assert(cond) SPM_ASSERT(cond) + +#endif /* __TFM_PRIV_ASSERT_H__ */ diff --git a/secure_fw/spm/include/tfm_arch_v8m.h b/secure_fw/spm/include/tfm_arch_v8m.h index d302bc38b..43b47f0e8 100644 --- a/secure_fw/spm/include/tfm_arch_v8m.h +++ b/secure_fw/spm/include/tfm_arch_v8m.h @@ -13,6 +13,7 @@ #include "cmsis_compiler.h" #include "tfm_core_trustzone.h" #include "utilities.h" +#include "private/assert.h" #define EXC_RETURN_RES1 (0x1FFFFUL << 7) diff --git a/secure_fw/spm/include/utilities.h b/secure_fw/spm/include/utilities.h index bef9cddb0..4f76081a0 100644 --- a/secure_fw/spm/include/utilities.h +++ b/secure_fw/spm/include/utilities.h @@ -16,25 +16,9 @@ */ void tfm_core_panic(void); -/* SPM assert */ -#ifndef NDEBUG -#define SPM_ASSERT(cond) \ - do { \ - if (!(cond)) { \ - SPMLOG_INFMSG("Assert:"); \ - SPMLOG_INFMSG(__func__); \ - SPMLOG_INFMSGVAL(",", __LINE__); \ - while (1) \ - ; \ - } \ - } while (0) -#else -#define SPM_ASSERT(cond) -#endif - /* Get container structure start address from member */ #define TO_CONTAINER(ptr, type, member) \ - (type *)((unsigned long)(ptr) - offsetof(type, member)) + ((type *)((unsigned long)(ptr) - offsetof(type, member))) /* FixMe: Replace ERROR_MSG() in platform code with a suitable API */ #define ERROR_MSG(msg) SPMLOG_ERRMSG(msg "\r\n") diff --git a/toolchain_GNUARM.cmake b/toolchain_GNUARM.cmake index 4d053b849..08cfaea29 100644 --- a/toolchain_GNUARM.cmake +++ b/toolchain_GNUARM.cmake @@ -121,6 +121,8 @@ add_compile_options( -mthumb $<$:-std=c99> $<$:-std=c++11> + # Force DWARF version 4 for zephyr as pyelftools does not support version 5 at present + -gdwarf-4 $<$,$>:-g> ) diff --git a/tools/CMakeLists.txt b/tools/CMakeLists.txt index bf37274e8..8467ede01 100644 --- a/tools/CMakeLists.txt +++ b/tools/CMakeLists.txt @@ -159,12 +159,17 @@ set(MANIFEST_COMMAND -o ${CMAKE_BINARY_DIR}/generated ${PARSE_MANIFEST_QUIET_FLAG}) +set(NO_BUILD_CMD_FOR_MANIFEST 1) + +if(NO_BUILD_CMD_FOR_MANIFEST) +else() add_custom_command( OUTPUT ${CMAKE_BINARY_DIR}/generated COMMAND ${MANIFEST_COMMAND} DEPENDS ${MANIFEST_LISTS} ${GENERATED_FILE_LISTS} ${MANIFEST_FILES} ${TEMPLATE_FILES} ) +endif() add_custom_target( manifest_tool diff --git a/tools/modules/bin2hex.py b/tools/modules/bin2hex.py new file mode 100644 index 000000000..2098e3387 --- /dev/null +++ b/tools/modules/bin2hex.py @@ -0,0 +1,114 @@ +#!/usr/bin/python +# Copyright (c) 2008-2018 Alexander Belchenko +# All rights reserved. +# +# Redistribution and use in source and binary forms, +# with or without modification, are permitted provided +# that the following conditions are met: +# +# * Redistributions of source code must retain +# the above copyright notice, this list of conditions +# and the following disclaimer. +# * Redistributions in binary form must reproduce +# the above copyright notice, this list of conditions +# and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# * Neither the name of the author nor the names +# of its contributors may be used to endorse +# or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, +# BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +'''Intel HEX file format bin2hex convertor utility.''' + +VERSION = '2.3.0' + +if __name__ == '__main__': + import getopt + import os + import sys + + usage = '''Bin2Hex convertor utility. +Usage: + python bin2hex.py [options] INFILE [OUTFILE] + +Arguments: + INFILE name of bin file for processing. + Use '-' for reading from stdin. + + OUTFILE name of output file. If omitted then output + will be writing to stdout. + +Options: + -h, --help this help message. + -v, --version version info. + --offset=N offset for loading bin file (default: 0). +''' + + offset = 0 + + try: + opts, args = getopt.getopt(sys.argv[1:], "hv", + ["help", "version", "offset="]) + + for o, a in opts: + if o in ("-h", "--help"): + print(usage) + sys.exit(0) + elif o in ("-v", "--version"): + print(VERSION) + sys.exit(0) + elif o in ("--offset"): + base = 10 + if a[:2].lower() == '0x': + base = 16 + try: + offset = int(a, base) + except: + raise getopt.GetoptError('Bad offset value') + + if not args: + raise getopt.GetoptError('Input file is not specified') + + if len(args) > 2: + raise getopt.GetoptError('Too many arguments') + + except getopt.GetoptError: + msg = sys.exc_info()[1] # current exception + txt = 'ERROR: '+str(msg) # that's required to get not-so-dumb result from 2to3 tool + print(txt) + print(usage) + sys.exit(2) + + from intelhex import compat + + fin = args[0] + if fin == '-': + # read from stdin + fin = compat.get_binary_stdin() + elif not os.path.isfile(fin): + txt = "ERROR: File not found: %s" % fin # that's required to get not-so-dumb result from 2to3 tool + print(txt) + sys.exit(1) + + if len(args) == 2: + fout = args[1] + else: + # write to stdout + fout = sys.stdout # compat.get_binary_stdout() + + from intelhex import bin2hex + sys.exit(bin2hex(fin, fout, offset)) diff --git a/zephyr/module.yml b/zephyr/module.yml new file mode 100644 index 000000000..53d4569bd --- /dev/null +++ b/zephyr/module.yml @@ -0,0 +1,10 @@ +name: trusted-firmware-m + +build: + cmake-ext: True + kconfig-ext: True + +security: + external-references: + - cpe:2.3:o:arm:trusted_firmware-m:2.1.2:-:*:*:*:*:*:* + - pkg:generic/trusted-firmware-m@TF-Mv2.1.2?vcs_url=git%2Bhttps://review.trustedfirmware.org/TF-M/trusted-firmware-m