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Update datasheets (#119)
- Update datasheets to match latest public firmware - Fix formatting in glossary sections
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‎source/Hardware Guide/Datasheets/bno055.rst‎

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -99,38 +99,35 @@ All IMU data is signed with the exception of the calibration status bits (last
9999
byte in the frame). The unit conversions for each of these measurements are as
100100
follows:
101101

102-
- Euler angle (Tait-Bryan formalism)
102+
Euler angle (Tait-Bryan formalism)
103+
- Pitch: -180 to 180 degrees
104+
- Roll: -90 to 90 degrees
105+
- Yaw: 0 to 360 degrees
103106

104-
- Yaw: 0 to 360 degrees
105-
- Roll: -180 to 180 degrees
106-
- Pitch: -90 to 90 degrees
107+
.. math::
107108
108-
.. math::
109+
1^{\circ} = 16\ LSB
109110
110-
1^{\circ} = 16\ LSB
111+
Quaternion
112+
.. math::
111113
112-
- Quaternion
114+
1 = 2^{14}\ LSB
113115
114-
.. math::
116+
Acceleration & Gravity Vector
117+
.. math::
115118
116-
1 = 2^{14}\ LSB
119+
1\ m/s^2 = 100\ LSB
117120
118-
- Acceleration & Gravity Vector
121+
Temperature
122+
.. math::
119123
120-
.. math::
124+
1^{\circ}C = 1\ LSB
121125
122-
1\ m/s^2 = 100\ LSB
123-
124-
- Temperature
125-
126-
.. math::
127-
128-
1^{\circ}C = 1\ LSB
129-
130-
- Calibration Status
131-
132-
- 0: not calibrated
133-
- 3: fully calibrated
126+
Calibration Status
127+
- 0: Not calibrated
128+
- 1: Poorly calibrated
129+
- 2: Partially Calibrated
130+
- 3: Fully calibrated
134131

135132
Host To Device Data Frames
136133
******************************************

‎source/Hardware Guide/Datasheets/fmc-digital-io.rst‎

Lines changed: 109 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22

33
FMC Host Digital IO Device
44
###########################################
5-
:Authors: Jonathan P. Newman
6-
:Version: 1
5+
:Authors: Jonathan P. Newman, Aarón Cuevas López
6+
:Version: 2
77
:IO: Frame Source, Frame Sink, Register Access
88
:ONIX ID: 18
99
:ONIX Hubs: :ref:`pcie_host`
@@ -46,26 +46,26 @@ The breakout to host serialization protocol is as follows:
4646

4747
|
4848
49-
Buttons
50-
Buttons press state. Each bit represents the press state of a single
51-
button in the 6-buttons bank.
49+
Buttons
50+
Buttons press state. Each bit represents the press state of a single
51+
button in the 6-buttons bank.
5252

53-
- 0: Up
54-
- 1: Down
53+
- 0: Up
54+
- 1: Down
5555

56-
Digital In
57-
Digital input port. Each bit represents state of a signal line in the
58-
8-bit port.
56+
Digital In
57+
Digital input port. Each bit represents state of a signal line in the
58+
8-bit port.
5959

60-
- 0: Low
61-
- 1: High
60+
- 0: Low
61+
- 1: High
6262

63-
Pnn
64-
Headstage port power state. Each bit represents the power state of one of
65-
the four headstage ports.
63+
Pnn
64+
Headstage port power state. Each bit represents the power state of one of
65+
the four headstage ports.
6666

67-
- 0: Power off
68-
- 1: Power on
67+
- 0: Power off
68+
- 1: Power on
6969

7070
A clock recovery circuit is required at the receiver to generate ``clk`` from
7171
``sclk`` in order to sample the ``dat`` lines.
@@ -93,67 +93,67 @@ The host to breakout serialization protocol is as follows:
9393

9494
|
9595
96-
CMD
97-
Two bit command word that determines what to do with SW.
98-
99-
- 0b00: Shift slow bits into slow shift register
100-
- 0b01: Validate and move slow shift register to outputs and set initial
101-
state to [0, ..., 0, slow1, slow0]. slow1 should be the desired MSB at
102-
next command.
103-
- 0b10: Reserved, same as 0b00 currently. Don't use.
104-
- 0b11: Reset
105-
106-
SW
107-
Two-bit "slow-word" part. These bits are accumulated over time in order
108-
to control the display state and non-timing critical apsects of the
109-
breakout board. For instance, LED colors and brightness, headstage lock
110-
state, etc. As of this writing, for :ref:`breakout`, a complete
111-
slow-word is as follows.
112-
113-
.. wavedrom::
114-
115-
{
116-
reg: [
117-
{bits: 1, name: "Acq. Running" },
118-
{bits: 1, name: "Acq. Reset Done" },
119-
{bits: 2, name: "Reserved" },
120-
{bits: 4, name: "LED Level" },
121-
{bits: 2, name: "LED Mode" },
122-
{bits: 2, name: "Port A Status" },
123-
{bits: 2, name: "Port B Status" },
124-
{bits: 2, name: "Port C Status" },
125-
{bits: 2, name: "Port D Status" },
126-
{bits: 12, name: "Analog IO Dir." },
127-
{bits: 2, name: "HARP Conf." },
128-
{bits: 16, name: "GPIO Dir." }
129-
],
130-
config: {bits: 48, lanes: 8, vflip: true, hflip: true, fontsize: 11}
131-
}
132-
133-
which are defined as follows:
134-
135-
- Acq. Running: Host hardware run state. 0 = not running, 1 = running
136-
- Acq. Reset Done: Host reset state. 0 = reset not complete, 1 = reset
137-
complete
138-
- Reserved: NA
139-
- LED Level: 4 bit register for general LED brighness. 0 = dimmest, 16 =
140-
brightest
141-
- LED Mode: 2 bit register for LED mode. 0 = all off, 1 = only
142-
power/running, 2 = power/running, pll, harp, 3 = all on
143-
- Port X Status: 2 bit register describing the headstage port state. 00:
144-
power off, 01: power on, 10: locked, 11: device map good.
145-
- Analog IO Dir.: 12 bit register describing the direcitonality of each
146-
of the analog inputs. 0 = input, 1 = output.
147-
- HARP Config.: 2 bit register for possible future harp configuration.
148-
- GPIO Dir.: 16 bit register for possible future digital io
149-
directionality configuration.
150-
151-
Digital Out
152-
Digital output port state. Each bit represents state of an output signal
153-
line in the 8-bit port.
154-
155-
- 0: Low
156-
- 1: High
96+
CMD
97+
Two bit command word that determines what to do with SW.
98+
99+
- 0b00: Shift slow bits into slow shift register
100+
- 0b01: Validate and move slow shift register to outputs and set initial
101+
state to [0, ..., 0, slow1, slow0]. slow1 should be the desired MSB at
102+
next command.
103+
- 0b10: Reserved, same as 0b00 currently. Don't use.
104+
- 0b11: Reset
105+
106+
SW
107+
Two-bit "slow-word" part. These bits are accumulated over time in order
108+
to control the display state and non-timing critical apsects of the
109+
breakout board. For instance, LED colors and brightness, headstage lock
110+
state, etc. As of this writing, for :ref:`breakout`, a complete
111+
slow-word is as follows.
112+
113+
.. wavedrom::
114+
115+
{
116+
reg: [
117+
{bits: 1, name: "Acq. Running" },
118+
{bits: 1, name: "Acq. Reset Done" },
119+
{bits: 2, name: "Reserved" },
120+
{bits: 4, name: "LED Level" },
121+
{bits: 2, name: "LED Mode" },
122+
{bits: 2, name: "Port A Status" },
123+
{bits: 2, name: "Port B Status" },
124+
{bits: 2, name: "Port C Status" },
125+
{bits: 2, name: "Port D Status" },
126+
{bits: 12, name: "Analog IO Dir." },
127+
{bits: 2, name: "HARP Conf." },
128+
{bits: 16, name: "GPIO Dir." }
129+
],
130+
config: {bits: 48, lanes: 8, vflip: true, hflip: true, fontsize: 11}
131+
}
132+
133+
which are defined as follows:
134+
135+
- Acq. Running: Host hardware run state. 0 = not running, 1 = running
136+
- Acq. Reset Done: Host reset state. 0 = reset not complete, 1 = reset
137+
complete
138+
- Reserved: NA
139+
- LED Level: 4 bit register for general LED brighness. 0 = dimmest, 16 =
140+
brightest
141+
- LED Mode: 2 bit register for LED mode. 0 = all off, 1 = only
142+
power/running, 2 = power/running, pll, harp, 3 = all on
143+
- Port X Status: 2 bit register describing the headstage port state. 00:
144+
power off, 01: power on, 10: locked, 11: device map good.
145+
- Analog IO Dir.: 12 bit register describing the direcitonality of each
146+
of the analog inputs. 0 = input, 1 = output.
147+
- HARP Config.: 2 bit register for possible future harp configuration.
148+
- GPIO Dir.: 16 bit register for possible future digital io
149+
directionality configuration.
150+
151+
Digital Out
152+
Digital output port state. Each bit represents state of an output signal
153+
line in the 8-bit port.
154+
155+
- 0: Low
156+
- 1: High
157157

158158
A clock recovery circuit is required at the receiver to generate ``clk`` from
159159
``sclk`` in order to sample the ``dat`` line.
@@ -203,9 +203,9 @@ Register Programming
203203
- LEDLVL
204204
- R/W
205205
- On Reset
206-
- 0x0007
206+
- 0x0003
207207
- None
208-
- The four LSBs dertermine the overall LED brightness. Brightness
208+
- The four LSBs determine the overall LED brightness. Brightness
209209
increases linearly with this register's 0-15 value.
210210

211211
* - 0x03
@@ -222,7 +222,33 @@ Register Programming
222222
- On Reset
223223
- 0x0000
224224
- None
225-
- GPIO configuraiton. Reserved for future use.
225+
- GPIO configuration. Reserved for future use.
226+
227+
* - 0x05
228+
- CLKHZ
229+
- R
230+
- N/A
231+
- N/A
232+
- None
233+
- The system clock frequency in Hz
234+
235+
* - 0x06
236+
- SPACING
237+
- R/W
238+
- On Reset
239+
- 0x0000
240+
- None
241+
- Minimum CLK_HZ cycles between samples. Can be used to debounce inputs.
242+
Ignored if SAMPLING > 0.
243+
244+
* - 0x07
245+
- SAMPLING
246+
- R/W
247+
- On Reset
248+
- 0x0000
249+
- None
250+
- If > 0, produce one sample with each SAMPLING value of the CLK_HZ clock.
251+
regardless of if there are changes in digital input state or not.
226252

227253
.. _onidatasheet_fmc_digital_io_d2h:
228254

@@ -254,8 +280,6 @@ current digital input and user input state.
254280
config: {bits: 224, lanes: 7, vflip: true, hflip: true, fontsize: 11}
255281
}
256282

257-
|
258-
259283
Input Port State
260284
8-bit input port state
261285

@@ -287,5 +311,5 @@ output port state:
287311

288312
|
289313
290-
Output Port State
291-
8-bit output port state
314+
Output Port State
315+
8-bit output port state

‎source/Hardware Guide/Datasheets/fmc-link-control.rst‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ Register Programming
109109
- R
110110
- When LOCK or PASS change
111111
- 0
112-
- None
112+
- None
113113
- Link state
114114

115115
* Bit 0: LOCK
@@ -123,7 +123,7 @@ Register Programming
123123
- None
124124
- Misc. options for the link device
125125

126-
* Bit 0: `0` Port auto-shutdown disabled `1` Port auto-shutdown enabled
126+
* Bit 0: `0` Port auto-shutdown disabled `1` Port auto-shutdown enabled
127127

128128
.. _onidatasheet_fmc_link_control_d2h:
129129

@@ -158,28 +158,28 @@ Each frame transmitted to the host is structured as follows:
158158
This device produces frames when triggered by the **CV**, **PP**, or **SL**
159159
bits. These are defined as follows:
160160

161-
CV
162-
Codeword valid. Indicates that the Status Codeword field has valid data.
163-
A frame is produced when this bit goes high. The codeword meaning is
164-
hub-dependent. See hub documentation for definitions.
161+
CV
162+
Codeword valid. Indicates that the Status Codeword field has valid data.
163+
A frame is produced when this bit goes high. The codeword meaning is
164+
hub-dependent. See hub documentation for definitions.
165165

166-
PP
167-
Parity check pass. This bit reflects the state of the PASS pin on the
168-
DS90UB9x4 deserializer.
166+
PP
167+
Parity check pass. This bit reflects the state of the PASS pin on the
168+
DS90UB9x4 deserializer.
169169

170-
- 0b0: One or more errors were detected in the received payload.
171-
- 0b1: Error free transmission in forward channel operation.
170+
- 0b0: One or more errors were detected in the received payload.
171+
- 0b1: Error free transmission in forward channel operation.
172172

173-
A frame is produced whenever this bit changes state.
173+
A frame is produced whenever this bit changes state.
174174

175-
SL
176-
SERDES lock. This bit reflects the state of the LOCK pin on the DS90UB9x4
177-
deserializer, which monitors the lock status of FPD-Link III channel.
175+
SL
176+
SERDES lock. This bit reflects the state of the LOCK pin on the DS90UB9x4
177+
deserializer, which monitors the lock status of FPD-Link III channel.
178178

179-
- 0b0: PLL is unlocked link is down.
180-
- 0b1: PLL is locked, link is active.
179+
- 0b0: PLL is unlocked link is down.
180+
- 0b1: PLL is locked, link is active.
181181

182-
A frame is produced whenever this bit changes state.
182+
A frame is produced whenever this bit changes state.
183183

184184
Host To Device Data Frames
185185
******************************************

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