Problem when Make Verilate

[Aleone7]

Hello everyone,

We are 3 students to work on optimisation for CVA6 processor. We have been started the installation on our virtual machine (Debian version 11.5.0). We have followed the "getting started instructions":

we made the Checkout Repo

then we have installed the toolchain risv-gnu-toolchain

and we have started to Install Verilator Simulation Flow
-->export RISCV=/opt/riscv
-->./ci/setup.sh --> I have verifying that ventilator has been correctly installed (it is the version 4.110)

And when we enter the instruction make verilate it happens this: the VM start to run instructions and at a point it crashed and after a while the VM just restart. --> That's why I was not able to catch all instruction and paste it there but I have attached a picture of the screen when the VM crashed.

I hope I post my issue in the good section, I'm not very familiar with GitHub.

Thanks for your help,

Antoine

[gent-bujupaj]

Greetings,

Have you made sure that all the needed prerequisites are installed?
I noticed my self that the running Verilator is very computationally expensive, and in my case, it often happened that the VM crashed.
Have you checked if a work-ver file is created? Other than that, you could probably change on the Make file the architecture from default 64-bit to a 32-bit. Maybe it does not need that much computation.
Hope you manage to solve it !

Best Regards,
Gent