feat: initial code for memcpy chip

Author: pjabbarzade

Cargo.lock

@@ -61,6 +61,8 @@ members = [
     "extensions/ecc/tests",
     "extensions/pairing/circuit",
     "extensions/pairing/guest",
+    "extensions/memcpy/circuit",
+    "extensions/memcpy/transpiler",
     "guest-libs/ff_derive/",
     "guest-libs/k256/",
     "guest-libs/p256/",

Cargo.toml

@@ -3,7 +3,7 @@ use openvm_circuit_primitives_derive::AlignedBorrow;
 use openvm_stark_backend::{
     interaction::InteractionBuilder,
     p3_air::AirBuilder,
-    p3_field::{Field, FieldAlgebra},
+    p3_field::{Field, FieldAlgebra, PrimeField32},
 };
 
 use crate::{
@@ -58,6 +58,14 @@ pub struct LessThanAuxCols<T, const AUX_LEN: usize> {
     pub lower_decomp: [T; AUX_LEN],
 }
 
+impl<F: PrimeField32, const AUX_LEN: usize> Default for LessThanAuxCols<F, AUX_LEN> {
+    fn default() -> Self {
+        Self {
+            lower_decomp: [F::ZERO; AUX_LEN],
+        }
+    }
+}
+
 /// This is intended for use as a **SubAir**, not as a standalone Air.
 ///
 /// This SubAir constrains that `x < y` when `count != 0`, assuming

crates/circuits/primitives/src/assert_less_than/mod.rs

@@ -252,30 +252,7 @@ memcpy:
 	addi	a3, a4, 16
 	li	a4, 16
 .LBBmemcpy0_9:
-	lw	a6, -12(a3)
-	srli	a5, a5, 24
-	slli	a7, a6, 8
-	lw	t0, -8(a3)
-	or	a5, a7, a5
-	sw	a5, 0(a1)
-	srli	a5, a6, 24
-	slli	a6, t0, 8
-	lw	a7, -4(a3)
-	or	a5, a6, a5
-	sw	a5, 4(a1)
-	srli	a6, t0, 24
-	slli	t0, a7, 8
-	lw	a5, 0(a3)
-	or	a6, t0, a6
-	sw	a6, 8(a1)
-	srli	a6, a7, 24
-	slli	a7, a5, 8
-	or	a6, a7, a6
-	sw	a6, 12(a1)
-	addi	a1, a1, 16
-	addi	a2, a2, -16
-	addi	a3, a3, 16
-	bltu	a4, a2, .LBBmemcpy0_9
+	memcpy_loop 1
 	addi	a4, a3, -13
 	j	.LBBmemcpy0_25
 .LBBmemcpy0_11:
@@ -288,18 +265,7 @@ memcpy:
 	bltu	a2, a1, .LBBmemcpy0_15
 	li	a1, 15
 .LBBmemcpy0_14:
-	lw	a5, 0(a4)
-	lw	a6, 4(a4)
-	lw	a7, 8(a4)
-	lw	t0, 12(a4)
-	sw	a5, 0(a3)
-	sw	a6, 4(a3)
-	sw	a7, 8(a3)
-	sw	t0, 12(a3)
-	addi	a4, a4, 16
-	addi	a2, a2, -16
-	addi	a3, a3, 16
-	bltu	a1, a2, .LBBmemcpy0_14
+	memcpy_loop 0
 .LBBmemcpy0_15:
 	andi	a1, a2, 8
 	beqz	a1, .LBBmemcpy0_17
@@ -325,30 +291,7 @@ memcpy:
 	addi	a3, a4, 16
 	li	a4, 18
 .LBBmemcpy0_20:
-	lw	a6, -12(a3)
-	srli	a5, a5, 8
-	slli	a7, a6, 24
-	lw	t0, -8(a3)
-	or	a5, a7, a5
-	sw	a5, 0(a1)
-	srli	a5, a6, 8
-	slli	a6, t0, 24
-	lw	a7, -4(a3)
-	or	a5, a6, a5
-	sw	a5, 4(a1)
-	srli	a6, t0, 8
-	slli	t0, a7, 24
-	lw	a5, 0(a3)
-	or	a6, t0, a6
-	sw	a6, 8(a1)
-	srli	a6, a7, 8
-	slli	a7, a5, 24
-	or	a6, a7, a6
-	sw	a6, 12(a1)
-	addi	a1, a1, 16
-	addi	a2, a2, -16
-	addi	a3, a3, 16
-	bltu	a4, a2, .LBBmemcpy0_20
+	memcpy_loop 3
 	addi	a4, a3, -15
 	j	.LBBmemcpy0_25
 .LBBmemcpy0_22:
@@ -361,30 +304,7 @@ memcpy:
 	addi	a3, a4, 16
 	li	a4, 17
 .LBBmemcpy0_23:
-	lw	a6, -12(a3)
-	srli	a5, a5, 16
-	slli	a7, a6, 16
-	lw	t0, -8(a3)
-	or	a5, a7, a5
-	sw	a5, 0(a1)
-	srli	a5, a6, 16
-	slli	a6, t0, 16
-	lw	a7, -4(a3)
-	or	a5, a6, a5
-	sw	a5, 4(a1)
-	srli	a6, t0, 16
-	slli	t0, a7, 16
-	lw	a5, 0(a3)
-	or	a6, t0, a6
-	sw	a6, 8(a1)
-	srli	a6, a7, 16
-	slli	a7, a5, 16
-	or	a6, a7, a6
-	sw	a6, 12(a1)
-	addi	a1, a1, 16
-	addi	a2, a2, -16
-	addi	a3, a3, 16
-	bltu	a4, a2, .LBBmemcpy0_23
+	memcpy_loop 2
 	addi	a4, a3, -14
 .LBBmemcpy0_25:
 	mv	a3, a1

crates/toolchain/openvm/src/memcpy.s

@@ -26,6 +26,15 @@ impl<F: PrimeField32> MemoryBaseAuxCols<F> {
     }
 }
 
+impl<F: PrimeField32> Default for MemoryBaseAuxCols<F> {
+    fn default() -> Self {
+        Self {
+            prev_timestamp: F::ZERO,
+            timestamp_lt_aux: LessThanAuxCols::default(),
+        }
+    }
+}
+
 #[repr(C)]
 #[derive(Clone, Copy, Debug, AlignedBorrow)]
 pub struct MemoryWriteAuxCols<T, const N: usize> {
@@ -43,6 +52,11 @@ impl<const N: usize, T> MemoryWriteAuxCols<T, N> {
         self.base
     }
 
+    #[inline(always)]
+    pub fn set_base(&mut self, base: MemoryBaseAuxCols<T>) {
+        self.base = base;
+    }
+
     #[inline(always)]
     pub fn prev_data(&self) -> &[T; N] {
         &self.prev_data
@@ -80,6 +94,11 @@ impl<F: PrimeField32> MemoryReadAuxCols<F> {
         self.base
     }
 
+    #[inline(always)]
+    pub fn set_base(&mut self, base: MemoryBaseAuxCols<F>) {
+        self.base = base;
+    }
+
     /// Sets the previous timestamp **without** updating the less than auxiliary columns.
     #[inline(always)]
     pub fn set_prev(&mut self, timestamp: F) {

crates/vm/src/system/memory/offline_checker/columns.rs

@@ -5,13 +5,45 @@ mod columns;
 pub use bridge::*;
 pub use bus::*;
 pub use columns::*;
+use openvm_circuit_primitives::is_less_than::LessThanAuxCols;
+use openvm_stark_backend::p3_field::PrimeField32;
 
 #[repr(C)]
 #[derive(Debug, Clone)]
-pub struct MemoryReadAuxRecord {
+pub struct MemoryBaseAuxRecord {
     pub prev_timestamp: u32,
 }
 
+#[repr(C)]
+#[derive(Debug, Clone)]
+pub struct MemoryExtendedAuxRecord {
+    pub prev_timestamp: u32,
+    pub timestamp_lt_aux: [u32; AUX_LEN],
+}
+
+impl MemoryExtendedAuxRecord {
+    pub fn from_aux_cols<F: PrimeField32>(aux_cols: MemoryBaseAuxCols<F>) -> Self {
+        Self {
+            prev_timestamp: aux_cols.prev_timestamp.as_canonical_u32(),
+            timestamp_lt_aux: aux_cols
+                .timestamp_lt_aux
+                .lower_decomp
+                .map(|x| x.as_canonical_u32()),
+        }
+    }
+
+    pub fn to_aux_cols<F: PrimeField32>(&self) -> MemoryBaseAuxCols<F> {
+        MemoryBaseAuxCols {
+            prev_timestamp: F::from_canonical_u32(self.prev_timestamp),
+            timestamp_lt_aux: LessThanAuxCols {
+                lower_decomp: self.timestamp_lt_aux.map(|x| F::from_canonical_u32(x)),
+            },
+        }
+    }
+}
+
+pub type MemoryReadAuxRecord = MemoryBaseAuxRecord;
+
 #[repr(C)]
 #[derive(Debug, Clone)]
 pub struct MemoryWriteAuxRecord<T, const NUM_LIMBS: usize> {

crates/vm/src/system/memory/offline_checker/mod.rs

@@ -0,0 +1,86 @@
+# OpenVM Memcpy Extension
+
+This extension provides a custom RISC-V instruction `memcpy_loop` that optimizes memory copy operations by handling different alignment shifts efficiently.
+
+## Custom Instruction: `memcpy_loop shift`
+
+### Format
+```
+memcpy_loop shift
+```
+
+Where `shift` is an immediate value (0, 1, 2, or 3) representing the byte alignment shift.
+
+### RISC-V Encoding
+- **Opcode**: `0x73` (custom opcode)
+- **Funct3**: `0x0` (custom funct3)
+- **Immediate**: 12-bit signed immediate for shift value
+- **Format**: I-type instruction
+
+### Usage
+The `memcpy_loop` instruction is designed to replace repetitive shift-handling code in memcpy implementations. Instead of having separate code blocks for each shift value, you can use a single instruction:
+
+```assembly
+# Instead of this repetitive code:
+.Lshift_1:
+    lw      a5, 0(a4)
+    sb      a5, 0(a3)
+    srli    a1, a5, 8
+    sb      a1, 1(a3)
+    # ... more shift handling code
+
+# You can use:
+memcpy_loop 1    # Handles shift=1 case
+```
+
+### Benefits
+1. **Code Size Reduction**: Eliminates repetitive shift-handling code
+2. **Performance**: Optimized implementation in the circuit layer
+3. **Maintainability**: Single instruction handles all shift cases
+4. **Verification**: Zero-knowledge proof ensures correct execution
+
+## Implementation Details
+
+### Circuit Layer
+The instruction is implemented in the `MemcpyIterationAir` circuit which:
+- Reads 4 words (16 bytes) from memory
+- Applies the specified shift to combine words
+- Writes the result to the destination
+- Handles all shift values (0, 1, 2, 3) efficiently
+
+### Transpiler Extension
+The `MemcpyTranspilerExtension` translates the RISC-V instruction into OpenVM's internal format:
+- Parses I-type instruction format
+- Validates shift value (0-3)
+- Converts to OpenVM instruction with shift as operand
+
+### Example Usage
+See `example_memcpy_optimized.s` for a complete example showing how to use the custom instruction to optimize a memcpy implementation.
+
+## Building and Testing
+
+### Compilation
+```bash
+# Build the extension
+cargo build --package openvm-memcpy-circuit --package openvm-memcpy-transpiler
+
+# Check for compilation errors
+cargo check --package openvm-memcpy-circuit --package openvm-memcpy-transpiler
+```
+
+### Integration
+To use this extension in your OpenVM project:
+
+1. Add the transpiler extension to your OpenVM configuration
+2. Use the `memcpy_loop` instruction in your RISC-V assembly
+3. The circuit will handle the execution and verification
+
+## Architecture
+
+```
+RISC-V Assembly → Transpiler Extension → OpenVM Instruction → MemcpyIterationAir → Execution
+```
+
+The extension provides:
+- **Transpiler**: `extensions/memcpy/transpiler/` - Translates RISC-V to OpenVM
+- **Circuit**: `extensions/memcpy/circuit/` - Implements the instruction logic

extensions/memcpy/README.md

@@ -0,0 +1,24 @@
+[package]
+name = "openvm-memcpy-circuit"
+description = "OpenVM circuit extension for memcpy"
+version.workspace = true
+authors.workspace = true
+edition.workspace = true
+homepage.workspace = true
+repository.workspace = true
+
+[dependencies]
+openvm-circuit = { workspace = true }
+openvm-circuit-primitives = { workspace = true }
+openvm-circuit-primitives-derive = { workspace = true }
+openvm-circuit-derive = { workspace = true }
+openvm-instructions = { workspace = true }
+openvm-stark-backend = { workspace = true }
+openvm-memcpy-transpiler = { path = "../transpiler" }
+openvm-rv32im-transpiler = { workspace = true }
+openvm-rv32im-circuit = { workspace = true }
+
+derive-new.workspace = true
+derive_more = { workspace = true, features = ["from"] }
+serde.workspace = true
+strum = { workspace = true }