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Modified FPGA input content to explicity mention fields and their defaults.
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‎docs/source/user_guide/FPGA_index.rst‎

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@@ -14,25 +14,42 @@ Clocking
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The clocking section is located on the top left of the FPGA input section.
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.. image:: figures/FPGA-figures-clocking-clocking_selected.JPG
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Selecting the clocking section will display an empty table, click the "Add" button above the table to fill out clock information.
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Selecting the clocking section will display an empty table at the botton of the screen, click the "+Add" button above the table to fill out clock information.
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.. image:: figures/FPGA-figures-clocking-input_clock_info.JPG
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Select the clock source using the source dropdown, then provide a description (optional) and name for the clock. Enter the clock frequency and lastly it's state. Repeat the following steps for each clock used in the RTL design.
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1. Select the clock source using the source dropdown menu
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2. Provide a description *(optional)*
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3. Enter the Port/Signal name of the clock, *Note: Clock info will be required by all RPE sections, naming should be done clearly to be able to select the correct clocks.*
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4. Enter the clock frequency
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#. For **Boot Clock** & **RC Oscillator** sources refer to your device's datasheet and enter frequencies accordingly.
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5. Select the Clock State - default is **active**
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#. Active for regular clock signals
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#. Idle for unused not actively toggling or gated off signals
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Repeat the steps above for each clock used in the RTL design.
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FLE - Functional Logic Element
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FLE - Fabric Logic Element
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###############################
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The FLE section is located on the top right of the FPGA input section.
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.. image:: figures/FPGA-figures-FLE-FLE_selected.JPG
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Selecting the FLE section displays an empty table, click the "Add" button above the table to fill out the FLE info.
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Selecting the FLE section displays an empty table at the botton of the screen, click the "+Add" button above the table to fill out the FLE info.
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.. image:: figures/FPGA-figures-FLE-input_FLE_info.JPG
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Enter the no. of LUTs & flip-flops, then select the main clock from the clock dropdown. Lastly enter toggle rate, glitch factor and clock enable rate.
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1. Enter the name of your RTL module from your project's hierarchial view. *Note: You can leave this blank if you are providing FLE info for the entire design at once.*
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2. Enter the no. of LUTs
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3. Enter the no. of flip-flops
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4. Click on the clock dropdown, select the main clock responsible for running the design.
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5. Enter toggle rate - Industry standard default is **12.5%**
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6. Select glitch factor - default is **typical**
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#. Typical - Default option, for standard designs.
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#. Fast - For designs with high switching activity or complex logic.
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#. Very Fast - For high performance designs with high-frequency logic or heavy use of pipelining.
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7. Enter clock enable rate - Inudustry standard default is **50.0%**
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BRAM - Block Randon Access Memory
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##################################
@@ -47,9 +64,15 @@ Selecting the BRAM section displays an empty table, click the "Add" button above
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.. image:: figures/FPGA-figures-BRAM-input_BRAM_ports_info.JPG
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Select the type of BRAM used on the RTL design, then the no. of that type of BRAM used.
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Next fill out the read & write ports info. For each, select the clock, enter port width and senter write enable, read enable as well as toggle rates.
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1. Provide a name to label the BRAM function within the hierarchy (optional)
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2. Select the type of BRAM used in the RTL design
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3. Enter the no. of this type of BRAM used in the design
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4. Enter Port A-White & Port B-Read info based on the type of BRAM selected
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#. Clock - Select the clock which will be used to drive the BRAM Port
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#. width - Enter BRAM's channel width, default is **16**
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#. Write enable - Select based on BRAM type, default is **50% for SDP port A**
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#. Read enable - Select based on BRAM type, default is **50% for SDP port B**
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#. Toggle Rate - Industry standard default is **12.5%**
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DSP - Digital Signal Processor
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###############################
@@ -62,7 +85,15 @@ Selecting the DSP section displays an empty table, click the "Add" button above
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.. image:: figures/FPGA-figures-DSP-input_DSP_info.JPG
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Ener the no. of DSP multipliers used, select the DSP's mode, enter channel width for all inputs, select a clock, then select the pipeline type and enter toggle rate.
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1. Provide a name to label the DSP function within the hierarchy (optional)
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2. Enter the no. of DSP multipliers
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3. Select the DSP's mode from the dropdown menu
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4. Enter channel width for DSP inputs, *Note: The DSP Block is 20x18*
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#. Input-A width must be between **1 & 20**
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#. Input-B width must be between **1 & 18**
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5. Select a clock to drive the DSP
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6. Select the pipeline type
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7. Enter toggle rate - Industry standard default is **12.5%**
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IO - Input/Output
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##################
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.. image:: figures/FPGA-figures-IO-input_IO_info2.JPG
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Enter I/O port name, bus width, select clock, enter duty cycle, select IO direction & standard, drive strength (current in Amperes), slew rate, differential termination, pullup/pulldown resistors, data type, enter input enable rate, output enable rate, select synchronization & enter toggle rate
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1. Provide an IO port name
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2. Enter the IO's bus width
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3. Select main RTL clock to drive the IO
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4. Enter duty cycle - Inudustry standard default is **50.0%**
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5. Select IO direction
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#. Input
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#. Output
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#. Open-Drain
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#. Bi-Directional
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6. Select IO standard - **LVCMOS 1.8v (HR)** as default
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7. Select drive strength - current the output buffer can supply to drive a signal through the connected load
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8. Select slew rate - how quickly the output signal transitions between logic levels
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#. Fast - for high-speed signals
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#. Slow - for lower power designs
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9. Turn differential termination on/off - **off** as default
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10. Select pullup/pulldown resistors - **None** as default
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11. Select data type - default is **SDR**
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#. SDR (Single Data Rate)
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#. DDR (Double Data Rate)
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#. Clock
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#. Asynchronus
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12. Enter input enable rate - default is **50%** for inputs
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13. Enter output enable rate - default is **50%** for outputs
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14. select synchronization option - default is **none** for signals that are already clocked and don't cross domains
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15. Enter toggle rate - Industry standard default is **12.5%**

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