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refactor: disable all interrupts outside of inner impls
1 parent 8be3fba commit 54bd5be

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1 file changed

+4
-12
lines changed

1 file changed

+4
-12
lines changed

drv/stm32h7-qspi/src/lib.rs

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -235,9 +235,8 @@ impl Qspi {
235235
data: &[u8],
236236
) -> Result<(), QspiError> {
237237
let result = self.write_impl_inner(command, addr, data);
238-
if result.is_err() {
239-
self.disable_all_interrupts();
240-
}
238+
// Clean up by disabling our interrupt sources.
239+
self.disable_all_interrupts();
241240
result
242241
}
243242

@@ -329,9 +328,6 @@ impl Qspi {
329328
// We're now interested in transfer complete, not FIFO ready.
330329
self.wait_for_transfer_complete();
331330

332-
// Clean up by disabling our interrupt sources.
333-
self.disable_all_interrupts();
334-
335331
Ok(())
336332
}
337333

@@ -342,9 +338,8 @@ impl Qspi {
342338
out: &mut [u8],
343339
) -> Result<(), QspiError> {
344340
let result = self.read_impl_inner(command, addr, out);
345-
if result.is_err() {
346-
self.disable_all_interrupts();
347-
}
341+
// Clean up by disabling our interrupt sources.
342+
self.disable_all_interrupts();
348343
result
349344
}
350345

@@ -455,9 +450,6 @@ impl Qspi {
455450
// set, it appears.
456451
self.wait_for_transfer_complete();
457452

458-
// Clean up by disabling our interrupt sources.
459-
self.disable_all_interrupts();
460-
461453
Ok(())
462454
}
463455

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