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1 parent f7699d0 commit f0c8b61Copy full SHA for f0c8b61
drv/stm32h7-startup/src/lib.rs
@@ -154,7 +154,7 @@ pub fn system_init_custom(
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// Turn on CPU I/D caches to improve performance at the higher clock speeds
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// we're about to enable.
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cp.SCB.enable_icache();
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- cp.SCB.enable_dcache(&mut cp.CPUID);
+ //cp.SCB.enable_dcache(&mut cp.CPUID);
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// The Flash controller comes out of reset configured for 3 wait states.
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// That's approximately correct for 64MHz at VOS3, which is fortunate, since
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