There are three power rails missing from the temperature sensors list on Gimlet:
VPP_ABCD_A0
VPP_EFGH_A0
V1P8_SP3_A0 (shortened from V1P8_SP3_VDD_18_A0)

These are all on the ISL68224 controller at address b1011 100x

In this list of sensors, there is also only one temperature listed for the power rails that are regulated by Renesas power controllers, but there should be another temperature measurement, per controller IC, that is the internal controller temperature. I have not investigated Sidecar's list of sensors, but I would assume the Renesas controller temperatures on it are also missing.

export const sensorValues: SensorValues = {
  Southwest: 28.1,
  South: 28.54,
  Southeast: 25.66,
  U2_N0: 52.0,
  U2_N1: 34.0,
  U2_N2: 34.0,
  U2_N3: 34.0,
  U2_N4: 34.0,
  U2_N5: 34.0,
  U2_N6: 34.0,
  U2_N7: 33.0,
  U2_N8: 33.0,
  U2_N9: 33.0,
  t6: 46.88,
  V3P3_SP_A2: 34.0,
  V3P3_SYS_A0: 36.5,
  V5_SYS_A2: 36.25,
  V1P8_SYS_A2: 36.25,
  CPU: 57.5,
  VDD_VCORE: 40.0,
  VDD_MEM_ABCD: 41.0,
  VDDCR_SOC: 42.0,
  VDD_MEM_EFGH: 42.0,
  V54_FAN: 31.4,
  V54_HS_OUTPUT: 31.64,
  V0P96_NIC_VDD_A0HP: 37.5,
  Northeast: 50.54,
  North: 30.99,
  Northwest: 24.52,
  V12_SYS_A2: 39.5,
  DIMM_A0: 35.44,
  DIMM_A1: 35.62,
  DIMM_B0: 35.31,
  DIMM_B1: 34.75,
  DIMM_C0: 33.69,
  DIMM_C1: 33.0,
  DIMM_D0: 32.88,
  DIMM_D1: 32.56,
  DIMM_E0: 32.94,
  DIMM_E1: 32.88,
  DIMM_F0: 32.0,
  DIMM_F1: 31.38,
  DIMM_G0: 30.75,
  DIMM_G1: 30.62,
  DIMM_H0: 30.06,
  DIMM_H1: 29.94,
  M2_A: 32.0,
  M2_B: 33.0,
}

Based on this Hubris code, the measurement that's being used for the Renesas power rails is READ_TEMPERATURE_1, which represents the temperature of the hottest power stage in the rail. What's missing is something that pulls in READ_TEMPERATURE_2, which is the temperature of the controller chip itself:

The register address is the same for both the RAA229618 and the ISL68224 controllers.

A possible naming scheme could be:
CONT_[short rail list]

To indicate that it is the temperature of the controller itself, i.e.

CONT_CORE_MEM_ABCD
CONT_SOC_MEM_EFGH
CONT_VPP_1V8_SP3