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MIR Codegen: Full Stack Scheduling with Spilling #697
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A-codegenArea: code generation and MIRArea: code generation and MIRC-enhancementCategory: an issue proposing an enhancement or a PR with oneCategory: an issue proposing an enhancement or a PR with oneE-hardCall for participation: Hard difficulty. Experience needed to fix: A lot.Call for participation: Hard difficulty. Experience needed to fix: A lot.P-highHigh priorityHigh priority
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A-codegenArea: code generation and MIRArea: code generation and MIRC-enhancementCategory: an issue proposing an enhancement or a PR with oneCategory: an issue proposing an enhancement or a PR with oneE-hardCall for participation: Hard difficulty. Experience needed to fix: A lot.Call for participation: Hard difficulty. Experience needed to fix: A lot.P-highHigh priorityHigh priority
Summary
Extend the stack scheduler to handle arbitrary control-flow and >16 live values with spilling into memory.
Parent issue: #687
Context
When more than 16 values are live simultaneously, we exceed the EVM's DUP/SWAP visibility window. Values must be spilled to memory (MSTORE) and reloaded (MLOAD) when needed.
Additionally, at control-flow merge points (block boundaries), we need consistent stack shapes so that jumps land with the expected stack layout.
This is the most complex piece of the codegen pipeline.
Tasks
Canonical stack shape at block boundaries
Prolog/epilog reshuffles
Memory spilling
SpillSlotId → memory_offsetAbstractStack:MSTOREto spill slot, remove from abstract stack (keep logically live)MLOAD, push to stackSpilling heuristics
next_usedata from liveness to guide spillingLoop and complex CFG handling
Patterns to follow
From Venom:
From Sonatina:
Example: Spilling
Acceptance Criteria
Estimated Complexity
Extra Large - This is the hardest piece of the codegen pipeline
Dependencies
Risks