Problem
Currently the CI checks for rv32imac support. Theres been consensus around rv64im here.
Looking at the discrepancies between the two targets:
rv32 vs rv64
32 bit vs 64 bit is not that important right now, re compatibility because if it compiles for 32, then it most likely will compile for 64
C extension
The C extension is purely additive, so its not a big issue
A extension
This is important, because code that is compiled assuming the atomic extension may use atomic instructions and fault/panic on a zkVM that conforms to rv64im.
Suggested solutions
There are roughly two solutions:
- llvm has a lower-atomics pass that can be used when compiling to the zkVM related target
- Modify code to not require atomics
1) LLVM lower atomics pass
This is the easiest solution and depending on how LLVM lowers your code, it may be insignificant in terms of performance. Noting that fence opcodes are also no-ops in a single threaded context.
2) Modify code and dependencies
As of commit 385f86d the dependencies that would need changing are tracing-core, bytes, serde_core and radium.
bytes: This is supported, however it needs to be enabled in alloy-primitives. See here
tracing-core: This is an external dependency to this org/team, so is harder to change, however, fortunately, support was added here
radium: For rv32im, a fix has been released here however v0.7.0 is being used and it doesn't have that fix. Also note that the newer version doesn't check for rv64im, so this would break once we switch to rv64im.
serde_core: This seems to trace to the alloy-trie crate which enables rc unconditionally for serde here. I didn't check further if rc is needed or ways around it. This seems like it would entail a more general refactor of Arc
Problem
Currently the CI checks for
rv32imacsupport. Theres been consensus aroundrv64imhere.Looking at the discrepancies between the two targets:
rv32 vs rv64
32 bit vs 64 bit is not that important right now, re compatibility because if it compiles for 32, then it most likely will compile for 64
C extension
The C extension is purely additive, so its not a big issue
A extension
This is important, because code that is compiled assuming the atomic extension may use atomic instructions and fault/panic on a zkVM that conforms to rv64im.
Suggested solutions
There are roughly two solutions:
1) LLVM lower atomics pass
This is the easiest solution and depending on how LLVM lowers your code, it may be insignificant in terms of performance. Noting that fence opcodes are also no-ops in a single threaded context.
2) Modify code and dependencies
As of commit 385f86d the dependencies that would need changing are
tracing-core,bytes,serde_coreandradium.bytes: This is supported, however it needs to be enabled in alloy-primitives. See here
tracing-core: This is an external dependency to this org/team, so is harder to change, however, fortunately, support was added here
radium: For rv32im, a fix has been released here however v0.7.0 is being used and it doesn't have that fix. Also note that the newer version doesn't check for rv64im, so this would break once we switch to rv64im.
serde_core: This seems to trace to the
alloy-triecrate which enablesrcunconditionally for serde here. I didn't check further ifrcis needed or ways around it. This seems like it would entail a more general refactor ofArc