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axi_bus_compare: Fixes and changes from the PR, add README entry
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‎README.md‎

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@@ -61,6 +61,15 @@ In addition to the documents linked in the following table, we are setting up [d
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| [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) |
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| [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous slave and master ports. | |
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## Synthesizable Verification Modules
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The following modules are meant to be used for verification purposes only but are synthesizable to be used in FPGA environments.
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| Name | Description |
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|------------------------------------------------------|---------------------------------------------------------------------------------------------------------|
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| [`axi_bus_compare`](src/axi_bus_compare.sv) | Compares two buses of the same type (and in the same clock domain), returns events on mismatch. |
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| [`axi_slave_compare`](src/axi_slave_compare.sv) | Compares two slave devices of the same type (and in the same clock domain), returns events on mismatch. |
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### Simulation-Only Modules
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In addition to the modules above, which are available in synthesis and simulation, the following modules are available only in simulation. Those modules are widely used in our testbenches, but they are also suitable to build testbenches for AXI modules and systems outside this repository.

‎src/axi_bus_compare.sv‎

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@@ -12,6 +12,7 @@
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// Authors:
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// - Thomas Benz <[email protected]>
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`include "axi/assign.svh"
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/// Synthesizable test module comparing two AXI channels of the same type
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/// This module is meant to be used in FPGA-based verification.
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module axi_bus_compare #(
@@ -79,22 +80,23 @@ module axi_bus_compare #(
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// Channel Signals
8081
//-----------------------------------
8182
// assign request payload A
82-
assign axi_a_req_o.aw = axi_a_req_i.aw;
83-
assign axi_a_req_o.w = axi_a_req_i.w;
84-
assign axi_a_req_o.ar = axi_a_req_i.ar;
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`AXI_ASSIGN_AW_STRUCT(axi_a_req_o.aw, axi_a_req_i.aw)
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`AXI_ASSIGN_W_STRUCT(axi_a_req_o.w, axi_a_req_i.w)
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`AXI_ASSIGN_AR_STRUCT(axi_a_req_o.ar, axi_a_req_i.ar)
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// assign response payload A
87-
assign axi_a_rsp_o.r = axi_a_rsp_i.r;
88-
assign axi_a_rsp_o.b = axi_a_rsp_i.b;
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`AXI_ASSIGN_R_STRUCT(axi_a_rsp_o.r, axi_a_rsp_i.r)
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`AXI_ASSIGN_B_STRUCT(axi_a_rsp_o.b, axi_a_rsp_i.b)
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// assign request payload B
91-
assign axi_b_req_o.aw = axi_b_req_i.aw;
92-
assign axi_b_req_o.w = axi_b_req_i.w;
93-
assign axi_b_req_o.ar = axi_b_req_i.ar;
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`AXI_ASSIGN_AW_STRUCT(axi_b_req_o.aw, axi_b_req_i.aw)
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`AXI_ASSIGN_W_STRUCT(axi_b_req_o.w, axi_b_req_i.w)
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`AXI_ASSIGN_AR_STRUCT(axi_b_req_o.ar, axi_b_req_i.ar)
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// assign response payload B
96-
assign axi_b_rsp_o.r = axi_b_rsp_i.r;
97-
assign axi_b_rsp_o.b = axi_b_rsp_i.b;
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`AXI_ASSIGN_R_STRUCT(axi_b_rsp_o.r, axi_b_rsp_i.r)
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`AXI_ASSIGN_B_STRUCT(axi_b_rsp_o.b, axi_b_rsp_i.b)
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// fifo handshaking signals A
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id_t fifo_valid_aw_a, fifo_ready_aw_a;
@@ -314,40 +316,38 @@ module axi_bus_compare #(
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// Input Handshaking A
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//-----------------------------------
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always_comb begin : gen_handshaking_a
317-
for (int id = 0; id < 2**AxiIdWidth; id++) begin
318-
// aw
319-
// defaults
320-
fifo_valid_aw_a = '0;
321-
fifo_sel_ready_aw_a = '0;
322-
// assign according id
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fifo_valid_aw_a [axi_a_req_i.aw.id] = fifo_sel_valid_aw_a;
324-
fifo_sel_ready_aw_a = fifo_ready_aw_a[axi_a_req_i.aw.id];
325-
326-
327-
// b
328-
// defaults
329-
fifo_valid_b_a = '0;
330-
fifo_sel_ready_b_a = '0;
331-
// assign according id
332-
fifo_valid_b_a [axi_a_rsp_i.b.id] = fifo_sel_valid_b_a;
333-
fifo_sel_ready_b_a = fifo_ready_b_a[axi_a_rsp_i.b.id];
334-
335-
// ar
336-
// defaults
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fifo_valid_ar_a = '0;
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fifo_sel_ready_ar_a = '0;
339-
// assign according id
340-
fifo_valid_ar_a [axi_a_req_i.ar.id] = fifo_sel_valid_ar_a;
341-
fifo_sel_ready_ar_a = fifo_ready_ar_a[axi_a_req_i.ar.id];
342-
343-
// b
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// defaults
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fifo_valid_r_a = '0;
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fifo_sel_ready_r_a = '0;
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// assign according id
348-
fifo_valid_r_a [axi_a_rsp_i.r.id] = fifo_sel_valid_r_a;
349-
fifo_sel_ready_r_a = fifo_ready_r_a[axi_a_rsp_i.r.id];
350-
end
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// aw
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// defaults
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fifo_valid_aw_a = '0;
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fifo_sel_ready_aw_a = '0;
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// assign according id
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fifo_valid_aw_a [axi_a_req_i.aw.id] = fifo_sel_valid_aw_a;
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fifo_sel_ready_aw_a = fifo_ready_aw_a[axi_a_req_i.aw.id];
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// b
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// defaults
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fifo_valid_b_a = '0;
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fifo_sel_ready_b_a = '0;
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// assign according id
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fifo_valid_b_a [axi_a_rsp_i.b.id] = fifo_sel_valid_b_a;
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fifo_sel_ready_b_a = fifo_ready_b_a[axi_a_rsp_i.b.id];
335+
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// ar
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// defaults
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fifo_valid_ar_a = '0;
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fifo_sel_ready_ar_a = '0;
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// assign according id
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fifo_valid_ar_a [axi_a_req_i.ar.id] = fifo_sel_valid_ar_a;
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fifo_sel_ready_ar_a = fifo_ready_ar_a[axi_a_req_i.ar.id];
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// b
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// defaults
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fifo_valid_r_a = '0;
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fifo_sel_ready_r_a = '0;
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// assign according id
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fifo_valid_r_a [axi_a_rsp_i.r.id] = fifo_sel_valid_r_a;
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fifo_sel_ready_r_a = fifo_ready_r_a[axi_a_rsp_i.r.id];
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end
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@@ -516,40 +516,38 @@ module axi_bus_compare #(
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// Input Handshaking B
517517
//-----------------------------------
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always_comb begin : gen_handshaking_b
519-
for (int id = 0; id < 2**AxiIdWidth; id++) begin
520-
// aw
521-
// defaults
522-
fifo_valid_aw_b = '0;
523-
fifo_sel_ready_aw_b = '0;
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// assign according id
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fifo_valid_aw_b [axi_b_req_i.aw.id] = fifo_sel_valid_aw_b;
526-
fifo_sel_ready_aw_b = fifo_ready_aw_b[axi_b_req_i.aw.id];
527-
528-
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// b
530-
// defaults
531-
fifo_valid_b_b = '0;
532-
fifo_sel_ready_b_b = '0;
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// assign according id
534-
fifo_valid_b_b [axi_b_rsp_i.b.id] = fifo_sel_valid_b_b;
535-
fifo_sel_ready_b_b = fifo_ready_b_b[axi_b_rsp_i.b.id];
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// ar
538-
// defaults
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fifo_valid_ar_b = '0;
540-
fifo_sel_ready_ar_b = '0;
541-
// assign according id
542-
fifo_valid_ar_b [axi_b_req_i.ar.id] = fifo_sel_valid_ar_b;
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fifo_sel_ready_ar_b = fifo_ready_ar_b[axi_b_req_i.ar.id];
544-
545-
// b
546-
// defaults
547-
fifo_valid_r_b = '0;
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fifo_sel_ready_r_b = '0;
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// assign according id
550-
fifo_valid_r_b [axi_b_rsp_i.r.id] = fifo_sel_valid_r_b;
551-
fifo_sel_ready_r_b = fifo_ready_r_b[axi_b_rsp_i.r.id];
552-
end
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// aw
520+
// defaults
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fifo_valid_aw_b = '0;
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fifo_sel_ready_aw_b = '0;
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// assign according id
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fifo_valid_aw_b [axi_b_req_i.aw.id] = fifo_sel_valid_aw_b;
525+
fifo_sel_ready_aw_b = fifo_ready_aw_b[axi_b_req_i.aw.id];
526+
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// b
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// defaults
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fifo_valid_b_b = '0;
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fifo_sel_ready_b_b = '0;
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// assign according id
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fifo_valid_b_b [axi_b_rsp_i.b.id] = fifo_sel_valid_b_b;
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fifo_sel_ready_b_b = fifo_ready_b_b[axi_b_rsp_i.b.id];
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// ar
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// defaults
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fifo_valid_ar_b = '0;
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fifo_sel_ready_ar_b = '0;
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// assign according id
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fifo_valid_ar_b [axi_b_req_i.ar.id] = fifo_sel_valid_ar_b;
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fifo_sel_ready_ar_b = fifo_ready_ar_b[axi_b_req_i.ar.id];
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// b
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// defaults
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fifo_valid_r_b = '0;
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fifo_sel_ready_r_b = '0;
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// assign according id
549+
fifo_valid_r_b [axi_b_rsp_i.r.id] = fifo_sel_valid_r_b;
550+
fifo_sel_ready_r_b = fifo_ready_r_b[axi_b_rsp_i.r.id];
553551
end
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@@ -584,4 +582,4 @@ module axi_bus_compare #(
584582
assign mismatch_o = (|aw_mismatch_o) | (|w_mismatch_o) | (|b_mismatch_o) |
585583
(|ar_mismatch_o) | (|r_mismatch_o);
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587-
endmodule : axi_bus_compare
585+
endmodule

‎src/axi_slave_compare.sv‎

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@@ -12,6 +12,7 @@
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// Authors:
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// - Thomas Benz <[email protected]>
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`include "axi/assign.svh"
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/// Synthesizable test module comparing two AXI slaves of the same type.
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/// The reference response is always passed to the master, whereas the test response
1718
/// is discarded after handshaking.
@@ -123,8 +124,8 @@ module axi_slave_compare #(
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// assemble buses
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always_comb begin
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// request
126-
axi_ref_req_in = axi_mst_req_i;
127-
axi_test_req_in = axi_mst_req_i;
127+
`AXI_SET_REQ_STRUCT(axi_ref_req_in, axi_mst_req_i)
128+
`AXI_SET_REQ_STRUCT(axi_test_req_in, axi_mst_req_i)
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// overwrite valids in requests
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axi_ref_req_in.aw_valid = aw_valid_ref;
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axi_ref_req_in.ar_valid = ar_valid_ref;
@@ -140,7 +141,7 @@ module axi_slave_compare #(
140141
ar_ready_test = axi_test_rsp_in.ar_ready;
141142
w_ready_test = axi_test_rsp_in.w_ready;
142143
// response
143-
axi_mst_rsp_o = axi_ref_rsp_in;
144+
`AXI_SET_RESP_STRUCT(axi_mst_rsp_o, axi_ref_rsp_in)
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// overwrite readies
145146
axi_mst_rsp_o.aw_ready = aw_ready_mst;
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axi_mst_rsp_o.w_ready = w_ready_mst;
@@ -181,4 +182,4 @@ module axi_slave_compare #(
181182
.axi_b_rsp_i ( axi_test_rsp_i )
182183
);
183184

184-
endmodule : axi_slave_compare
185+
endmodule

‎test/tb_axi_bus_compare.sv‎

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@@ -109,8 +109,8 @@ module tb_axi_bus_compare #(
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// assemble buses
110110
always_comb begin
111111
// request
112-
axi_req_a_in = axi_req;
113-
axi_req_b_in = axi_req;
112+
`AXI_SET_REQ_STRUCT(axi_req_a_in, axi_req)
113+
`AXI_SET_REQ_STRUCT(axi_req_b_in, axi_req)
114114
// overwrite valids in requests
115115
axi_req_a_in.aw_valid = aw_valid_a;
116116
axi_req_a_in.ar_valid = ar_valid_a;
@@ -126,7 +126,7 @@ module tb_axi_bus_compare #(
126126
ar_ready_b = axi_rsp_b_in.ar_ready;
127127
w_ready_b = axi_rsp_b_in.w_ready;
128128
// response
129-
axi_rsp = axi_rsp_a_in;
129+
`AXI_SET_RESP_STRUCT(axi_rsp, axi_rsp_a_in)
130130
// overwrite readies
131131
axi_rsp.aw_ready = aw_ready;
132132
axi_rsp.w_ready = w_ready;
@@ -307,4 +307,4 @@ module tb_axi_bus_compare #(
307307
$finish();
308308
end
309309

310-
endmodule : tb_axi_bus_compare
310+
endmodule

‎test/tb_axi_slave_compare.sv‎

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@@ -236,4 +236,4 @@ module tb_axi_slave_compare #(
236236
$finish();
237237
end
238238

239-
endmodule : tb_axi_slave_compare
239+
endmodule

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