treewide: Add SCMI support

fpga/control_pulp-txilzu9eg/constraints/zcu102_peripherals.xdc

@@ -171,9 +171,20 @@ set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports pad_pms0_st
 set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports pad_pms0_strap_3_0]
 
 
-### JTAG
+### JTAG ON PMOD 0
 set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33} [get_ports jtag_tms_i_0]
 set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33} [get_ports jtag_tdi_i_0]
 set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports jtag_tdo_o_0]
 set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports jtag_tck_i_0]
 set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33} [get_ports jtag_trst_ni_0]
+
+# BOOTMODE SELECTION FROM SW13 ON ZCU102
+set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS33} [get_ports pad_bootsel0]
+set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS33} [get_ports pad_bootsel1]
+set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS33} [get_ports pad_bootsel_valid]
+set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS33} [get_ports pad_fc_fetch_en]
+set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS33} [get_ports pad_fc_fetch_en_valid]
+
+# MAILBOX TEST INTERRUPT SIGNALS ON PMOD 1
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports pad_doorbell_irq]
+set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports pad_completion_irq]

fpga/control_pulp-txilzu9eg/constraints/zcu102_timing.xdc

@@ -1,51 +1,39 @@
-// Timing constraints
+# Timing constraints
 
 # JTAG
 create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports jtag_tck_i_0]
 set_input_jitter tck 1.000
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_0]
 
 # minimize routing delay
-set_input_delay -clock tck -clock_fall 5.000 [get_ports jtag_tdi_0]
-set_input_delay -clock tck -clock_fall 5.000 [get_ports jtag_tms_0]
-set_output_delay -clock tck 5.000 [get_ports pad_jtag_tdo_0]
 
 set_max_delay -to [get_ports jtag_tdo_o_0] 20.000
 set_max_delay -from [get_ports jtag_tms_i_0] 20.000
 set_max_delay -from [get_ports jtag_tdi_i_0] 20.000
 
 # JTAG CDC
-set_max_delay -datapath_only \
-    -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] \
-    -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] \
-    20.000
 
-set_max_delay -datapath_only \
-    -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] \
-    -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
 
-set_max_delay -datapath_only \
-    -from [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] \
-    -to [get_pins control_pulp_exilzcu102_i/i_pulp_txilzu9eg/inst/i_pulp_txilzu9eg_0/i_control_pulp_txilzu9eg/i_control_pulp_with_mem/i_control_pulp_structs/i_soc_domain/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
 
 # Timers
-set_false_path -to [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_cluster_domain/cluster_i/cluster_peripherals_i/cluster_timer_wrap_i/timer_unit_i/s_ref_clk0_reg/D]
 
 # Periphs
-set_false_path -to [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_spim_gen[*].i_spim/u_spictrl/i_edgeprop/sync_a_reg[*]/D]
+set_false_path -to [get_pins {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_spim_gen[*].i_spim/u_spictrl/i_edgeprop/sync_a_reg[*]/D}]
 
 # CDC FIFOs in UDMA
-set_max_delay 50.000 -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/D]
-set_max_delay 50.000 -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*i_sync/*reg*/D]
+set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/D] 50.000
+set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/i_spill_register/spill_register_flushable_i/*reg*/C] 50.000
+set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*i_sync/*reg*/D] 50.000
+set_max_delay -through [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_udma/i_*/*dc*/i_cdc_fifo/i_*/*reg*/D] 50.000
 
 # reset signal
-set_false_path -from [get_pins {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_cluster_domain/cluster_i/rstgen_i/i_rstgen_bypass/synch_regs_q_reg[*]/C}]
 
 # Set ASYNC_REG attribute for ff synchronizers to place them closer together and
 # increase MTBF
-set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[0]}]
+set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[1]}]
+set_property ASYNC_REG true [get_cells {control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg[2]}]
 set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
-set_property ASYNC_REG true [get_cells control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_control_pulp/i_soc_domain/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
 
 # Create asynchronous clock group between slow-clk and SoC clock. Those clocks
 # are considered asynchronously and proper synchronization regs are in place
@@ -57,3 +45,4 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins control_
 
 ### Create asynchronous clock group between JTAG TCK and SoC clock.
 set_clock_groups -asynchronous -group [get_clocks tck] -group [get_clocks -of_objects [get_pins control_pulp_exilzcu102_i/i_pms_top_fpga/inst/i_control_pulp_fpga/i_system_clk_rst_gen/i_fpga_clk_gen/i_clk_manager/inst/mmcme4_adv_inst/CLKOUT0]]
+

fpga/control_pulp-txilzu9eg/rtl/pad_frame_fpga.sv

@@ -226,6 +226,9 @@ module pad_frame_fpga import control_pulp_pkg::*; (
   input logic [1:0]       out_cpu_socket_id_i,
   input logic [3:0]       out_cpu_strap_i,
 
+  input logic             out_doorbell,
+  input logic             out_completion,
+
 
   // PMB PADS INOUT WIRES
   inout wire              pad_pmb_vr1_pms0_sda,
@@ -319,6 +322,20 @@ module pad_frame_fpga import control_pulp_pkg::*; (
   inout wire              pad_uart1_pms0_rxd,
   inout wire              pad_uart1_pms0_txd,
 
+  inout wire              pad_bootsel0,
+  inout wire              pad_bootsel1,
+  inout wire              pad_bootsel_valid,
+  inout wire              pad_fc_fetch_en,
+  inout wire              pad_fc_fetch_en_valid,
+
+  inout wire              pad_doorbell_irq,
+  inout wire              pad_completion_irq,
+
+  output logic [1:0]      bootsel_o, 
+  output logic            bootsel_valid_o,
+  output logic            fc_fetch_en_o,
+  output logic            fc_fetch_en_valid_o,
+
   input logic [31:0][5:0] pad_cfg_i
 );
 
@@ -414,4 +431,16 @@ module pad_frame_fpga import control_pulp_pkg::*; (
   pad_functional_pu padinst_uart1_pms0_rxd( .OEN(~oe_uart1_rxd_i ), .I(out_uart1_rxd_i ), .O(in_uart1_rxd_o ), .PAD(pad_uart1_pms0_rxd ), .PEN(1'b0 ));
   pad_functional_pu padinst_uart1_pms0_txd( .OEN(~oe_uart1_txd_i ), .I(out_uart1_txd_i ), .O(in_uart1_txd_o ), .PAD(pad_uart1_pms0_txd ), .PEN(1'b0 ));
 
+
+  // BOOT SELECTION SIGNALS
+  pad_functional_pd padinst_pad_bootsel0          ( .OEN(1'b1), .I(), .O(bootsel_o[0]),         .PAD(pad_bootsel0), .PEN(1'b0 ));
+  pad_functional_pd padinst_pad_bootsel1          ( .OEN(1'b1), .I(), .O(bootsel_o[1]),         .PAD(pad_bootsel1), .PEN(1'b0 ));
+  pad_functional_pd padinst_pad_bootsel_valid     ( .OEN(1'b1), .I(), .O(bootsel_valid_o),      .PAD(pad_bootsel_valid), .PEN(1'b0 ));
+  pad_functional_pd padinst_pad_fc_fetch_en       ( .OEN(1'b1), .I(), .O(fc_fetch_en_o),        .PAD(pad_fc_fetch_en), .PEN(1'b0 ));
+  pad_functional_pd padinst_pad_fc_fetch_en_valid ( .OEN(1'b1), .I(), .O(fc_fetch_en_valid_o),  .PAD(pad_fc_fetch_en_valid), .PEN(1'b0 ));
+
+  // TEST INTERRUPT SIGNALS
+  pad_functional_pd padinst_pad_doorbell_irq       ( .OEN(1'b0), .I(out_doorbell), .O(),        .PAD(pad_doorbell_irq), .PEN(1'b0 ));
+  pad_functional_pd padinst_pad_completion_irq     ( .OEN(1'b0), .I(out_completion), .O(),      .PAD(pad_completion_irq), .PEN(1'b0 ));
+
 endmodule

fpga/control_pulp-txilzu9eg/rtl/pms_top_fpga.v

@@ -192,8 +192,21 @@ module pms_top_fpga (
 
   // UART PADS INOUT WIRES
   inout wire              pad_uart1_pms0_rxd,
-  inout wire              pad_uart1_pms0_txd
+  inout wire              pad_uart1_pms0_txd,
 
+  // BOOT SELECTION INOUT WIRES
+  inout wire              pad_bootsel0,
+  inout wire              pad_bootsel1,
+  inout wire              pad_bootsel_valid,
+  inout wire              pad_fc_fetch_en,
+  inout wire              pad_fc_fetch_en_valid,
+
+  // MAILBOX COMPLETION INTERRUPT OUTPUT WIRE
+  output wire             out_completion_irq,
+
+  // TEST INTERRUPT SIGNALS
+  inout wire pad_completion_irq,
+  inout wire pad_doorbell_irq
 );
 
   // SIM_STDOUT default is:
@@ -343,10 +356,10 @@ module pms_top_fpga (
     .ref_clk_i                 ( ref_clk                   ),
     .sys_clk_i                 ( /*sys_clk_i*/             ), // unconnected for FPGA
     .rst_ni                    ( pad_reset                 ), //active_low
-    .bootsel_valid_i           ( 1'b0                      ), //0 -> memory-mapped reg
-    .bootsel_i                 ( 3'b0                      ), //has no effect if bootsel_valid == 0
-    .fc_fetch_en_valid_i       ( 1'b0                      ), //0 -> memory-mapped reg
-    .fc_fetch_en_i             ( 1'b0                      ), //has no effect if fetch_en_valid == 0
+    // .bootsel_valid_i           ( 1'b0                      ), //0 -> memory-mapped reg
+    // .bootsel_i                 ( 3'b0                      ), //has no effect if bootsel_valid == 0
+    // .fc_fetch_en_valid_i       ( 1'b0                      ), //0 -> memory-mapped reg
+    // .fc_fetch_en_i             ( 1'b0                      ), //has no effect if fetch_en_valid == 0
     .jtag_tdo_o                ( jtag_tdo_o                ),
     .jtag_tck_i                ( jtag_tck_i                ),
     .jtag_tdi_i                ( jtag_tdi_i                ),
@@ -435,7 +448,15 @@ module pms_top_fpga (
     .pad_pms0_strap_0              ( pad_pms0_strap_0              ),
     .pad_pms0_strap_1              ( pad_pms0_strap_1              ),
     .pad_pms0_strap_2              ( pad_pms0_strap_2              ),
-    .pad_pms0_strap_3              ( pad_pms0_strap_3              )
+    .pad_pms0_strap_3              ( pad_pms0_strap_3              ),
+    .pad_bootsel0                  ( pad_bootsel0                  ),
+    .pad_bootsel1                  ( pad_bootsel1                  ),
+    .pad_bootsel_valid             ( pad_bootsel_valid             ),
+    .pad_fc_fetch_en               ( pad_fc_fetch_en               ),
+    .pad_fc_fetch_en_valid         ( pad_fc_fetch_en_valid         ),
+    .pad_completion_irq            ( pad_completion_irq            ),
+    .pad_doorbell_irq              ( pad_doorbell_irq              ),
+    .out_completion_irq            ( out_completion_irq            )
 );
 
 

fpga/control_pulp-txilzu9eg/tcl/control_pulp_exilzcu102.tcl

@@ -82,6 +82,11 @@ connect_bd_intf_net [get_bd_intf_pins i_pms_top_fpga/pl_axi_slv] \
 connect_bd_net [get_bd_pins i_pms_top_fpga/soc_clk_o] [get_bd_pins i_zynq_ps/maxihpm0_fpd_aclk]
 connect_bd_net [get_bd_pins i_pms_top_fpga/soc_clk_o] [get_bd_pins i_zynq_ps/saxihp0_fpd_aclk]
 
+
+# connect Completion interrupt from PL to PS
+connect_bd_net [get_bd_pins i_pms_top_fpga/out_completion_irq] [get_bd_pins i_zynq_ps/pl_ps_irq0]
+
+
 # make pad pins external
 source tcl/zcu102_pins_bd.tcl
 

fpga/control_pulp-txilzu9eg/tcl/zcu102_pins_bd.tcl

@@ -84,4 +84,11 @@ make_bd_pins_external \
   [get_bd_pins i_pms_top_fpga/jtag_tdi_i] \
   [get_bd_pins i_pms_top_fpga/jtag_tdo_o] \
   [get_bd_pins i_pms_top_fpga/jtag_tck_i] \
-  [get_bd_pins i_pms_top_fpga/jtag_trst_ni]
+  [get_bd_pins i_pms_top_fpga/jtag_trst_ni] \
+  [get_bd_pins i_pms_top_fpga/pad_bootsel0] \
+  [get_bd_pins i_pms_top_fpga/pad_bootsel1] \
+  [get_bd_pins i_pms_top_fpga/pad_bootsel_valid] \
+  [get_bd_pins i_pms_top_fpga/pad_fc_fetch_en] \
+  [get_bd_pins i_pms_top_fpga/pad_fc_fetch_en_valid] \
+  [get_bd_pins i_pms_top_fpga/pad_doorbell_irq] \
+  [get_bd_pins i_pms_top_fpga/pad_completion_irq] 

fpga/linux/board/xilzcu102/control_pulp.dtsi

@@ -1,36 +1,89 @@
-/* #include "xilinx/zynqmp-zcu102.dts" */
-
-/ {
-    reserved-memory {
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-
-        /* contiguous L3 memory for PULP: last 128MiB of DRAM */
-        pulp_reserved: pulp_l3_mem@78000000 {
-            compatible = "pulp,bigpulp";
-            no-map;
-            reg = <0x0 0x78000000 0x0 0x8000000>;
+/ { //space after / is needed
+    firmware{
+        scmi {
+            compatible ="arm,scmi";
+            mboxes = <&mhu_bdr 0 &mhu_bdr 0>; 
+            mbox-names = "tx","rx";
+            shmem = <&scp_scmi_mem>;
+            #address-cells = <1>;
+            #size-cells = <0>; 
+
+
+    		scmi_devpd: protocol@11 {
+		    	reg = <0x11>;
+		    	#power-domain-cells = <1>;
+	    	};
+
+
+            scmi_dvfs: protocol@13 {
+			    reg = <0x13>;
+			    #clock-cells = <1>;
+		    };
+
+            scmi_clk: protocol@14 {
+			    reg = <0x14>;
+			    #clock-cells = <1>;
+	    	};
+
+            // scmi_reset: protocol@16 {
+			//     reg = <0x16>;
+			//     #reset-cells = <1>;
+	    	// };
+
+            // scmi_volt: protocol@17 {
+			//     reg = <0x17>;
+			//     #clock-cells = <1>;
+	    	// };
+
         };
     };
 
-    /* Ensure serial terminal is enabled at boot. */
-    chosen {
-        bootargs = "earlycon clk_ignore_unused console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait";
-        stdout-path = "serial0:115200n8";
-    };
+};//root node has to stay here (if amba is included in this node -> syntax error)
+
+&cpu0 {
+	clocks = <&scmi_clk 0>;
+    power-domains = <&scmi_devpd 0>;
 };
 
-&amba {
-    pulp: pulp@a0000000 {
-        memory-region = <&pulp_reserved>;
-        compatible = "pulp,bigpulp";
-        reg = <0x0 0xa0000000 0x0 0x10000000>;
-        iommus = <&smmu 0x280>, <&smmu 0x281>, <&smmu 0x282>; /* FIXME: check this */
-    };
+&cpu1 {
+	clocks = <&scmi_clk 0>;
+    power-domains = <&scmi_devpd 0>;
 };
 
-/* FIXME: test why this hangs */
-/*&smmu {
-    status = "okay";
-};*/
+&cpu2 {
+	clocks = <&scmi_clk 0>;
+    power-domains = <&scmi_devpd 0>;
+};
+
+&cpu3 {
+	clocks = <&scmi_clk 0>;
+	power-domains = <&scmi_devpd 0>;
+};
+
+&amba{
+    scmi_sram: sram@A6000000{
+        compatible = "mmio-sram";
+        reg = <0x0 0xA6000000 0x0 0xA0>; 
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x0 0xA6000000 0xA0>; 
+
+        scp_scmi_mem: scp-shmem@0{
+            compatible = "arm,scmi-shmem";
+            reg = <0x0 0xA0>;
+        };
+    }; 
+
+    mhu_bdr: mhu@A60000A0{ 
+        #mbox-cells = <1>;
+        compatible = "arm,mhu", "arm,primecell";
+        clock-names = "clk_apb"; 
+        reg = <0x0 0xA60000A0 0x0 0x18>;
+        interrupt-parent = <&gic>; 
+        interrupts =    <0 89 1>,
+                        <0 91 1>,
+                        <0 92 1>;
+        interrupt-names = "mhu_bdr";
+        clocks = <&zynqmp_clk 31>;
+    };
+}; 

fpga/linux/configs/har_exilzcu102_defconfig

@@ -10,15 +10,17 @@ BR2_TOOLCHAIN_EXTERNAL_CUSTOM_GLIBC=y
 BR2_TOOLCHAIN_EXTERNAL_CXX=y
 BR2_TARGET_GENERIC_HOSTNAME="zynqmp"
 BR2_TARGET_GENERIC_ISSUE="Welcome to ZynqMP"
-BR2_TARGET_GENERIC_ROOT_PASSWD="change-this-root-pw"
+BR2_TARGET_GENERIC_ROOT_PASSWD="pms-root"
 BR2_SYSTEM_BIN_SH_BASH=y
 BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_CPULP_PATH)/board/common/overlay/"
 BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_CPULP_PATH)/board/common/post_build.sh $(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/post_build.sh"
 BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/post_image.sh"
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_GIT=y
-BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git"
-BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2019.2.01"
+# BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git"
+# BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2019.2.01"
+BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Antoniodv/linux-xlnx.git"
+BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="linux-scmi"
 BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
 BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_CPULP_PATH)/board/xilzcu102/kernel_config"
 BR2_LINUX_KERNEL_DTS_SUPPORT=y
@@ -42,6 +44,6 @@ BR2_PACKAGE_HOST_DOSFSTOOLS=y
 BR2_PACKAGE_HOST_GENIMAGE=y
 BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_PMSCTL=y
-BR2_PACKAGE_PMSRST=y
+BR2_PACKAGE_PMSRST
 BR2_PACKAGE_HOST_ZYNQ_MKBOOTIMAGE=y
 BR2_CPULP_BITSTREAM="$(BR2_EXTERNAL_CPULP_PATH)/../output/pms.bit"

fpga/linux/mhu_test/.gitignore

@@ -0,0 +1 @@
+pmsctl