misc: remove unused registers

Author: redchenjs

rtl/pulse_counter.sv

@@ -16,11 +16,11 @@ module pulse_counter(
     output logic [8:0] segment_led_2_out
 );
 
-parameter [31:0] CNT_1_S = 2 * 100 * 1000 * 1000;
+parameter [27:0] CNT_1_S = 2 * 100 * 1000 * 1000;
 
 logic [7:0] pul;
 logic [7:0] pul_cnt;
-logic [31:0] tim_cnt;
+logic [27:0] tim_cnt;
 
 wire timeout = (tim_cnt == CNT_1_S);
 
@@ -41,12 +41,12 @@ begin
         pul <= 8'h00;
 
         pul_cnt <= 8'h00;
-        tim_cnt <= 32'h00;
+        tim_cnt <= 28'h000_0000;
     end else begin
         pul <= timeout ? pul_cnt : pul;
 
         pul_cnt <= timeout ? 8'h00 : pul_cnt + pulse_in;
-        tim_cnt <= timeout ? 32'h00 : tim_cnt + 1'b1;
+        tim_cnt <= timeout ? 28'h000_0000 : tim_cnt + 1'b1;
     end
 end
 

rtl/ws2812_ctl.sv

@@ -20,7 +20,7 @@ module ws2812_ctl(
     output logic bit_data_out
 );
 
-parameter [15:0] CNT_50_US = 2 * 5000;
+parameter [13:0] CNT_50_US = 2 * 5000;
 
 parameter [1:0] IDLE = 2'b00;       // Idle
 parameter [1:0] READ_RAM = 2'b01;   // Read RAM Data
@@ -38,7 +38,7 @@ logic [23:0] ram_rd_data;
 logic [1:0] ctl_sta;
 
 logic [4:0] bit_sel;
-logic [15:0] rst_cnt;
+logic [13:0] rst_cnt;
 
 logic ram_rd_rdy;
 logic ram_rd_done;
@@ -85,10 +85,10 @@ begin
 
         ram_rd_cnt <= 6'h00;
         ram_rd_addr <= 6'h00;
-        ram_rd_data <= 24'h000000;
+        ram_rd_data <= 24'h00_0000;
 
         bit_sel <= 5'h00;
-        rst_cnt <= 16'h0000;
+        rst_cnt <= 14'h0000;
 
         bit_rdy_out <= 1'b0;
         bit_data_out <= 1'b0;
@@ -114,7 +114,7 @@ begin
         ram_rd_data <= ram_rd_done ? ram_rd_q[23:0] : ram_rd_data;
 
         bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + (bit_done & ~ram_next) : 5'h00;
-        rst_cnt <= (ctl_sta == SEND_RST) ? rst_cnt + 1'b1 : 16'h0000;
+        rst_cnt <= (ctl_sta == SEND_RST) ? rst_cnt + 1'b1 : 14'h0000;
 
         bit_rdy_out <= bit_next;
         bit_data_out <= bit_next ? ram_rd_data[5'd23 - bit_sel] : bit_data_out;

rtl/ws2812_out.sv

@@ -16,24 +16,24 @@ module ws2812_out(
     output logic ws2812_data_out
 );
 
-parameter [15:0] CNT_0_35_US = 2 * 35;
-parameter [15:0] CNT_0_70_US = 2 * 70;
-parameter [15:0] CNT_1_25_US = 2 * 125;
+parameter [7:0] CNT_0_35_US = 2 * 35;
+parameter [7:0] CNT_0_70_US = 2 * 70;
+parameter [7:0] CNT_1_25_US = 2 * 125;
 
 logic bit_bsy;
-logic [15:0] bit_cnt;
+logic [7:0] bit_cnt;
 
 always_ff @(posedge clk_in or negedge rst_n_in)
 begin
     if (!rst_n_in) begin
         bit_bsy <= 1'b0;
-        bit_cnt <= 16'h0000;
+        bit_cnt <= 8'h00;
 
         bit_done_out <= 1'b0;
         ws2812_data_out <= 1'b0;
     end else begin
         bit_bsy <= bit_bsy ? (bit_cnt != CNT_1_25_US) : bit_rdy_in;
-        bit_cnt <= bit_bsy ? bit_cnt + 1'b1 : 16'h0000;
+        bit_cnt <= bit_bsy ? bit_cnt + 1'b1 : 8'h00;
 
         bit_done_out <= bit_bsy & (bit_cnt == CNT_1_25_US);
         ws2812_data_out <= bit_bsy & ((bit_data_in & (bit_cnt < CNT_0_70_US))