ws2812_ctl: code refactoring

Author: redchenjs

rtl/ws2812_ctl.sv

@@ -28,25 +28,25 @@ parameter [1:0] READ_RAM = 2'b01;   // Read RAM Data
 parameter [1:0] SEND_BIT = 2'b10;   // Send Data Bit
 parameter [1:0] SEND_RST = 2'b11;   // Send Reset Code
 
+logic [1:0] ctl_sta;
+
 logic ram_rd_st;
 logic ram_rd_done;
 logic [31:0] ram_rd_q;
 
 logic [5:0] ram_rd_addr;
 logic [23:0] ram_rd_data;
 
-logic [1:0] ctl_sta;
-
 logic [4:0] bit_sel;
 logic [16:0] rst_cnt;
 
 wire ram_rd_en = (ctl_sta == READ_RAM);
 
-wire bit_done = ram_rd_st | bit_done_in;
-wire bit_next = (ctl_sta == SEND_BIT) & bit_done;
+wire bit_next = ram_rd_st | bit_done_in;
+wire bit_done = (ctl_sta == SEND_BIT) & bit_next;
 
-wire ram_done = (ram_rd_addr == 6'h00);
 wire ram_next = (bit_sel == 5'd23);
+wire ram_done = (ram_rd_addr == 6'h00);
 
 wire rst_done = (rst_cnt[16:1] == rst_cnt_in);
 
@@ -85,7 +85,7 @@ begin
             READ_RAM:
                 ctl_sta <= ram_rd_done ? SEND_BIT : ctl_sta;
             SEND_BIT:
-                ctl_sta <= (bit_done & ram_next) ? (ram_done ? SEND_RST : READ_RAM) : ctl_sta;
+                ctl_sta <= (bit_next & ram_next) ? (ram_done ? SEND_RST : READ_RAM) : ctl_sta;
             SEND_RST:
                 ctl_sta <= rst_done ? IDLE : ctl_sta;
             default:
@@ -98,11 +98,11 @@ begin
         ram_rd_addr <= ram_rd_done ? ram_rd_q[29:24] : ram_rd_addr;
         ram_rd_data <= ram_rd_done ? ram_rd_q[23:0] : ram_rd_data;
 
-        bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + (bit_done & ~ram_next) : 5'h00;
+        bit_sel <= (ctl_sta == SEND_BIT) ? bit_sel + bit_next : 5'h00;
         rst_cnt <= (ctl_sta == SEND_RST) ? rst_cnt + 1'b1 : 17'h0_0000;
 
-        bit_rdy_out <= bit_next;
-        bit_data_out <= bit_next ? ram_rd_data[5'd23 - bit_sel] : bit_data_out;
+        bit_rdy_out <= bit_done;
+        bit_data_out <= bit_done ? ram_rd_data[5'd23 - bit_sel] : bit_data_out;
     end
 end