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ip: update to 20.1
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‎ip/clk/globalclk.qsys‎

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@@ -55,7 +55,7 @@
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<module
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name="altclkctrl_0"
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kind="altclkctrl"
58-
version="19.1"
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version="20.1"
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enabled="1"
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autoexport="1">
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<parameter name="CLOCK_TYPE" value="1" />

‎ip/clk/globalclk.sopcinfo‎

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Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="globalclk" kind="globalclk" version="1.0" fabric="QSYS">
3-
<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
4-
<!-- 2020.05.08.07:04:05 -->
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<!-- Format version 20.1 711 (Future versions may contain additional information.) -->
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<!-- 2020.07.11.18:44:04 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
8-
<value>1588892645</value>
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<value>1594464244</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
@@ -68,7 +68,7 @@
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<module
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name="altclkctrl_0"
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kind="altclkctrl"
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version="19.1"
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version="20.1"
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path="altclkctrl_0">
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<!-- Describes a single module. Module parameters are
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the requested settings for a module instance. -->
@@ -137,7 +137,7 @@ the requested settings for a module instance. -->
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<interface name="altclkctrl_input" kind="conduit_end" version="19.1">
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<interface name="altclkctrl_input" kind="conduit_end" version="20.1">
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<!-- The connection points exposed by a module instance for the
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particular module parameters. Connection points and their
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parameters are a RESULT of the module parameters. -->
@@ -186,7 +186,7 @@ parameters are a RESULT of the module parameters. -->
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<role>inclk</role>
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</port>
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</interface>
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<interface name="altclkctrl_output" kind="conduit_end" version="19.1">
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<interface name="altclkctrl_output" kind="conduit_end" version="20.1">
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<!-- The connection points exposed by a module instance for the
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particular module parameters. Connection points and their
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parameters are a RESULT of the module parameters. -->
@@ -242,16 +242,16 @@ parameters are a RESULT of the module parameters. -->
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<type>com.altera.entityinterfaces.IElementClass</type>
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<subtype>com.altera.entityinterfaces.IModule</subtype>
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<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
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<version>19.1</version>
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<version>20.1</version>
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</plugin>
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<plugin>
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<instanceCount>2</instanceCount>
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<name>conduit_end</name>
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<type>com.altera.entityinterfaces.IElementClass</type>
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<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
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<displayName>Conduit</displayName>
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<version>19.1</version>
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<version>20.1</version>
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</plugin>
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<reportVersion>19.1 670</reportVersion>
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<reportVersion>20.1 711</reportVersion>
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<uniqueIdentifier></uniqueIdentifier>
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</EnsembleReport>

‎ip/clk/globalclk/synthesis/globalclk.debuginfo‎

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Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="globalclk" kind="system" version="19.1" fabric="QSYS">
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<!-- Format version 19.1 670 (Future versions may contain additional information.) -->
4-
<!-- 2020.05.08.07:04:06 -->
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<EnsembleReport name="globalclk" kind="system" version="20.1" fabric="QSYS">
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<!-- Format version 20.1 711 (Future versions may contain additional information.) -->
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<!-- 2020.07.11.18:44:05 -->
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<!-- A collection of modules and connections -->
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<parameter name="clockCrossingAdapter">
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<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -53,7 +53,7 @@
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</parameter>
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<parameter name="generationId">
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<type>int</type>
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<value>1588892645</value>
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<value>1594464244</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
@@ -150,7 +150,7 @@
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<module
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name="altclkctrl_0"
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kind="altclkctrl"
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version="19.1"
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version="20.1"
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path="altclkctrl_0">
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<!-- Describes a single module. Module parameters are
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the requested settings for a module instance. -->
@@ -219,7 +219,7 @@ the requested settings for a module instance. -->
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<interface name="altclkctrl_input" kind="conduit_end" version="19.1">
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<interface name="altclkctrl_input" kind="conduit_end" version="20.1">
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<!-- The connection points exposed by a module instance for the
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particular module parameters. Connection points and their
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parameters are a RESULT of the module parameters. -->
@@ -268,7 +268,7 @@ parameters are a RESULT of the module parameters. -->
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<role>inclk</role>
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</port>
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</interface>
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<interface name="altclkctrl_output" kind="conduit_end" version="19.1">
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<interface name="altclkctrl_output" kind="conduit_end" version="20.1">
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<!-- The connection points exposed by a module instance for the
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particular module parameters. Connection points and their
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parameters are a RESULT of the module parameters. -->
@@ -324,16 +324,16 @@ parameters are a RESULT of the module parameters. -->
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<type>com.altera.entityinterfaces.IElementClass</type>
325325
<subtype>com.altera.entityinterfaces.IModule</subtype>
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<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
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<version>19.1</version>
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<version>20.1</version>
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</plugin>
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<plugin>
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<instanceCount>2</instanceCount>
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<name>conduit_end</name>
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<type>com.altera.entityinterfaces.IElementClass</type>
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<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
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<displayName>Conduit</displayName>
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<version>19.1</version>
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<version>20.1</version>
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</plugin>
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<reportVersion>19.1 670</reportVersion>
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<uniqueIdentifier>5CE0C587F67700000171F161BA18</uniqueIdentifier>
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<reportVersion>20.1 711</reportVersion>
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<uniqueIdentifier>B8975A199DE2000001733D7995C8</uniqueIdentifier>
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</EnsembleReport>

‎ip/clk/globalclk/synthesis/globalclk.qip‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_NAME "Qsys"
2-
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "19.1"
2+
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_VERSION "20.1"
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TOOL_ENV "Qsys"
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set_global_assignment -library "globalclk" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../globalclk.sopcinfo"]
5-
set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1588892645"
5+
set_global_assignment -entity "globalclk" -library "globalclk" -name SLD_INFO "QSYS_NAME globalclk HAS_SOPCINFO 1 GENERATION_ID 1594464244"
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set_global_assignment -library "globalclk" -name MISC_FILE [file join $::quartus(qip_path) "../globalclk.cmp"]
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set_global_assignment -library "globalclk" -name SLD_FILE [file join $::quartus(qip_path) "globalclk.debuginfo"]
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@ set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONEN
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "On"
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_VERSION "MS4w"
18-
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4ODg5MjY0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
18+
set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU5NDQ2NDI0NA==::QXV0byBHRU5FUkFUSU9OX0lE"
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDhTQ00xNTNDOEc=::QXV0byBERVZJQ0U="
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set_global_assignment -entity "globalclk" -library "globalclk" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@@ -24,7 +24,7 @@ set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -nam
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
27-
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_VERSION "MTkuMQ=="
27+
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_VERSION "MjAuMQ=="
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIEZhbWlseQ=="
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
@@ -35,5 +35,5 @@ set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quar
3535
set_global_assignment -library "globalclk" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/globalclk_altclkctrl_0.v"]
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3737
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_NAME "altclkctrl"
38-
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_VERSION "19.1"
38+
set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_VERSION "20.1"
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set_global_assignment -entity "globalclk_altclkctrl_0" -library "globalclk" -name IP_TOOL_ENV "Qsys"

‎ip/clk/globalclk/synthesis/globalclk.v‎

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@@ -1,6 +1,6 @@
11
// globalclk.v
22

3-
// Generated using ACDS version 19.1 670
3+
// Generated using ACDS version 20.1 711
44

55
`timescale 1 ps / 1 ps
66
module globalclk (

‎ip/clk/globalclk/synthesis/submodules/globalclk_altclkctrl_0.v‎

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Original file line numberDiff line numberDiff line change
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11
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="MAX 10" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
2-
//VERSION_BEGIN 19.1 cbx_altclkbuf 2019:09:22:08:02:34:SJ cbx_cycloneii 2019:09:22:08:02:34:SJ cbx_lpm_add_sub 2019:09:22:08:02:34:SJ cbx_lpm_compare 2019:09:22:08:02:34:SJ cbx_lpm_decode 2019:09:22:08:02:34:SJ cbx_lpm_mux 2019:09:22:08:02:34:SJ cbx_mgl 2019:09:22:09:26:20:SJ cbx_nadder 2019:09:22:08:02:34:SJ cbx_stratix 2019:09:22:08:02:34:SJ cbx_stratixii 2019:09:22:08:02:34:SJ cbx_stratixiii 2019:09:22:08:02:34:SJ cbx_stratixv 2019:09:22:08:02:34:SJ VERSION_END
2+
//VERSION_BEGIN 20.1 cbx_altclkbuf 2020:06:05:12:04:51:SJ cbx_cycloneii 2020:06:05:12:04:51:SJ cbx_lpm_add_sub 2020:06:05:12:04:51:SJ cbx_lpm_compare 2020:06:05:12:04:51:SJ cbx_lpm_decode 2020:06:05:12:04:51:SJ cbx_lpm_mux 2020:06:05:12:04:51:SJ cbx_mgl 2020:06:05:12:11:10:SJ cbx_nadder 2020:06:05:12:04:51:SJ cbx_stratix 2020:06:05:12:04:51:SJ cbx_stratixii 2020:06:05:12:04:51:SJ cbx_stratixiii 2020:06:05:12:04:51:SJ cbx_stratixv 2020:06:05:12:04:51:SJ VERSION_END
33
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
44
// altera message_off 10463
55

66

77

8-
// Copyright (C) 2019 Intel Corporation. All rights reserved.
8+
// Copyright (C) 2020 Intel Corporation. All rights reserved.
99
// Your use of Intel Corporation's design tools, logic functions
1010
// and other software and tools, and any partner logic
1111
// functions, and any output files from any of the foregoing
@@ -70,7 +70,7 @@ module globalclk_altclkctrl_0_sub
7070
inclk_wire = {inclk},
7171
outclk = wire_clkctrl1_outclk;
7272
endmodule //globalclk_altclkctrl_0_sub
73-
//VALID FILE // (C) 2001-2019 Intel Corporation. All rights reserved.
73+
//VALID FILE // (C) 2001-2020 Intel Corporation. All rights reserved.
7474
// Your use of Intel Corporation's design tools, logic functions and other
7575
// software and tools, and its AMPP partner logic functions, and any output
7676
// files from any of the foregoing (including device programming or simulation

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