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redchenjsredchenjs
committed
rtl: update to v4.0
1 parent 6aad598 commit cdee2f0

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lines changed

‎README.md‎

Lines changed: 37 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,30 +1,30 @@
1-
WS281X Cube Controller
2-
======================
1+
NeoPixel LED Controller
2+
=======================
33

4-
WS281X Cube Controller based on MAX10 FPGA.
4+
NeoPixel LED Controller based on MAX10 FPGA.
55

66
## Main Features
77

8-
* 4-wire SPI interface
9-
* High refresh rate (up to 500fps@8x8x8)
10-
* 8 parallel output data lines (64 LEDs per line)
11-
* Configurable waveform generator (T0H, T0L, T1H, T1L)
12-
* Configurable LED serial connection sequence (address linked list)
8+
* 4-wire SPI interface (SCLK, MOSI, CS, DC)
9+
* High refresh rate (500fps@8x8x8, 125fps@16x16x16)
10+
* 16 parallel output channels (up to 256 LEDs per channel)
11+
* Each output channel has a programmable circular linked list
12+
* Each output channel has a programmable waveform generator (T0H, T0L, T1H, T1L)
1313

1414
## Pinout
1515

16-
| Input Port | FPGA Pin | Output Port | FPGA Pin |
17-
| ---------: | :------- | :--------------: | :------: |
18-
| clk_i | PIN_J5 | ws281x_code_o[7] | PIN_R5 |
19-
| rst_n_i | PIN_R9 | ws281x_code_o[6] | PIN_L7 |
20-
| dc_i | PIN_P15 | ws281x_code_o[5] | PIN_P4 |
21-
| spi_sclk_i | PIN_R14 | ws281x_code_o[4] | PIN_L6 |
22-
| spi_mosi_i | PIN_P12 | ws281x_code_o[3] | PIN_R3 |
23-
| spi_cs_n_i | PIN_R11 | ws281x_code_o[2] | PIN_M5 |
24-
| - | | ws281x_code_o[1] | PIN_P3 |
25-
| - | | ws281x_code_o[0] | PIN_M4 |
16+
| Input Port | FPGA Pin | Output Port | FPGA Pin | Output Port | FPGA Pin |
17+
| ---------: | :------- | :----------------: | :------: | :-----------------: | :------: |
18+
| clk_i | PIN_J5 | neopixel_code_o[7] | PIN_R5 | neopixel_code_o[15] | PIN_C8 |
19+
| rst_n_i | PIN_R9 | neopixel_code_o[6] | PIN_L7 | neopixel_code_o[14] | PIN_B7 |
20+
| dc_i | PIN_P15 | neopixel_code_o[5] | PIN_P4 | neopixel_code_o[13] | PIN_D7 |
21+
| spi_sclk_i | PIN_R14 | neopixel_code_o[4] | PIN_L6 | neopixel_code_o[12] | PIN_E7 |
22+
| spi_mosi_i | PIN_P12 | neopixel_code_o[3] | PIN_R3 | neopixel_code_o[11] | PIN_B6 |
23+
| spi_cs_n_i | PIN_R11 | neopixel_code_o[2] | PIN_M5 | neopixel_code_o[10] | PIN_A7 |
24+
| - | | neopixel_code_o[1] | PIN_P3 | neopixel_code_o[9] | PIN_A5 |
25+
| - | | neopixel_code_o[0] | PIN_M4 | neopixel_code_o[8] | PIN_B4 |
2626

27-
* SPI slave mode: MODE 0, CPOL=0, CPHA=0, MSB first
27+
* SPI slave mode: F_MAX=33MHz, CPOL=0, CPHA=0, MSB first
2828

2929
## Commands
3030

@@ -37,16 +37,15 @@ WS281X Cube Controller based on MAX10 FPGA.
3737
| 2nd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
3838
| 3rd Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
3939
| 4th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
40+
| 5th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
41+
| 6th Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
4042

41-
* 1st Param: T0H time, range: 1-255, unit: 10 ns
42-
* 2nd Param: T0L time, range: 1-255, unit: 10 ns
43-
* 3rd Param: T1H time, range: 1-255, unit: 10 ns
44-
* 4th Param: T1L time, range: 1-255, unit: 10 ns
45-
46-
Limits:
47-
48-
* T0H + T0L <= 257 = 2570 ns = 2.57 us
49-
* T1H + T1L <= 257 = 2570 ns = 2.57 us
43+
* 1st Param: T0H time (10 ns), range: 0 - 255
44+
* 2nd Param: T0L time (10 ns), range: 0 - 255
45+
* 3rd Param: T1H time (10 ns), range: 0 - 255
46+
* 4th Param: T1L time (10 ns), range: 0 - 255
47+
* 5th Param: channel length, range: 0 - 255
48+
* 6th Param: channel count, range: 0 - 15
5049

5150
### ADDR_WR
5251

@@ -57,15 +56,12 @@ Limits:
5756
| ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
5857
| Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
5958

60-
* 1st Param: 2nd LED address, range: 0-63
61-
* 2nd Param: 3rd LED address, range: 0-63
62-
* 3rd Param: 4th LED address, range: 0-63
59+
* 1st Param: channel 0, the next pointer of the 1st color data, range: 0 - 255
60+
* 2nd Param: channel 0, the next pointer of the 2nd color data, range: 0 - 255
6361
* ...
64-
* Nth Param: 1st LED address, range: 0-63
65-
66-
* N = 64
62+
* Nth Param: ...
6763

68-
* These configurations will be applied to all 8 layers
64+
* N_MAX = 256 x 16 = 4096
6965

7066
### DATA_WR
7167

@@ -76,26 +72,21 @@ Limits:
7672
| ... | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
7773
| Nth Param | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
7874

79-
* 1st Param: 1st LED color byte 2, range: 0-255
80-
* 2nd Param: 1st LED color byte 1, range: 0-255
81-
* 3rd Param: 1st LED color byte 0, range: 0-255
82-
* 4th Param: 2nd LED color byte 2, range: 0-255
83-
* 5th Param: 2nd LED color byte 1, range: 0-255
84-
* 6th Param: 2nd LED color byte 0, range: 0-255
75+
* 1st Param: channel 0, the 1st color data, byte 2, range: 0 - 255
76+
* 2nd Param: channel 0, the 1st color data, byte 1, range: 0 - 255
77+
* 3rd Param: channel 0, the 1st color data, byte 0, range: 0 - 255
78+
* 4th Param: channel 0, the 2nd color data, byte 2, range: 0 - 255
8579
* ...
8680
* Nth Param: ...
8781

88-
* N = 8 x 8 x 8 x 3 = 1536
89-
90-
* Layer data order: layer 7 first (layer 7 - layer 0)
91-
* Color byte order: high byte first (byte 2 - byte 0)
82+
* N_MAX = 256 x 16 x 3 = 12288
9283

9384
## Preparing
9485

9586
### Obtain the source
9687

9788
```
98-
git clone https://github.com/redchenjs/ws281x_cube_controller_max10.git
89+
git clone https://github.com/redchenjs/neopixel_led_controller_max10.git
9990
```
10091

10192
### Update an existing repository

‎ip/pll/pll.v‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
// altpll
1010
//
1111
// Simulation Library Files(s):
12-
//
12+
// altera_mf
1313
// ============================================================
1414
// ************************************************************
1515
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@@ -55,20 +55,20 @@ module pll (
5555
// synopsys translate_on
5656
`endif
5757

58-
wire [0:0] sub_wire2 = 1'h0;
59-
wire [4:0] sub_wire3;
60-
wire sub_wire5;
61-
wire sub_wire0 = inclk0;
62-
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
63-
wire [0:0] sub_wire4 = sub_wire3[0:0];
64-
wire c0 = sub_wire4;
65-
wire locked = sub_wire5;
58+
wire [4:0] sub_wire0;
59+
wire sub_wire2;
60+
wire [0:0] sub_wire5 = 1'h0;
61+
wire [0:0] sub_wire1 = sub_wire0[0:0];
62+
wire c0 = sub_wire1;
63+
wire locked = sub_wire2;
64+
wire sub_wire3 = inclk0;
65+
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
6666

6767
altpll altpll_component (
6868
.areset (areset),
69-
.inclk (sub_wire1),
70-
.clk (sub_wire3),
71-
.locked (sub_wire5),
69+
.inclk (sub_wire4),
70+
.clk (sub_wire0),
71+
.locked (sub_wire2),
7272
.activeclock (),
7373
.clkbad (),
7474
.clkena ({6{1'b1}}),
@@ -106,7 +106,7 @@ module pll (
106106
altpll_component.bandwidth_type = "AUTO",
107107
altpll_component.clk0_divide_by = 3,
108108
altpll_component.clk0_duty_cycle = 50,
109-
altpll_component.clk0_multiply_by = 50,
109+
altpll_component.clk0_multiply_by = 25,
110110
altpll_component.clk0_phase_shift = "0",
111111
altpll_component.compensate_clock = "CLK0",
112112
altpll_component.inclk0_input_frequency = 83333,
@@ -183,7 +183,7 @@ endmodule
183183
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
184184
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
185185
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
186-
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
186+
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
187187
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
188188
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
189189
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -208,7 +208,7 @@ endmodule
208208
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
209209
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
210210
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
211-
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
211+
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
212212
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
213213
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
214214
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -253,7 +253,7 @@ endmodule
253253
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
254254
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
255255
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
256-
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
256+
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
257257
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
258258
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
259259
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
@@ -321,4 +321,5 @@ endmodule
321321
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
322322
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
323323
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
324+
// Retrieval info: LIB_FILE: altera_mf
324325
// Retrieval info: CBX_MODULE_PREFIX: ON

ip/ram/ram64.qip renamed to ip/ram/ram256.qip

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
22
set_global_assignment -name IP_TOOL_VERSION "20.1"
33
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
4-
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram64.v"]
5-
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram64_syn.v"]
4+
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram256.v"]
5+
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram256_syn.v"]

ip/ram/ram64.v renamed to ip/ram/ram256.v

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// MODULE: altsyncram
55

66
// ============================================================
7-
// File Name: ram64.v
7+
// File Name: ram256.v
88
// Megafunction Name(s):
99
// altsyncram
1010
//
@@ -37,7 +37,7 @@
3737
// synopsys translate_off
3838
`timescale 1 ps / 1 ps
3939
// synopsys translate_on
40-
module ram64 (
40+
module ram256 (
4141
aclr,
4242
byteena_a,
4343
clock,
@@ -52,9 +52,9 @@ module ram64 (
5252
input [3:0] byteena_a;
5353
input clock;
5454
input [31:0] data;
55-
input [5:0] rdaddress;
55+
input [7:0] rdaddress;
5656
input rden;
57-
input [5:0] wraddress;
57+
input [7:0] wraddress;
5858
input wren;
5959
output [31:0] q;
6060
`ifndef ALTERA_RESERVED_QIS
@@ -105,16 +105,16 @@ module ram64 (
105105
altsyncram_component.clock_enable_output_b = "BYPASS",
106106
altsyncram_component.intended_device_family = "MAX 10",
107107
altsyncram_component.lpm_type = "altsyncram",
108-
altsyncram_component.numwords_a = 64,
109-
altsyncram_component.numwords_b = 64,
108+
altsyncram_component.numwords_a = 256,
109+
altsyncram_component.numwords_b = 256,
110110
altsyncram_component.operation_mode = "DUAL_PORT",
111111
altsyncram_component.outdata_aclr_b = "CLEAR0",
112112
altsyncram_component.outdata_reg_b = "UNREGISTERED",
113113
altsyncram_component.power_up_uninitialized = "TRUE",
114114
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
115115
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
116-
altsyncram_component.widthad_a = 6,
117-
altsyncram_component.widthad_b = 6,
116+
altsyncram_component.widthad_a = 8,
117+
altsyncram_component.widthad_b = 8,
118118
altsyncram_component.width_a = 32,
119119
altsyncram_component.width_b = 32,
120120
altsyncram_component.width_byteena_a = 4;
@@ -155,9 +155,9 @@ endmodule
155155
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
156156
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
157157
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
158-
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
158+
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
159159
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
160-
// Retrieval info: PRIVATE: MIFfilename STRING "ram64.mif"
160+
// Retrieval info: PRIVATE: MIFfilename STRING "ram256.mif"
161161
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
162162
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
163163
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
@@ -193,16 +193,16 @@ endmodule
193193
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
194194
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
195195
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
196-
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
197-
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
196+
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
197+
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
198198
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
199199
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
200200
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
201201
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
202202
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
203203
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
204-
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
205-
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
204+
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
205+
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
206206
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
207207
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
208208
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
@@ -211,24 +211,24 @@ endmodule
211211
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
212212
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
213213
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
214-
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[5..0]"
214+
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
215215
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
216-
// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[5..0]"
216+
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
217217
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
218218
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
219-
// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
220-
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
219+
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
220+
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
221221
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
222222
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
223223
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
224224
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
225225
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
226226
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
227-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.v TRUE
228-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.inc FALSE
229-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.cmp FALSE
230-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64.bsf FALSE
231-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_inst.v FALSE
232-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_bb.v FALSE
233-
// Retrieval info: GEN_FILE: TYPE_NORMAL ram64_syn.v TRUE
227+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.v TRUE
228+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.inc FALSE
229+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.cmp FALSE
230+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256.bsf FALSE
231+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_inst.v FALSE
232+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_bb.v FALSE
233+
// Retrieval info: GEN_FILE: TYPE_NORMAL ram256_syn.v TRUE
234234
// Retrieval info: LIB_FILE: altera_mf

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