fix spi to be compatible with embedded-hal v1.0.0-alpha.8

Author: almindor

Cargo.toml

@@ -10,7 +10,7 @@ license = "ISC"
 edition = "2018"
 
 [dependencies]
-embedded-hal = "=1.0.0-alpha.7"
+embedded-hal = "=1.0.0-alpha.8"
 nb = "1.0.0"
 riscv = "0.9.0-alpha.1"
 e310x = { version = "0.9.1", features = ["rt"] }

src/spi/bus.rs

@@ -1,10 +1,8 @@
-use embedded_hal::spi::blocking::Operation;
-pub use embedded_hal::spi::blocking::{Read, Transfer, TransferInplace, Write, WriteIter};
-pub use embedded_hal::spi::nb::FullDuplex;
+use embedded_hal::spi::blocking::{SpiBus as SpiBusTransfer, SpiBusFlush};
+use embedded_hal::spi::blocking::{SpiBusRead, SpiBusWrite};
+use embedded_hal::spi::ErrorType;
 pub use embedded_hal::spi::{ErrorKind, Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 
-use nb;
-
 use super::{Pins, PinsNoCS, SharedBus, SpiConfig, SpiExclusiveDevice, SpiX};
 
 /// SPI bus abstraction
@@ -101,38 +99,18 @@ where
         }
     }
 
-    // ex-traits now only accessible via devices
-
-    pub(crate) fn read(&mut self) -> nb::Result<u8, ErrorKind> {
-        let rxdata = self.spi.rxdata.read();
-
-        if rxdata.empty().bit_is_set() {
-            Err(nb::Error::WouldBlock)
-        } else {
-            Ok(rxdata.data().bits())
-        }
-    }
-
-    pub(crate) fn send(&mut self, byte: u8) -> nb::Result<(), ErrorKind> {
-        let txdata = self.spi.txdata.read();
-
-        if txdata.full().bit_is_set() {
-            Err(nb::Error::WouldBlock)
-        } else {
-            self.spi.txdata.write(|w| unsafe { w.data().bits(byte) });
-            Ok(())
-        }
-    }
-
-    pub(crate) fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), ErrorKind> {
+    /// Transfer implementation out of trait for reuse in Read and Write
+    fn perform_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), ErrorKind> {
         let mut iwrite = 0;
         let mut iread = 0;
+        let bytes = core::cmp::max(read.len(), write.len());
 
         // Ensure that RX FIFO is empty
         self.wait_for_rxfifo();
 
         // go through entire write buffer and read back (even if read buffer is empty)
-        while iwrite < write.len() || iread < write.len() {
+        // while iwrite < write.len() || iread < write.len() {
+        while iwrite < bytes || iread < bytes {
             if iwrite < write.len() && self.spi.txdata.read().full().bit_is_clear() {
                 let byte = write.get(iwrite).unwrap_or(&0);
                 iwrite += 1;
@@ -152,8 +130,49 @@ where
 
         Ok(())
     }
+}
+
+impl<SPI, PINS> ErrorType for SpiBus<SPI, PINS> {
+    type Error = ErrorKind;
+}
+
+impl<SPI, PINS> SpiBusFlush for SpiBus<SPI, PINS>
+where
+    SPI: SpiX,
+{
+    fn flush(&mut self) -> Result<(), Self::Error> {
+        // unnecessary
+
+        Ok(())
+    }
+}
+impl<SPI, PINS> SpiBusRead for SpiBus<SPI, PINS>
+where
+    SPI: SpiX,
+{
+    fn read(&mut self, words: &mut [u8]) -> Result<(), ErrorKind> {
+        self.perform_transfer(words, &[])
+    }
+}
+
+impl<SPI, PINS> SpiBusWrite for SpiBus<SPI, PINS>
+where
+    SPI: SpiX,
+{
+    fn write(&mut self, words: &[u8]) -> Result<(), ErrorKind> {
+        self.perform_transfer(&mut [], words)
+    }
+}
+
+impl<SPI, PINS> SpiBusTransfer for SpiBus<SPI, PINS>
+where
+    SPI: SpiX,
+{
+    fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), ErrorKind> {
+        self.perform_transfer(read, write)
+    }
 
-    pub(crate) fn transfer_inplace(&mut self, words: &mut [u8]) -> Result<(), ErrorKind> {
+    fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), ErrorKind> {
         let mut iwrite = 0;
         let mut iread = 0;
 
@@ -178,63 +197,6 @@ where
 
         Ok(())
     }
-
-    pub(crate) fn write_iter<WI>(&mut self, words: WI) -> Result<(), ErrorKind>
-    where
-        WI: IntoIterator<Item = u8>,
-    {
-        let mut iter = words.into_iter();
-
-        let mut read_count = 0;
-        let mut has_data = true;
-
-        // Ensure that RX FIFO is empty
-        self.wait_for_rxfifo();
-
-        while has_data || read_count > 0 {
-            if has_data && self.spi.txdata.read().full().bit_is_clear() {
-                if let Some(byte) = iter.next() {
-                    self.spi.txdata.write(|w| unsafe { w.data().bits(byte) });
-                    read_count += 1;
-                } else {
-                    has_data = false;
-                }
-            }
-
-            if read_count > 0 {
-                // Read and discard byte, if any
-                if self.spi.rxdata.read().empty().bit_is_clear() {
-                    read_count -= 1;
-                }
-            }
-        }
-
-        Ok(())
-    }
-
-    pub(crate) fn exec<'op>(
-        &mut self,
-        operations: &mut [Operation<'op, u8>],
-    ) -> Result<(), ErrorKind> {
-        for op in operations {
-            match op {
-                Operation::Read(words) => {
-                    self.transfer(words, &[])?;
-                }
-                Operation::Write(words) => {
-                    self.transfer(&mut [], words)?;
-                }
-                Operation::Transfer(read_words, write_words) => {
-                    self.transfer(read_words, write_words)?;
-                }
-                Operation::TransferInplace(words) => {
-                    self.transfer_inplace(words)?;
-                }
-            }
-        }
-
-        Ok(())
-    }
 }
 
 impl<SPI, PINS> SpiBus<SPI, PINS>

src/spi/exclusive_device.rs

@@ -1,8 +1,4 @@
-use embedded_hal::spi::{
-    blocking::{Operation, Transactional, Transfer, TransferInplace, Write, WriteIter},
-    nb::FullDuplex,
-    ErrorKind, ErrorType,
-};
+use embedded_hal::spi::{blocking::SpiDevice, ErrorKind, ErrorType};
 
 use crate::spi::SpiConfig;
 
@@ -39,89 +35,21 @@ impl<SPI, PINS> ErrorType for SpiExclusiveDevice<SPI, PINS> {
     type Error = ErrorKind;
 }
 
-impl<SPI, PINS> FullDuplex for SpiExclusiveDevice<SPI, PINS>
+impl<SPI, PINS> SpiDevice for SpiExclusiveDevice<SPI, PINS>
 where
     SPI: SpiX,
     PINS: Pins<SPI>,
 {
-    fn read(&mut self) -> nb::Result<u8, Self::Error> {
-        self.bus.read()
-    }
-
-    fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> {
-        self.bus.send(byte)
-    }
-}
-
-impl<SPI, PINS> Transfer for SpiExclusiveDevice<SPI, PINS>
-where
-    SPI: SpiX,
-    PINS: Pins<SPI>,
-{
-    fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
-        self.bus.start_frame();
-        let result = self.bus.transfer(read, write);
-        self.bus.end_frame();
-
-        result
-    }
-}
-
-impl<SPI, PINS> TransferInplace for SpiExclusiveDevice<SPI, PINS>
-where
-    SPI: SpiX,
-    PINS: Pins<SPI>,
-{
-    fn transfer_inplace<'w>(&mut self, words: &'w mut [u8]) -> Result<(), Self::Error> {
-        self.bus.start_frame();
-        let result = self.bus.transfer_inplace(words);
-        self.bus.end_frame();
-
-        result
-    }
-}
-
-impl<SPI, PINS> Write for SpiExclusiveDevice<SPI, PINS>
-where
-    SPI: SpiX,
-    PINS: Pins<SPI>,
-{
-    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
-        self.bus.start_frame();
-        let result = self.bus.transfer(&mut [], words);
-        self.bus.end_frame();
+    type Bus = SpiBus<SPI, PINS>;
 
-        result
-    }
-}
-
-impl<SPI, PINS> WriteIter for SpiExclusiveDevice<SPI, PINS>
-where
-    SPI: SpiX,
-    PINS: Pins<SPI>,
-{
-    fn write_iter<WI>(&mut self, words: WI) -> Result<(), Self::Error>
-    where
-        WI: IntoIterator<Item = u8>,
-    {
-        self.bus.start_frame();
-        let result = self.bus.write_iter(words);
-        self.bus.end_frame();
-
-        result
-    }
-}
-
-impl<SPI, PINS> Transactional for SpiExclusiveDevice<SPI, PINS>
-where
-    SPI: SpiX,
-    PINS: Pins<SPI>,
-{
-    fn exec<'op>(&mut self, operations: &mut [Operation<'op, u8>]) -> Result<(), Self::Error> {
+    fn transaction<R>(
+        &mut self,
+        f: impl FnOnce(&mut Self::Bus) -> Result<R, <Self::Bus as ErrorType>::Error>,
+    ) -> Result<R, Self::Error> {
         self.bus.start_frame();
-        let result = self.bus.exec(operations);
+        let result = f(&mut self.bus)?;
         self.bus.end_frame();
 
-        result
+        Ok(result)
     }
 }

src/spi/shared_bus.rs

@@ -1,5 +1,6 @@
 use core::cell::RefCell;
 use core::ops::Deref;
+use embedded_hal::spi::{ErrorKind, ErrorType};
 pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 use riscv::interrupt;
 use riscv::interrupt::Mutex;
@@ -10,6 +11,10 @@ use super::{PinCS, PinsNoCS, SpiBus, SpiConfig, SpiSharedDevice, SpiX};
 /// Used to hold the [SpiBus] instance so it can be used for multiple [SpiSharedDevice] instances.
 pub struct SharedBus<SPI, PINS>(Mutex<RefCell<SpiBus<SPI, PINS>>>);
 
+impl<SPI, PINS> ErrorType for SharedBus<SPI, PINS> {
+    type Error = ErrorKind;
+}
+
 impl<SPI, PINS> SharedBus<SPI, PINS>
 where
     SPI: SpiX,