When will hart trap into S-mode?

[ChunYen Tai (ranvd)]

Currently, I'm reading the RISC-V Instruction Set Manual: Volume II (2024). I'm confused about how RISC-V handles traps. According to the content in § 3.1.8:

By default, all traps at any privilege level are handled in machine mode, though a machine-mode handler can redirect traps back to the appropriate level with the MRET instruction

We can know that all traps will be handled in machine mode if the corresponding medeleg or mideleg bits are not set. However, as mentioned in § 10.1.3:

An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the sstatus register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both sip and sie.

The above descriptions confuse me a bit. Does a hart trap into S-mode only if the corresponding medeleg or mideleg bits are set? Or can it trap into S-mode solely with the condition mentioned in section 10.1.3?

Thanks in advance.

[Andrew Waterman (aswaterman)]

Interrupts can only become visible in sip if they have been delegated via mideleg. So, Sec. 10.1.3 is true, but doesn’t override any facts mentioned in the M-mode chapter.

[ChunYen Tai (ranvd)]

Thank you so much!

[Andrew Waterman (aswaterman)]

You’re welcome!