[V-ext] Rationale behind setting vill and zeroing the remaining bits.

[Marcello Ranone (ipocentro87)]

Hi all, in the current Vector specification, it is stated that when vill is set in vtype, all the remaining bits are cleared (subsection "Vector Type Illegal vill").
I was wondering what is the reason behind the clearing, since vill already specifies that the vtype value is not supported. Wouldn't it be better, from a debugging purpose, to have the illegal value in vtype?

[gfavor]

Since this question is about an architectural design choice made when developing RVV, versus some issue with the ISA manual's documentation of RVV, it would be better to post this question to the sig-vector@lists.riscv.org email list.