From 4469cf45d2eb2dabdffbcc6ed08cc57ec71ba9e1 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Wed, 29 Oct 2025 11:45:49 +0000 Subject: [PATCH 1/3] More typos and crate renames in the docs --- aarch32-cpu/build.rs | 2 +- aarch32-cpu/src/critical_section.rs | 2 +- aarch32-cpu/src/interrupt.rs | 2 +- aarch32-cpu/src/lib.rs | 3 +-- aarch32-cpu/src/register/armv8r/hvbar.rs | 2 +- aarch32-cpu/src/register/armv8r/vbar.rs | 2 +- aarch32-rt-macros/Cargo.toml | 2 +- aarch32-rt/Cargo.toml | 2 +- aarch32-rt/build.rs | 2 +- examples/mps3-an536/Cargo.toml | 2 +- examples/mps3-an536/build.rs | 2 +- examples/mps3-an536/src/bin/fpu-test.rs | 2 +- examples/mps3-an536/src/bin/generic_timer.rs | 2 +- examples/mps3-an536/src/bin/generic_timer_irq.rs | 2 +- examples/mps3-an536/src/bin/gic-map.rs | 4 ++-- examples/mps3-an536/src/bin/gic-priority-ceiling.rs | 4 ++-- examples/mps3-an536/src/bin/gic-static-section-irq.rs | 4 ++-- examples/mps3-an536/src/bin/gic-unified-irq.rs | 4 ++-- examples/mps3-an536/src/bin/hello.rs | 2 +- examples/mps3-an536/src/bin/registers.rs | 2 +- examples/mps3-an536/src/bin/smp_test.rs | 2 +- examples/versatileab/build.rs | 2 +- 22 files changed, 26 insertions(+), 27 deletions(-) diff --git a/aarch32-cpu/build.rs b/aarch32-cpu/build.rs index 9306423..8371f21 100644 --- a/aarch32-cpu/build.rs +++ b/aarch32-cpu/build.rs @@ -1,4 +1,4 @@ -//! # Build script for the Cortex-R library +//! # Build script for the aarch32-cpu library //! //! This script only executes when using `cargo` to build the project. //! diff --git a/aarch32-cpu/src/critical_section.rs b/aarch32-cpu/src/critical_section.rs index 08094b2..ba98402 100644 --- a/aarch32-cpu/src/critical_section.rs +++ b/aarch32-cpu/src/critical_section.rs @@ -1,4 +1,4 @@ -//! Code that implements the `critical-section` traits on Cortex-R or Cortex-A +//! Code that implements the `critical-section` traits on AArch32 //! //! We have single-core and multi-core versions. Select with the //! `critical-section-single-core` and `critical-section-multi-core` features. diff --git a/aarch32-cpu/src/interrupt.rs b/aarch32-cpu/src/interrupt.rs index 48d5fb2..49ce38f 100644 --- a/aarch32-cpu/src/interrupt.rs +++ b/aarch32-cpu/src/interrupt.rs @@ -1,4 +1,4 @@ -//! Interrupts on Arm Cortex-R +//! Interrupts on Arm AArch32 use core::sync::atomic::{compiler_fence, Ordering}; diff --git a/aarch32-cpu/src/lib.rs b/aarch32-cpu/src/lib.rs index 051cc7d..9c965af 100644 --- a/aarch32-cpu/src/lib.rs +++ b/aarch32-cpu/src/lib.rs @@ -1,5 +1,4 @@ -//! CPU/peripheral support for Arm Cortex-R - +//! CPU/peripheral support for Arm AArch32 #![no_std] mod critical_section; diff --git a/aarch32-cpu/src/register/armv8r/hvbar.rs b/aarch32-cpu/src/register/armv8r/hvbar.rs index 43a032d..643f180 100644 --- a/aarch32-cpu/src/register/armv8r/hvbar.rs +++ b/aarch32-cpu/src/register/armv8r/hvbar.rs @@ -35,7 +35,7 @@ impl Hvbar { /// /// # Safety /// - /// You must supply a correctly-aligned address of a valid Arm Cortex-R + /// You must supply a correctly-aligned address of a valid Arm AArch32 /// Vector Table. #[inline] pub unsafe fn write(value: Self) { diff --git a/aarch32-cpu/src/register/armv8r/vbar.rs b/aarch32-cpu/src/register/armv8r/vbar.rs index 97cf177..f81f140 100644 --- a/aarch32-cpu/src/register/armv8r/vbar.rs +++ b/aarch32-cpu/src/register/armv8r/vbar.rs @@ -34,7 +34,7 @@ impl Vbar { /// /// # Safety /// - /// You must supply a correctly-aligned address of a valid Arm Cortex-R + /// You must supply a correctly-aligned address of a valid Arm AArch32 /// Vector Table. #[inline] pub unsafe fn write(value: Self) { diff --git a/aarch32-rt-macros/Cargo.toml b/aarch32-rt-macros/Cargo.toml index 6803152..c3d0ce3 100644 --- a/aarch32-rt-macros/Cargo.toml +++ b/aarch32-rt-macros/Cargo.toml @@ -4,7 +4,7 @@ authors = [ "Jonathan Pallant ", "The Embedded Devices Working Group Arm Team " ] -description = "Run-Time macros for Arm Cortex-A and Cortex-R" +description = "Run-Time macros for aarch32-rt" edition = "2021" license = "MIT OR Apache-2.0" name = "aarch32-rt-macros" diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml index 25e55d9..4e203e1 100644 --- a/aarch32-rt/Cargo.toml +++ b/aarch32-rt/Cargo.toml @@ -7,7 +7,7 @@ categories = [ "embedded", "no-std", ] -description = "Run-time support for Arm Cortex-R" +description = "Run-time support for Arm AArch32" edition = "2021" keywords = [ "arm", diff --git a/aarch32-rt/build.rs b/aarch32-rt/build.rs index 75fbd87..2f0bd78 100644 --- a/aarch32-rt/build.rs +++ b/aarch32-rt/build.rs @@ -1,4 +1,4 @@ -//! # Build script for the Cortex-R Runtime +//! # Build script for aarch32-rt //! //! This script only executes when using `cargo` to build the project. //! diff --git a/examples/mps3-an536/Cargo.toml b/examples/mps3-an536/Cargo.toml index 9f5a762..0fea219 100644 --- a/examples/mps3-an536/Cargo.toml +++ b/examples/mps3-an536/Cargo.toml @@ -4,7 +4,7 @@ authors = [ "The Embedded Devices Working Group Arm Team " ] default-run = "hello" -description = "Examples for MPS3-AN536 device (Arm Cortex-R)" +description = "Examples for MPS3-AN536 device (Arm Cortex-R52)" edition = "2021" homepage = "https://github.com/rust-embedded/cortex-ar.git" license = "MIT OR Apache-2.0" diff --git a/examples/mps3-an536/build.rs b/examples/mps3-an536/build.rs index f863833..b0b9f09 100644 --- a/examples/mps3-an536/build.rs +++ b/examples/mps3-an536/build.rs @@ -1,4 +1,4 @@ -//! # Build script for the Cortex-R Examples +//! # Build script for the MPS3-AN536 Examples //! //! This script only executes when using `cargo` to build the project. //! diff --git a/examples/mps3-an536/src/bin/fpu-test.rs b/examples/mps3-an536/src/bin/fpu-test.rs index e7d8b41..ede20b8 100644 --- a/examples/mps3-an536/src/bin/fpu-test.rs +++ b/examples/mps3-an536/src/bin/fpu-test.rs @@ -12,7 +12,7 @@ const MAX_LEN: f32 = BAR.len() as f32; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { const STEPS: u16 = 100; diff --git a/examples/mps3-an536/src/bin/generic_timer.rs b/examples/mps3-an536/src/bin/generic_timer.rs index a292b2b..eff7c30 100644 --- a/examples/mps3-an536/src/bin/generic_timer.rs +++ b/examples/mps3-an536/src/bin/generic_timer.rs @@ -10,7 +10,7 @@ use semihosting::println; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/generic_timer_irq.rs b/examples/mps3-an536/src/bin/generic_timer_irq.rs index 358ec36..98cad0a 100644 --- a/examples/mps3-an536/src/bin/generic_timer_irq.rs +++ b/examples/mps3-an536/src/bin/generic_timer_irq.rs @@ -11,7 +11,7 @@ use semihosting::println; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/gic-map.rs b/examples/mps3-an536/src/bin/gic-map.rs index 99118b6..8be088c 100644 --- a/examples/mps3-an536/src/bin/gic-map.rs +++ b/examples/mps3-an536/src/bin/gic-map.rs @@ -1,4 +1,4 @@ -//! # GIC example for Arm Cortex-R52 on an MPS2-AN336 +//! # GIC example for Arm Cortex-R52 on an MPS2-AN536 //! //! Uses a run-time map of interrupt handlers. @@ -24,7 +24,7 @@ static INTERRUPT_HANDLERS: critical_section::Mutex ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs index 82a7a16..43c6367 100644 --- a/examples/mps3-an536/src/bin/gic-priority-ceiling.rs +++ b/examples/mps3-an536/src/bin/gic-priority-ceiling.rs @@ -1,4 +1,4 @@ -//! GIC example to implement Priority Ceilings for Arm Cortex-R52 on an MPS2-AN336 +//! GIC example to implement Priority Ceilings for Arm Cortex-R52 on an MPS2-AN536 #![no_std] #![no_main] @@ -21,7 +21,7 @@ const HIGH_PRIORITY: u8 = 0x10; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/gic-static-section-irq.rs b/examples/mps3-an536/src/bin/gic-static-section-irq.rs index 5f4a5d0..18717d3 100644 --- a/examples/mps3-an536/src/bin/gic-static-section-irq.rs +++ b/examples/mps3-an536/src/bin/gic-static-section-irq.rs @@ -1,4 +1,4 @@ -//! # GIC example for Arm Cortex-R52 on an MPS2-AN336 +//! # GIC example for Arm Cortex-R52 on an MPS2-AN536 //! //! Uses a linker section to store InterruptHandler objects. @@ -18,7 +18,7 @@ const SGI_INTID_HI: IntId = IntId::sgi(4); /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/gic-unified-irq.rs b/examples/mps3-an536/src/bin/gic-unified-irq.rs index 7d4455d..0cb00c2 100644 --- a/examples/mps3-an536/src/bin/gic-unified-irq.rs +++ b/examples/mps3-an536/src/bin/gic-unified-irq.rs @@ -1,4 +1,4 @@ -//! GIC example for Arm Cortex-R52 on an MPS2-AN336 +//! GIC example for Arm Cortex-R52 on an MPS2-AN536 //! //! As a single, unified, `#[irq]` handler. @@ -18,7 +18,7 @@ const SGI_INTID_HI: IntId = IntId::sgi(4); /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let mut board = mps3_an536::Board::new().unwrap(); diff --git a/examples/mps3-an536/src/bin/hello.rs b/examples/mps3-an536/src/bin/hello.rs index ff719ef..ffb3f11 100644 --- a/examples/mps3-an536/src/bin/hello.rs +++ b/examples/mps3-an536/src/bin/hello.rs @@ -9,7 +9,7 @@ use semihosting::println; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let x = 1.0f64; diff --git a/examples/mps3-an536/src/bin/registers.rs b/examples/mps3-an536/src/bin/registers.rs index 75be143..114ac90 100644 --- a/examples/mps3-an536/src/bin/registers.rs +++ b/examples/mps3-an536/src/bin/registers.rs @@ -9,7 +9,7 @@ use semihosting::println; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { chip_info(); diff --git a/examples/mps3-an536/src/bin/smp_test.rs b/examples/mps3-an536/src/bin/smp_test.rs index 47fa896..37d1dd1 100644 --- a/examples/mps3-an536/src/bin/smp_test.rs +++ b/examples/mps3-an536/src/bin/smp_test.rs @@ -57,7 +57,7 @@ const CS_MUTEX_LOOPS: u32 = 1000; /// The entry-point to the Rust application. /// -/// It is called by the start-up code in `cortex-r-rt`. +/// It is called by the start-up code in `aarch32-rt`. #[entry] fn main() -> ! { let fpga_led = 0xE020_2000 as *mut u32; diff --git a/examples/versatileab/build.rs b/examples/versatileab/build.rs index 701d520..7871f45 100644 --- a/examples/versatileab/build.rs +++ b/examples/versatileab/build.rs @@ -1,4 +1,4 @@ -//! # Build script for the Cortex-R Examples +//! # Build script for the VersatileAB Examples //! //! This script only executes when using `cargo` to build the project. //! From 45dc402d984babfa418aa34f6d4557750facafdf Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Wed, 29 Oct 2025 12:22:38 +0000 Subject: [PATCH 2/3] Support thumbv4t-none-eabi and thumbv5te-none-eabi --- .cargo/config.toml | 6 + aarch32-cpu/src/asmv4.rs | 68 ++++++ aarch32-cpu/src/{asm.rs => asmv7.rs} | 57 ++--- aarch32-cpu/src/interrupt.rs | 70 +----- aarch32-cpu/src/lib.rs | 17 +- aarch32-cpu/src/register/cpsr.rs | 18 +- aarch32-cpu/src/register/mod.rs | 12 +- aarch32-rt/src/arch_v4/abort.rs | 2 + aarch32-rt/src/arch_v4/interrupt.rs | 1 + aarch32-rt/src/arch_v4/svc.rs | 1 + aarch32-rt/src/arch_v4/undefined.rs | 1 + aarch32-rt/src/lib.rs | 5 +- arm-targets/src/lib.rs | 22 +- .../abt-exception-a32-thumbv4t-none-eabi.out | 14 ++ .../abt-exception-a32-thumbv5te-none-eabi.out | 14 ++ .../abt-exception-t32-thumbv4t-none-eabi.out | 14 ++ .../abt-exception-t32-thumbv5te-none-eabi.out | 14 ++ .../reference/fpu-test-thumbv4t-none-eabi.out | 202 ++++++++++++++++++ .../fpu-test-thumbv5te-none-eabi.out | 202 ++++++++++++++++++ .../reference/hello-thumbv4t-none-eabi.out | 11 + .../reference/hello-thumbv5te-none-eabi.out | 11 + .../interrupt-thumbv4t-none-eabi.out | 3 + .../interrupt-thumbv5te-none-eabi.out | 3 + ...fetch-exception-a32-thumbv4t-none-eabi.out | 10 + ...etch-exception-a32-thumbv5te-none-eabi.out | 10 + ...fetch-exception-t32-thumbv4t-none-eabi.out | 10 + ...etch-exception-t32-thumbv5te-none-eabi.out | 10 + .../registers-thumbv4t-none-eabi.out | 5 + .../registers-thumbv5te-none-eabi.out | 5 + .../reference/svc-a32-armv4t-none-eabi.out | 2 +- .../reference/svc-a32-armv5te-none-eabi.out | 2 +- .../reference/svc-a32-armv7a-none-eabi.out | 2 +- .../reference/svc-a32-armv7a-none-eabihf.out | 2 +- .../reference/svc-a32-armv7r-none-eabi.out | 2 +- .../reference/svc-a32-armv7r-none-eabihf.out | 2 +- .../reference/svc-a32-thumbv4t-none-eabi.out | 12 ++ .../reference/svc-a32-thumbv5te-none-eabi.out | 12 ++ .../reference/svc-t32-thumbv4t-none-eabi.out | 14 ++ .../reference/svc-t32-thumbv5te-none-eabi.out | 14 ++ ...undef-exception-a32-thumbv4t-none-eabi.out | 8 + ...ndef-exception-a32-thumbv5te-none-eabi.out | 8 + ...undef-exception-t32-thumbv4t-none-eabi.out | 8 + ...ndef-exception-t32-thumbv5te-none-eabi.out | 8 + examples/versatileab/src/bin/svc-a32.rs | 2 + tests.sh | 18 ++ 45 files changed, 803 insertions(+), 131 deletions(-) create mode 100644 aarch32-cpu/src/asmv4.rs rename aarch32-cpu/src/{asm.rs => asmv7.rs} (74%) create mode 100644 examples/versatileab/reference/abt-exception-a32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/abt-exception-a32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/abt-exception-t32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/abt-exception-t32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/fpu-test-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/fpu-test-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/hello-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/hello-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/interrupt-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/interrupt-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/prefetch-exception-a32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/prefetch-exception-a32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/prefetch-exception-t32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/prefetch-exception-t32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/registers-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/registers-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/svc-a32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/svc-a32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/svc-t32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/svc-t32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/undef-exception-a32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/undef-exception-a32-thumbv5te-none-eabi.out create mode 100644 examples/versatileab/reference/undef-exception-t32-thumbv4t-none-eabi.out create mode 100644 examples/versatileab/reference/undef-exception-t32-thumbv5te-none-eabi.out diff --git a/.cargo/config.toml b/.cargo/config.toml index a34439b..e06644f 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -22,5 +22,11 @@ runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nograph [target.armv4t-none-eabi] runner = "qemu-system-arm -machine versatileab -cpu pxa250 -semihosting -nographic -audio none -kernel" +[target.thumbv5te-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel" + +[target.thumbv4t-none-eabi] +runner = "qemu-system-arm -machine versatileab -cpu pxa250 -semihosting -nographic -audio none -kernel" + [unstable] build-std = ["core", "alloc"] diff --git a/aarch32-cpu/src/asmv4.rs b/aarch32-cpu/src/asmv4.rs new file mode 100644 index 0000000..4c696a2 --- /dev/null +++ b/aarch32-cpu/src/asmv4.rs @@ -0,0 +1,68 @@ +//! Simple assembly routines for ARMv4 + +/// Emit an NOP instruction +#[cfg_attr(not(feature = "check-asm"), inline)] +pub fn nop() { + unsafe { core::arch::asm!("nop", options(nomem, nostack, preserves_flags)) } +} + +/// Mask IRQ +#[cfg_attr(not(feature = "check-asm"), inline)] +#[instruction_set(arm::a32)] +pub fn irq_disable() { + unsafe { + core::arch::asm!(r#" + mrs {0}, cpsr + orr {0}, {flag} + msr cpsr, {0} + "#, + in(reg) 0, + flag = const { + crate::register::Cpsr::new_with_raw_value(0) + .with_i(true) + .raw_value() + }, + options(nomem, nostack, preserves_flags)); + }; +} + +/// Unmask IRQ +#[cfg_attr(not(feature = "check-asm"), inline)] +#[instruction_set(arm::a32)] +pub fn irq_enable() { + unsafe { + core::arch::asm!(r#" + mrs {0}, cpsr + bic {0}, #{flag} + msr cpsr, {0} + "#, + in(reg) 0, + flag = const { + crate::register::Cpsr::new_with_raw_value(0) + .with_i(true) + .raw_value() + }, + options(nomem, nostack, preserves_flags)); + }; +} + +/// Which core are we? +/// +/// Return the bottom 24-bits of the MPIDR +#[cfg_attr(not(feature = "check-asm"), inline)] +#[instruction_set(arm::a32)] +pub fn core_id() -> u32 { + let r: u32; + unsafe { + core::arch::asm!("MRC p15, 0, {}, c0, c0, 5", out(reg) r, options(nomem, nostack, preserves_flags)); + } + r & 0x00FF_FFFF +} + +#[no_mangle] +pub extern "C" fn __sync_synchronize() { + // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block + unsafe { + core::arch::asm!(""); + } +} diff --git a/aarch32-cpu/src/asm.rs b/aarch32-cpu/src/asmv7.rs similarity index 74% rename from aarch32-cpu/src/asm.rs rename to aarch32-cpu/src/asmv7.rs index 62e4c5a..e7f184c 100644 --- a/aarch32-cpu/src/asm.rs +++ b/aarch32-cpu/src/asmv7.rs @@ -1,4 +1,4 @@ -//! Simple assembly routines +//! Simple assembly routines for ARMv7 /// Data Memory Barrier /// @@ -6,11 +6,6 @@ /// instruction are observed before any explicit memory accesses that appear in program order /// after the `DMB` instruction. #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn dmb() { use core::sync::atomic::{compiler_fence, Ordering}; compiler_fence(Ordering::SeqCst); @@ -28,11 +23,6 @@ pub fn dmb() { /// * any explicit memory access made before this instruction is complete /// * all cache and branch predictor maintenance operations before this instruction complete #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn dsb() { use core::sync::atomic::{compiler_fence, Ordering}; compiler_fence(Ordering::SeqCst); @@ -47,11 +37,6 @@ pub fn dsb() { /// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched /// from cache or memory, after the instruction has been completed. #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn isb() { use core::sync::atomic::{compiler_fence, Ordering}; compiler_fence(Ordering::SeqCst); @@ -69,39 +54,40 @@ pub fn nop() { /// Emit an WFI instruction #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn wfi() { unsafe { core::arch::asm!("wfi", options(nomem, nostack, preserves_flags)) } } /// Emit an WFE instruction #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn wfe() { unsafe { core::arch::asm!("wfe", options(nomem, nostack, preserves_flags)) } } /// Emit an SEV instruction #[cfg_attr(not(feature = "check-asm"), inline)] -#[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" -))] pub fn sev() { unsafe { core::arch::asm!("sev"); } } +/// Mask IRQ +#[cfg_attr(not(feature = "check-asm"), inline)] +pub fn irq_disable() { + unsafe { + core::arch::asm!("cpsid i"); + } +} + +/// Unmask IRQ +#[cfg_attr(not(feature = "check-asm"), inline)] +pub fn irq_enable() { + unsafe { + core::arch::asm!("cpsie i"); + } +} + /// Which core are we? /// /// Return the bottom 24-bits of the MPIDR @@ -113,12 +99,3 @@ pub fn core_id() -> u32 { } r & 0x00FF_FFFF } - -#[cfg(any(arm_architecture = "v4t", arm_architecture = "v5te"))] -#[no_mangle] -pub extern "C" fn __sync_synchronize() { - // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block - unsafe { - core::arch::asm!(""); - } -} diff --git a/aarch32-cpu/src/interrupt.rs b/aarch32-cpu/src/interrupt.rs index 49ce38f..b8d5140 100644 --- a/aarch32-cpu/src/interrupt.rs +++ b/aarch32-cpu/src/interrupt.rs @@ -14,40 +14,7 @@ use core::sync::atomic::{compiler_fence, Ordering}; pub unsafe fn enable() { // Ensure no preceeding memory accesses are reordered to after interrupts are enabled. compiler_fence(Ordering::SeqCst); - // Safety: A Data Store Barrier is OK to call anywhere, and we're - // atomically setting a bit in a special register, and we're in an unsafe - // function that places restrictions on when you can call it - #[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" - ))] - unsafe { - core::arch::asm!( - r#" - dsb - cpsie i - "#, - options(nomem, nostack, preserves_flags) - ); - }; - #[cfg(all( - target_arch = "arm", - not(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" - )) - ))] - unsafe { - core::arch::asm!(r#" - mrs {0}, cpsr - orr {0}, #0xC0 - msr cpsr, {0} - "#, - in(reg) 0, - options(nomem, nostack, preserves_flags)); - }; + crate::asm::irq_enable(); } /// Disable IRQ @@ -56,40 +23,7 @@ pub unsafe fn enable() { /// * Doesn't disable FIQ. #[inline] pub fn disable() { - // Safety: A Data Store Barrier is OK to call anywhere, and we're - // atomically setting a bit in a special register, and we're in an unsafe - // function that places restrictions on when you can call it - #[cfg(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" - ))] - unsafe { - core::arch::asm!( - r#" - cpsid i - dsb - "#, - options(nomem, nostack, preserves_flags) - ); - }; - #[cfg(all( - target_arch = "arm", - not(any( - arm_architecture = "v7-r", - arm_architecture = "v7-a", - arm_architecture = "v8-r" - )) - ))] - unsafe { - core::arch::asm!(r#" - mrs {0}, cpsr - bic {0}, #0xC0 - msr cpsr, {0} - "#, - in(reg) 0, - options(nomem, nostack, preserves_flags)); - }; + crate::asm::irq_disable(); // Ensure no subsequent memory accesses are reordered to before interrupts are disabled. compiler_fence(Ordering::SeqCst); } diff --git a/aarch32-cpu/src/lib.rs b/aarch32-cpu/src/lib.rs index 9c965af..2ffdb32 100644 --- a/aarch32-cpu/src/lib.rs +++ b/aarch32-cpu/src/lib.rs @@ -3,7 +3,22 @@ mod critical_section; -#[cfg(any(doc, target_arch = "arm"))] +#[cfg(any( + doc, + arm_architecture = "v7-a", + arm_architecture = "v7-r", + arm_architecture = "v8-r" +))] +#[path = "asmv7.rs"] +pub mod asm; + +#[cfg(not(any( + doc, + arm_architecture = "v7-a", + arm_architecture = "v7-r", + arm_architecture = "v8-r" +)))] +#[path = "asmv4.rs"] pub mod asm; pub mod cache; diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs index 41b5b20..8fab4af 100644 --- a/aarch32-cpu/src/register/cpsr.rs +++ b/aarch32-cpu/src/register/cpsr.rs @@ -70,7 +70,14 @@ pub struct Cpsr { impl Cpsr { /// Read CPSR (*Current Program Status Register*) - #[inline] + /// + /// On Armv4T and Armv5TE this will be an Arm function, even on the + /// `thumb*` targets, as Thumb-1 cannot do an MRS. + #[cfg_attr(not(feature = "check-asm"), inline)] + #[cfg_attr( + any(arm_architecture = "v4t", arm_architecture = "v5te"), + instruction_set(arm::a32) + )] pub fn read() -> Self { let r: u32; // Safety: Reading this register has no side-effects and is atomic @@ -96,7 +103,14 @@ impl Cpsr { /// /// You almost certainly want to follow this with an [ISB](crate::asm::isb) /// instruction. - #[inline] + /// + /// On Armv4T and Armv5TE this will be an Arm function, even on the + /// `thumb*` targets, as Thumb-1 cannot do an MSR. + #[cfg_attr(not(feature = "check-asm"), inline)] + #[cfg_attr( + any(arm_architecture = "v4t", arm_architecture = "v5te"), + instruction_set(arm::a32) + )] pub unsafe fn write(_value: Self) { // Safety: This is risky, but we're in an unsafe function #[cfg(target_arch = "arm")] diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs index e60041a..7dac1a3 100644 --- a/aarch32-cpu/src/register/mod.rs +++ b/aarch32-cpu/src/register/mod.rs @@ -223,7 +223,11 @@ pub trait SysRegRead: SysReg { /// /// You need to read the Architecture Reference Manual because this read /// may have side-effects. - #[inline] + #[cfg_attr(not(feature = "check-asm"), inline)] + #[cfg_attr( + any(arm_architecture = "v4t", arm_architecture = "v5te"), + instruction_set(arm::a32) + )] unsafe fn read_raw() -> u32 { let r: u32; #[cfg(target_arch = "arm")] @@ -255,7 +259,11 @@ pub trait SysRegWrite: SysReg { /// /// You need to read the Architecture Reference Manual to verify that you are /// writing valid data here. - #[inline] + #[cfg_attr(not(feature = "check-asm"), inline)] + #[cfg_attr( + any(arm_architecture = "v4t", arm_architecture = "v5te"), + instruction_set(arm::a32) + )] unsafe fn write_raw(_value: u32) { #[cfg(target_arch = "arm")] unsafe { diff --git a/aarch32-rt/src/arch_v4/abort.rs b/aarch32-rt/src/arch_v4/abort.rs index db3a085..bca1038 100644 --- a/aarch32-rt/src/arch_v4/abort.rs +++ b/aarch32-rt/src/arch_v4/abort.rs @@ -11,6 +11,7 @@ core::arch::global_asm!( // Saves state and calls a C-compatible handler like // `extern "C" fn _data_abort_handler(addr: usize);` .global _asm_default_data_abort_handler + .arm .type _asm_default_data_abort_handler, %function _asm_default_data_abort_handler: // Subtract 8 from the stored LR, see p.1214 of the ARMv7-A architecture manual. @@ -44,6 +45,7 @@ core::arch::global_asm!( // Saves state and calls a C-compatible handler like // `extern "C" fn _prefetch_abort_handler(addr: usize);` .global _asm_default_prefetch_abort_handler + .arm .type _asm_default_prefetch_abort_handler, %function _asm_default_prefetch_abort_handler: // Subtract 4 from the stored LR, see p.1212 of the ARMv7-A architecture manual. diff --git a/aarch32-rt/src/arch_v4/interrupt.rs b/aarch32-rt/src/arch_v4/interrupt.rs index 975c71e..3a9a19d 100644 --- a/aarch32-rt/src/arch_v4/interrupt.rs +++ b/aarch32-rt/src/arch_v4/interrupt.rs @@ -14,6 +14,7 @@ core::arch::global_asm!( // Saves state and calls a C-compatible handler like // `extern "C" fn _irq_handler();` .global _asm_default_irq_handler + .arm .type _asm_default_irq_handler, %function _asm_default_irq_handler: // make sure we jump back to the right place diff --git a/aarch32-rt/src/arch_v4/svc.rs b/aarch32-rt/src/arch_v4/svc.rs index 26ff233..91dc019 100644 --- a/aarch32-rt/src/arch_v4/svc.rs +++ b/aarch32-rt/src/arch_v4/svc.rs @@ -12,6 +12,7 @@ core::arch::global_asm!( // Saves state and calls a C-compatible handler like // `extern "C" fn _svc_handler(svc: u32);` .global _asm_default_svc_handler + .arm .type _asm_default_svc_handler, %function _asm_default_svc_handler: stmfd sp!, {{ r0, lr }} diff --git a/aarch32-rt/src/arch_v4/undefined.rs b/aarch32-rt/src/arch_v4/undefined.rs index 99c0403..9297ee1 100644 --- a/aarch32-rt/src/arch_v4/undefined.rs +++ b/aarch32-rt/src/arch_v4/undefined.rs @@ -12,6 +12,7 @@ core::arch::global_asm!( // or // `extern "C" fn _undefined_handler(addr: usize) -> !;` .section .text._asm_default_undefined_handler + .arm .global _asm_default_undefined_handler .type _asm_default_undefined_handler, %function _asm_default_undefined_handler: diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs index a6e3f93..176409d 100644 --- a/aarch32-rt/src/lib.rs +++ b/aarch32-rt/src/lib.rs @@ -491,6 +491,7 @@ pub extern "C" fn _default_handler() { core::arch::global_asm!( r#" .section .vector_table,"ax",%progbits + .arm .global _vector_table .type _vector_table, %function _vector_table: @@ -776,6 +777,7 @@ core::arch::global_asm!( // Initialises stacks, .data and .bss .section .text._init_segments .global _init_segments + .arm .type _init_segments, %function _init_segments: // Initialise .bss @@ -862,6 +864,7 @@ core::arch::global_asm!( .fpu vfp2 .section .text.default_start + .arm .global _default_start .type _default_start, %function _default_start: @@ -908,7 +911,7 @@ core::arch::global_asm!( .fpu vfp2 .section .text.default_start - + .arm .global _default_start .type _default_start, %function _default_start: diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs index b503417..259e4e5 100644 --- a/arm-targets/src/lib.rs +++ b/arm-targets/src/lib.rs @@ -133,15 +133,15 @@ pub enum Isa { impl Isa { /// Decode a target string pub fn get(target: &str) -> Option { - let arch = Arch::get(target)?; - Some(match arch { - Arch::Armv4T | Arch::Armv5TE | Arch::Armv6 => Isa::A32, - Arch::Armv6M | Arch::Armv7M | Arch::Armv7EM | Arch::Armv8MBase | Arch::Armv8MMain => { - Isa::T32 - } - Arch::Armv7R | Arch::Armv8R | Arch::Armv7A => Isa::A32, - Arch::Armv8A => Isa::A64, - }) + if target.starts_with("arm") { + Some(Isa::A32) + } else if target.starts_with("thumb") { + Some(Isa::T32) + } else if target.starts_with("aarch64") { + Some(Isa::A64) + } else { + None + } } /// Get a comma-separated list of values, suitable for cfg-check @@ -202,9 +202,9 @@ pub enum Arch { impl Arch { /// Decode a target string pub fn get(target: &str) -> Option { - if target.starts_with("armv4t-") { + if target.starts_with("armv4t-") || target.starts_with("thumbv4t-") { Some(Arch::Armv4T) - } else if target.starts_with("armv5te-") { + } else if target.starts_with("armv5te-") || target.starts_with("thumbv5te-") { Some(Arch::Armv5TE) } else if target.starts_with("thumbv6m-") { Some(Arch::Armv6M) diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv4t-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv4t-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-a32-thumbv5te-none-eabi.out b/examples/versatileab/reference/abt-exception-a32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..a41df9a --- /dev/null +++ b/examples/versatileab/reference/abt-exception-a32-thumbv5te-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_a32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv4t-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv4t-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/abt-exception-t32-thumbv5te-none-eabi.out b/examples/versatileab/reference/abt-exception-t32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..35dff8b --- /dev/null +++ b/examples/versatileab/reference/abt-exception-t32-thumbv5te-none-eabi.out @@ -0,0 +1,14 @@ +Hello, this is an data abort exception example +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Doing it again +data abort occurred +DFSR (Fault Status Register): DFSR { ext=false wnr=false Domain=0b0000 Status=0b00001 } +DFSR Status: Ok(AlignmentFault) +caught unaligned_from_t32 +caught fault on COUNTER +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/fpu-test-thumbv4t-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv4t-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv4t-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) 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.................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/fpu-test-thumbv5te-none-eabi.out b/examples/versatileab/reference/fpu-test-thumbv5te-none-eabi.out new file mode 100644 index 0000000..e26f6b9 --- /dev/null +++ b/examples/versatileab/reference/fpu-test-thumbv5te-none-eabi.out @@ -0,0 +1,202 @@ +Sine wave test (f32)... +( 0.0000) ..............................o +( 0.1253) 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.........................................................o +( 0.9511) ..........................................................o +( 0.9823) ...........................................................o +( 0.9980) ...........................................................o +( 0.9980) ...........................................................o +( 0.9823) ...........................................................o +( 0.9511) ..........................................................o +( 0.9048) .........................................................o +( 0.8443) .......................................................o +( 0.7705) .....................................................o +( 0.6845) ..................................................o +( 0.5878) ...............................................o +( 0.4818) ............................................o +( 0.3681) .........................................o +( 0.2487) .....................................o +( 0.1253) .................................o +(-0.0000) .............................o +(-0.1253) ..........................o +(-0.2487) ......................o +(-0.3681) ..................o +(-0.4818) ...............o +(-0.5878) ............o +(-0.6845) .........o +(-0.7705) ......o +(-0.8443) ....o +(-0.9048) ..o +(-0.9511) .o +(-0.9823) o +(-0.9980) o +(-0.9980) o +(-0.9823) o +(-0.9511) .o +(-0.9048) ..o +(-0.8443) ....o +(-0.7705) ......o +(-0.6845) .........o +(-0.5878) ............o +(-0.4818) ...............o +(-0.3681) ..................o +(-0.2487) ......................o +(-0.1253) ..........................o diff --git a/examples/versatileab/reference/hello-thumbv4t-none-eabi.out b/examples/versatileab/reference/hello-thumbv4t-none-eabi.out new file mode 100644 index 0000000..0d377af --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv4t-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 18, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/hello-thumbv5te-none-eabi.out b/examples/versatileab/reference/hello-thumbv5te-none-eabi.out new file mode 100644 index 0000000..0d377af --- /dev/null +++ b/examples/versatileab/reference/hello-thumbv5te-none-eabi.out @@ -0,0 +1,11 @@ +Hello, this is semihosting! x = 1.000, y = 2.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/hello.rs", + line: 18, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/interrupt-thumbv4t-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv4t-none-eabi.out new file mode 100644 index 0000000..f7caea3 --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv4t-none-eabi.out @@ -0,0 +1,3 @@ +Firing interrupt... +Clearing interrupt... +Got interrupted :) diff --git a/examples/versatileab/reference/interrupt-thumbv5te-none-eabi.out b/examples/versatileab/reference/interrupt-thumbv5te-none-eabi.out new file mode 100644 index 0000000..f7caea3 --- /dev/null +++ b/examples/versatileab/reference/interrupt-thumbv5te-none-eabi.out @@ -0,0 +1,3 @@ +Firing interrupt... +Clearing interrupt... +Got interrupted :) diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv4t-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv4t-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-a32-thumbv5te-none-eabi.out b/examples/versatileab/reference/prefetch-exception-a32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-a32-thumbv5te-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv4t-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv4t-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/prefetch-exception-t32-thumbv5te-none-eabi.out b/examples/versatileab/reference/prefetch-exception-t32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..6d48bd3 --- /dev/null +++ b/examples/versatileab/reference/prefetch-exception-t32-thumbv5te-none-eabi.out @@ -0,0 +1,10 @@ +Hello, this is a prefetch abort exception example +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Doing it again +prefetch abort occurred +IFSR (Fault Status Register): IFSR { ext=false Domain=0b0000 Status=0b00010 } +IFSR Status: Ok(DebugEvent) +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/registers-thumbv4t-none-eabi.out b/examples/versatileab/reference/registers-thumbv4t-none-eabi.out new file mode 100644 index 0000000..5837893 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv4t-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x69 variant=0x0 arch=0x5 part_no=0x210 rev=0x0 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(1761943808) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/registers-thumbv5te-none-eabi.out b/examples/versatileab/reference/registers-thumbv5te-none-eabi.out new file mode 100644 index 0000000..48cca85 --- /dev/null +++ b/examples/versatileab/reference/registers-thumbv5te-none-eabi.out @@ -0,0 +1,5 @@ +MIDR { implementer=0x41 variant=0x0 arch=0x6 part_no=0x926 rev=0x5 } +CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=1 I=1 F=1 T=0 MODE=Ok(Sys) } +Mpidr(1090949733) +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=0 Z=0 SW=0 C=0 A=0 M=0 } before setting C, I and Z +SCTLR { IE=0 TE=0 NMFI=0 EE=0 U=0 FI=0 DZ=0 BR=0 RR=0 V=0 I=1 Z=1 SW=0 C=1 A=0 M=0 } after diff --git a/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out b/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out +++ b/examples/versatileab/reference/svc-a32-armv4t-none-eabi.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out b/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out +++ b/examples/versatileab/reference/svc-a32-armv5te-none-eabi.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out b/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out +++ b/examples/versatileab/reference/svc-a32-armv7a-none-eabi.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out +++ b/examples/versatileab/reference/svc-a32-armv7a-none-eabihf.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out b/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out +++ b/examples/versatileab/reference/svc-a32-armv7r-none-eabi.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out b/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out index d8cc028..aa7cc28 100644 --- a/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out +++ b/examples/versatileab/reference/svc-a32-armv7r-none-eabihf.out @@ -6,7 +6,7 @@ PANIC: PanicInfo { message: I am an example panic, location: Location { file: "src/bin/svc-a32.rs", - line: 21, + line: 22, column: 5, }, can_unwind: true, diff --git a/examples/versatileab/reference/svc-a32-thumbv4t-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..1eeccb9 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv4t-none-eabi.out @@ -0,0 +1,12 @@ +x = 1, y = 2, z = 3.000 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-a32.rs", + line: 22, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-a32-thumbv5te-none-eabi.out b/examples/versatileab/reference/svc-a32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..1eeccb9 --- /dev/null +++ b/examples/versatileab/reference/svc-a32-thumbv5te-none-eabi.out @@ -0,0 +1,12 @@ +x = 1, y = 2, z = 3.000 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-a32.rs", + line: 22, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-t32-thumbv4t-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..3476848 --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv4t-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-t32.rs", + line: 23, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/svc-t32-thumbv5te-none-eabi.out b/examples/versatileab/reference/svc-t32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..3476848 --- /dev/null +++ b/examples/versatileab/reference/svc-t32-thumbv5te-none-eabi.out @@ -0,0 +1,14 @@ +x = 1, y = 2, z = 3.000 +In svc_handler, with arg=0x000012 +In svc_handler, with arg=0x000034 +x = 1, y = 2, z = 3.000 +PANIC: PanicInfo { + message: I am an example panic, + location: Location { + file: "src/bin/svc-t32.rs", + line: 23, + column: 5, + }, + can_unwind: true, + force_no_backtrace: false, +} diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv4t-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv4t-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-a32-thumbv5te-none-eabi.out b/examples/versatileab/reference/undef-exception-a32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..dbafb84 --- /dev/null +++ b/examples/versatileab/reference/undef-exception-a32-thumbv5te-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_a32 +Doing it again +undefined abort occurred +caught udf_from_a32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv4t-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv4t-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv4t-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/reference/undef-exception-t32-thumbv5te-none-eabi.out b/examples/versatileab/reference/undef-exception-t32-thumbv5te-none-eabi.out new file mode 100644 index 0000000..083a29c --- /dev/null +++ b/examples/versatileab/reference/undef-exception-t32-thumbv5te-none-eabi.out @@ -0,0 +1,8 @@ +Hello, this is a undef exception example +undefined abort occurred +caught udf_from_t32 +Doing it again +undefined abort occurred +caught udf_from_t32 +Skipping instruction +Recovered from fault OK! diff --git a/examples/versatileab/src/bin/svc-a32.rs b/examples/versatileab/src/bin/svc-a32.rs index 0006eef..556c26a 100644 --- a/examples/versatileab/src/bin/svc-a32.rs +++ b/examples/versatileab/src/bin/svc-a32.rs @@ -16,6 +16,7 @@ fn main() -> ! { let y = x + 1; let z = (y as f64) * 1.5; println!("x = {}, y = {}, z = {:0.3}", x, y, z); + #[cfg(arm_isa = "a32")] aarch32_cpu::svc!(0xABCDEF); println!("x = {}, y = {}, z = {:0.3}", x, y, z); panic!("I am an example panic"); @@ -27,6 +28,7 @@ fn svc_handler(arg: u32) { println!("In svc_handler, with arg=0x{:06x}", arg); if arg == 0xABCDEF { // test nested SVC calls + #[cfg(arm_isa = "a32")] aarch32_cpu::svc!(0x456789); } } diff --git a/tests.sh b/tests.sh index 72bcc4f..97f2762 100755 --- a/tests.sh +++ b/tests.sh @@ -100,6 +100,15 @@ for bin_path in $(ls examples/versatileab/src/bin/*.rs); do my_diff ./examples/versatileab/reference/$binary-armv5te-none-eabi.out ./target/$binary-armv5te-none-eabi.out || fail $binary "armv5te-none-eabi" done +# thumbv5te-none-eabi tests +RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=thumbv5te-none-eabi +for bin_path in $(ls examples/versatileab/src/bin/*.rs); do + filename=${bin_path##*/} + binary=${filename%.rs} + RUSTC_BOOTSTRAP=1 cargo run ${versatile_ab_cargo} --target=thumbv5te-none-eabi --bin $binary > ./target/$binary-thumbv5te-none-eabi.out + my_diff ./examples/versatileab/reference/$binary-thumbv5te-none-eabi.out ./target/$binary-thumbv5te-none-eabi.out || fail $binary "thumbv5te-none-eabi" +done + # armv4t-none-eabi tests RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=armv4t-none-eabi for bin_path in $(ls examples/versatileab/src/bin/*.rs); do @@ -109,6 +118,15 @@ for bin_path in $(ls examples/versatileab/src/bin/*.rs); do my_diff ./examples/versatileab/reference/$binary-armv4t-none-eabi.out ./target/$binary-armv4t-none-eabi.out || fail $binary "armv4t-none-eabi" done +# thumbv4t-none-eabi tests +RUSTC_BOOTSTRAP=1 cargo build ${versatile_ab_cargo} --target=thumbv4t-none-eabi +for bin_path in $(ls examples/versatileab/src/bin/*.rs); do + filename=${bin_path##*/} + binary=${filename%.rs} + RUSTC_BOOTSTRAP=1 cargo run ${versatile_ab_cargo} --target=thumbv4t-none-eabi --bin $binary > ./target/$binary-thumbv4t-none-eabi.out + my_diff ./examples/versatileab/reference/$binary-thumbv4t-none-eabi.out ./target/$binary-thumbv4t-none-eabi.out || fail $binary "thumbv4t-none-eabi" +done + # These tests only run on QEMU 9 or higher. # Ubuntu 24.04 supplies QEMU 8, which doesn't support the machine we have configured for this target RUSTC_BOOTSTRAP=1 cargo build ${mps3_an536_cargo} --target=armv8r-none-eabihf || exit 1 From 75890e8788e6f17441a22e7e7089853e4db25d23 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Wed, 29 Oct 2025 12:59:15 +0000 Subject: [PATCH 3/3] Provide empty irq_enable/irq_disable asm stubs so the tests work. --- aarch32-cpu/src/asmv4.rs | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/aarch32-cpu/src/asmv4.rs b/aarch32-cpu/src/asmv4.rs index 4c696a2..b1273b5 100644 --- a/aarch32-cpu/src/asmv4.rs +++ b/aarch32-cpu/src/asmv4.rs @@ -8,8 +8,9 @@ pub fn nop() { /// Mask IRQ #[cfg_attr(not(feature = "check-asm"), inline)] -#[instruction_set(arm::a32)] +#[cfg_attr(target_arch = "arm", instruction_set(arm::a32))] pub fn irq_disable() { + #[cfg(target_arch = "arm")] unsafe { core::arch::asm!(r#" mrs {0}, cpsr @@ -28,8 +29,9 @@ pub fn irq_disable() { /// Unmask IRQ #[cfg_attr(not(feature = "check-asm"), inline)] -#[instruction_set(arm::a32)] +#[cfg_attr(target_arch = "arm", instruction_set(arm::a32))] pub fn irq_enable() { + #[cfg(target_arch = "arm")] unsafe { core::arch::asm!(r#" mrs {0}, cpsr @@ -50,6 +52,7 @@ pub fn irq_enable() { /// /// Return the bottom 24-bits of the MPIDR #[cfg_attr(not(feature = "check-asm"), inline)] +#[cfg(target_arch = "arm")] #[instruction_set(arm::a32)] pub fn core_id() -> u32 { let r: u32;