update MMU code

Author: robamu

cortex-ar/CHANGELOG.md

@@ -10,6 +10,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - `dmb` data memory barrier in ASM module.
+- MMU code: `SectionAttributes::raw()` method and `SectionAttributes::from_raw()` and
+  `SectionAttributes::from_raw_unchecked` constructors.
+
+### Changed
+
+- MMU code: Use more `arbitrary-int` types for MMU configuration bits.
 
 ## [v0.2.0]
 

cortex-ar/Cargo.toml

@@ -29,6 +29,7 @@ arbitrary-int = "1.3.0"
 bitbybit = "1.3.3"
 num_enum = { version = "0.7", default-features = false }
 critical-section = {version = "1.2.0", features = ["restore-state-u8"], optional = true}
+thiserror = { version = "2", default-features = false }
 defmt = {version = "0.3", optional = true}
 
 [build-dependencies]
@@ -42,7 +43,7 @@ critical-section-single-core = ["critical-section"]
 # a CAS spinlock.
 critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
-defmt = ["dep:defmt"]
+defmt = ["dep:defmt", "arbitrary-int/defmt"]
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]

cortex-ar/src/mmu.rs

@@ -1,7 +1,13 @@
 use arbitrary_int::{u12, u2, u3, u4};
 
-#[derive(Debug, Copy, Clone)]
-#[repr(u8)]
+#[derive(Debug, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[error("invalid L1 entry type {0:?}")]
+pub struct InvalidL1EntryType(pub L1EntryType);
+
+#[bitbybit::bitenum(u3, exhaustive = true)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Debug)]
 pub enum AccessPermissions {
     PermissionFault = 0b000,
     PrivilegedOnly = 0b001,
@@ -14,18 +20,28 @@ pub enum AccessPermissions {
 }
 
 impl AccessPermissions {
-    const fn ap(&self) -> u8 {
-        (*self as u8) & 0b11
+    #[inline]
+    pub const fn new(apx: bool, ap: u2) -> Self {
+        Self::new_with_raw_value(u3::new(((apx as u8) << 2) | ap.value()))
     }
 
-    const fn apx(&self) -> bool {
+    /// AP bit for the given access permission.
+    #[inline]
+    pub const fn ap(&self) -> u2 {
+        u2::new((*self as u8) & 0b11)
+    }
+
+    /// APX bit for the given access permission.
+    #[inline]
+    pub const fn apx(&self) -> bool {
         (*self as u8) > (AccessPermissions::FullAccess as u8)
     }
 }
 
-#[derive(Debug)]
-#[repr(u8)]
 #[bitbybit::bitenum(u2, exhaustive = true)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Debug, PartialEq, Eq)]
+#[repr(u8)]
 pub enum L1EntryType {
     /// Access generates an abort exception. Indicates an unmapped virtual address.
     Fault = 0b00,
@@ -43,15 +59,17 @@ pub enum L1EntryType {
 /// earlier versions of the architecture. These names no longer adequately describe the function
 /// of the B, C, and TEX bits.
 #[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct MemoryRegionAttributesRaw {
     /// TEX bits
-    type_extensions: u8,
+    type_extensions: u3,
     c: bool,
     b: bool,
 }
 
 impl MemoryRegionAttributesRaw {
-    pub const fn new(type_extensions: u8, c: bool, b: bool) -> Self {
+    #[inline]
+    pub const fn new(type_extensions: u3, c: bool, b: bool) -> Self {
         Self {
             type_extensions,
             c,
@@ -60,7 +78,9 @@ impl MemoryRegionAttributesRaw {
     }
 }
 
-#[derive(Debug, Copy, Clone)]
+#[bitbybit::bitenum(u2, exhaustive = true)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Debug)]
 pub enum CacheableMemoryAttribute {
     NonCacheable = 0b00,
     WriteBackWriteAlloc = 0b01,
@@ -69,6 +89,7 @@ pub enum CacheableMemoryAttribute {
 }
 
 #[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum MemoryRegionAttributes {
     StronglyOrdered,
     ShareableDevice,
@@ -87,29 +108,29 @@ impl MemoryRegionAttributes {
     pub const fn as_raw(&self) -> MemoryRegionAttributesRaw {
         match self {
             MemoryRegionAttributes::StronglyOrdered => {
-                MemoryRegionAttributesRaw::new(0b000, false, false)
+                MemoryRegionAttributesRaw::new(u3::new(0b000), false, false)
             }
             MemoryRegionAttributes::ShareableDevice => {
-                MemoryRegionAttributesRaw::new(0b000, false, true)
+                MemoryRegionAttributesRaw::new(u3::new(0b000), false, true)
             }
             MemoryRegionAttributes::OuterAndInnerWriteThroughNoWriteAlloc => {
-                MemoryRegionAttributesRaw::new(0b000, true, false)
+                MemoryRegionAttributesRaw::new(u3::new(0b000), true, false)
             }
             MemoryRegionAttributes::OuterAndInnerWriteBackNoWriteAlloc => {
-                MemoryRegionAttributesRaw::new(0b000, true, true)
+                MemoryRegionAttributesRaw::new(u3::new(0b000), true, true)
             }
             MemoryRegionAttributes::OuterAndInnerNonCacheable => {
-                MemoryRegionAttributesRaw::new(0b001, false, false)
+                MemoryRegionAttributesRaw::new(u3::new(0b001), false, false)
             }
             MemoryRegionAttributes::OuterAndInnerWriteBackWriteAlloc => {
-                MemoryRegionAttributesRaw::new(0b001, true, true)
+                MemoryRegionAttributesRaw::new(u3::new(0b001), true, true)
             }
             MemoryRegionAttributes::NonShareableDevice => {
-                MemoryRegionAttributesRaw::new(0b010, false, false)
+                MemoryRegionAttributesRaw::new(u3::new(0b010), false, false)
             }
             MemoryRegionAttributes::CacheableMemory { inner, outer } => {
                 MemoryRegionAttributesRaw::new(
-                    (1 << 2) | (*outer as u8),
+                    u3::new((1 << 2) | (outer.raw_value().value())),
                     (*inner as u8 & 0b10) != 0,
                     (*inner as u8 & 0b01) != 0,
                 )
@@ -118,7 +139,9 @@ impl MemoryRegionAttributes {
     }
 }
 
+/// Individual section attributes for a L1 section.
 #[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct SectionAttributes {
     /// NG bit
     pub non_global: bool,
@@ -128,22 +151,68 @@ pub struct SectionAttributes {
     /// AP bits
     pub access: AccessPermissions,
     pub memory_attrs: MemoryRegionAttributesRaw,
-    pub domain: u8,
+    pub domain: u4,
     /// xN bit.
     pub execute_never: bool,
 }
 
+impl SectionAttributes {
+    /// Extract the section attributes from a raw L1 section entry.
+    #[inline]
+    fn from_raw(raw: u32) -> Result<Self, InvalidL1EntryType> {
+        let section_type = L1EntryType::new_with_raw_value(u2::new((raw & 0b11) as u8));
+        if section_type != L1EntryType::Section {
+            return Err(InvalidL1EntryType(section_type));
+        }
+        Ok(Self::from_raw_unchecked(raw))
+    }
+
+    /// Retrieves the corresponding L1 section part without the section base address being set.
+    const fn l1_section_part(&self) -> L1Section {
+        L1Section::builder()
+            .with_base_addr_upper_bits(u12::new(0))
+            .with_ng(self.non_global)
+            .with_s(self.shareable)
+            .with_apx(self.access.apx())
+            .with_tex(self.memory_attrs.type_extensions)
+            .with_ap(self.access.ap())
+            .with_p_bit(self.p_bit)
+            .with_domain(self.domain)
+            .with_xn(self.execute_never)
+            .with_c(self.memory_attrs.c)
+            .with_b(self.memory_attrs.b)
+            .with_entry_type(L1EntryType::Section)
+            .build()
+    }
+
+    /// Extract the section attributes without checking the entry type bits.
+    #[inline]
+    const fn from_raw_unchecked(raw: u32) -> Self {
+        let l1 = L1Section::new_with_raw_value(raw);
+        Self {
+            non_global: l1.ng(),
+            shareable: l1.s(),
+            p_bit: l1.p_bit(),
+            access: AccessPermissions::new(l1.apx(), l1.ap()),
+            memory_attrs: MemoryRegionAttributesRaw::new(l1.tex(), l1.c(), l1.b()),
+            domain: l1.domain(),
+            execute_never: l1.xn(),
+        }
+    }
+}
+
 /// 1 MB section translation entry, mapping a 1 MB region to a physical address.
 ///
 /// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) specifies these attributes
 /// in more detail.
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x00)]
+#[derive(PartialEq, Eq)]
 pub struct L1Section {
-    /// Section base address.
+    /// Section base address upper bits.
     #[bits(20..=31, rw)]
-    base_addr: u12,
+    base_addr_upper_bits: u12,
     /// Non-global bit.
-    #[bit(16, rw)]
+    #[bit(17, rw)]
     ng: bool,
     /// Shareable bit.
     #[bit(16, rw)]
@@ -174,7 +243,7 @@ impl core::fmt::Debug for L1Section {
         write!(
             f,
             "L1Section {{ base_addr={:#x} ng={} s={} apx={} tex={:#b} ap={:#b} domain={:#b} xn={} c={} b={} }}",
-            self.base_addr(),
+            self.base_addr_upper_bits(),
             self.ng() as u8,
             self.s() as u8,
             self.apx() as u8,
@@ -198,24 +267,51 @@ impl L1Section {
     /// # Panics
     ///
     /// Physcal address not aligned to 1 MB.
-    pub const fn new(phys_addr: u32, section_attrs: SectionAttributes) -> Self {
+    pub const fn new_with_addr_and_attrs(phys_addr: u32, section_attrs: SectionAttributes) -> Self {
         // Must be aligned to 1 MB
         if phys_addr & 0x000F_FFFF != 0 {
             panic!("physical base address for L1 section must be aligned to 1 MB");
         }
-        let higher_bits = phys_addr >> 20;
-        let raw = (higher_bits << 20)
-            | ((section_attrs.non_global as u32) << 17)
-            | ((section_attrs.shareable as u32) << 16)
-            | ((section_attrs.access.apx() as u32) << 15)
-            | ((section_attrs.memory_attrs.type_extensions as u32) << 12)
-            | ((section_attrs.access.ap() as u32) << 10)
-            | ((section_attrs.p_bit as u32) << 9)
-            | ((section_attrs.domain as u32) << 5)
-            | ((section_attrs.execute_never as u32) << 4)
-            | ((section_attrs.memory_attrs.c as u32) << 3)
-            | ((section_attrs.memory_attrs.b as u32) << 2)
-            | L1EntryType::Section as u32;
-        Self::new_with_raw_value(raw)
+        let attrs = section_attrs.l1_section_part();
+        L1Section::builder()
+            .with_base_addr_upper_bits(u12::new((phys_addr >> 20) as u16))
+            .with_ng(attrs.ng())
+            .with_s(attrs.s())
+            .with_apx(attrs.apx())
+            .with_tex(attrs.tex())
+            .with_ap(attrs.ap())
+            .with_p_bit(attrs.p_bit())
+            .with_domain(attrs.domain())
+            .with_xn(attrs.xn())
+            .with_c(attrs.c())
+            .with_b(attrs.b())
+            .with_entry_type(attrs.entry_type())
+            .build()
+    }
+
+    /// Retrieve the section attributes.
+    #[inline]
+    pub fn section_attrs(&self) -> Result<SectionAttributes, InvalidL1EntryType> {
+        SectionAttributes::from_raw(self.raw_value())
+    }
+
+    /// Set the section attributes without changing the address.
+    #[inline]
+    pub fn set_section_attrs(&mut self, section_attrs: SectionAttributes) {
+        let attrs = section_attrs.l1_section_part();
+        *self = L1Section::builder()
+            .with_base_addr_upper_bits(self.base_addr_upper_bits())
+            .with_ng(attrs.ng())
+            .with_s(attrs.s())
+            .with_apx(attrs.apx())
+            .with_tex(attrs.tex())
+            .with_ap(attrs.ap())
+            .with_p_bit(attrs.p_bit())
+            .with_domain(attrs.domain())
+            .with_xn(attrs.xn())
+            .with_c(attrs.c())
+            .with_b(attrs.b())
+            .with_entry_type(attrs.entry_type())
+            .build()
     }
 }