Skip to content

Commit b69370d

Browse files
committed
correction for changelog
1 parent ef2bb46 commit b69370d

File tree

1 file changed

+3
-2
lines changed

1 file changed

+3
-2
lines changed

cortex-ar/CHANGELOG.md

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1313
- API for inner cache maintenance as part of the new `cache` module. This includes functions to
1414
completely clean, invalidate or clean & invalidate the L1 data cache or perform data cache
1515
maintenance by MVA (specific address).
16-
- MMU code: `SectionAttributes::raw()` method and `SectionAttributes::from_raw()` and
17-
`SectionAttributes::from_raw_unchecked` constructors.
1816

1917
### Changed
2018

2119
- MMU code: Use more `arbitrary-int` types for MMU configuration bits.
20+
- Renamed `L1Section::new` to `L1Section::new_with_addr_and_attrs`. Added new
21+
`L1Section::set_section_attrs` and `L1Section::section_attrs` method. Also added
22+
low-level `L1Section::new_with_addr_upper_bits_and_attrs` constructor.
2223

2324
## [v0.2.0]
2425

0 commit comments

Comments
 (0)