Merge pull request #606 from rust-embedded/c-m-cherrypick

Cherrypick old cortex-m PRs

Author: adamgreig

.github/workflows/ci.yml

@@ -1,7 +1,4 @@
 on:
-  push:
-    branches-ignore:
-      - "gh-readonly-queue/**"
   pull_request:
   merge_group:
   workflow_dispatch:

.github/workflows/clippy.yml

@@ -1,7 +1,4 @@
 on:
-  push:
-    branches-ignore:
-      - "gh-readonly-queue/**"
   pull_request:
   merge_group:
   workflow_dispatch:

.github/workflows/on-target.yml

@@ -1,7 +1,4 @@
 on:
-  push:
-    branches-ignore:
-      - "gh-readonly-queue/**"
   pull_request:
   merge_group:
   # allows manual triggering

.github/workflows/rt-ci.yml

@@ -1,7 +1,4 @@
 on:
-  push:
-    branches-ignore:
-      - "gh-readonly-queue/**"
   pull_request:
   merge_group:
   workflow_dispatch:

.github/workflows/rustfmt.yml

@@ -1,7 +1,4 @@
 on:
-  push:
-    branches-ignore:
-      - "gh-readonly-queue/**"
   pull_request:
   merge_group:
   workflow_dispatch:

cortex-m/Cargo.toml

@@ -18,10 +18,11 @@ rust-version = "1.61"
 
 [dependencies]
 bare-metal = { version = "0.2.4", features = ["const-fn"] }
-critical-section = { version = "1.0.0", optional = true }
-volatile-register = "0.2.0"
+critical-section = "1.0.0"
+volatile-register = "0.2.2"
 bitfield = "0.13.2"
-embedded-hal = "0.2.4"
+eh0 = { package = "embedded-hal", version = "0.2.4" }
+eh1 = { package = "embedded-hal", version = "1.0.0" }
 
 [dependencies.serde]
 version = "1"
@@ -38,7 +39,9 @@ cm7-r0p1 = ["cm7"]
 inline-asm = []
 linker-plugin-lto = []
 std = []
-critical-section-single-core = ["critical-section/restore-state-bool"]
+critical-section-single-core = ["critical-section/restore-state-u32"]
+# Deprecated feature from when critical-section was an optional dependency
+critical-section = []
 
 [package.metadata.docs.rs]
 targets = [

cortex-m/asm/inline.rs

@@ -60,6 +60,10 @@ pub unsafe fn __delay(cyc: u32) {
     // Add 1 to prevent an integer underflow which would cause a long freeze
     let real_cyc = 1 + cyc / 2;
     asm!(
+        // The `bne` on some cores (eg Cortex-M4) will take a different number of instructions
+        // depending on the alignment of the branch target.  Set the alignment of the top of the
+        // loop to prevent surprising timing changes when the alignment of the delay() changes.
+        ".p2align 3",
         // Use local labels to avoid R_ARM_THM_JUMP8 relocations which fail on thumbv6m.
         "1:",
         "subs {}, #1",