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2 parents 2c5b62c + cef7f32 commit 392144eCopy full SHA for 392144e
riscv-peripheral/src/aclint/mtimer.rs
@@ -56,6 +56,12 @@ impl<M: Mtimer> MTIMER<M> {
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M::MTIMECMP_BASE as *const u64
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}
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+ /// Returns the clock frequency of the `MTIME` register.
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+ #[inline]
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+ pub const fn mtime_freq(self) -> usize {
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+ M::MTIME_FREQ
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+ }
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+
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/// Returns `true` if a machine timer interrupt is pending.
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#[inline]
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pub fn is_interrupting(self) -> bool {
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