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Merge pull request #340 from rust-embedded/v0.15
Prepare for new `riscv` releases
2 parents 00a818c + 2d90e00 commit 527f6e2

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riscv-peripheral/CHANGELOG.md

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## [Unreleased]
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## [v0.4.0] - 2025-09-08
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### Added
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- Constant methods to access to PLIC and ACLINT registers for HART 0.
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These new methods are especially convenient for single-HART targets.
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### Removed
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- Removed `riscv` reexport.
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## [v0.3.0] - 2025-06-10
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### Changed

riscv-peripheral/Cargo.toml

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[package]
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name = "riscv-peripheral"
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version = "0.3.0"
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version = "0.4.0"
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edition = "2021"
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rust-version = "1.75"
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repository = "https://github.com/rust-embedded/riscv"
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[dependencies]
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embedded-hal = "1.0.0"
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paste = "1.0"
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riscv = { path = "../riscv", version = "0.14.0" }
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riscv = { path = "../riscv", version = "0.15.0" }
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riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
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[package.metadata.docs.rs]

riscv-peripheral/src/lib.rs

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#![deny(missing_docs)]
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#![no_std]
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pub use riscv; // re-export riscv crate to allow macros to use it
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pub use riscv_pac::result; // re-export the result module
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pub mod common; // common definitions for all peripherals

riscv-rt/CHANGELOG.md

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## [Unreleased]
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## [v0.16.0] - 2025-09-08
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### Added
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- New `post-init` feature to run a Rust `__post_init` function before jumping to `main`.
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- Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3)
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- Additional feature `defmt` which will implement `defmt::Format` on certain types
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- Additional feature `pre-default-start-trap` to execute custom code before `_default_start_trap`
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- `main` function no longer needs to be close to `_start`. A linker script may copy

riscv-rt/Cargo.toml

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[package]
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name = "riscv-rt"
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version = "0.15.0"
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version = "0.16.0"
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rust-version = "1.67"
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repository = "https://github.com/rust-embedded/riscv"
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authors = ["The RISC-V Team <[email protected]>"]
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riscv-target-parser = { path = "../riscv-target-parser", version = "0.1.2" }
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[dependencies]
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riscv = { path = "../riscv", version = "0.14.0" }
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riscv = { path = "../riscv", version = "0.15.0" }
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riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
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riscv-rt-macros = { path = "macros", version = "0.5.0" }
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riscv-rt-macros = { path = "macros", version = "0.6.0" }
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defmt = { version = "1.0.1", optional = true }
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riscv-rt/macros/Cargo.toml

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license = "MIT OR Apache-2.0"
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name = "riscv-rt-macros"
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repository = "https://github.com/rust-embedded/riscv"
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version = "0.5.0"
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version = "0.6.0"
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edition = "2021"
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[lib]

riscv-semihosting/CHANGELOG.md

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## [Unreleased]
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## [v0.2.1] - 2025-09-08
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- Removed `riscv` dependency, as it was unused.
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- Use `cfg(any(target_arch = "riscv32", target_arch = "riscv64"))` instead of `cfg(riscv)`.
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### Removed

riscv-semihosting/Cargo.toml

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name = "riscv-semihosting"
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readme = "README.md"
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repository = "https://github.com/riscv-rust/riscv"
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version = "0.2.0"
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version = "0.2.1"
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edition = "2021"
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rust-version = "1.67"
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[dependencies]
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critical-section = "1.2.0"
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riscv = { path = "../riscv", version = "0.14.0" }

riscv/CHANGELOG.md

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## [Unreleased]
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## [v0.15.0] - 2025-09-08
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- New convenience `try_new` and `new` associated functions for `Mtvec` and `Stvec`.

riscv/Cargo.toml

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[package]
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name = "riscv"
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version = "0.14.0"
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version = "0.15.0"
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edition = "2021"
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rust-version = "1.67"
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repository = "https://github.com/rust-embedded/riscv"
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critical-section = "1.2.0"
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embedded-hal = "1.0.0"
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riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
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riscv-macros = { path = "macros", version = "0.2.0", optional = true }
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riscv-macros = { path = "macros", version = "0.3.0", optional = true }
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paste = "1.0.15"

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