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1 parent 64dec8a commit f8565d9Copy full SHA for f8565d9
riscv/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Added
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- Add `dcsratch0` and `dscratch1` CSRs
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+- Add new `read-write_csr_as_usize` macro for registers
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- Add `dpc` CSR support for RISC-V
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- Add Mtopi
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- Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
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