From ac789327cfa0317ed5b3574577a9c59c83c29232 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Tue, 15 Jul 2025 08:33:03 +0200 Subject: [PATCH 1/5] Use riscv_pac::CoreInterrupt in mie register --- riscv/CHANGELOG.md | 2 + riscv/src/register/mie.rs | 78 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 97233feb..6c24289b 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -10,6 +10,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - New convenience `try_new` and `new` associated functions for `Mtvec` and `Stvec`. +- New methods and functions for enabling core interrupts in the `mie` register using + the `riscv_pac::CoreInterrupt` trait. ### Changed diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index 2c273ecf..5e9ce184 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -1,9 +1,11 @@ //! mie register +use riscv_pac::CoreInterruptNumber; + read_write_csr! { /// `mie` register Mie: 0x304, - mask: 0xaaa, + mask: usize::MAX, } read_write_csr_field! { @@ -42,6 +44,26 @@ read_write_csr_field! { mext: 11, } +impl Mie { + /// Check if a specific core interrupt source is enabled. + #[inline] + pub fn is_enabled(&self, interrupt: I) -> bool { + (self.bits & (1 << interrupt.number())) != 0 + } + + /// Enable a specific core interrupt source. + #[inline] + pub fn enable(&mut self, interrupt: I) { + self.bits |= 1 << interrupt.number(); + } + + /// Disable a specific core interrupt source. + #[inline] + pub fn disable(&mut self, interrupt: I) { + self.bits &= !(1 << interrupt.number()); + } +} + set!(0x304); clear!(0x304); @@ -64,9 +86,28 @@ set_clear_csr!( /// Machine External Interrupt Enable , set_mext, clear_mext, 1 << 11); +/// Disables a specific core interrupt source. +#[inline] +pub fn clear_interrupt(interrupt: I) { + // SAFETY: it is safe to disable an interrupt source + unsafe { _clear(1 << interrupt.number()) }; +} + +/// Enables a specific core interrupt source. +/// +/// # Safety +/// +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. +#[inline] +pub unsafe fn set_interrupt(interrupt: I) { + unsafe { _set(1 << interrupt.number()) }; +} + #[cfg(test)] mod tests { use super::*; + use crate::interrupt::machine::Interrupt; #[test] fn test_mie() { @@ -79,4 +120,39 @@ mod tests { test_csr_field!(m, sext); test_csr_field!(m, mext); } + + #[test] + fn test_mie_interrupt() { + let mut m = Mie::from_bits(0); + + m.enable(Interrupt::SupervisorSoft); + assert!(m.is_enabled(Interrupt::SupervisorSoft)); + m.disable(Interrupt::SupervisorSoft); + assert!(!m.is_enabled(Interrupt::SupervisorSoft)); + + m.enable(Interrupt::MachineSoft); + assert!(m.is_enabled(Interrupt::MachineSoft)); + m.disable(Interrupt::MachineSoft); + assert!(!m.is_enabled(Interrupt::MachineSoft)); + + m.enable(Interrupt::SupervisorTimer); + assert!(m.is_enabled(Interrupt::SupervisorTimer)); + m.disable(Interrupt::SupervisorTimer); + assert!(!m.is_enabled(Interrupt::SupervisorTimer)); + + m.enable(Interrupt::MachineTimer); + assert!(m.is_enabled(Interrupt::MachineTimer)); + m.disable(Interrupt::MachineTimer); + assert!(!m.is_enabled(Interrupt::MachineTimer)); + + m.enable(Interrupt::SupervisorExternal); + assert!(m.is_enabled(Interrupt::SupervisorExternal)); + m.disable(Interrupt::SupervisorExternal); + assert!(!m.is_enabled(Interrupt::SupervisorExternal)); + + m.enable(Interrupt::MachineExternal); + assert!(m.is_enabled(Interrupt::MachineExternal)); + m.disable(Interrupt::MachineExternal); + assert!(!m.is_enabled(Interrupt::MachineExternal)); + } } From 350fec32d21f060348ca228363e458ba12ab2988 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Tue, 15 Jul 2025 22:00:18 +0200 Subject: [PATCH 2/5] Use riscv_pac::CoreInterrupt in sie register --- riscv/CHANGELOG.md | 5 ++- riscv/src/interrupt/machine.rs | 32 ++++++++++++++-- riscv/src/interrupt/supervisor.rs | 32 ++++++++++++++-- riscv/src/register/mie.rs | 4 +- riscv/src/register/sie.rs | 63 ++++++++++++++++++++++++++++++- 5 files changed, 123 insertions(+), 13 deletions(-) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 6c24289b..fcf2368a 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -10,8 +10,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - New convenience `try_new` and `new` associated functions for `Mtvec` and `Stvec`. -- New methods and functions for enabling core interrupts in the `mie` register using - the `riscv_pac::CoreInterrupt` trait. +- New methods and functions for enabling core interrupts in the `mie` and `sie` registers + using the `riscv_pac::CoreInterrupt` trait. +- New `riscv::interrupt::{disable_interrupt, enable_interrupt}` functions. ### Changed diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs index d88ceb46..09f2eb50 100644 --- a/riscv/src/interrupt/machine.rs +++ b/riscv/src/interrupt/machine.rs @@ -1,6 +1,6 @@ use crate::{ interrupt::Trap, - register::{mcause, mepc, mstatus}, + register::{mcause, mepc, mie, mstatus}, }; use riscv_pac::{ result::{Error, Result}, @@ -96,18 +96,42 @@ unsafe impl ExceptionNumber for Exception { } } -/// Disables all interrupts in the current hart (machine mode). +/// Disables interrupts for a specific core interrupt source in the current hart (machine mode). +#[inline] +pub fn disable_interrupt(interrupt: I) { + // SAFETY: it is safe to disable an interrupt source + mie::disable_interrupt(interrupt); +} + +/// Enables interrupts for a specific core interrupt source in the current hart (machine mode). +/// +/// # Note +/// +/// Interrupts will only be triggered if interrupts are globally enabled in the hart. +/// To do this, you must call [`enable`] after enabling the interrupt. +/// +/// # Safety +/// +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. +#[inline] +pub unsafe fn enable_interrupt(interrupt: I) { + mie::enable_interrupt(interrupt); +} + +/// Disables interrupts globally in the current hart (machine mode). #[inline] pub fn disable() { // SAFETY: It is safe to disable interrupts unsafe { mstatus::clear_mie() } } -/// Enables all the interrupts in the current hart (machine mode). +/// Enables interrupts globally in the current hart (machine mode). /// /// # Safety /// -/// Do not call this function inside a critical section. +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] pub unsafe fn enable() { mstatus::set_mie() diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs index ddb913c2..e81fb163 100644 --- a/riscv/src/interrupt/supervisor.rs +++ b/riscv/src/interrupt/supervisor.rs @@ -1,6 +1,6 @@ use crate::{ interrupt::Trap, - register::{scause, sepc, sstatus}, + register::{scause, sepc, sie, sstatus}, }; use riscv_pac::{ result::{Error, Result}, @@ -88,18 +88,42 @@ unsafe impl ExceptionNumber for Exception { } } -/// Disables all interrupts in the current hart (supervisor mode). +/// Disables interrupts for a specific core interrupt source in the current hart (supervisor mode). +#[inline] +pub fn disable_interrupt(interrupt: I) { + // SAFETY: it is safe to disable an interrupt source + sie::disable_interrupt(interrupt); +} + +/// Enables interrupts for a specific core interrupt source in the current hart (supervisor mode). +/// +/// # Note +/// +/// Interrupts will only be triggered if interrupts are globally enabled in the hart. +/// To do this, you must call [`enable`] after enabling the interrupt. +/// +/// # Safety +/// +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. +#[inline] +pub unsafe fn enable_interrupt(interrupt: I) { + sie::enable_interrupt(interrupt); +} + +/// Disables interrupts globally in the current hart (supervisor mode). #[inline] pub fn disable() { // SAFETY: It is safe to disable interrupts unsafe { sstatus::clear_sie() } } -/// Enables all the interrupts in the current hart (supervisor mode). +/// Enables interrupts globally in the current hart (supervisor mode). /// /// # Safety /// -/// Do not call this function inside a critical section. +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] pub unsafe fn enable() { sstatus::set_sie() diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index 5e9ce184..527e566a 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -88,7 +88,7 @@ set_clear_csr!( /// Disables a specific core interrupt source. #[inline] -pub fn clear_interrupt(interrupt: I) { +pub fn disable_interrupt(interrupt: I) { // SAFETY: it is safe to disable an interrupt source unsafe { _clear(1 << interrupt.number()) }; } @@ -100,7 +100,7 @@ pub fn clear_interrupt(interrupt: I) { /// Enabling interrupts might break critical sections or other synchronization mechanisms. /// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] -pub unsafe fn set_interrupt(interrupt: I) { +pub unsafe fn enable_interrupt(interrupt: I) { unsafe { _set(1 << interrupt.number()) }; } diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs index a8ee2812..3da6dbc5 100644 --- a/riscv/src/register/sie.rs +++ b/riscv/src/register/sie.rs @@ -1,9 +1,11 @@ //! sie register +use riscv_pac::CoreInterruptNumber; + read_write_csr! { /// sie register Sie: 0x104, - mask: 0x222, + mask: usize::MAX, } read_write_csr_field! { @@ -24,6 +26,26 @@ read_write_csr_field! { sext: 9, } +impl Sie { + /// Check if a specific core interrupt source is enabled. + #[inline] + pub fn is_enabled(&self, interrupt: I) -> bool { + (self.bits & (1 << interrupt.number())) != 0 + } + + /// Enable a specific core interrupt source. + #[inline] + pub fn enable(&mut self, interrupt: I) { + self.bits |= 1 << interrupt.number(); + } + + /// Disable a specific core interrupt source. + #[inline] + pub fn disable(&mut self, interrupt: I) { + self.bits &= !(1 << interrupt.number()); + } +} + set!(0x104); clear!(0x104); @@ -37,9 +59,28 @@ set_clear_csr!( /// Supervisor External Interrupt Enable , set_sext, clear_sext, 1 << 9); +/// Disables a specific core interrupt source. +#[inline] +pub fn disable_interrupt(interrupt: I) { + // SAFETY: it is safe to disable an interrupt source + unsafe { _clear(1 << interrupt.number()) }; +} + +/// Enables a specific core interrupt source. +/// +/// # Safety +/// +/// Enabling interrupts might break critical sections or other synchronization mechanisms. +/// Ensure that this is called in a safe context where interrupts can be enabled. +#[inline] +pub unsafe fn enable_interrupt(interrupt: I) { + unsafe { _set(1 << interrupt.number()) }; +} + #[cfg(test)] mod tests { use super::*; + use crate::interrupt::supervisor::Interrupt; #[test] fn test_sie() { @@ -49,4 +90,24 @@ mod tests { test_csr_field!(sie, stimer); test_csr_field!(sie, sext); } + + #[test] + fn test_sie_interrupt() { + let mut s = Sie::from_bits(0); + + s.enable(Interrupt::SupervisorSoft); + assert!(s.is_enabled(Interrupt::SupervisorSoft)); + s.disable(Interrupt::SupervisorSoft); + assert!(!s.is_enabled(Interrupt::SupervisorSoft)); + + s.enable(Interrupt::SupervisorTimer); + assert!(s.is_enabled(Interrupt::SupervisorTimer)); + s.disable(Interrupt::SupervisorTimer); + assert!(!s.is_enabled(Interrupt::SupervisorTimer)); + + s.enable(Interrupt::SupervisorExternal); + assert!(s.is_enabled(Interrupt::SupervisorExternal)); + s.disable(Interrupt::SupervisorExternal); + assert!(!s.is_enabled(Interrupt::SupervisorExternal)); + } } From e884b55eb41b8a2965fe8192113e6554331b0b6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Wed, 16 Jul 2025 07:46:29 +0200 Subject: [PATCH 3/5] Apply suggestions from code review Co-authored-by: rmsyn <117854522+rmsyn@users.noreply.github.com> --- riscv/src/register/mie.rs | 7 ++++--- riscv/src/register/sie.rs | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index 527e566a..2bb90242 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -1,6 +1,7 @@ //! mie register use riscv_pac::CoreInterruptNumber; +use crate::bits::{bf_extract, bf_insert}; read_write_csr! { /// `mie` register @@ -48,19 +49,19 @@ impl Mie { /// Check if a specific core interrupt source is enabled. #[inline] pub fn is_enabled(&self, interrupt: I) -> bool { - (self.bits & (1 << interrupt.number())) != 0 + bf_extract(self.bits, interrupt.number(), 1) != 0 } /// Enable a specific core interrupt source. #[inline] pub fn enable(&mut self, interrupt: I) { - self.bits |= 1 << interrupt.number(); + self.bits = bf_insert(self.bits, interrupt.number(), 1, 1); } /// Disable a specific core interrupt source. #[inline] pub fn disable(&mut self, interrupt: I) { - self.bits &= !(1 << interrupt.number()); + self.bits = bf_insert(self.bits, interrupt.number(), 1, 0); } } diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs index 3da6dbc5..933c3609 100644 --- a/riscv/src/register/sie.rs +++ b/riscv/src/register/sie.rs @@ -1,6 +1,7 @@ //! sie register use riscv_pac::CoreInterruptNumber; +use crate::bits::{bf_insert, bf_extract}; read_write_csr! { /// sie register @@ -30,19 +31,19 @@ impl Sie { /// Check if a specific core interrupt source is enabled. #[inline] pub fn is_enabled(&self, interrupt: I) -> bool { - (self.bits & (1 << interrupt.number())) != 0 + bf_extract(self.bits, interrupt.number(), 1) != 0 } /// Enable a specific core interrupt source. #[inline] pub fn enable(&mut self, interrupt: I) { - self.bits |= 1 << interrupt.number(); + self.bits = bf_insert(self.bits, interrupt.number(), 1, 1); } /// Disable a specific core interrupt source. #[inline] pub fn disable(&mut self, interrupt: I) { - self.bits &= !(1 << interrupt.number()); + self.bits = bf_insert(self.bits, interrupt.number(), 1, 0); } } From 30b36b0204c5b854fef9583f12f541ea6349c902 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Wed, 16 Jul 2025 07:51:23 +0200 Subject: [PATCH 4/5] Improve docs --- riscv/src/interrupt/machine.rs | 8 ++++++-- riscv/src/interrupt/supervisor.rs | 8 ++++++-- riscv/src/register/mie.rs | 2 +- riscv/src/register/sie.rs | 2 +- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs index 09f2eb50..8603ff3f 100644 --- a/riscv/src/interrupt/machine.rs +++ b/riscv/src/interrupt/machine.rs @@ -107,8 +107,7 @@ pub fn disable_interrupt(interrupt: I) { /// /// # Note /// -/// Interrupts will only be triggered if interrupts are globally enabled in the hart. -/// To do this, you must call [`enable`] after enabling the interrupt. +/// Interrupts will only be triggered if globally enabled in the hart. To do this, use [`enable`]. /// /// # Safety /// @@ -128,6 +127,11 @@ pub fn disable() { /// Enables interrupts globally in the current hart (machine mode). /// +/// # Note +/// +/// Only enabled interrupt sources will be triggered. +/// To enable specific interrupt sources, use [`enable_interrupt`]. +/// /// # Safety /// /// Enabling interrupts might break critical sections or other synchronization mechanisms. diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs index e81fb163..60d848a0 100644 --- a/riscv/src/interrupt/supervisor.rs +++ b/riscv/src/interrupt/supervisor.rs @@ -99,8 +99,7 @@ pub fn disable_interrupt(interrupt: I) { /// /// # Note /// -/// Interrupts will only be triggered if interrupts are globally enabled in the hart. -/// To do this, you must call [`enable`] after enabling the interrupt. +/// Interrupts will only be triggered if globally enabled in the hart. To do this, use [`enable`]. /// /// # Safety /// @@ -120,6 +119,11 @@ pub fn disable() { /// Enables interrupts globally in the current hart (supervisor mode). /// +/// # Note +/// +/// Only enabled interrupt sources will be triggered. +/// To enable specific interrupt sources, use [`enable_interrupt`]. +/// /// # Safety /// /// Enabling interrupts might break critical sections or other synchronization mechanisms. diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index 2bb90242..b2b176f9 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -1,7 +1,7 @@ //! mie register -use riscv_pac::CoreInterruptNumber; use crate::bits::{bf_extract, bf_insert}; +use riscv_pac::CoreInterruptNumber; read_write_csr! { /// `mie` register diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs index 933c3609..fb0d6f01 100644 --- a/riscv/src/register/sie.rs +++ b/riscv/src/register/sie.rs @@ -1,7 +1,7 @@ //! sie register +use crate::bits::{bf_extract, bf_insert}; use riscv_pac::CoreInterruptNumber; -use crate::bits::{bf_insert, bf_extract}; read_write_csr! { /// sie register From a334f8aeea86c66cc3fcc61255c54c60b8ae1971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rom=C3=A1n=20C=C3=A1rdenas=20Rodr=C3=ADguez?= Date: Fri, 18 Jul 2025 08:13:46 +0200 Subject: [PATCH 5/5] Added is_interrupt_enabled --- riscv/CHANGELOG.md | 2 +- riscv/src/interrupt/machine.rs | 11 ++++++++--- riscv/src/interrupt/supervisor.rs | 10 ++++++++-- riscv/src/register/mie.rs | 4 ++-- riscv/src/register/sie.rs | 4 ++-- 5 files changed, 21 insertions(+), 10 deletions(-) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index fcf2368a..0ec3f138 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -12,7 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - New convenience `try_new` and `new` associated functions for `Mtvec` and `Stvec`. - New methods and functions for enabling core interrupts in the `mie` and `sie` registers using the `riscv_pac::CoreInterrupt` trait. -- New `riscv::interrupt::{disable_interrupt, enable_interrupt}` functions. +- New `riscv::interrupt::{is_interrupt_enabled, disable_interrupt, enable_interrupt}` functions. ### Changed diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs index 8603ff3f..52212f1d 100644 --- a/riscv/src/interrupt/machine.rs +++ b/riscv/src/interrupt/machine.rs @@ -96,11 +96,16 @@ unsafe impl ExceptionNumber for Exception { } } +/// Checks if a specific core interrupt source is enabled in the current hart (machine mode). +#[inline] +pub fn is_interrupt_enabled(interrupt: I) -> bool { + mie::read().is_enabled(interrupt) +} + /// Disables interrupts for a specific core interrupt source in the current hart (machine mode). #[inline] pub fn disable_interrupt(interrupt: I) { - // SAFETY: it is safe to disable an interrupt source - mie::disable_interrupt(interrupt); + mie::disable(interrupt); } /// Enables interrupts for a specific core interrupt source in the current hart (machine mode). @@ -115,7 +120,7 @@ pub fn disable_interrupt(interrupt: I) { /// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] pub unsafe fn enable_interrupt(interrupt: I) { - mie::enable_interrupt(interrupt); + mie::enable(interrupt); } /// Disables interrupts globally in the current hart (machine mode). diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs index 60d848a0..8db43f98 100644 --- a/riscv/src/interrupt/supervisor.rs +++ b/riscv/src/interrupt/supervisor.rs @@ -88,11 +88,17 @@ unsafe impl ExceptionNumber for Exception { } } +/// Checks if a specific core interrupt source is enabled in the current hart (supervisor mode). +#[inline] +pub fn is_interrupt_enabled(interrupt: I) -> bool { + sie::read().is_enabled(interrupt) +} + /// Disables interrupts for a specific core interrupt source in the current hart (supervisor mode). #[inline] pub fn disable_interrupt(interrupt: I) { // SAFETY: it is safe to disable an interrupt source - sie::disable_interrupt(interrupt); + sie::disable(interrupt); } /// Enables interrupts for a specific core interrupt source in the current hart (supervisor mode). @@ -107,7 +113,7 @@ pub fn disable_interrupt(interrupt: I) { /// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] pub unsafe fn enable_interrupt(interrupt: I) { - sie::enable_interrupt(interrupt); + sie::enable(interrupt); } /// Disables interrupts globally in the current hart (supervisor mode). diff --git a/riscv/src/register/mie.rs b/riscv/src/register/mie.rs index b2b176f9..0ca87677 100644 --- a/riscv/src/register/mie.rs +++ b/riscv/src/register/mie.rs @@ -89,7 +89,7 @@ set_clear_csr!( /// Disables a specific core interrupt source. #[inline] -pub fn disable_interrupt(interrupt: I) { +pub fn disable(interrupt: I) { // SAFETY: it is safe to disable an interrupt source unsafe { _clear(1 << interrupt.number()) }; } @@ -101,7 +101,7 @@ pub fn disable_interrupt(interrupt: I) { /// Enabling interrupts might break critical sections or other synchronization mechanisms. /// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] -pub unsafe fn enable_interrupt(interrupt: I) { +pub unsafe fn enable(interrupt: I) { unsafe { _set(1 << interrupt.number()) }; } diff --git a/riscv/src/register/sie.rs b/riscv/src/register/sie.rs index fb0d6f01..dfeecdaa 100644 --- a/riscv/src/register/sie.rs +++ b/riscv/src/register/sie.rs @@ -62,7 +62,7 @@ set_clear_csr!( /// Disables a specific core interrupt source. #[inline] -pub fn disable_interrupt(interrupt: I) { +pub fn disable(interrupt: I) { // SAFETY: it is safe to disable an interrupt source unsafe { _clear(1 << interrupt.number()) }; } @@ -74,7 +74,7 @@ pub fn disable_interrupt(interrupt: I) { /// Enabling interrupts might break critical sections or other synchronization mechanisms. /// Ensure that this is called in a safe context where interrupts can be enabled. #[inline] -pub unsafe fn enable_interrupt(interrupt: I) { +pub unsafe fn enable(interrupt: I) { unsafe { _set(1 << interrupt.number()) }; }