Merge pull request #285 from Ckaf/add_mux

add mux function

Author: ryukzak

app/Main.hs

@@ -378,6 +378,7 @@ defMicroarch ioSync = defineNetwork "net1" ioSync $ do
             }
     add "compare" CompareIO
     add "logicalUnit" LogicalUnitIO
+    add "mux" MultiplexerIO
 
 microarchWithProtos ioSync = defineNetwork "net1" ioSync $ do
     addCustomPrototype "fram{x}" (framWithSize 32) FramIO
@@ -394,3 +395,4 @@ microarchWithProtos ioSync = defineNetwork "net1" ioSync $ do
             }
     addPrototype "compare{x}" CompareIO
     addPrototype "logicalUnit{x}" LogicalUnitIO
+    addPrototype "mux{x}" MultiplexerIO

examples/mux.lua

@@ -0,0 +1,7 @@
+function muxf(a, b)
+    local cond = 1
+    local res = if_mux (cond, a, b)
+    muxf(res, a)
+end
+
+muxf(1, 0)

hdl/Makefile

@@ -8,7 +8,7 @@ define test
 	$(shell which vvp) $(PWD)/$(3).out
 endef
 
-all: pu_accum pu_fram pu_mux pu_fifo pu_shift pu_div pu_multiplier pu_i2c pu_spi pu_compare
+all: pu_accum pu_fram pu_multiplexer pu_fifo pu_shift pu_div pu_multiplier pu_i2c pu_spi pu_compare
 
 clean:
 	$(RM) -r $(PWD)/*.vcd $(PWD)/*.out
@@ -23,8 +23,8 @@ pu_accum:
 pu_fram:
 	$(call test,pu_fram.v,pu_fram_tb.v,test_pu_fram_tb)
 
-pu_mux:
-	$(call test,pu_mux.v,pu_mux_tb.v,test_pu_mux_tb)
+pu_multiplexer:
+	$(call test,pu_multiplexer.v,pu_multiplexer_tb.v,test_pu_multiplexer_tb)
 
 pu_fifo:
 	$(call test,pu_fifo.v,pu_fifo_tb.v,test_pu_fifo_tb)

hdl/pu_multiplexer.v

@@ -0,0 +1,54 @@
+module pu_multiplexer #(
+    parameter DATA_WIDTH = 32,
+    parameter ATTR_WIDTH = 4,
+    parameter SEL_WIDTH = 1
+)(
+    input wire clk,
+    input wire rst,
+    input wire signal_wr,
+    input wire signal_sel,
+    input wire signal_oe,
+    
+    input wire signed [DATA_WIDTH-1:0] data_in,
+    input wire [ATTR_WIDTH-1:0] attr_in,
+    output wire signed [DATA_WIDTH-1:0] data_out,
+    output wire [ATTR_WIDTH-1:0] attr_out
+);
+    reg signed [DATA_WIDTH-1:0] buffer [0:(2**SEL_WIDTH)-1];
+    reg [SEL_WIDTH-1:0] sel_reg;
+    reg [SEL_WIDTH-1:0] write_index = 0;
+    reg is_prev_out = 0;
+
+
+    integer i;
+
+    always @(posedge clk) begin
+        if (signal_wr) begin
+            if (is_prev_out) begin
+                sel_reg <= 0;
+                is_prev_out <= 0;
+                buffer[0] <= data_in;
+                write_index <= 1;
+            end else begin
+                buffer[write_index] <= data_in;
+                write_index <= write_index + 1;
+            end
+        end
+        
+        if (signal_sel) begin
+            if (is_prev_out) begin
+                write_index <= 0;
+                is_prev_out <= 0;
+            end
+            sel_reg <= data_in;
+        end
+
+        if (signal_oe) begin
+            is_prev_out <= 1;
+        end
+    end
+
+assign attr_out = 0;
+assign data_out = (signal_oe && (sel_reg < write_index))? buffer[sel_reg] : 0;
+
+endmodule

hdl/pu_multiplexer_tb.v

@@ -0,0 +1,109 @@
+module pu_multiplexer_tb();
+
+    parameter DATA_WIDTH = 32;
+    parameter ATTR_WIDTH = 4;
+    parameter SEL_WIDTH = 1;
+
+    reg clk;
+    reg signal_wr;
+    reg signal_sel;
+    reg signal_oe;
+    reg [DATA_WIDTH-1:0] data_in;
+    reg [ATTR_WIDTH-1:0] attr_in;
+    wire [DATA_WIDTH-1:0] data_out;
+    wire [ATTR_WIDTH-1:0] attr_out;
+
+    pu_multiplexer #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .ATTR_WIDTH(ATTR_WIDTH),
+        .SEL_WIDTH(SEL_WIDTH))
+    dut (
+        .clk(clk),
+        .signal_wr(signal_wr),
+        .signal_sel(signal_sel),
+        .signal_oe(signal_oe),
+        .data_in(data_in),
+        .attr_in(attr_in),
+        .data_out(data_out),
+        .attr_out(attr_out)
+    );
+
+    initial begin
+        clk = 0;
+        forever #1 clk = ~clk;
+    end
+
+    task automatic write_data;
+        input [SEL_WIDTH-1:0] sel;
+        input [DATA_WIDTH-1:0] data;
+        input [ATTR_WIDTH-1:0] attr;
+        begin
+            @(posedge clk);
+            signal_sel <= 1;
+            data_in <= sel;
+            @(posedge clk);
+            signal_sel <= 0;
+            
+            signal_wr <= 1;
+            data_in <= data;
+            attr_in <= attr;
+            @(posedge clk);
+            signal_wr <= 0;
+            $display("[%0t] Write: sel=%0d, data=0x%h, attr=0x%h", $time, sel, data, attr);
+        end
+    endtask
+
+    task automatic check_output;
+        input [SEL_WIDTH-1:0] expected_sel;
+        input [DATA_WIDTH-1:0] expected_data;
+        input [ATTR_WIDTH-1:0] expected_attr;
+        begin
+            @(posedge clk);
+            signal_oe <= 1;
+            @(posedge clk);
+            if (data_out !== expected_data || attr_out !== expected_attr)
+                $display("FAIL: sel=%0d, expected (0x%h, 0x%h), got (0x%h, 0x%h)",
+                        expected_sel, expected_data, expected_attr, data_out, attr_out);
+            else
+                $display("PASS: sel=%0d, data=0x%h, attr=0x%h",
+                        expected_sel, data_out, attr_out);
+            signal_oe <= 0;
+            @(posedge clk);
+        end
+    endtask
+
+    initial begin
+        $dumpfile("pu_multiplexer_tb.vcd");
+        $dumpvars(0, pu_multiplexer_tb);
+
+        signal_wr = 0;
+        signal_sel = 0;
+        signal_oe = 0;
+        data_in = 0;
+        attr_in = 0;
+        
+        write_data(0, 32'hAAAA_AAAA, 4'hA);
+        write_data(1, 32'h5555_5555, 4'h5);
+        
+        write_data(0, 0, 0);
+        check_output(0, 32'hAAAA_AAAA, 4'hA);
+        
+        write_data(1, 0, 0);
+        check_output(1, 32'h5555_5555, 4'h5);
+
+        @(posedge clk);
+        signal_oe <= 0;
+        @(posedge clk);
+        if (data_out !== 0 || attr_out !== 0)
+            $display("FAIL: Output not reset");
+        else
+            $display("PASS: Output reset");
+
+        write_data(0, 32'hDEAD_BEEF, 4'hF);
+        check_output(0, 32'hDEAD_BEEF, 4'hF);
+
+        #100;
+        $finish;
+    end
+
+endmodule