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bugA bug or regressionA bug or regression
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Line labels can potentially be reordered during +
between Circuit
objects. Some protocols (such as circuit-mirroring-based techniques) compute expected output bitstrings, and this addition reordering can happen unexpectedly and cause a mismatch between final circuit line labels and implicit line labels of the computed bitstring.
We're catching these reorderings in our MCFE-based code now, but we should revisit this to see if there could have been better behavior to prevent the bug in the first place.
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bugA bug or regressionA bug or regression