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1 | | -# Systolic CNN AcceLErator Simulator (SCALE-Sim) |
| 1 | +# SystoliC AcceLErator Simulator (SCALE-Sim) |
2 | 2 |
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3 | 3 | <!-- [](https://scale-sim-project.readthedocs.io/en/latest/?badge=latest) --> |
4 | 4 |
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5 | | -SCALE Sim is a simulator for systolic array based accelerators for Convolution, Feed Forward, and any layer that uses GEMMs. |
| 5 | +SCALE-Sim is a simulator for systolic array based accelerators supporting Deep Neural Network layers such as Convolution, Fully Connected, and any layer that uses GEMMs (e.g., Attention). |
6 | 6 |
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7 | | -## Features of v2 |
| 7 | + |
| 8 | +## Features of SCALE-sim Releases |
| 9 | + |
| 10 | +### Features of v2 |
8 | 11 |
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9 | 12 | SCALE-Sim v2 includes following features: |
10 | 13 |
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11 | | -1. Simulation of both GEMM and convolution (as im2col) operations |
| 14 | +1. Simulation of GEMM and convolution (as im2col) operations |
12 | 15 | 2. Analytical compute cycles validated by RTL simulation |
13 | 16 | 3. Separate double-buffered memory modeling for Input, Filter and Output matrices |
14 | 17 | 4. Multi-Fidelity: Bandwidth calculation mode (CALC) and Stall cycle calculation/Use user bandwidth mode (USER) |
15 | 18 | 5. Save cycle-accurate SRAM and DRAM traces for separately for Input, Filter and Output |
16 | 19 |
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17 | 20 |  |
18 | 21 |
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19 | | -The previous version (ARM) of the simulator is a legacy version that can be found [here](https://github.com/ARM-software/SCALE-Sim) and is no longer maintained. |
20 | | - |
21 | | - |
| 22 | +Note: **SCALE-sim v1** (developed with ARM) is a legacy version that can be found [here](https://github.com/ARM-software/SCALE-Sim) and is no longer maintained. |
22 | 23 |
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23 | | -## Features of v3 |
| 24 | +### Features of v3 |
24 | 25 |
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25 | | -SCALE-Sim v3 includes several advanced features: |
| 26 | +SCALE-Sim v3 includes several advanced features over v2: |
26 | 27 |
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27 | 28 | 1. **Sparsity Support**: Layer-wise and row-wise sparsity support for efficient neural network execution |
28 | 29 | 2. **Ramulator Integration**: Detailed memory model integration for evaluating DRAM performance |
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