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babybear test for addi/logici
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9 files changed

+190
-90
lines changed

9 files changed

+190
-90
lines changed

.github/workflows/tests.yml

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ name: Tests
33
on:
44
merge_group:
55
pull_request:
6-
types: [synchronize, opened, reopened, ready_for_review]
6+
types: [ synchronize, opened, reopened, ready_for_review ]
77
push:
88
branches:
99
- master
@@ -44,3 +44,5 @@ jobs:
4444
cargo make --version || cargo install cargo-make
4545
- name: run test
4646
run: cargo make tests
47+
- name: run test + feature u16limb_circuit
48+
run: cargo make tests_v2

Makefile.toml

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,22 @@ args = [
1414
command = "cargo"
1515
workspace = false
1616

17+
[tasks.tests_v2]
18+
args = [
19+
"test",
20+
# Run everything but 'benches'.
21+
"--lib",
22+
"--bins",
23+
"--tests",
24+
"--examples",
25+
"--workspace",
26+
"--features",
27+
"u16limb_circuit",
28+
]
29+
command = "cargo"
30+
workspace = false
31+
32+
1733
[tasks.riscv_stats]
1834
args = ["run", "--bin", "riscv_stats"]
1935
command = "cargo"

ceno_zkvm/Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ ceno-examples = { path = "../examples-builder" }
6161
glob = "0.3"
6262

6363
[features]
64-
default = ["forbid_overflow", "u16limb_circuit"]
64+
default = ["forbid_overflow"]
6565
flamegraph = ["pprof2/flamegraph", "pprof2/criterion"]
6666
forbid_overflow = []
6767
jemalloc = ["dep:tikv-jemallocator", "dep:tikv-jemalloc-ctl"]

ceno_zkvm/src/instructions/riscv/arith_imm.rs

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -26,34 +26,42 @@ mod test {
2626
structs::ProgramParams,
2727
};
2828
use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32};
29-
use ff_ext::GoldilocksExt2;
29+
#[cfg(feature = "u16limb_circuit")]
30+
use ff_ext::BabyBearExt4;
31+
use ff_ext::{ExtensionField, GoldilocksExt2};
3032
use gkr_iop::circuit_builder::DebugIndex;
3133

3234
#[test]
33-
fn test_opcode_addi_v1() {
34-
test_opcode_addi(1000, 1003, 3);
35-
test_opcode_addi(1000, 997, -3);
35+
fn test_opcode_addi() {
36+
let cases = vec![
37+
(1000, 1003, 3), // positive immediate
38+
(1000, 997, -3), // negative immediate
39+
];
40+
41+
for &(rs1, expected, imm) in &cases {
42+
test_opcode_addi_internal::<GoldilocksExt2>(rs1, expected, imm);
43+
#[cfg(feature = "u16limb_circuit")]
44+
test_opcode_addi_internal::<BabyBearExt4>(rs1, expected, imm);
45+
}
3646
}
3747

38-
fn test_opcode_addi(rs1: u32, rd: u32, imm: i32) {
39-
let mut cs = ConstraintSystem::<GoldilocksExt2>::new(|| "riscv");
48+
fn test_opcode_addi_internal<E: ExtensionField>(rs1: u32, rd: u32, imm: i32) {
49+
let mut cs = ConstraintSystem::<E>::new(|| "riscv");
4050
let mut cb = CircuitBuilder::new(&mut cs);
4151
let config = cb
4252
.namespace(
4353
|| "addi",
4454
|cb| {
45-
let config = AddiInstruction::<GoldilocksExt2>::construct_circuit(
46-
cb,
47-
&ProgramParams::default(),
48-
);
55+
let config =
56+
AddiInstruction::<E>::construct_circuit(cb, &ProgramParams::default());
4957
Ok(config)
5058
},
5159
)
5260
.unwrap()
5361
.unwrap();
5462

5563
let insn_code = encode_rv32(InsnKind::ADDI, 2, 0, 4, imm);
56-
let (raw_witin, lkm) = AddiInstruction::<GoldilocksExt2>::assign_instances(
64+
let (raw_witin, lkm) = AddiInstruction::<E>::assign_instances(
5765
&config,
5866
cb.cs.num_witin as usize,
5967
cb.cs.num_structural_witin as usize,

ceno_zkvm/src/instructions/riscv/branch/test.rs

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
use ceno_emul::{ByteAddr, Change, PC_STEP_SIZE, StepRecord, Word, encode_rv32};
2-
use ff_ext::{BabyBearExt4, ExtensionField, GoldilocksExt2};
2+
#[cfg(feature = "u16limb_circuit")]
3+
use ff_ext::BabyBearExt4;
4+
use ff_ext::{ExtensionField, GoldilocksExt2};
35

46
use super::*;
57
use crate::{

ceno_zkvm/src/instructions/riscv/logic_imm/logic_imm_circuit.rs

Lines changed: 46 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,9 @@ impl<E: ExtensionField> LogicConfig<E> {
124124
#[cfg(test)]
125125
mod test {
126126
use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32u};
127-
use ff_ext::GoldilocksExt2;
127+
#[cfg(feature = "u16limb_circuit")]
128+
use ff_ext::BabyBearExt4;
129+
use ff_ext::{ExtensionField, GoldilocksExt2};
128130
use gkr_iop::circuit_builder::DebugIndex;
129131

130132
use crate::{
@@ -150,27 +152,56 @@ mod test {
150152

151153
#[test]
152154
fn test_opcode_andi() {
153-
verify::<AndiOp>("basic", 0x0000_0011, 3, 0x0000_0011 & 3);
154-
verify::<AndiOp>("zero result", 0x0000_0100, 3, 0x0000_0100 & 3);
155-
verify::<AndiOp>("negative imm", TEST, NEG, TEST & NEG);
155+
let cases = vec![
156+
("basic", 0x0000_0011, 3, 0x0000_0011 & 3),
157+
("zero result", 0x0000_0100, 3, 0x0000_0100 & 3),
158+
("negative imm", TEST, NEG, TEST & NEG),
159+
];
160+
161+
for &(name, rs1, imm, expected) in &cases {
162+
verify::<AndiOp, GoldilocksExt2>(name, rs1, imm, expected);
163+
#[cfg(feature = "u16limb_circuit")]
164+
verify::<AndiOp, BabyBearExt4>(name, rs1, imm, expected);
165+
}
156166
}
157167

158168
#[test]
159169
fn test_opcode_ori() {
160-
verify::<OriOp>("basic", 0x0000_0011, 3, 0x0000_0011 | 3);
161-
verify::<OriOp>("basic2", 0x0000_0100, 3, 0x0000_0100 | 3);
162-
verify::<OriOp>("negative imm", TEST, NEG, TEST | NEG);
170+
let cases = vec![
171+
("basic", 0x0000_0011, 3, 0x0000_0011 | 3),
172+
("basic2", 0x0000_0100, 3, 0x0000_0100 | 3),
173+
("negative imm", TEST, NEG, TEST | NEG),
174+
];
175+
176+
for &(name, rs1, imm, expected) in &cases {
177+
verify::<OriOp, GoldilocksExt2>(name, rs1, imm, expected);
178+
#[cfg(feature = "u16limb_circuit")]
179+
verify::<OriOp, BabyBearExt4>(name, rs1, imm, expected);
180+
}
163181
}
164182

165183
#[test]
166184
fn test_opcode_xori() {
167-
verify::<XoriOp>("basic", 0x0000_0011, 3, 0x0000_0011 ^ 3);
168-
verify::<XoriOp>("non-overlap", 0x0000_0100, 3, 0x0000_0100 ^ 3);
169-
verify::<XoriOp>("negative imm", TEST, NEG, TEST ^ NEG);
185+
let cases = vec![
186+
("basic", 0x0000_0011, 3, 0x0000_0011 ^ 3),
187+
("non-overlap", 0x0000_0100, 3, 0x0000_0100 ^ 3),
188+
("negative imm", TEST, NEG, TEST ^ NEG),
189+
];
190+
191+
for &(name, rs1, imm, expected) in &cases {
192+
verify::<XoriOp, GoldilocksExt2>(name, rs1, imm, expected);
193+
#[cfg(feature = "u16limb_circuit")]
194+
verify::<XoriOp, BabyBearExt4>(name, rs1, imm, expected);
195+
}
170196
}
171197

172-
fn verify<I: LogicOp>(name: &'static str, rs1_read: u32, imm: u32, expected_rd_written: u32) {
173-
let mut cs = ConstraintSystem::<GoldilocksExt2>::new(|| "riscv");
198+
fn verify<I: LogicOp, E: ExtensionField>(
199+
name: &'static str,
200+
rs1_read: u32,
201+
imm: u32,
202+
expected_rd_written: u32,
203+
) {
204+
let mut cs = ConstraintSystem::<E>::new(|| "riscv");
174205
let mut cb = CircuitBuilder::new(&mut cs);
175206

176207
let (prefix, rd_written) = match I::INST_KIND {
@@ -184,18 +215,16 @@ mod test {
184215
.namespace(
185216
|| format!("{prefix}_({name})"),
186217
|cb| {
187-
let config = LogicInstruction::<GoldilocksExt2, I>::construct_circuit(
188-
cb,
189-
&ProgramParams::default(),
190-
);
218+
let config =
219+
LogicInstruction::<E, I>::construct_circuit(cb, &ProgramParams::default());
191220
Ok(config)
192221
},
193222
)
194223
.unwrap()
195224
.unwrap();
196225

197226
let insn_code = encode_rv32u(I::INST_KIND, 2, 0, 4, imm);
198-
let (raw_witin, lkm) = LogicInstruction::<GoldilocksExt2, I>::assign_instances(
227+
let (raw_witin, lkm) = LogicInstruction::<E, I>::assign_instances(
199228
&config,
200229
cb.cs.num_witin as usize,
201230
cb.cs.num_structural_witin as usize,

ceno_zkvm/src/instructions/riscv/slt.rs

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,9 @@ pub type SltuInstruction<E> = slt_circuit::SetLessThanInstruction<E, SltuOp>;
2626
#[cfg(test)]
2727
mod test {
2828
use ceno_emul::{Change, StepRecord, Word, encode_rv32};
29-
use ff_ext::{BabyBearExt4, ExtensionField, GoldilocksExt2};
29+
#[cfg(feature = "u16limb_circuit")]
30+
use ff_ext::BabyBearExt4;
31+
use ff_ext::{ExtensionField, GoldilocksExt2};
3032

3133
use rand::RngCore;
3234

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