clk sync JTAG and Debug module

[ohadbox]

Hey,

I'm working on an Unleashed configuration of Freedom and having an issue with clk syncing in the design:

1. Top level generates JTAG inputs and clk.
2. There's a Debug module (DM) conversion.
3. In DM, some of the signals are synced to system clk (sys_clk).
4. Most signals go straight to core which is also under sys_clk.
5. There's in output named "ndmreset" going to core (via OR gate). But this signal isn't synced to sys_clk and is still under jtag_clk freq.

Is there something I'm missing?
Shouldn't there be a sync to sys_clk on this signal as well?

Thanks!