Merge #391

391: replace GetBusFreq with BusClock r=therealprof a=burrbull

Same as in f3xx-hal, f4xx-hal

Co-authored-by: Andrey Zgarbul <[email protected]>

Author: bors[bot]

CHANGELOG.md

@@ -12,6 +12,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `Instance` for Timer's, rtic-monotonic fugit impl
 - Serial can now be reconfigured, allowing to change e.g. the baud rate after initialisation.
 
+### Changed
+
+- replace `GetBusFreq` with `BusClock` and `BusTimerClock`
+
 ## [v0.8.0] - 2021-12-29
 
 ### Breaking changes

src/i2c.rs

@@ -9,7 +9,7 @@ use crate::gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9};
 use crate::gpio::{Alternate, OpenDrain};
 use crate::hal::blocking::i2c::{Read, Write, WriteRead};
 use crate::pac::{DWT, I2C1, I2C2, RCC};
-use crate::rcc::{Clocks, Enable, GetBusFreq, Reset};
+use crate::rcc::{BusClock, Clocks, Enable, Reset};
 use crate::time::Hertz;
 use core::ops::Deref;
 use nb::Error::{Other, WouldBlock};
@@ -117,7 +117,7 @@ pub struct I2c<I2C, PINS> {
 }
 
 pub trait Instance:
-    crate::Sealed + Deref<Target = crate::pac::i2c1::RegisterBlock> + Enable + Reset + GetBusFreq
+    crate::Sealed + Deref<Target = crate::pac::i2c1::RegisterBlock> + Enable + Reset + BusClock
 {
 }
 
@@ -162,7 +162,7 @@ where
         I2C::enable(rcc);
         I2C::reset(rcc);
 
-        let pclk1 = I2C::get_frequency(&clocks).0;
+        let pclk1 = I2C::clock(&clocks).0;
 
         assert!(mode.get_frequency().0 <= 400_000);
 

src/pwm_input.rs

@@ -13,7 +13,7 @@ use crate::pac::{TIM2, TIM3};
 
 use crate::afio::MAPR;
 use crate::gpio::{self, Input};
-use crate::rcc::{Clocks, GetBusFreq, RccBus};
+use crate::rcc::{BusTimerClock, Clocks};
 use crate::time::Hertz;
 use crate::timer::Timer;
 
@@ -273,7 +273,7 @@ macro_rules! hal {
                     if ccr1 == 0 {
                         Err(Error::FrequencyTooLow)
                     } else {
-                        let clk : u32 = <$TIMX as RccBus>::Bus::get_timer_frequency(&clocks).0;
+                        let clk : u32 = <$TIMX>::timer_clock(&clocks).0;
                         Ok(Hertz(clk/((presc+1) as u32*(ccr1 + 1)as u32)))
                     }
                 }

src/rcc.rs

@@ -416,46 +416,64 @@ impl Clocks {
     }
 }
 
-pub trait GetBusFreq {
-    fn get_frequency(clocks: &Clocks) -> Hertz;
-    fn get_timer_frequency(clocks: &Clocks) -> Hertz {
-        Self::get_frequency(clocks)
-    }
+/// Frequency on bus that peripheral is connected in
+pub trait BusClock {
+    /// Calculates frequency depending on `Clock` state
+    fn clock(clocks: &Clocks) -> Hertz;
+}
+
+/// Frequency on bus that timer is connected in
+pub trait BusTimerClock {
+    /// Calculates base frequency of timer depending on `Clock` state
+    fn timer_clock(clocks: &Clocks) -> Hertz;
 }
 
-impl<T> GetBusFreq for T
+impl<T> BusClock for T
 where
     T: RccBus,
-    T::Bus: GetBusFreq,
+    T::Bus: BusClock,
 {
-    fn get_frequency(clocks: &Clocks) -> Hertz {
-        T::Bus::get_frequency(clocks)
+    fn clock(clocks: &Clocks) -> Hertz {
+        T::Bus::clock(clocks)
     }
-    fn get_timer_frequency(clocks: &Clocks) -> Hertz {
-        T::Bus::get_timer_frequency(clocks)
+}
+
+impl<T> BusTimerClock for T
+where
+    T: RccBus,
+    T::Bus: BusTimerClock,
+{
+    fn timer_clock(clocks: &Clocks) -> Hertz {
+        T::Bus::timer_clock(clocks)
     }
 }
 
-impl GetBusFreq for AHB {
-    fn get_frequency(clocks: &Clocks) -> Hertz {
+impl BusClock for AHB {
+    fn clock(clocks: &Clocks) -> Hertz {
         clocks.hclk
     }
 }
 
-impl GetBusFreq for APB1 {
-    fn get_frequency(clocks: &Clocks) -> Hertz {
+impl BusClock for APB1 {
+    fn clock(clocks: &Clocks) -> Hertz {
         clocks.pclk1
     }
-    fn get_timer_frequency(clocks: &Clocks) -> Hertz {
-        clocks.pclk1_tim()
-    }
 }
 
-impl GetBusFreq for APB2 {
-    fn get_frequency(clocks: &Clocks) -> Hertz {
+impl BusClock for APB2 {
+    fn clock(clocks: &Clocks) -> Hertz {
         clocks.pclk2
     }
-    fn get_timer_frequency(clocks: &Clocks) -> Hertz {
+}
+
+impl BusTimerClock for APB1 {
+    fn timer_clock(clocks: &Clocks) -> Hertz {
+        clocks.pclk1_tim()
+    }
+}
+
+impl BusTimerClock for APB2 {
+    fn timer_clock(clocks: &Clocks) -> Hertz {
         clocks.pclk2_tim()
     }
 }

src/serial.rs

@@ -53,7 +53,7 @@ use crate::gpio::gpiob::{PB10, PB11, PB6, PB7};
 use crate::gpio::gpioc::{PC10, PC11};
 use crate::gpio::gpiod::{PD5, PD6, PD8, PD9};
 use crate::gpio::{Alternate, Input};
-use crate::rcc::{Clocks, Enable, GetBusFreq, Reset};
+use crate::rcc::{BusClock, Clocks, Enable, Reset};
 use crate::time::{Bps, U32Ext};
 
 /// Interrupt event
@@ -192,7 +192,7 @@ pub struct Serial<USART, PINS> {
 }
 
 pub trait Instance:
-    crate::Sealed + Deref<Target = uart_base::RegisterBlock> + Enable + Reset + GetBusFreq
+    crate::Sealed + Deref<Target = uart_base::RegisterBlock> + Enable + Reset + BusClock
 {
     #[doc(hidden)]
     fn ptr() -> *const uart_base::RegisterBlock;
@@ -249,7 +249,7 @@ where
 
     fn apply_config(&self, config: Config, clocks: Clocks) {
         // Configure baud rate
-        let brr = USART::get_frequency(&clocks).0 / config.baudrate.0;
+        let brr = USART::clock(&clocks).0 / config.baudrate.0;
         assert!(brr >= 16, "impossible baud rate");
         self.usart.brr.write(|w| unsafe { w.bits(brr) });
 

src/spi.rs

@@ -51,7 +51,7 @@ use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
 #[cfg(feature = "connectivity")]
 use crate::gpio::gpioc::{PC10, PC11, PC12};
 use crate::gpio::{Alternate, Input};
-use crate::rcc::{Clocks, Enable, GetBusFreq, Reset};
+use crate::rcc::{BusClock, Clocks, Enable, Reset};
 use crate::time::Hertz;
 
 use core::sync::atomic::{self, Ordering};
@@ -142,7 +142,7 @@ remap!(Spi3NoRemap, SPI3, false, PB3, PB4, PB5);
 remap!(Spi3Remap, SPI3, true, PC10, PC11, PC12);
 
 pub trait Instance:
-    crate::Sealed + Deref<Target = crate::pac::spi1::RegisterBlock> + Enable + Reset + GetBusFreq
+    crate::Sealed + Deref<Target = crate::pac::spi1::RegisterBlock> + Enable + Reset + BusClock
 {
 }
 
@@ -342,7 +342,7 @@ where
         // disable SS output
         spi.cr2.write(|w| w.ssoe().clear_bit());
 
-        let br = match SPI::get_frequency(&clocks).0 / freq.0 {
+        let br = match SPI::clock(&clocks).0 / freq.0 {
             0 => unreachable!(),
             1..=2 => 0b000,
             3..=5 => 0b001,

src/timer.rs

@@ -278,7 +278,7 @@ impl Cancel for CountDownTimer<SYST> {
 
 impl Periodic for CountDownTimer<SYST> {}
 
-pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + rcc::GetBusFreq {}
+pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + rcc::BusTimerClock {}
 
 impl<TIM> Timer<TIM>
 where
@@ -295,7 +295,7 @@ where
         }
 
         Self {
-            clk: TIM::get_timer_frequency(&clocks),
+            clk: TIM::timer_clock(clocks),
             tim,
         }
     }