add constructor aliases

Author: burrbull

examples/pwm.rs

@@ -13,7 +13,7 @@ use stm32f1xx_hal::{
     pac,
     prelude::*,
     pwm::Channel,
-    time::MilliSeconds,
+    time::ms,
     timer::{Tim2NoRemap, Timer},
 };
 
@@ -62,8 +62,7 @@ fn main() -> ! {
     //// Operations affecting all defined channels on the Timer
 
     // Adjust period to 0.5 seconds
-    let m500: MilliSeconds = 500.millis();
-    pwm.set_period(m500.into_rate());
+    pwm.set_period(ms(500).into_rate());
 
     asm::bkpt();
 

src/adc.rs

@@ -11,10 +11,10 @@ use crate::gpio::gpiof;
 use crate::gpio::Analog;
 use crate::gpio::{gpioa, gpiob, gpioc};
 use crate::rcc::{Clocks, Enable, Reset};
+use crate::time::kHz;
 use core::sync::atomic::{self, Ordering};
 use cortex_m::asm::delay;
 use embedded_dma::StaticWriteBuffer;
-use fugit::{HertzU32 as Hertz, RateExtU32};
 
 #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
 use crate::pac::ADC2;
@@ -206,11 +206,9 @@ macro_rules! adc_hal {
                     // The manual states that we need to wait two ADC clocks cycles after power-up
                     // before starting calibration, we already delayed in the power-up process, but
                     // if the adc clock is too low that was not enough.
-                    let m2_5: Hertz = 2500.kHz();
-                    if s.clocks.adcclk() < m2_5 {
+                    if s.clocks.adcclk() < kHz(2500) {
                         let two_adc_cycles = s.clocks.sysclk() / s.clocks.adcclk() * 2;
-                        let k800: Hertz = 800.kHz();
-                        let already_delayed = s.clocks.sysclk() / k800;
+                        let already_delayed = s.clocks.sysclk() / kHz(800);
                         if two_adc_cycles > already_delayed {
                             delay(two_adc_cycles - already_delayed);
                         }
@@ -272,8 +270,7 @@ macro_rules! adc_hal {
                     // this time can be found in the datasheets.
                     // Here we are delaying for approximately 1us, considering 1.25 instructions per
                     // cycle. Do we support a chip which needs more than 1us ?
-                    let k800: Hertz = 800.kHz();
-                    delay(self.clocks.sysclk() / k800);
+                    delay(self.clocks.sysclk() / kHz(800));
                 }
 
                 fn power_down(&mut self) {

src/i2c.rs

@@ -10,8 +10,8 @@ use crate::gpio::{Alternate, OpenDrain};
 use crate::hal::blocking::i2c::{Read, Write, WriteRead};
 use crate::pac::{DWT, I2C1, I2C2, RCC};
 use crate::rcc::{BusClock, Clocks, Enable, Reset};
+use crate::time::{kHz, Hertz};
 use core::ops::Deref;
-use fugit::{HertzU32 as Hertz, RateExtU32};
 use nb::Error::{Other, WouldBlock};
 use nb::{Error as NbError, Result as NbResult};
 
@@ -74,8 +74,7 @@ impl Mode {
 
 impl From<Hertz> for Mode {
     fn from(frequency: Hertz) -> Self {
-        let k100: Hertz = 100.kHz();
-        if frequency <= k100 {
+        if frequency <= kHz(100) {
             Self::Standard { frequency }
         } else {
             Self::Fast {
@@ -159,8 +158,7 @@ where
 
         let pclk1 = I2C::clock(&clocks);
 
-        let k400: Hertz = 400.kHz();
-        assert!(mode.get_frequency() <= k400);
+        assert!(mode.get_frequency() <= kHz(400));
 
         let mut i2c = I2c {
             i2c,

src/rcc.rs

@@ -3,6 +3,7 @@
 use crate::pac::{rcc, PWR, RCC};
 
 use crate::flash::ACR;
+use crate::time::MHz;
 use fugit::{HertzU32 as Hertz, RateExtU32};
 
 use crate::backup_domain::BackupDomain;
@@ -190,12 +191,10 @@ impl CFGR {
         // adjust flash wait states
         #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
         unsafe {
-            let m24: Hertz = 24.MHz();
-            let m48: Hertz = 48.MHz();
             acr.acr().write(|w| {
-                w.latency().bits(if clocks.sysclk <= m24 {
+                w.latency().bits(if clocks.sysclk <= MHz(24) {
                     0b000
-                } else if clocks.sysclk <= m48 {
+                } else if clocks.sysclk <= MHz(48) {
                     0b001
                 } else {
                     0b010

src/rtc.rs

@@ -4,14 +4,14 @@
 use crate::pac::{RCC, RTC};
 
 use crate::backup_domain::BackupDomain;
-use crate::time::Hertz;
+use crate::time::{Hertz, Hz};
 
 use core::convert::Infallible;
 use core::marker::PhantomData;
 
 // The LSE runs at at 32 768 hertz unless an external clock is provided
-const LSE_HERTZ: Hertz = Hertz::from_raw(32_768);
-const LSI_HERTZ: Hertz = Hertz::from_raw(40_000);
+const LSE_HERTZ: Hertz = Hz(32_768);
+const LSI_HERTZ: Hertz = Hz(40_000);
 
 /// RTC clock source HSE clock divided by 128 (type state)
 pub struct RtcClkHseDiv128;

src/time.rs

@@ -27,6 +27,8 @@
 //! assert_eq!(freq_khz, freq_mhz);
 //! ```
 
+#![allow(non_snake_case)]
+
 use core::ops;
 use cortex_m::peripheral::{DCB, DWT};
 
@@ -53,6 +55,26 @@ impl U32Ext for u32 {
     }
 }
 
+pub const fn Hz(val: u32) -> Hertz {
+    Hertz::from_raw(val)
+}
+
+pub const fn kHz(val: u32) -> KiloHertz {
+    KiloHertz::from_raw(val)
+}
+
+pub const fn MHz(val: u32) -> MegaHertz {
+    MegaHertz::from_raw(val)
+}
+
+pub const fn ms(val: u32) -> MilliSeconds {
+    MilliSeconds::from_ticks(val)
+}
+
+pub const fn us(val: u32) -> MicroSeconds {
+    MicroSeconds::from_ticks(val)
+}
+
 /// Macro to implement arithmetic operations (e.g. multiplication, division)
 /// for wrapper types.
 macro_rules! impl_arithmetic {