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WIP: Starting to implement the I2S macros
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-112
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2 files changed

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-112
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‎Cargo.toml‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,8 +52,9 @@ version = "1.0.2"
5252
# https://github.com/rust-embedded/embedded-hal/pull/204
5353
features = ["unproven"]
5454
# version = "0.2.3"
55-
git = "https://github.com/eldruin/embedded-hal/"
56-
branch = "i2s-v0.2.x"
55+
# git = "https://github.com/eldruin/embedded-hal/"
56+
# branch = "i2s-v0.2.x"
57+
path = "../embedded-hal"
5758

5859
[dev-dependencies]
5960
panic-semihosting = "0.5.3"

‎src/i2s.rs‎

Lines changed: 155 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,7 @@
11
use core::ops::Deref;
22
use core::ptr;
33

4-
// use embedded_hal::spi;
5-
// pub use embedded_hal::spi::{Mode, Phase, Polarity};
6-
// use nb;
4+
use embedded_hal::blocking::i2s::{Read, Write, WriteIter};
75

86
#[cfg(any(
97
feature = "stm32f401",
@@ -389,42 +387,24 @@ pub struct NoSd;
389387
/// A filler type for when the SdExt pin is unnecessary
390388
pub struct NoSdExt;
391389

392-
// NOTE: Manual pins for I2S3 during development.
393-
// TODO: Should be created with macro.
394-
impl PinCk<SPI3> for NoCk {}
395-
impl PinCk<SPI3> for PB3<Alternate<AF6>> {}
396-
impl PinCk<SPI3> for PC10<Alternate<AF6>> {}
397-
398-
impl PinWs<SPI3> for NoWs {}
399-
impl PinWs<SPI3> for PA4<Alternate<AF6>> {}
400-
impl PinWs<SPI3> for PA15<Alternate<AF6>> {}
401-
402-
impl PinSd<SPI3> for NoSd {}
403-
impl PinSd<SPI3> for PB5<Alternate<AF6>> {}
404-
impl PinSd<SPI3> for PC12<Alternate<AF6>> {}
405-
406-
impl PinSdExt<SPI3> for NoSdExt {}
407-
impl PinSdExt<SPI3> for PB4<Alternate<AF7>> {}
408-
impl PinSdExt<SPI3> for PC11<Alternate<AF5>> {}
409-
410-
// macro_rules! pins {
411-
// ($($SPIX:ty: CK: [$($CK:ty),*] WS: [$($WS:ty),*] SD: [$($SD:ty),*] SDEXT: [$($SDEXT:ty),*])+) => {
412-
// $(
413-
// $(
414-
// impl PinCk<$SPIX> for $CK {}
415-
// )*
416-
// $(
417-
// impl PinWs<$SPIX> for $WS {}
418-
// )*
419-
// $(
420-
// impl PinSd<$SPIX> for $SD {}
421-
// )*
422-
// $(
423-
// impl PinSdExt<$SPIX> for $SDEXT {}
424-
// )*
425-
// )+
426-
// }
427-
// }
390+
macro_rules! pins {
391+
($($SPIX:ty: CK: [$($CK:ty),*] WS: [$($WS:ty),*] SD: [$($SD:ty),*] SDEXT: [$($SDEXT:ty),*])+) => {
392+
$(
393+
$(
394+
impl PinCk<$SPIX> for $CK {}
395+
)*
396+
$(
397+
impl PinWs<$SPIX> for $WS {}
398+
)*
399+
$(
400+
impl PinSd<$SPIX> for $SD {}
401+
)*
402+
$(
403+
impl PinSdExt<$SPIX> for $SDEXT {}
404+
)*
405+
)+
406+
}
407+
}
428408

429409
// #[cfg(any(
430410
// feature = "stm32f401",
@@ -483,43 +463,65 @@ impl PinSdExt<SPI3> for PC11<Alternate<AF5>> {}
483463
// ]
484464
// }
485465

486-
// #[cfg(any(
487-
// feature = "stm32f401",
488-
// feature = "stm32f405",
489-
// feature = "stm32f407",
490-
// feature = "stm32f411",
491-
// feature = "stm32f412",
492-
// feature = "stm32f413",
493-
// feature = "stm32f415",
494-
// feature = "stm32f417",
495-
// feature = "stm32f423",
496-
// feature = "stm32f427",
497-
// feature = "stm32f429",
498-
// feature = "stm32f437",
499-
// feature = "stm32f439",
500-
// feature = "stm32f446",
501-
// feature = "stm32f469",
502-
// feature = "stm32f479"
503-
// ))]
504-
// pins! {
505-
// SPI3:
506-
// CK: [
507-
// NoCk,
508-
// PB3<Alternate<AF6>>,
509-
// PC10<Alternate<AF6>>
510-
// ]
511-
// WS: [] // TODO: Fill in.
512-
// SD: [
513-
// NoSd,
514-
// PB5<Alternate<AF6>>,
515-
// PC12<Alternate<AF6>>
516-
// ]
517-
// SDEXT: [
518-
// NoSdExt,
519-
// PB4<Alternate<AF6>>,
520-
// PC11<Alternate<AF6>>
521-
// ]
522-
// }
466+
#[cfg(any(
467+
feature = "stm32f401",
468+
feature = "stm32f405",
469+
feature = "stm32f407",
470+
feature = "stm32f411",
471+
feature = "stm32f412",
472+
feature = "stm32f413",
473+
feature = "stm32f415",
474+
feature = "stm32f417",
475+
feature = "stm32f423",
476+
feature = "stm32f427",
477+
feature = "stm32f429",
478+
feature = "stm32f437",
479+
feature = "stm32f439",
480+
feature = "stm32f446",
481+
feature = "stm32f469",
482+
feature = "stm32f479"
483+
))]
484+
pins! {
485+
SPI3:
486+
CK: [
487+
NoCk,
488+
PB3<Alternate<AF6>>,
489+
PC10<Alternate<AF6>>
490+
]
491+
WS: [
492+
NoWs,
493+
PA4<Alternate<AF6>>,
494+
PA15<Alternate<AF6>>
495+
]
496+
SD: [
497+
NoSd,
498+
PB5<Alternate<AF6>>,
499+
PC12<Alternate<AF6>>
500+
]
501+
SDEXT: [
502+
NoSdExt,
503+
PB4<Alternate<AF7>>,
504+
PC11<Alternate<AF5>>
505+
]
506+
}
507+
508+
// NOTE: Manual pins for I2S3 during development.
509+
// TODO: Should be created with the macro above.
510+
// impl PinCk<SPI3> for NoCk {}
511+
// impl PinCk<SPI3> for PB3<Alternate<AF6>> {}
512+
// impl PinCk<SPI3> for PC10<Alternate<AF6>> {}
513+
514+
// impl PinWs<SPI3> for NoWs {}
515+
// impl PinWs<SPI3> for PA4<Alternate<AF6>> {}
516+
// impl PinWs<SPI3> for PA15<Alternate<AF6>> {}
517+
518+
// impl PinSd<SPI3> for NoSd {}
519+
// impl PinSd<SPI3> for PB5<Alternate<AF6>> {}
520+
// impl PinSd<SPI3> for PC12<Alternate<AF6>> {}
521+
522+
// impl PinSdExt<SPI3> for NoSdExt {}
523+
// impl PinSdExt<SPI3> for PB4<Alternate<AF7>> {}
524+
// impl PinSdExt<SPI3> for PC11<Alternate<AF5>> {}
523525

524526
// #[cfg(any(
525527
// feature = "stm32f401",
@@ -832,26 +834,46 @@ pub struct I2s<SPI, PINS> {
832834
// }
833835
// }
834836

835-
// #[cfg(any(
836-
// feature = "stm32f401",
837-
// feature = "stm32f405",
838-
// feature = "stm32f407",
839-
// feature = "stm32f411",
840-
// feature = "stm32f412",
841-
// feature = "stm32f413",
842-
// feature = "stm32f415",
843-
// feature = "stm32f417",
844-
// feature = "stm32f423",
845-
// feature = "stm32f427",
846-
// feature = "stm32f429",
847-
// feature = "stm32f437",
848-
// feature = "stm32f439",
849-
// feature = "stm32f446",
850-
// feature = "stm32f469",
851-
// feature = "stm32f479"
852-
// ))]
853-
// impl<PINS> Spi<SPI3, PINS> {
854-
// pub fn spi3(spi: SPI3, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self
837+
#[cfg(any(
838+
feature = "stm32f401",
839+
feature = "stm32f405",
840+
feature = "stm32f407",
841+
feature = "stm32f411",
842+
feature = "stm32f412",
843+
feature = "stm32f413",
844+
feature = "stm32f415",
845+
feature = "stm32f417",
846+
feature = "stm32f423",
847+
feature = "stm32f427",
848+
feature = "stm32f429",
849+
feature = "stm32f437",
850+
feature = "stm32f439",
851+
feature = "stm32f446",
852+
feature = "stm32f469",
853+
feature = "stm32f479"
854+
))]
855+
impl<PINS> I2s<SPI3, PINS> {
856+
pub fn i2s3(spi: SPI3, pins: PINS, freq: Hertz, clocks: Clocks) -> Self
857+
where
858+
PINS: Pins<SPI3>,
859+
{
860+
// NOTE(unsafe) This executes only during initialisation
861+
let rcc = unsafe { &(*RCC::ptr()) };
862+
863+
// Enable clock for SPI
864+
rcc.apb1enr.modify(|_, w| w.spi3en().set_bit());
865+
866+
// TODO: Use PLL I2S clock.
867+
// if clocks.plli2sclk().is_some() {
868+
// I2s { spi, pins }.init(freq, clocks.plli2sclk())
869+
// }
870+
871+
I2s { spi, pins }.init(freq, freq)
872+
}
873+
}
874+
875+
// impl<PINS> I2s<SPI3, PINS> {
876+
// pub fn i2s3(spi: SPI3, pins: PINS, freq: Hertz, clocks: Clocks) -> Self
855877
// where
856878
// PINS: Pins<SPI3>,
857879
// {
@@ -861,7 +883,8 @@ pub struct I2s<SPI, PINS> {
861883
// // Enable clock for SPI
862884
// rcc.apb1enr.modify(|_, w| w.spi3en().set_bit());
863885

864-
// Spi { spi, pins }.init(mode, freq, clocks.pclk1())
886+
// // TODO: Use Real clock value from I2S PLL.
887+
// I2s { spi, pins }.init(freq, freq)
865888
// }
866889
// }
867890

@@ -945,27 +968,49 @@ pub struct I2s<SPI, PINS> {
945968
// }
946969
// }
947970

948-
impl<PINS> I2s<SPI3, PINS> {
949-
pub fn i2s3(spi: SPI3, pins: PINS, freq: Hertz, clocks: Clocks) -> Self
950-
where
951-
PINS: Pins<SPI3>,
952-
{
953-
// NOTE(unsafe) This executes only during initialisation
954-
let rcc = unsafe { &(*RCC::ptr()) };
955-
956-
// Enable clock for SPI
957-
rcc.apb1enr.modify(|_, w| w.spi3en().set_bit());
971+
impl<SPI, PINS, W> Read<W> for I2s<SPI, PINS>
972+
where
973+
SPI: Deref<Target = spi1::RegisterBlock>,
974+
{
975+
type Error = Error;
976+
977+
fn try_read<'w>(
978+
&mut self,
979+
left_words: &'w mut [W],
980+
right_words: &'w mut [W],
981+
) -> Result<(), Self::Error> {
982+
// TODO
983+
Ok(())
984+
}
985+
}
958986

959-
// TODO: Use Real clock value from I2S PLL.
960-
I2s { spi, pins }.init(freq, freq)
987+
impl<SPI, PINS, W> Write<W> for I2s<SPI, PINS>
988+
where
989+
SPI: Deref<Target = spi1::RegisterBlock>,
990+
W: Copy,
991+
{
992+
type Error = Error;
993+
994+
fn try_write<'w>(
995+
&mut self,
996+
left_words: &'w [W],
997+
right_words: &'w [W],
998+
) -> Result<(), Self::Error> {
999+
for (lw, rw) in left_words.iter().zip(right_words.iter()) {
1000+
while self.spi.sr.read().txe().bit_is_clear() {}
1001+
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut W, *lw) }
1002+
while self.spi.sr.read().txe().bit_is_clear() {}
1003+
unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut W, *rw) }
1004+
}
1005+
Ok(())
9611006
}
9621007
}
9631008

9641009
impl<SPI, PINS> I2s<SPI, PINS>
9651010
where
9661011
SPI: Deref<Target = spi1::RegisterBlock>,
9671012
{
968-
pub fn init(self, freq: Hertz, clock: Hertz) -> Self {
1013+
pub fn init(self, _freq: Hertz, _clock: Hertz) -> Self {
9691014
// disable SS output
9701015
self.spi.cr2.write(|w| w.ssoe().clear_bit());
9711016

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