spi: add DMA support for TX (#107)

* spi: add support for TX DMA
* spi: add example for DMA usage
---------

Signed-off-by: Jean-Baptiste Theou <[email protected]>
Co-authored-by: Jean-Baptiste Theou <[email protected]>

Author: jbtheou

examples/spi-dma.rs

@@ -0,0 +1,74 @@
+// This example is to test the SPI with DMA support. Will output a pattern
+// in a loop
+
+#![no_main]
+#![no_std]
+
+use crate::hal::{
+    block,
+    delay::DelayFromCountDownTimer,
+    gpio::gpioa::PA5,
+    gpio::gpioa::PA6,
+    gpio::gpioa::PA7,
+    gpio::Alternate,
+    gpio::AF5,
+    prelude::*,
+    pwr::PwrExt,
+    rcc::Config,
+    spi,
+    stm32::Peripherals,
+    time::{ExtU32, RateExtU32},
+    timer::Timer,
+};
+
+use cortex_m_rt::entry;
+use log::info;
+use stm32g4xx_hal as hal;
+use stm32g4xx_hal::dma::config::DmaConfig;
+use stm32g4xx_hal::dma::stream::DMAExt;
+use stm32g4xx_hal::dma::TransferExt;
+
+#[macro_use]
+mod utils;
+
+const BUFFER_SIZE: usize = 254;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+
+    let dp = Peripherals::take().unwrap();
+    let rcc = dp.RCC.constrain();
+    let pwr = dp.PWR.constrain().freeze();
+    let mut rcc = rcc.freeze(Config::hsi(), pwr);
+    let timer2 = Timer::new(dp.TIM2, &rcc.clocks);
+    let mut delay_tim2 = DelayFromCountDownTimer::new(timer2.start_count_down(100.millis()));
+
+    let gpioa = dp.GPIOA.split(&mut rcc);
+    let sclk: PA5<Alternate<AF5>> = gpioa.pa5.into_alternate();
+    let miso: PA6<Alternate<AF5>> = gpioa.pa6.into_alternate();
+    let mosi: PA7<Alternate<AF5>> = gpioa.pa7.into_alternate();
+
+    let mut spi = dp
+        .SPI1
+        .spi((sclk, miso, mosi), spi::MODE_0, 400.kHz(), &mut rcc);
+    let mut streams = dp.DMA1.split(&rcc);
+    let config = DmaConfig::default()
+        .transfer_complete_interrupt(false)
+        .circular_buffer(true)
+        .memory_increment(true);
+
+    let mut buf: [u8; BUFFER_SIZE] = [0; BUFFER_SIZE];
+    for index in 0..BUFFER_SIZE {
+        buf[index] = index as u8;
+    }
+    let dma_buf = cortex_m::singleton!(: [u8; BUFFER_SIZE] = buf).unwrap();
+    let mut transfer_dma =
+        streams
+            .0
+            .into_memory_to_peripheral_transfer(spi.enable_tx_dma(), &mut dma_buf[..], config);
+    transfer_dma.start(|_spi| {});
+    loop {
+        delay_tim2.delay_ms(1000_u16);
+    }
+}

src/spi.rs

@@ -1,3 +1,6 @@
+use crate::dma::mux::DmaMuxResources;
+use crate::dma::traits::TargetAddress;
+use crate::dma::MemoryToPeripheral;
 use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiof::*, Alternate, AF5, AF6};
 #[cfg(any(
     feature = "stm32g471",
@@ -20,6 +23,7 @@ use crate::stm32::{RCC, SPI1, SPI2, SPI3};
 use crate::time::Hertz;
 use core::cell::UnsafeCell;
 use core::ptr;
+
 pub use hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 
 /// SPI error
@@ -74,6 +78,7 @@ macro_rules! spi {
         sck: [ $($( #[ $pmetasck:meta ] )* $SCK:ty,)+ ],
         miso: [ $($( #[ $pmetamiso:meta ] )* $MISO:ty,)+ ],
         mosi: [ $($( #[ $pmetamosi:meta ] )* $MOSI:ty,)+ ],
+        $mux:expr,
     ) => {
         impl PinSck<$SPIX> for NoSck {}
 
@@ -166,6 +171,14 @@ macro_rules! spi {
             pub fn release(self) -> ($SPIX, PINS) {
                 (self.spi, self.pins)
             }
+
+            pub fn enable_tx_dma(self) -> Spi<$SPIX, PINS> {
+                self.spi.cr2.modify(|_, w| w.txdmaen().set_bit());
+                Spi {
+                    spi: self.spi,
+                    pins: self.pins,
+                }
+            }
         }
 
         impl SpiExt<$SPIX> for $SPIX {
@@ -220,6 +233,18 @@ macro_rules! spi {
                 })
             }
         }
+        unsafe impl<Pin> TargetAddress<MemoryToPeripheral> for Spi<$SPIX, Pin> {
+            #[inline(always)]
+            fn address(&self) -> u32 {
+                // unsafe: only the Tx part accesses the Tx register
+                &unsafe { &*<$SPIX>::ptr() }.dr as *const _ as u32
+            }
+
+            type MemSize = u8;
+
+            const REQUEST_LINE: Option<u8> = Some($mux as u8);
+        }
+
 
         impl<PINS> ::hal::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
 
@@ -266,6 +291,7 @@ spi!(
         ))]
         PG4<Alternate<AF5>>,
     ],
+    DmaMuxResources::SPI1_TX,
 );
 
 spi!(
@@ -285,6 +311,7 @@ spi!(
         PA11<Alternate<AF5>>,
         PB15<Alternate<AF5>>,
     ],
+    DmaMuxResources::SPI2_TX,
 );
 
 spi!(
@@ -310,6 +337,7 @@ spi!(
         PB5<Alternate<AF6>>,
         PC12<Alternate<AF6>>,
     ],
+    DmaMuxResources::SPI3_TX,
 );
 
 #[cfg(any(
@@ -334,4 +362,5 @@ spi!(
         PE6<Alternate<AF5>>,
         PE14<Alternate<AF5>>,
     ],
+    DmaMuxResources::SPI4_TX,
 );