Interrupts Enabled light?

[sg]

I’ve been learning to setup NZ-COM and playing a bit with BDS-C and have noticed that occasionally the Interrupts Enabled light will turn on. Additionally, most of the other lights will be lit as well rather than the typical flickering and flashing. As far as I can tell, things are still working normally and I can issue commands, etc. I haven’t been able to determine what is causing it to go into this state and I haven’t been able to find a reference as to what that light indicates. Can anyone shed any light (haha) on what this means?

[nbreeden2]

This article gives a pretty high level description of 8080 interrupts. You'll find the detail in the 8080 Assembly Programming manual.
https://stackoverflow.com/questions/2165914/how-do-interrupts-work-on-the-intel-8080#:~:text=The%208080%20has%20an%20Interrupt%20line%20%28pin%2014%29.,EI%20and%20DI%2C%20set%20and%20clear%20this%20bit.

There are two opcodes in the 8080 CPU set that enable and disable interrupts.
EI 0xFB Enable Interrupts
DI 0xF3 Disable Interrupts

The 8080 CPU has an output on Pin 16 (INTE) that is used to indicate to the rest of the systems hardware that Interrupts are enabled.
This S-100 bus has Pin 28/pINTE which is derived from Pin 16 (INTE) on the 8080.
The "Interrupts Enabled" LED is driven from S-100 PIN 28 (pINTE).
I highly recommend you look at the IMSAI 8080 Manual MPU section to find this in the schematic.

The S-100 Pin 28/pINTE tells other cards in the system that Interrupts are enabled. An example of an interrupt could be from an RS-232 card connected to a terminal. Each time the RS-232 card receives a byte from the terminal (a key is pressed) an interrupt is generated on the S-100 bus Pin 73 (pINT) connected to 8080 Pin 14 (INT). With interrupts enable (EI 0xFB) the 8080 will pause what it's doing and take the interrupt vector to execute code written to manage the character from the terminal. As I recall CPM on the emulator is written to use keyboard polling, CPM checks for a pressed key every so often and isn't setup to use the interrupt method described above.

Enabling (EI 0xFB Enable Interrupts) is benign on the IMSAI as long as nothing generates one, so seeing this LED lit isn't a disaster.

With this explanation let's do a bit of diagnostic work. I haven't tested the code below as I don't have access to my IMSAI.
Write a small assembly program on paper to do four opcodes.
EI 0xFB Enable Interrupts
HLT 0x76 Halt
DI 0xF3 Disable Interrupts
HLT 0x76 Halt

This is a good reference; you should technically use the 8080 Programmers Manual but we'll pretend I handed you a cheat sheet at a user group meeting.
https://www.pastraiser.com/cpu/i8080/i8080_opcodes.html

RESET the IMSAI and enter the 4 instructions from the Front Panel (the CPA).

At the address of the EI instruction run the program from the front panel, the LED should be on.
At the address of the DI instruction run the program from the front panel, the LED should be off.
These should be repeatable and work every time ran.

Run the EI bit of the program.
The LED should light.
Press RESET on the CPA, it should go off.
Make sure this is repeatable.

Please share the results.

Note that I've done a fair amount of BDSC coding under CPM on the IMSAI Emulator and haven't run into the issue you describe.
As I recall some of the functions BDSC provides can enable/disable interrupts, are you using any of these?

I haven't used NZ-COM so I don't know if it can enable interrupts.

Let us know what you find.
-Neil

[sg]

Neil,

Thank you for the great info! I particularly like that 8080 opcode cheat sheet.

I input the sample code via the front panel and it worked as expected with respect to the EI and DI instructions. The Interrupts Enabled light turned on or off when the relevant instruction was executed. The 0x76 HLT instruction, though, seemed to lock everything up at that point and I couldn't Stop/Single-Step past it. I'm not sure what the expected behavior is. So instead of toggling Run at address 0 I used Single-Step to execute address 0 (EI) and then used Examine to load address 3, bypassing the HLT instruction, and used Single-Step again to execute the DI.

I'm not sure what enabled the Interrupts in my general usage of CP/M, NZ-COM, BDS-C, etc. I was just compiling and running some of the example programs. Maybe somewhere in messing with the Z-System configuration stuff and NZCOM triggered it. In any case, it's not a show stopper so I won't worry about it too much but I'll try to pay attention if it gets triggered again and report back.

Thanks again!
-Steve

[nbreeden2]

Hi, the 0x76 instruction is the HALT opcode, it stops the processor. It should act the same as pressing STOP on the front panel.
Let us know what your find as you work through and learn, and most important, have fun!
-Neil