Error for SKY130

[Flians]

When I use lclayout to do P&R for cell AND4, there is an error.

lclayout --output-dir ../Tech.SKY130/test/ --tech ../Tech.SKY130/librecell_tech.py --netlist ../Catalog/AND4.sp --cell AND4 --verbose

2024-03-12 13:00:51        tech_util     INFO: Loading tech file: tools/StdCellLib/Tech.SKY130/librecell_tech.py
Minimum Spacing 270 for pdiff_contact too small because of pdiffusion, minimum should be 390(=270+2*60) Fixing minimum_spacing
Minimum Spacing 270 for ndiff_contact too small because of ndiffusion, minimum should be 390(=270+2*60) Fixing minimum_spacing
Minimum Spacing 390 for pdiff_contact - ndiff_contact too small because of ndiffusion, minimum should be 390(=270+60+60) Fixing minimum_spacing
Minimum Spacing 190 for via1 too small because of metal1, minimum should be 260(=140+2*60) Fixing minimum_spacing
grid_before: [45, 180, 315, 450, 585, 720, 855, 990, 1125, 1260, 1395, 1530, 1665, 1800, 1935, 2070, 2205, 2340, 2475, 2610, 2745, 2880, 3015, 3150, 3285]
grid_after: [0, 425, 450, 585, 720, 855, 990, 1125, 1260, 1395, 1530, 1665, 1800, 1925, 2070, 2205, 2340, 2475, 2610, 2745, 2880, 2905, 3330]
2024-03-12 13:00:51       standalone     INFO: Placement algorithm: MetaTransistorPlacer
2024-03-12 13:00:51       standalone     INFO: Signal routing algorithm: DijkstraRouter
2024-03-12 13:00:51       standalone     INFO: Create layout for cell 'AND4' from 'tools/StdCellLib/Catalog/AND4.sp'.
2024-03-12 13:00:51       standalone     INFO: Load netlist: tools/StdCellLib/Catalog/AND4.sp
2024-03-12 13:00:51         net_util    DEBUG: Loaded cells: 'AND4'
2024-03-12 13:00:51       standalone     INFO: Supply net: VDD
2024-03-12 13:00:51       standalone     INFO: Ground net: GND
2024-03-12 13:00:51       standalone    DEBUG: Rescale transistors.
2024-03-12 13:00:51       standalone    DEBUG: Setup layout.
2024-03-12 13:00:51       standalone     INFO: Find transistor placement
2024-03-12 13:00:51      meta_placer    DEBUG: Estimate placement complexity.
2024-03-12 13:00:51      meta_placer    DEBUG: Number of even-degree graphs (NMOS): 1
2024-03-12 13:00:51      meta_placer    DEBUG: Number of even-degree graphs (PMOS): 1
2024-03-12 13:00:51      meta_placer    DEBUG: Find eulerian tours.
2024-03-12 13:00:51      meta_placer    DEBUG: Estimated placement complexity: 288
2024-03-12 13:00:51      meta_placer     INFO: Placement engine: EulerPlacer
2024-03-12 13:00:51     euler_placer    DEBUG: Find eulerian tours.
2024-03-12 13:00:51     euler_placer    DEBUG: Number of even-degree graphs: 1
2024-03-12 13:00:51     euler_placer    DEBUG: Number of eulertours: 2
2024-03-12 13:00:51     euler_placer    DEBUG: Number of deduplicated eulertours: 2
2024-03-12 13:00:51     euler_placer    DEBUG: Number of even-degree graphs: 1
2024-03-12 13:00:51     euler_placer    DEBUG: Number of eulertours: 144
2024-03-12 13:00:51     euler_placer    DEBUG: Number of deduplicated eulertours: 144
2024-03-12 13:00:51     euler_placer    DEBUG: Number of NMOS placements with cyclic shifts: 2
2024-03-12 13:00:51     euler_placer    DEBUG: Number of PMOS placements with cyclic shifts: 48
2024-03-12 13:00:51       standalone     INFO: Cell placement:

  (VDD, A, Y)    |   (Y, B, VDD)    |   (VDD, C, Y)    |   (Y, D, VDD)    |   (VDD, Y, Z)   
   (Y, A, 1)     |    (1, B, 2)     |    (2, C, 3)     |   (3, D, GND)    |   (GND, Y, Z)   

2024-03-12 13:00:51       standalone    DEBUG: Draw transistors.
2024-03-12 13:00:51       standalone    DEBUG: Draw cell template.
2024-03-12 13:00:51              lvs    DEBUG: Extracting netlist from layout
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net C: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net D: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net Y: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net B: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net A: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net VDD: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net GND: 1
2024-03-12 13:00:51           router    DEBUG: Number of pin shapes of net : 12
2024-03-12 13:00:51    routing_graph    DEBUG: Create routing graph.
2024-03-12 13:00:51    routing_graph  WARNING: No via weight specified from layer 'metal1' to 'pplus'.
2024-03-12 13:00:51    routing_graph  WARNING: No via weight specified from layer 'metal1' to 'nplus'.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `C` of transistor 2.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `D` of transistor 3.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `Y` of transistor 9.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `B` of transistor 6.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `D` of transistor 8.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `B` of transistor 1.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `A` of transistor 0.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `Y` of transistor 4.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `C` of transistor 7.
2024-03-12 13:00:52    routing_graph    DEBUG: No neighbour node for terminal with net `A` of transistor 5.
2024-03-12 13:00:52           router    ERROR: Net 'A' has no routing terminal.
2024-03-12 13:00:52           router    ERROR: Net 'C' has no routing terminal.
2024-03-12 13:00:52           router    ERROR: Net 'D' has no routing terminal.
2024-03-12 13:00:52           router    ERROR: Net 'B' has no routing terminal.
Traceback (most recent call last):
  File "/home/flynn/.local/bin/lclayout", line 8, in <module>
    sys.exit(main())
  File "/home/flynn/.local/lib/python3.10/site-packages/lclayout/standalone.py", line 873, in main
    cell, pin_geometries = layouter.create_cell_layout(cell_name, netlist_path, args.placement_file)
  File "/home/flynn/.local/lib/python3.10/site-packages/lclayout/standalone.py", line 756, in create_cell_layout
    self._06_route()
  File "/home/flynn/.local/lib/python3.10/site-packages/lclayout/standalone.py", line 289, in _06_route
    self._routing_trees = router.route(self.shapes, io_pins=self.io_pins,
  File "/home/flynn/.local/lib/python3.10/site-packages/lclayout/router.py", line 220, in route
    routing_trees = self._06_route(shapes, io_pins, transistor_layouts,
  File "/home/flynn/.local/lib/python3.10/site-packages/lclayout/router.py", line 417, in _06_route
    assert not error, "Nets without terminals. Check the routing graph (--debug-routing-graph)!"
AssertionError: Nets without terminals. Check the routing graph (--debug-routing-graph)!

Could you please help me to check it? Thank you.

[thesourcerer8]

I am getting a different error at the moment:

2024-03-13 21:28:19        tech_util     INFO: Loading tech file: ../StdCellLib/Tech.SKY130/librecell_tech.py
Minimum Spacing 270 for pdiff_contact too small because of pdiffusion, minimum should be 390(=270+2*60) Fixing minimum_spacing
Minimum Spacing 270 for ndiff_contact too small because of ndiffusion, minimum should be 390(=270+2*60) Fixing minimum_spacing
Minimum Spacing 390 for pdiff_contact - ndiff_contact too small because of ndiffusion, minimum should be 390(=270+60+60) Fixing minimum_spacing
Minimum Spacing 190 for via1 too small because of metal1, minimum should be 260(=140+2*60) Fixing minimum_spacing
grid_before: [45, 180, 315, 450, 585, 720, 855, 990, 1125, 1260, 1395, 1530, 1665, 1800, 1935, 2070, 2205, 2340, 2475, 2610, 2745, 2880, 3015, 3150, 3285]
grid_after: [0, 425, 450, 585, 720, 855, 990, 1125, 1260, 1395, 1530, 1665, 1800, 1925, 2070, 2205, 2340, 2475, 2610, 2745, 2880, 2905, 3330]
2024-03-13 21:28:19       standalone     INFO: Placement algorithm: MetaTransistorPlacer
2024-03-13 21:28:19       standalone     INFO: Signal routing algorithm: DijkstraRouter
2024-03-13 21:28:19       standalone     INFO: Create layout for cell 'AND4' from '../StdCellLib/Catalog/AND4.sp'.
2024-03-13 21:28:19       standalone     INFO: Load netlist: ../StdCellLib/Catalog/AND4.sp
2024-03-13 21:28:19         net_util    DEBUG: Loaded cells: 'AND4'
2024-03-13 21:28:19       standalone     INFO: Supply net: VDD
2024-03-13 21:28:19       standalone     INFO: Ground net: GND
2024-03-13 21:28:19       standalone    DEBUG: Rescale transistors.
2024-03-13 21:28:19       standalone     INFO: Initialize placer
2024-03-13 21:28:19      meta_placer    DEBUG: Estimate placement complexity.
2024-03-13 21:28:19       eulertours    DEBUG: Graph is empty.
2024-03-13 21:28:19       standalone    ERROR: failed to create layout: ('Connectivity is undefined ', 'for the null graph.')
Traceback (most recent call last):
  File "/home/philipp/.local/bin/lclayout", line 33, in <module>
    sys.exit(load_entry_point('lclayout', 'console_scripts', 'lclayout')())
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/standalone.py", line 987, in main
    raise e
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/standalone.py", line 967, in main
    cell, pin_geometries, debug_cell = layouter.create_cell_layout(cell_name, netlist_path, args.placement_file)
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/standalone.py", line 804, in create_cell_layout
    self._03_1_init_placer()
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/standalone.py", line 226, in _03_1_init_placer
    placements = self.placer.place(self._transistors_abstract)
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/place/meta_placer.py", line 85, in place
    placer = self.get_placer(transistors)
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/place/meta_placer.py", line 51, in get_placer
    even_degree_graphs_n = eulertours.construct_even_degree_graphs(nmos_graph)
  File "/home/philipp/libresilicon/lclayout-philipp/lclayout/place/eulertours.py", line 39, in construct_even_degree_graphs
    assert nx.is_connected(graph), Exception("G must be a connected graph.")
  File "/home/philipp/.local/lib/python3.10/site-packages/decorator.py", line 232, in fun
    return caller(func, *(extras + args), **kw)
  File "/usr/local/lib/python3.10/dist-packages/networkx/utils/decorators.py", line 78, in _not_implemented_for
    return not_implement_for_func(*args, **kwargs)
  File "/usr/local/lib/python3.10/dist-packages/networkx/algorithms/components/connected.py", line 135, in is_connected
    raise nx.NetworkXPointlessConcept(
networkx.exception.NetworkXPointlessConcept: ('Connectivity is undefined ', 'for the null graph.')`

[thesourcerer8]

Just to give you some ideas, these are the parameters I am usually using to call lclayout:
lclayout --output-dir outputlib --tech ../Tech/librecell_tech.py --netlist $cellname.sp --cell $cellname -v $placer --placement-file $cellname.place --ignore-lvs --debug-routing-graph --route-max-iter 100

[Flians]

test.zip
I used the attached files, and lclayout can work normally. However, the generated cell layout's area (11.52 * 3.33 = 38.3616) is larger than the data (10.0096) from SKY130. Is it correct?