Merge pull request #635 from smarsching/xc7k325tfbg900

trabucayre · web-flow · commit cde80a5a8576 · 2026-03-04T07:51:45.000+01:00
Add SPI over JTAG bitfile for XC7K325TFBG900
diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile
@@ -7,7 +7,7 @@ XILINX_PARTS := xc3s500evq100 \
 	xc7s6 xc7s15 xc7s25 xc7s50 xc7s75 xc7s100 \
 	xc7k70tfbg484 xc7k70tfbg676 \
 	xc7k160tffg676 \
-	xc7k325tffg676 xc7k325tffg900 \
+	xc7k325tfbg900 xc7k325tffg676 xc7k325tffg900 \
 	xc7k420tffg901 \
 	xcku3p-ffva676 \
 	xc7vx330tffg1157 \
diff --git a/spiOverJtag/constr_xc7k_fbg900.ucf b/spiOverJtag/constr_xc7k_fbg900.ucf
@@ -0,0 +1,6 @@
+NET "csn"       LOC = U19 | IOSTANDARD = LVCMOS33;
+NET "sdi_dq0"   LOC = P24 | IOSTANDARD = LVCMOS33;
+NET "sdo_dq1"   LOC = R25 | IOSTANDARD = LVCMOS33;
+NET "wpn_dq2"   LOC = R20 | IOSTANDARD = LVCMOS33;
+NET "hldn_dq3"  LOC = R21 | IOSTANDARD = LVCMOS33;
+
diff --git a/spiOverJtag/constr_xc7k_fbg900.xdc b/spiOverJtag/constr_xc7k_fbg900.xdc
@@ -0,0 +1,12 @@
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design]
+
+set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVTTL} [get_ports {csn}]
+set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVTTL} [get_ports {sdi_dq0}]
+set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVTTL} [get_ports {sdo_dq1}]
+set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVTTL} [get_ports {wpn_dq2}]
+set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVTTL} [get_ports {hldn_dq3}]
+
diff --git a/spiOverJtag/spiOverJtag_xc7k325tfbg900.bit.gz b/spiOverJtag/spiOverJtag_xc7k325tfbg900.bit.gz
