diff --git a/seal5/backends/llvmir/writer.py b/seal5/backends/llvmir/writer.py index 6e539273..4aff2903 100644 --- a/seal5/backends/llvmir/writer.py +++ b/seal5/backends/llvmir/writer.py @@ -75,6 +75,8 @@ def main(): assert out_path.is_dir(), "Expecting output directory when using --splitted" for set_name, set_def in model_obj.sets.items(): + if len(set_def.instructions) == 0: + continue xlen = set_def.xlen metrics["n_sets"] += 1 ext_settings = set_def.settings diff --git a/seal5/backends/patterngen/writer.py b/seal5/backends/patterngen/writer.py index f68b97d4..844e5437 100644 --- a/seal5/backends/patterngen/writer.py +++ b/seal5/backends/patterngen/writer.py @@ -83,6 +83,8 @@ def main(): assert out_path.is_dir(), "Expecting output directory when using --splitted" for set_name, set_def in model_obj.sets.items(): + if len(set_def.instructions) == 0: + continue xlen = set_def.xlen artifacts[set_name] = [] metrics["n_sets"] += 1 diff --git a/seal5/backends/report/properties/writer.py b/seal5/backends/report/properties/writer.py index f8d3e599..3ca8c323 100644 --- a/seal5/backends/report/properties/writer.py +++ b/seal5/backends/report/properties/writer.py @@ -52,6 +52,8 @@ def main(): # print("model", model) for set_name, set_def in model_obj.sets.items(): # print("set_name", set_name) + if len(set_def.instructions) == 0: + continue xlen = set_def.xlen model = top_level.stem @@ -104,7 +106,7 @@ def detect_opcode(instr_def): # TODO: move to transform and store as attr # "48bit2": 0b10111, "BRANCH": 0b11000, "JALR": 0b11001, - # "reserved": 0b11010, + "reserved": 0b11010, "JAL": 0b11011, "SYSTEM": 0b11100, "OP-P": 0b11101, diff --git a/seal5/backends/report/status/writer.py b/seal5/backends/report/status/writer.py index 3950773b..d5bf24df 100644 --- a/seal5/backends/report/status/writer.py +++ b/seal5/backends/report/status/writer.py @@ -143,6 +143,8 @@ def get_status(filtered_metrics, instr_name, invert: bool = False): model_obj = load_model(top_level, compat=args.compat) for set_name, set_def in model_obj.sets.items(): + if len(set_def.instructions) == 0: + continue xlen = set_def.xlen model = top_level.stem filtered_metrics = process_metrics(settings, model=model) diff --git a/seal5/backends/report/test_results/writer.py b/seal5/backends/report/test_results/writer.py index 107ca2f9..dca65af8 100644 --- a/seal5/backends/report/test_results/writer.py +++ b/seal5/backends/report/test_results/writer.py @@ -196,6 +196,8 @@ def filter_tests_by_set(tests, set_def, settings, model_name): model_obj = load_model(top_level, compat=args.compat) for set_name, set_def in model_obj.sets.items(): + if len(set_def.instructions) == 0: + continue xlen = set_def.xlen model_name = top_level.stem diff --git a/seal5/backends/riscv_features/templates/riscv_features_experimental_new.mako b/seal5/backends/riscv_features/templates/riscv_features_experimental_new.mako index 083610bb..6c0e0dff 100644 --- a/seal5/backends/riscv_features/templates/riscv_features_experimental_new.mako +++ b/seal5/backends/riscv_features/templates/riscv_features_experimental_new.mako @@ -1,2 +1,2 @@ -def Feature${predicate} : RISCVExperimentalExtension<"${arch}", ${major}, ${minor}, "'${feature}' (${description})">; +def Feature${predicate} : RISCVExperimentalExtension<"${arch}", ${major}, ${minor}, "'${feature}' (${description})", ${implies}>; def Has${predicate} : Predicate<"Subtarget->has${predicate}()">, AssemblerPredicate<(any_of Feature${predicate}), "'${feature}' (${description})">; diff --git a/seal5/backends/riscv_features/templates/riscv_features_new.mako b/seal5/backends/riscv_features/templates/riscv_features_new.mako index 079a7c14..88498c79 100644 --- a/seal5/backends/riscv_features/templates/riscv_features_new.mako +++ b/seal5/backends/riscv_features/templates/riscv_features_new.mako @@ -1,2 +1,2 @@ -def Feature${predicate} : RISCVExtension<"${arch}", ${major}, ${minor}, "'${feature}' (${description})">; +def Feature${predicate} : RISCVExtension<"${arch}", ${major}, ${minor}, "'${feature}' (${description})", ${implies}>; def Has${predicate} : Predicate<"Subtarget->has${predicate}()">, AssemblerPredicate<(any_of Feature${predicate}), "'${feature}' (${description})">; diff --git a/seal5/backends/riscv_features/writer.py b/seal5/backends/riscv_features/writer.py index 35d5258a..b09e40e1 100644 --- a/seal5/backends/riscv_features/writer.py +++ b/seal5/backends/riscv_features/writer.py @@ -26,9 +26,10 @@ logger = logging.getLogger("riscv_features") -def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_settings: LLVMSettings): +def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_settings: LLVMSettings, all_sets): """Generate features string for LLVM patch.""" - requires = ext_settings.requires + # requires = ext_settings.requires + implies = ext_settings.requires feature = ext_settings.get_feature(name=name) arch_ = ext_settings.get_arch(name=name) description = ext_settings.get_description(name=name) @@ -37,8 +38,15 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_set experimental = ext_settings.experimental vendor = ext_settings.vendor - if requires: - raise NotImplementedError + implied_features = set() + if implies: + for implied in implies: + assert implied in all_sets + implied_set_def = all_sets[implied] + implied_ext_settings = implied_set_def.settings + implied_feature = implied_ext_settings.get_feature(name=implied) + # implied_features.add(f"Feature{implied_feature}") + implied_features.add(f"FeatureExt{implied_feature}") # TODO: check missing Ext? legacy = True slim = False @@ -70,7 +78,13 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_set assert feature.lower() == arch_, "LLVM 20 requires matching arch and feature names" assert predicate == (f"Vendor{feature}" if vendor else f"StdExt{feature}") content_text = content_template.render( - predicate=predicate, feature=feature, arch=arch_, description=description, major=major, minor=minor + predicate=predicate, + feature=feature, + arch=arch_, + description=description, + major=major, + minor=minor, + implies="[" + ", ".join(implied_features) + "]", ) return content_text + "\n" @@ -130,7 +144,7 @@ def main(): continue metrics["n_success"] += 1 metrics["success_sets"].append(set_name) - content += gen_riscv_features_str(set_name, ext_settings, llvm_settings) + content += gen_riscv_features_str(set_name, ext_settings, llvm_settings, model["sets"]) content = content.rstrip() if len(content) > 0: with open(out_path, "w", encoding="utf-8") as f: diff --git a/seal5/backends/riscv_instr_info/writer.py b/seal5/backends/riscv_instr_info/writer.py index 85df33f3..12f946c5 100644 --- a/seal5/backends/riscv_instr_info/writer.py +++ b/seal5/backends/riscv_instr_info/writer.py @@ -292,6 +292,8 @@ def main(): content = "" # errs = [] for set_name, set_def in model_obj.sets.items(): + if len(set_def.instructions) == 0: + continue metrics["n_sets"] += 1 set_name_lower = set_name.lower() artifacts[set_name] = [] diff --git a/seal5/backends/yaml/writer.py b/seal5/backends/yaml/writer.py index dc091b70..e3175a23 100644 --- a/seal5/backends/yaml/writer.py +++ b/seal5/backends/yaml/writer.py @@ -59,15 +59,23 @@ def main(): data = {"extensions": {}} for set_name, set_def in model_obj.sets.items(): # print("set", set_def) + is_group_set = False + if len(set_def.instructions) == 0: + assert len(set_def.extension) > 0 + is_group_set = True set_data = {"instructions": []} riscv_data = {} - riscv_data["xlen"] = set_def.xlen - set_data["riscv"] = riscv_data - llvm_imm_types = set() - for instr in set_def.instructions.values(): - set_data["instructions"].append(instr.name) - llvm_imm_types.update(instr.llvm_imm_types) - set_data["required_imm_types"] = list(llvm_imm_types) + if is_group_set: + # set_data["implies"] = set_def.extension + set_data["requires"] = set_def.extension + else: + riscv_data["xlen"] = set_def.xlen + set_data["riscv"] = riscv_data + llvm_imm_types = set() + for instr in set_def.instructions.values(): + set_data["instructions"].append(instr.name) + llvm_imm_types.update(instr.llvm_imm_types) + set_data["required_imm_types"] = list(llvm_imm_types) data["extensions"][set_name] = set_data data = {"models": {model_name: data}} with open(out_path, "w", encoding="utf-8") as f: diff --git a/seal5/frontends/coredsl2_seal5/architecture_model_builder.py b/seal5/frontends/coredsl2_seal5/architecture_model_builder.py index e651300a..bdbcddce 100644 --- a/seal5/frontends/coredsl2_seal5/architecture_model_builder.py +++ b/seal5/frontends/coredsl2_seal5/architecture_model_builder.py @@ -111,7 +111,7 @@ def visitInstruction_set(self, ctx: CoreDSL2Parser.Instruction_setContext): raise M2ValueError("unexpected item encountered") # instantiate M2-ISA-R object - i = arch.InstructionSet(name, extension, constants, memories, functions, instructions) + i = arch.InstructionSet(name, extension, constants, memories, functions, instructions, {}) if name in self._instruction_sets: raise M2DuplicateError(f'instruction set "{name}" already defined') @@ -184,6 +184,8 @@ def visitInstruction(self, ctx: CoreDSL2Parser.InstructionContext): assembly = ctx.assembly.text.replace('"', "") if ctx.assembly is not None else None mnemonic = ctx.mnemonic.text.replace('"', "") if ctx.mnemonic is not None else None + # TODO: add parsing of operands + # i = arch.Instruction(ctx.name.text, attributes, {}, encoding, mnemonic, assembly, ctx.behavior, None) i = arch.Instruction(ctx.name.text, attributes, encoding, mnemonic, assembly, ctx.behavior, None) self._instr_classes.add(i.size) diff --git a/seal5/model.py b/seal5/model.py index ddf80988..737586a3 100644 --- a/seal5/model.py +++ b/seal5/model.py @@ -43,13 +43,14 @@ def __init__( memories: "dict[str, Memory]", functions: "dict[str, Function]", instructions: "dict[tuple[int, int], Instruction]", + unencoded_instructions: "dict[str, Instruction]", intrinsics: "dict[str, Seal5Intrinsic]", constraints: "dict[str, Seal5Constraint]", aliases: "dict[str, Seal5Alias]", registers: "dict[str, Seal5Register]", register_groups: "dict[str, Seal5RegisterGroup]", ): - super().__init__(name, extension, constants, memories, functions, instructions) + super().__init__(name, extension, constants, memories, functions, instructions, unencoded_instructions) self.intrinsics = intrinsics self.constraints = constraints @@ -312,6 +313,10 @@ def __init__( operands: "dict[str, Seal5Operand]", ): del operands # TODO: use + function_info = None + # TODO: use user-defined operands + # operands_ = {} # TODO + # super().__init__(name, attributes, operands_, encoding, mnemonic, assembly, operation, function_info) super().__init__(name, attributes, encoding, mnemonic, assembly, operation, function_info) self.constraints = constraints self.operands = {} diff --git a/seal5/pass_list.py b/seal5/pass_list.py index 201241f3..e4379775 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -1612,6 +1612,8 @@ def convert_llvmir_to_gmir( if insn_names is None: logger.warning("Skipping empty set %s", set_name) continue + if len(insn_names) == 0 and len(ext_settings.requires) > 0: + continue assert len(insn_names) > 0, f"No instructions found in set: {set_name}" # TODO: populate model in yaml backend! for insn_name in insn_names: diff --git a/seal5/resources/patches/llvm/insert_markers_llvm18.patch b/seal5/resources/patches/llvm/insert_markers_llvm18.patch index de887f86..0e0c2a15 100644 --- a/seal5/resources/patches/llvm/insert_markers_llvm18.patch +++ b/seal5/resources/patches/llvm/insert_markers_llvm18.patch @@ -1,41 +1,3 @@ -diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def ---- a/clang/include/clang/Basic/BuiltinsRISCV.def -+++ b/clang/include/clang/Basic/BuiltinsRISCV.def -@@ -89,5 +89,8 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh") - TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl") - TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl") - -+// BuiltinsRISCV.def - builtins_riscv - INSERTION_START -+// BuiltinsRISCV.def - builtins_riscv - INSERTION_END -+ - #undef BUILTIN - #undef TARGET_BUILTIN -diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp ---- a/clang/lib/CodeGen/CGBuiltin.cpp -+++ b/clang/lib/CodeGen/CGBuiltin.cpp -@@ -21243,6 +21243,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, - ID = Intrinsic::riscv_sha256sum1; - break; - -+// CGBuiltin.cpp - cg_builtin - INSERTION_START -+// CGBuiltin.cpp - cg_builtin - INSERTION_END -+ - // Zksed - case RISCV::BI__builtin_riscv_sm4ks: - ID = Intrinsic::riscv_sm4ks; -diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td ---- a/llvm/include/llvm/IR/IntrinsicsRISCV.td -+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td -@@ -1882,6 +1882,9 @@ let TargetPrefix = "riscv" in { - // Zvksh - def int_riscv_vsm3c : RISCVBinaryAAXUnMaskedZvk; - def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; -+ -+// IntrinsicsRISCV.td - intrinsics_riscv - INSERTION_START -+// IntrinsicsRISCV.td - intrinsics_riscv - INSERTION_END - } // TargetPrefix = "riscv" - - // Vendor extensions diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h diff --git a/seal5/resources/patches/llvm/insert_markers_llvm18_future.patch b/seal5/resources/patches/llvm/insert_markers_llvm18_future.patch new file mode 100644 index 00000000..23757ff8 --- /dev/null +++ b/seal5/resources/patches/llvm/insert_markers_llvm18_future.patch @@ -0,0 +1,152 @@ +diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h +--- a/llvm/include/llvm/InitializePasses.h ++++ b/llvm/include/llvm/InitializePasses.h +@@ -315,6 +315,8 @@ void initializeWinEHPreparePass(PassRegistry&); + void initializeWriteBitcodePassPass(PassRegistry&); + void initializeXRayInstrumentationPass(PassRegistry&); + void initializeCDFGPassPass(PassRegistry&); ++// InitializePasses.h - initialize_passes_decl - INSERTION_START ++// InitializePasses.h - initialize_passes_decl - INSERTION_END + + } // end namespace llvm + +diff --git a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt +--- a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt ++++ b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt +@@ -26,6 +26,8 @@ add_llvm_component_library(LLVMGlobalISel + RegBankSelect.cpp + Utils.cpp + CDFGPass.cpp ++ # CMakeLists.txt - gisel_cmake_srcs - INSERTION_START ++ # CMakeLists.txt - gisel_cmake_srcs - INSERTION_END + + ADDITIONAL_HEADER_DIRS + ${LLVM_MAIN_INCLUDE_DIR}/llvm/CodeGen/GlobalISel +diff --git a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp +--- a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp ++++ b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp +@@ -22,4 +22,6 @@ void llvm::initializeGlobalISel(PassRegistry &Registry) { + initializeRegBankSelectPass(Registry); + initializeInstructionSelectPass(Registry); + initializeCDFGPassPass(Registry); ++ // GlobalISel.cpp - gisel_init - INSERTION_START ++ // GlobalISel.cpp - gisel_init - INSERTION_END + } +diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ++++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +@@ -704,6 +704,8 @@ public: + bool isUImm7() const { return IsUImm<7>(); } + bool isUImm8() const { return IsUImm<8>(); } + bool isUImm20() const { return IsUImm<20>(); } ++ // RISCVAsmParser.cpp - riscv_operands - INSERTION_START ++ // RISCVAsmParser.cpp - riscv_operands - INSERTION_END + + bool isUImm8GE32() const { + int64_t Imm; +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +@@ -119,6 +119,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) + nxv32s16, nxv1s32, nxv2s32, nxv4s32, nxv8s32, nxv16s32, + nxv1s64, nxv2s64, nxv4s64, nxv8s64}; + ++// RISCVLegalizerInfo.cpp - riscv_legalizer_info - INSERTION_START ++// RISCVLegalizerInfo.cpp - riscv_legalizer_info - INSERTION_END ++ + getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR}) + .legalFor({s32, sXLen}) + .legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST)) +diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h ++++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +@@ -293,6 +293,8 @@ enum OperandType : unsigned { + OPERAND_CLUI_IMM, + OPERAND_VTYPEI10, + OPERAND_VTYPEI11, ++ // RISCVBaseInfo.h - riscv_operands - INSERTION_START ++ // RISCVBaseInfo.h - riscv_operands - INSERTION_END + OPERAND_RVKRNUM, + OPERAND_RVKRNUM_0_7, + OPERAND_RVKRNUM_1_10, +diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td +--- a/llvm/lib/Target/RISCV/RISCV.td ++++ b/llvm/lib/Target/RISCV/RISCV.td +@@ -82,3 +82,6 @@ def RISCV : Target { + let AssemblyWriters = [RISCVAsmWriter]; + let AllowRegisterRenaming = 1; + } ++ ++// RISCV.td - riscv_td_includes - INSERTION_START ++// RISCV.td - riscv_td_includes - INSERTION_END +diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td +--- a/llvm/lib/Target/RISCV/RISCVFeatures.td ++++ b/llvm/lib/Target/RISCV/RISCVFeatures.td +@@ -947,6 +947,9 @@ def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, + AssemblerPredicate<(all_of FeatureStdExtSvinval), + "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; + ++// RISCVFeatures.td - riscv_features - INSERTION_START ++// RISCVFeatures.td - riscv_features - INSERTION_END ++ + def FeatureStdExtSvnapot + : RISCVExtension<"svnapot", 1, 0, + "'Svnapot' (NAPOT Translation Contiguity)">; +diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp ++++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +@@ -662,6 +662,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, + + setBooleanContents(ZeroOrOneBooleanContent); + ++// RISCVISelLowering.cpp - legal_ops - INSERTION_START ++// RISCVISelLowering.cpp - legal_ops - INSERTION_END ++ + if (getTargetMachine().getTargetTriple().isOSLinux()) { + // Custom lowering of llvm.clear_cache. + setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Custom); +diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +@@ -313,6 +313,9 @@ def simm21_lsb0_jal : Operand { + let OperandType = "OPERAND_PCREL"; + } + ++// RISCVInstrInfo.td - field_types - INSERTION_START ++// RISCVInstrInfo.td - field_types - INSERTION_END ++ + def BareSymbol : AsmOperandClass { + let Name = "BareSymbol"; + let RenderMethod = "addImmOperands"; +@@ -398,6 +401,8 @@ def uimm6gt32 : ImmLeaf; + def AddrRegImm : ComplexPattern; ++// RISCVInstrInfo.td - complex_patterns - INSERTION_START ++// RISCVInstrInfo.td - complex_patterns - INSERTION_END + + // Return the negation of an immediate value. + def NegImm : SDNodeXForm; + def FRM : RISCVReg<0, "frm">; + ++// RISCVRegisterInfo.td - riscv_register_info - INSERTION_START ++// RISCVRegisterInfo.td - riscv_register_info - INSERTION_END ++ + // Shadow Stack register + def SSP : RISCVReg<0, "ssp">; + diff --git a/seal5/settings.py b/seal5/settings.py index 762f6667..be2fec51 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -539,6 +539,7 @@ class ExtensionsSettings(YAMLSettings): vendor: Optional[bool] = None description: Optional[str] = None requires: Optional[List[str]] = None + # implies: Optional[List[str]] = None instructions: Optional[List[str]] = None riscv: Optional[RISCVSettings] = None passes: Optional[PassesSettings] = None diff --git a/seal5/transform/converter.py b/seal5/transform/converter.py index 848463e4..994cfffa 100644 --- a/seal5/transform/converter.py +++ b/seal5/transform/converter.py @@ -102,6 +102,7 @@ def run(args): {}, {}, {}, + {}, ) new_model_obj = seal5_model.Seal5Model(seal5_model.SEAL5_METAMODEL_VERSION, {}, sets, CodeInfoBase.database) diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index cd21a929..89d5a2aa 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -48,7 +48,7 @@ # "48bit2": 0b10111, "BRANCH": 0b11000, "JALR": 0b11001, - # "reserved": 0b11010, + "reserved": 0b11010, "JAL": 0b11011, "SYSTEM": 0b11100, "OP-P": 0b11101, @@ -228,10 +228,16 @@ def check_encoding_filter(name, enc, keep, drop, keep2, drop2): ) } # for instr_name, instr_def in set_def.instructions.items(): + for set_name, set_def in model_obj.sets.items(): + set_def.extension = [ + extension for extension in set_def.extension if len(model_obj.sets[extension].instructions) > 0 + ] # Remove sets without instructions model_obj.sets = { - set_name: set_def for set_name, set_def in model_obj.sets.items() if len(set_def.instructions) > 0 + set_name: set_def + for set_name, set_def in model_obj.sets.items() + if len(set_def.instructions) > 0 or len(set_def.extension) > 0 } dump_model(model_obj, out_path, compat=args.compat) diff --git a/seal5/transform/process_settings/transform.py b/seal5/transform/process_settings/transform.py index 49e9d521..1b1420db 100644 --- a/seal5/transform/process_settings/transform.py +++ b/seal5/transform/process_settings/transform.py @@ -53,16 +53,21 @@ def run(args): for set_name, set_def in model_obj.sets.items(): model_settings = settings.models.get(model_name) + is_group_set = False + if len(set_def.instructions) == 0: + assert len(set_def.extension) > 0 + is_group_set = True ext_settings = None if model_settings is not None: ext_settings = model_settings.extensions.get(set_name, None) if ext_settings is None: ext_settings = ExtensionsSettings(feature=set_name.replace("_", "")) - riscv_settings = ext_settings.riscv - if riscv_settings is None: - riscv_settings = RISCVSettings(xlen=set_def.xlen) - if riscv_settings.xlen is None: - riscv_settings.xlen = set_def.xlen + if not is_group_set: + riscv_settings = ext_settings.riscv + if riscv_settings is None: + riscv_settings = RISCVSettings(xlen=set_def.xlen) + if riscv_settings.xlen is None: + riscv_settings.xlen = set_def.xlen if set_def.settings is None: set_def.settings = ext_settings # TODO: decide how to do this properly else: