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yangbolu1991yangbolu1991
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mcux-sdk-ng: update netc driver to the latest
Updated netc driver to the latest SDK commit. 5309b12e [MCUX-80906] drivers: netc: enable ring0 for EP supporting tag Signed-off-by: Yangbo Lu <[email protected]>
1 parent 7a52cbb commit 0e2edee

27 files changed

+2512
-1226
lines changed

‎mcux/mcux-sdk-ng/drivers/netc/CMakeLists.txt‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ if(CONFIG_MCUX_COMPONENT_driver.netc_imx943)
3030
endif()
3131

3232
if(CONFIG_MCUX_COMPONENT_driver.netc)
33-
mcux_component_version(2.8.1)
33+
mcux_component_version(2.9.0)
3434

3535
mcux_add_source(
3636
SOURCES
@@ -63,6 +63,7 @@ if(CONFIG_MCUX_COMPONENT_driver.netc_switch)
6363
mcux_add_source(
6464
SOURCES
6565
fsl_netc_switch.h
66+
fsl_netc_tag.h
6667
fsl_netc_switch.c
6768
)
6869

‎mcux/mcux-sdk-ng/drivers/netc/fsl_netc.h‎

Lines changed: 263 additions & 196 deletions
Large diffs are not rendered by default.

‎mcux/mcux-sdk-ng/drivers/netc/fsl_netc_endpoint.c‎

Lines changed: 71 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2021-2024 NXP
2+
* Copyright 2021-2025 NXP
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -15,8 +15,8 @@
1515

1616
/*! @name Defines some Ethernet parameters. */
1717
/*@{*/
18-
#define NETC_ENETC_TXFRAME_LEN_MAX (9600U) /*!< The Maximum length of frame length. */
19-
#define NETC_ENETC_TXFRAME_LEN_MIN (16U) /*!< The Minimum length of frame length. */
18+
#define NETC_ENETC_TXFRAME_LEN_MAX (9600U) /*!< The Maximum length of frame length. */
19+
#define NETC_ENETC_TXFRAME_LEN_MIN (16U) /*!< The Minimum length of frame length. */
2020
/*@}*/
2121

2222
/*! @brief Mask the cache management code if cache control is disabled. */
@@ -188,12 +188,14 @@ static status_t EP_DescriptorInit(ep_handle_t *handle, const ep_config_t *config
188188
uint8_t idxStart = 0U;
189189
uint8_t ring;
190190

191+
#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG)
191192
/* Setup Tx/Rx buffer descriptor rings. */
192193
if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U))
193194
{
194195
/* For management ENETC, the SI 0 hardware Tx ring index 0 has been keep for direct switch enqueue feature */
195196
idxStart = 1;
196197
}
198+
#endif
197199
for (ring = 0; ring < config->siConfig.txRingUse; ring++)
198200
{
199201
if (NETC_SIConfigTxBDR(handle->hw.si, ring + idxStart, &bdrConfig->txBdrConfig[ring]) != kStatus_Success)
@@ -332,8 +334,9 @@ static status_t EP_MSIXSetEntryTable(ep_handle_t *handle, const ep_config_t *con
332334
return result;
333335
}
334336

335-
msixNum = (uint8_t)(
336-
((handle->hw.si->SIPCAPR1 & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK) >> ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT) + 1U);
337+
msixNum =
338+
(uint8_t)(((handle->hw.si->SIPCAPR1 & ENETC_SI_SIPCAPR1_NUM_MSIX_MASK) >> ENETC_SI_SIPCAPR1_NUM_MSIX_SHIFT) +
339+
1U);
337340

338341
/* Entry > 0, enable MSIX. */
339342
if (config->entryNum != 0U)
@@ -423,27 +426,28 @@ status_t EP_GetDefaultConfig(ep_config_t *config)
423426
#if (defined(FSL_FEATURE_NETC_HAS_PORT_FCSEA) && FSL_FEATURE_NETC_HAS_PORT_FCSEA)
424427
config->port.common.stompFcs = true;
425428
#endif
426-
config->port.common.rxPpduBco = 20U;
427-
config->port.common.txPpduBco = 20U;
428-
config->port.common.timeGate.holdSkew = 64;
429-
config->port.common.parser.l2PloadCount = 24;
430-
config->port.common.parser.l3PayloadCount = 24;
431-
config->port.common.parser.enableL3Parser = true;
432-
config->port.common.parser.l4PayloadCount = 24;
433-
config->port.common.parser.enableL4Parser = true;
434-
config->port.ethMac.enableRevMii = false;
435-
config->port.ethMac.preemptMode = kNETC_PreemptDisable;
436-
config->port.ethMac.enMergeVerify = false;
437-
config->port.ethMac.mergeVerifyTime = 10U;
438-
config->port.ethMac.txTsSelect = kNETC_SyncTime;
439-
config->port.ethMac.enTxPad = true;
440-
config->port.ethMac.rxMinFrameSize = 64U;
441-
config->port.ethMac.rxMaxFrameSize = 0x600U;
442-
config->port.ethMac.maxBackPressOn = 3036U;
443-
config->port.ethMac.minBackPressOff = 20U;
444-
config->port.enPseudoMacTxPad = true;
445-
config->psfpCfg.isiPortConfig.defaultISEID = 0xFFFFU;
446-
config->siConfig.ringPerBdrGroup = 0x1U;
429+
config->port.common.rxPpduBco = 20U;
430+
config->port.common.txPpduBco = 20U;
431+
config->port.common.timeGate.holdSkew = 64;
432+
config->port.common.parser.l2PloadCount = 24;
433+
config->port.common.parser.l3PayloadCount = 24;
434+
config->port.common.parser.enableL3Parser = true;
435+
config->port.common.parser.l4PayloadCount = 24;
436+
config->port.common.parser.enableL4Parser = true;
437+
config->port.ethMac.enableRevMii = false;
438+
config->port.ethMac.txTsSelect = kNETC_SyncTime;
439+
config->port.ethMac.enTxPad = true;
440+
config->port.ethMac.rxMinFrameSize = 64U;
441+
config->port.ethMac.rxMaxFrameSize = 0x600U;
442+
config->port.ethMac.maxBackPressOn = 3036U;
443+
config->port.ethMac.minBackPressOff = 20U;
444+
config->port.ethMac.PreemptionConfig.preemptMode = kNETC_PreemptDisable;
445+
config->port.ethMac.PreemptionConfig.enMergeVerify = false;
446+
config->port.ethMac.PreemptionConfig.mergeVerifyTime = 10U;
447+
config->port.ethMac.PreemptionConfig.raf_size = kNETC_RafSize64;
448+
config->port.enPseudoMacTxPad = true;
449+
config->psfpCfg.isiPortConfig.defaultISEID = 0xFFFFU;
450+
config->siConfig.ringPerBdrGroup = 0x1U;
447451
for (uint8_t i = 0U; i < 8U; i++)
448452
{
449453
config->txTcCfg[i].enTcGate = true;
@@ -668,9 +672,9 @@ status_t EP_Init(ep_handle_t *handle, uint8_t *macAddr, const ep_config_t *confi
668672
return result;
669673
}
670674

671-
if (siNum == 0U)
675+
if (siNum == 0U && config->preinitVsi != NULL)
672676
{
673-
result = NETC_SocPreInitVsi(&handle->hw, config->si);
677+
result = config->preinitVsi(&handle->hw, config->si);
674678
}
675679
return result;
676680
}
@@ -718,9 +722,10 @@ status_t EP_Down(ep_handle_t *handle)
718722
NETC_EnetcEnableSI(handle->hw.base, getSiNum(handle->cfg.si), false);
719723
NETC_SIEnable(handle->hw.si, false);
720724
#if defined(FSL_FEATURE_NETC_HAS_ERRATA_051936) && FSL_FEATURE_NETC_HAS_ERRATA_051936
721-
/* ERRATA051936: MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. In some cases, the transmitter
722-
may become inoperable and not be able to recover from FLR requiring a full reset instead. The issue can occur when FLR is triggered around
723-
the time MAC Tx has started backing off due to a half duplex collision detection. */
725+
/* ERRATA051936: MAC Tx FIFO status may not report empty after FLR when operating in RGMII half duplex mode. In some
726+
cases, the transmitter may become inoperable and not be able to recover from FLR requiring a full reset instead.
727+
The issue can occur when FLR is triggered around the time MAC Tx has started backing off due to a half duplex
728+
collision detection. */
724729
handle->hw.portGroup.eth->PM0_IF_MODE &= ~NETC_ETH_LINK_PM0_IF_MODE_HD_MASK;
725730
handle->hw.portGroup.eth->PM1_IF_MODE &= ~NETC_ETH_LINK_PM0_IF_MODE_HD_MASK;
726731
#endif
@@ -759,12 +764,12 @@ status_t EP_SendFrameCommon(ep_handle_t *handle,
759764
status_t result = kStatus_Success;
760765
netc_buffer_struct_t *txBuff = frame->buffArray;
761766
uint32_t totBdNum = frame->length;
762-
uint16_t frameLen = 0;
767+
uint32_t frameLen = 0;
763768
bool isExtEnable = (bool)txDesc[0].standard.isExtended;
764-
uint32_t address;
765769
netc_tx_bd_t *txDesTemp = NULL;
770+
uint32_t address;
766771

767-
/* Check the frame length. */
772+
/* The first descriptor in a chain must not have a BUFF_LEN that is less than 16 bytes. */
768773
if ((frame->buffArray[0].length < NETC_ENETC_TXFRAME_LEN_MIN) || (frame->length == 0U))
769774
{
770775
result = kStatus_NETC_TxFrameOverLen;
@@ -787,7 +792,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle,
787792
}
788793

789794
/* Check the frame total length. */
790-
if ((frameLen > NETC_ENETC_TXFRAME_LEN_MAX) || (frameLen < NETC_ENETC_TXFRAME_LEN_MIN))
795+
if (frameLen > NETC_ENETC_TXFRAME_LEN_MAX)
791796
{
792797
result = kStatus_NETC_TxFrameOverLen;
793798
}
@@ -825,6 +830,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle,
825830
{
826831
/* Update latest Tx dirty frame info. */
827832
txBdRing->dirtyBase[txBdRing->producerIndex].context = context;
833+
#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG)
828834
if (0U != (txDesc[0].standard.flags & NETC_SI_TXDESCRIP_RD_TSR_MASK))
829835
{
830836
txBdRing->dirtyBase[txBdRing->producerIndex].isTxTsIdAvail = true;
@@ -833,6 +839,7 @@ status_t EP_SendFrameCommon(ep_handle_t *handle,
833839
{
834840
txBdRing->dirtyBase[txBdRing->producerIndex].isTxTsIdAvail = false;
835841
}
842+
#endif
836843

837844
if (isExtEnable && (0U != (txDesc[1].ext.eFlags & (uint32_t)kNETC_TxExtTwoStepTs)))
838845
{
@@ -843,10 +850,15 @@ status_t EP_SendFrameCommon(ep_handle_t *handle,
843850
txBdRing->dirtyBase[txBdRing->producerIndex].isTsAvail = false;
844851
}
845852
/* Copy user Tx descriptors to hardware Tx BD. */
846-
txDesTemp->standard.flags = txDesc[0].standard.flags;
847-
txDesTemp->standard.addr = address;
848-
txDesTemp->standard.bufLen = txBuff->length;
849-
txDesTemp->standard.frameLen = frameLen;
853+
txDesTemp->standard.flags = txDesc[0].standard.flags;
854+
txDesTemp->standard.addr = address;
855+
txDesTemp->standard.bufLen = txBuff->length;
856+
#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG
857+
txDesc[1].ext.frameLenExt = (frameLen >> 16U) & 0x7U;
858+
txDesTemp->standard.frameLen = frameLen & 0xFFFFU;
859+
#else
860+
txDesTemp->standard.frameLen = frameLen;
861+
#endif
850862
txDesTemp->standard.isExtended = (uint32_t)isExtEnable;
851863
txDesTemp->standard.enableInterrupt =
852864
(uint32_t)((handle->hw.si->BDR[hwRing].TBIER & ENETC_SI_TBIER_TXFIE_MASK) != 0U);
@@ -897,12 +909,15 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr
897909
/* Tx BD ring index is out of range */
898910
return kStatus_InvalidArgument;
899911
}
912+
913+
#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG)
900914
if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U))
901915
{
902916
/* Switch management ENETC Tx BD hardware ring 0 can't be used to send regular frame, so the index need increase
903917
* 1 */
904918
hwRing = ring + 1U;
905919
}
920+
#endif
906921

907922
if (opt != NULL)
908923
{
@@ -911,6 +926,18 @@ status_t EP_SendFrame(ep_handle_t *handle, uint8_t ring, netc_frame_struct_t *fr
911926
txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FL(0x2U) | NETC_SI_TXDESCRIP_RD_TSE_MASK |
912927
NETC_SI_TXDESCRIP_RD_TXSTART(opt->timestamp);
913928
}
929+
#if defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG
930+
else
931+
{
932+
txDesc[0].standard.flags =
933+
NETC_SI_TXDESCRIP_RD_LSO(opt->offload.lso) | NETC_SI_TXDESCRIP_RD_L4CS(opt->offload.l4Checksum) |
934+
NETC_SI_TXDESCRIP_RD_L4T(opt->offload.l4Type) | NETC_SI_TXDESCRIP_RD_L3T(opt->offload.l3Type) |
935+
NETC_SI_TXDESCRIP_RD_L3HDRSIZE(opt->offload.l3HeaderSize) |
936+
NETC_SI_TXDESCRIP_RD_IPCS(opt->offload.ipv4Checksum) |
937+
NETC_SI_TXDESCRIP_RD_L3START(opt->offload.l3Start);
938+
}
939+
#endif
940+
914941
if ((opt->flags & (uint32_t)kEP_TX_OPT_VLAN_INSERT) != 0U)
915942
{
916943
txDesc[0].standard.isExtended = 1U;
@@ -978,10 +1005,12 @@ netc_tx_frame_info_t *EP_ReclaimTxDescCommon(ep_handle_t *handle,
9781005
{
9791006
frameInfo->timestamp = txDesc->writeback.timestamp;
9801007
}
1008+
#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG)
9811009
if (frameInfo->isTxTsIdAvail)
9821010
{
9831011
frameInfo->txtsid = (uint16_t)txDesc->writeback.txtsid;
9841012
}
1013+
#endif
9851014
frameInfo->status = (netc_ep_tx_status_t)txDesc->writeback.status;
9861015
}
9871016
else if (txDesc->standard.frameLen != 0U)
@@ -1027,13 +1056,14 @@ void EP_ReclaimTxDescriptor(ep_handle_t *handle, uint8_t ring)
10271056
netc_tx_frame_info_t *frameInfo;
10281057
uint8_t hwRing = ring;
10291058

1059+
#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG)
10301060
if (NETC_EnetcHasManagement(handle->hw.base) && (getSiNum(handle->cfg.si) == 0U))
10311061
{
10321062
/* Switch management ENETC Tx BD hardware ring 0 can't be used to send regular frame, so the index need increase
10331063
* 1 */
10341064
hwRing = ring + 1U;
10351065
}
1036-
1066+
#endif
10371067
do
10381068
{
10391069
frameInfo =
@@ -2140,7 +2170,7 @@ status_t EP_TxTGSConfigAdminGcl(ep_handle_t *handle, netc_tb_tgs_gcl_t *config)
21402170
uint64_t time, minBaseTime;
21412171

21422172
/* Read the previous active Operationa gate control list cycle time*/
2143-
(void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_data_t));
2173+
(void)memset(cdbrHandle.buffer, 0, sizeof(netc_tb_tgs_req_data_t));
21442174
cdbrHandle.buffer->tgs.request.entryID = config->entryID;
21452175
cdbrHandle.buffer->tgs.request.commonHeader.updateActions = 0U;
21462176
cdbrHandle.buffer->tgs.request.commonHeader.queryActions = 0U;

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