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plat: renesas: Add support for RZ/A series
Add support for Renesas RZ/A series Signed-off-by: Nhut Nguyen <[email protected]>
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‎plat/renesas/rza/board/a3m_ek_nor/platform.mk‎

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#
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# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BOARD := a3m_ek_nor
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APPLOAD ?= RZ_NOFIP
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$(eval $(call add_define,APPLOAD))
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include plat/renesas/rza/common/rz_common.mk
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XSPI0_DEVICE ?= qspiflash_mx25l25645g
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XSPI_DEVICE_TYPE := QSPI
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$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
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NAND := 0
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RZ_FLASH_SIZE ?= 33554432 # 32MB
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$(eval $(call add_define,RZ_FLASH_SIZE))
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ifneq (${USE_SDRAM},0)
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ifeq (${DDR_PLL4},1333)
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DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c \
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plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c
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else
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DDR_PLL4 := 1600
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DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c \
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plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c
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endif
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$(eval $(call add_define,DDR_PLL4))
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endif
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include plat/renesas/rza/soc/a3m/rz_xspi.mk
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include plat/renesas/rza/soc/a3m/soc.mk

‎plat/renesas/rza/board/a3ul_smarc_octal/platform.mk‎

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#
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# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BOARD := a3ul_smarc_octal
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APPLOAD ?= RZ_NOFIP
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$(eval $(call add_define,APPLOAD))
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include plat/renesas/rza/common/rz_common.mk
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XSPI1_DEVICE ?= octaflash_mx66uw
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XSPI1_IF_OPTION ?= .device_size=128*1024*1024
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XSPI2_DEVICE ?= octaram_apsxx
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XSPI2_IF_OPTION ?= .device_size=64*1024*1024
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XSPI_DEVICE_TYPE := OCTA
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$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
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NAND := 0
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RZ_FLASH_SIZE ?= 134217728 # 128MB
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$(eval $(call add_define,RZ_FLASH_SIZE))
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ifneq (${USE_SDRAM},0)
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DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \
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plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c
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DDR_PLL4 := 1600
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$(eval $(call add_define,DDR_PLL4))
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endif
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include plat/renesas/rza/soc/a3ul/rz_xspi.mk
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include plat/renesas/rza/soc/a3ul/soc.mk

‎plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk‎

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#
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# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BOARD := a3ul_smarc_qspi
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APPLOAD ?= RZ_NOFIP
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$(eval $(call add_define,APPLOAD))
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include plat/renesas/rza/common/rz_common.mk
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XSPI0_DEVICE ?= qspiflash_at25
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XSPI_DEVICE_TYPE := QSPI
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$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\"))
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NAND := 0
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RZ_FLASH_SIZE ?= 16777216 # 16MB
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$(eval $(call add_define,RZ_FLASH_SIZE))
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ifneq (${USE_SDRAM},0)
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DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \
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plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c
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DDR_PLL4 := 1600
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$(eval $(call add_define,DDR_PLL4))
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endif
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include plat/renesas/rza/soc/a3ul/rz_xspi.mk
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include plat/renesas/rza/soc/a3ul/soc.mk

‎plat/renesas/rza/common/aarch64/plat_helpers.S‎

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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func plat_my_core_pos
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mrs x0, mpidr_el1
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lsr x0, x0, #MPIDR_AFF1_SHIFT
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and x0, x0, #MPIDR_CPU_MASK
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ret
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endfunc plat_my_core_pos
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func plat_crash_console_init
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mov x0, #1
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ret
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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ret
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov x0, #0
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ret
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endfunc plat_crash_console_flush

‎plat/renesas/rza/common/bl2_plat_mem_params_desc.c‎

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/*
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* Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <common/desc_image_load.h>
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#if (APPLOAD == RZ_NOFIP)
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{
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.image_id = MAX_IMAGE_IDS,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.spsr =
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SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
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.ep_info.pc = BSP_BASE,
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.ep_info.args.arg0 = (uintptr_t)PARAMS_BASE,
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SET_STATIC_PARAM_HEAD(
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image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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#else
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{
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#if RZA3
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.spsr =
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SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
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.ep_info.pc = BSP_BASE,
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.ep_info.args.arg0 = (uintptr_t)PARAMS_BASE,
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SET_STATIC_PARAM_HEAD(
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image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_max_size = BSP_LIMIT - BSP_BASE,
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.image_info.image_base = BSP_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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#endif /* RZA3 */
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}
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#endif /* (APPLOAD == RZ_NOFIP) */
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

‎plat/renesas/rza/common/bl2_plat_setup.c‎

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/*
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* Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <plat/common/common_def.h>
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#include <plat_tzc_def.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <cpg.h>
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#include <ddr.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <pfc.h>
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#include <rz_private.h>
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#include <rza_ipl_version.h>
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#include <rza_mmu.h>
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#include <rza_printf.h>
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#include <scifa.h>
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#include <syc.h>
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#include <sys_regs.h>
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static console_t console;
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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{
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return 0;
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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static bl2_to_bl31_params_mem_t *params;
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bl_mem_params_node_t *bl_mem_params;
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if (!params) {
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params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
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memset((void *)PARAMS_BASE, 0, sizeof(*params));
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}
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bl_mem_params = get_bl_mem_params_node(image_id);
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switch (image_id) {
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case BL32_IMAGE_ID:
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memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
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sizeof(entry_point_info_t));
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break;
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case BL33_IMAGE_ID:
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memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
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sizeof(entry_point_info_t));
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return 0;
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}
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void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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int ret;
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/* early setup Clock and Reset */
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cpg_early_setup();
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/* initialize SYC */
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syc_init(PLAT_SYC_INCK_HZ);
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/* initialize Timer */
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generic_delay_timer_init();
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/* setup PFC */
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pfc_setup();
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/* setup Clock and Reset */
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cpg_setup();
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/* initialize console driver */
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ret = console_rza_register(PLAT_SCIF0_BASE, PLAT_UART_INCK_HZ,
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PLAT_UART_BARDRATE, &console);
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if (!ret)
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panic();
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console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH);
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RZA_PRINTF("Initial Program Loader %s\n", RZA_IPL_VERSION_STRING);
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}
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void bl2_el3_plat_arch_setup(void)
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{
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rza_mmu_pgtbl_cfg_t g_mmu_pagetable_array[] = {
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/* vaddress, paddress, size, attribute */
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{ 0x00000000, 0x00000000, 0x00200000,
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RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
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{ 0x00200000, 0x00200000, 0x0FE00000,
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RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
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{ 0x10000000, 0x10000000, 0x10000000,
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RZA_MMU_ATTRIBUTE_DEVICE },
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{ 0x20000000, 0x20000000, 0x10000000,
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RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
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{ 0x30000000, 0x30000000, 0x10000000,
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RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
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{ 0x40000000, 0x40000000, 0x40000000,
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RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE },
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{ 0x80000000, 0x80000000, 0x40000000,
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RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
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{ 0xC0000000, 0xC0000000, 0x40000000,
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RZA_MMU_ATTRIBUTE_ACCESS_FAULT },
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{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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RZA_MMU_ATTRIBUTE_CONFIG_END }
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};
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if (0 != plat_mmu_init(g_mmu_pagetable_array)) {
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panic();
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}
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plat_mmu_enable();
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}
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void bl2_platform_setup(void)
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{
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/* Setup TZC-400, Access Control */
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plat_security_setup();
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#if USE_SDRAM
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/* initialize DDR */
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ddr_setup();
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#endif /* DEBUG_FPGA */
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rz_io_setup();
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RZ_RUN_TESTS();
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#if (APPLOAD == RZ_NOFIP)
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rza_load_fsp();
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#endif
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rza_print_descs();
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}

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