From 3a21f7467241ee8373df26449bb778b4f4c326e4 Mon Sep 17 00:00:00 2001 From: Nhut Nguyen Date: Thu, 26 Jun 2025 13:49:04 +0700 Subject: [PATCH 1/2] plat: renesas: Add support for RZ/A series Add support for Renesas RZ/A series Signed-off-by: Nhut Nguyen --- plat/renesas/rza/board/a3m_ek_nor/platform.mk | 35 + .../rza/board/a3ul_smarc_octal/platform.mk | 34 + .../rza/board/a3ul_smarc_qspi/platform.mk | 31 + .../renesas/rza/common/aarch64/plat_helpers.S | 39 + .../rza/common/bl2_plat_mem_params_desc.c | 56 + plat/renesas/rza/common/bl2_plat_setup.c | 147 ++ .../rza/common/drivers/auth/auth_mod.c | 254 ++++ .../common/drivers/auth/sblib/crypto_sblib.c | 39 + .../drivers/auth/sblib/sblib_api_private.h | 165 +++ .../common/drivers/auth/sblib/sblib_parser.c | 110 ++ .../rza/common/drivers/auth/tbbr/tbbr_cot.c | 206 +++ plat/renesas/rza/common/drivers/cpg.c | 840 +++++++++++ plat/renesas/rza/common/drivers/ddr/ddr.c | 1083 +++++++++++++++ .../rza/common/drivers/ddr/param_swizzle_T1.c | 45 + .../common/drivers/ddr/param_swizzle_T1b.c | 46 + .../common/drivers/ddr/param_swizzle_T1bc.c | 46 + .../common/drivers/ddr/param_swizzle_T1c.c | 46 + .../common/drivers/ddr/param_swizzle_T1vbc.c | 46 + .../common/drivers/ddr/param_swizzle_T1vc.c | 46 + .../common/drivers/ddr/param_swizzle_T2c.c | 46 + .../common/drivers/ddr/param_swizzle_T2vc.c | 46 + .../common/drivers/ddr/param_swizzle_T3bc.c | 46 + .../common/drivers/ddr/param_swizzle_T3bcud.c | 46 + .../drivers/ddr/param_swizzle_T3bcud2.c | 46 + .../common/drivers/ddr/param_swizzle_T3bcul.c | 46 + .../common/drivers/ddr/param_swizzle_T3cl.c | 46 + .../rza/common/drivers/emmc/emmc_cmd.c | 495 +++++++ .../rza/common/drivers/emmc/emmc_config.h | 20 + .../rza/common/drivers/emmc/emmc_def.h | 78 ++ .../rza/common/drivers/emmc/emmc_hal.h | 535 +++++++ .../rza/common/drivers/emmc/emmc_init.c | 143 ++ .../rza/common/drivers/emmc/emmc_interrupt.c | 192 +++ .../rza/common/drivers/emmc/emmc_mount.c | 664 +++++++++ .../rza/common/drivers/emmc/emmc_read.c | 127 ++ .../rza/common/drivers/emmc/emmc_registers.h | 194 +++ .../rza/common/drivers/emmc/emmc_std.h | 475 +++++++ .../rza/common/drivers/emmc/emmc_utility.c | 200 +++ .../rza/common/drivers/io/io_emmcdrv.c | 203 +++ .../rza/common/drivers/io/io_emmcdrv.h | 13 + plat/renesas/rza/common/drivers/pfc.c | 217 +++ .../common/drivers/rza_mmu/ARMv8A/rza_mmu.c | 236 ++++ plat/renesas/rza/common/drivers/scifa.S | 229 +++ .../spi_multi/AT25QL128A/spi_multi_device.c | 55 + .../spi_multi/MT25QU512ABB/spi_multi_device.c | 10 + .../rza/common/drivers/spi_multi/spi_multi.c | 158 +++ plat/renesas/rza/common/drivers/syc.c | 37 + plat/renesas/rza/common/drivers/xspi/octa.c | 1215 ++++++++++++++++ plat/renesas/rza/common/drivers/xspi/spim.c | 1231 +++++++++++++++++ .../octaflash_mx66uw/octaflash_mx66uw.c | 518 +++++++ .../octaflash_mx66uw/octaflash_mx66uw_api.h | 27 + .../octaflash_mx66uw/rz_xspidevice.mk | 11 + .../xspidevice/octaram_apsxx/octaram_apsxx.c | 235 ++++ .../octaram_apsxx/octaram_apsxx_api.h | 27 + .../xspidevice/octaram_apsxx/rz_xspidevice.mk | 11 + .../qspiflash_at25/qspiflash_at25.c | 564 ++++++++ .../qspiflash_at25/qspiflash_at25_api.h | 27 + .../qspiflash_at25/rz_xspidevice.mk | 11 + .../qspiflash_mx25l25645g.c | 764 ++++++++++ .../qspiflash_mx25l25645g_api.h | 63 + .../qspiflash_mx25l25645g/rz_xspidevice.mk | 11 + plat/renesas/rza/common/include/cpg.h | 93 ++ plat/renesas/rza/common/include/cpg_regs.h | 707 ++++++++++ plat/renesas/rza/common/include/ddr.h | 12 + .../renesas/rza/common/include/ddr_internal.h | 51 + .../common/include/drivers/auth/auth_common.h | 127 ++ .../include/drivers/auth/sblib/crypto_sblib.h | 16 + .../AT25QL128A/spi_multi_reg_values.h | 105 ++ .../MT25QU512ABB/spi_multi_reg_values.h | 90 ++ .../include/drivers/spi_multi/spi_multi.h | 46 + .../drivers/spi_multi/spi_multi_regs.h | 255 ++++ plat/renesas/rza/common/include/octa.h | 33 + plat/renesas/rza/common/include/octa_regs.h | 279 ++++ plat/renesas/rza/common/include/pfc.h | 13 + plat/renesas/rza/common/include/pfc_regs.h | 746 ++++++++++ plat/renesas/rza/common/include/plat_macros.S | 13 + .../renesas/rza/common/include/plat_tzc_def.h | 51 + plat/renesas/rza/common/include/rz_private.h | 43 + plat/renesas/rza/common/include/rz_sip_svc.h | 16 + .../rza/common/include/rza_ipl_version.h | 12 + plat/renesas/rza/common/include/rza_mmu.h | 131 ++ plat/renesas/rza/common/include/rza_printf.h | 40 + plat/renesas/rza/common/include/scifa.h | 20 + plat/renesas/rza/common/include/spim.h | 30 + plat/renesas/rza/common/include/spim_regs.h | 295 ++++ plat/renesas/rza/common/include/syc.h | 13 + plat/renesas/rza/common/include/sys.h | 22 + plat/renesas/rza/common/include/sys_regs.h | 859 ++++++++++++ plat/renesas/rza/common/include/xspi_api.h | 217 +++ .../rza/common/include/xspidevice_api.h | 131 ++ plat/renesas/rza/common/plat_early_setup.S | 44 + plat/renesas/rza/common/plat_gic.c | 57 + plat/renesas/rza/common/plat_image_load.c | 191 +++ plat/renesas/rza/common/plat_pm.c | 74 + plat/renesas/rza/common/plat_rz_common.c | 12 + plat/renesas/rza/common/plat_security.c | 176 +++ plat/renesas/rza/common/plat_storage.c | 248 ++++ plat/renesas/rza/common/plat_topology.c | 33 + plat/renesas/rza/common/rz_bl2_xspi_config.sh | 159 +++ plat/renesas/rza/common/rz_common.mk | 112 ++ plat/renesas/rza/common/rz_image.pl | 74 + plat/renesas/rza/common/rz_plat_sip_handler.c | 63 + plat/renesas/rza/common/rz_sip_svc.c | 40 + plat/renesas/rza/common/rz_xspi_common.mk | 67 + .../renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c | 13 + .../a3m/drivers/ddr/param_mc_C-011_D3-01-1.c | 232 ++++ .../a3m/drivers/ddr/param_mc_C-011_D3-02-1.c | 232 ++++ plat/renesas/rza/soc/a3m/drivers/xspi.c | 71 + plat/renesas/rza/soc/a3m/include/cpg_opt.h | 12 + plat/renesas/rza/soc/a3m/include/ddr_mc_if.h | 62 + .../renesas/rza/soc/a3m/include/ddr_mc_regs.h | 470 +++++++ .../rza/soc/a3m/include/ddr_phy_regs.h | 95 ++ .../rza/soc/a3m/include/platform_def.h | 118 ++ plat/renesas/rza/soc/a3m/include/rza3m_def.h | 68 + plat/renesas/rza/soc/a3m/rz_image.pl | 124 ++ plat/renesas/rza/soc/a3m/rz_image_nand.pl | 143 ++ plat/renesas/rza/soc/a3m/rz_xspi.mk | 34 + plat/renesas/rza/soc/a3m/soc.mk | 64 + .../rza/soc/a3ul/drivers/ddr/ddr_a3ul.c | 13 + .../a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c | 232 ++++ .../a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c | 232 ++++ .../a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c | 232 ++++ .../a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c | 232 ++++ plat/renesas/rza/soc/a3ul/drivers/xspi.c | 71 + plat/renesas/rza/soc/a3ul/include/cpg_opt.h | 12 + plat/renesas/rza/soc/a3ul/include/ddr_mc_if.h | 62 + .../rza/soc/a3ul/include/ddr_mc_regs.h | 452 ++++++ .../rza/soc/a3ul/include/ddr_phy_regs.h | 95 ++ .../rza/soc/a3ul/include/platform_def.h | 118 ++ .../renesas/rza/soc/a3ul/include/rza3ul_def.h | 68 + plat/renesas/rza/soc/a3ul/rz_image.pl | 74 + plat/renesas/rza/soc/a3ul/rz_xspi.mk | 34 + plat/renesas/rza/soc/a3ul/soc.mk | 60 + 132 files changed, 22173 insertions(+) create mode 100644 plat/renesas/rza/board/a3m_ek_nor/platform.mk create mode 100644 plat/renesas/rza/board/a3ul_smarc_octal/platform.mk create mode 100644 plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk create mode 100644 plat/renesas/rza/common/aarch64/plat_helpers.S create mode 100644 plat/renesas/rza/common/bl2_plat_mem_params_desc.c create mode 100644 plat/renesas/rza/common/bl2_plat_setup.c create mode 100644 plat/renesas/rza/common/drivers/auth/auth_mod.c create mode 100644 plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c create mode 100644 plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h create mode 100644 plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c create mode 100644 plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c create mode 100644 plat/renesas/rza/common/drivers/cpg.c create mode 100644 plat/renesas/rza/common/drivers/ddr/ddr.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c create mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_cmd.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_config.h create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_def.h create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_hal.h create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_init.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_mount.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_read.c create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_registers.h create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_std.h create mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_utility.c create mode 100644 plat/renesas/rza/common/drivers/io/io_emmcdrv.c create mode 100644 plat/renesas/rza/common/drivers/io/io_emmcdrv.h create mode 100644 plat/renesas/rza/common/drivers/pfc.c create mode 100644 plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c create mode 100644 plat/renesas/rza/common/drivers/scifa.S create mode 100644 plat/renesas/rza/common/drivers/spi_multi/AT25QL128A/spi_multi_device.c create mode 100644 plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c create mode 100644 plat/renesas/rza/common/drivers/spi_multi/spi_multi.c create mode 100644 plat/renesas/rza/common/drivers/syc.c create mode 100644 plat/renesas/rza/common/drivers/xspi/octa.c create mode 100644 plat/renesas/rza/common/drivers/xspi/spim.c create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h create mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h create mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk create mode 100644 plat/renesas/rza/common/include/cpg.h create mode 100644 plat/renesas/rza/common/include/cpg_regs.h create mode 100644 plat/renesas/rza/common/include/ddr.h create mode 100644 plat/renesas/rza/common/include/ddr_internal.h create mode 100644 plat/renesas/rza/common/include/drivers/auth/auth_common.h create mode 100644 plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h create mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h create mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h create mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h create mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h create mode 100644 plat/renesas/rza/common/include/octa.h create mode 100644 plat/renesas/rza/common/include/octa_regs.h create mode 100644 plat/renesas/rza/common/include/pfc.h create mode 100644 plat/renesas/rza/common/include/pfc_regs.h create mode 100644 plat/renesas/rza/common/include/plat_macros.S create mode 100644 plat/renesas/rza/common/include/plat_tzc_def.h create mode 100644 plat/renesas/rza/common/include/rz_private.h create mode 100644 plat/renesas/rza/common/include/rz_sip_svc.h create mode 100644 plat/renesas/rza/common/include/rza_ipl_version.h create mode 100644 plat/renesas/rza/common/include/rza_mmu.h create mode 100644 plat/renesas/rza/common/include/rza_printf.h create mode 100644 plat/renesas/rza/common/include/scifa.h create mode 100644 plat/renesas/rza/common/include/spim.h create mode 100644 plat/renesas/rza/common/include/spim_regs.h create mode 100644 plat/renesas/rza/common/include/syc.h create mode 100644 plat/renesas/rza/common/include/sys.h create mode 100644 plat/renesas/rza/common/include/sys_regs.h create mode 100644 plat/renesas/rza/common/include/xspi_api.h create mode 100644 plat/renesas/rza/common/include/xspidevice_api.h create mode 100644 plat/renesas/rza/common/plat_early_setup.S create mode 100644 plat/renesas/rza/common/plat_gic.c create mode 100644 plat/renesas/rza/common/plat_image_load.c create mode 100644 plat/renesas/rza/common/plat_pm.c create mode 100644 plat/renesas/rza/common/plat_rz_common.c create mode 100644 plat/renesas/rza/common/plat_security.c create mode 100644 plat/renesas/rza/common/plat_storage.c create mode 100644 plat/renesas/rza/common/plat_topology.c create mode 100644 plat/renesas/rza/common/rz_bl2_xspi_config.sh create mode 100644 plat/renesas/rza/common/rz_common.mk create mode 100644 plat/renesas/rza/common/rz_image.pl create mode 100644 plat/renesas/rza/common/rz_plat_sip_handler.c create mode 100644 plat/renesas/rza/common/rz_sip_svc.c create mode 100644 plat/renesas/rza/common/rz_xspi_common.mk create mode 100644 plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c create mode 100644 plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c create mode 100644 plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c create mode 100644 plat/renesas/rza/soc/a3m/drivers/xspi.c create mode 100644 plat/renesas/rza/soc/a3m/include/cpg_opt.h create mode 100644 plat/renesas/rza/soc/a3m/include/ddr_mc_if.h create mode 100644 plat/renesas/rza/soc/a3m/include/ddr_mc_regs.h create mode 100644 plat/renesas/rza/soc/a3m/include/ddr_phy_regs.h create mode 100644 plat/renesas/rza/soc/a3m/include/platform_def.h create mode 100644 plat/renesas/rza/soc/a3m/include/rza3m_def.h create mode 100644 plat/renesas/rza/soc/a3m/rz_image.pl create mode 100644 plat/renesas/rza/soc/a3m/rz_image_nand.pl create mode 100644 plat/renesas/rza/soc/a3m/rz_xspi.mk create mode 100644 plat/renesas/rza/soc/a3m/soc.mk create mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c create mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c create mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c create mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c create mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c create mode 100644 plat/renesas/rza/soc/a3ul/drivers/xspi.c create mode 100644 plat/renesas/rza/soc/a3ul/include/cpg_opt.h create mode 100644 plat/renesas/rza/soc/a3ul/include/ddr_mc_if.h create mode 100644 plat/renesas/rza/soc/a3ul/include/ddr_mc_regs.h create mode 100644 plat/renesas/rza/soc/a3ul/include/ddr_phy_regs.h create mode 100644 plat/renesas/rza/soc/a3ul/include/platform_def.h create mode 100644 plat/renesas/rza/soc/a3ul/include/rza3ul_def.h create mode 100644 plat/renesas/rza/soc/a3ul/rz_image.pl create mode 100644 plat/renesas/rza/soc/a3ul/rz_xspi.mk create mode 100644 plat/renesas/rza/soc/a3ul/soc.mk diff --git a/plat/renesas/rza/board/a3m_ek_nor/platform.mk b/plat/renesas/rza/board/a3m_ek_nor/platform.mk new file mode 100644 index 0000000000..e8b5bfecbd --- /dev/null +++ b/plat/renesas/rza/board/a3m_ek_nor/platform.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BOARD := a3m_ek_nor + +APPLOAD ?= RZ_NOFIP +$(eval $(call add_define,APPLOAD)) + +include plat/renesas/rza/common/rz_common.mk + +XSPI0_DEVICE ?= qspiflash_mx25l25645g +XSPI_DEVICE_TYPE := QSPI +$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\")) + +NAND := 0 +RZ_FLASH_SIZE ?= 33554432 # 32MB +$(eval $(call add_define,RZ_FLASH_SIZE)) + +ifneq (${USE_SDRAM},0) +ifeq (${DDR_PLL4},1333) +DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c \ + plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c +else +DDR_PLL4 := 1600 +DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c \ + plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c +endif +$(eval $(call add_define,DDR_PLL4)) +endif + +include plat/renesas/rza/soc/a3m/rz_xspi.mk +include plat/renesas/rza/soc/a3m/soc.mk diff --git a/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk b/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk new file mode 100644 index 0000000000..cdb04c5588 --- /dev/null +++ b/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BOARD := a3ul_smarc_octal + +APPLOAD ?= RZ_NOFIP +$(eval $(call add_define,APPLOAD)) + +include plat/renesas/rza/common/rz_common.mk + +XSPI1_DEVICE ?= octaflash_mx66uw +XSPI1_IF_OPTION ?= .device_size=128*1024*1024 +XSPI2_DEVICE ?= octaram_apsxx +XSPI2_IF_OPTION ?= .device_size=64*1024*1024 +XSPI_DEVICE_TYPE := OCTA +$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\")) + +NAND := 0 +RZ_FLASH_SIZE ?= 134217728 # 128MB +$(eval $(call add_define,RZ_FLASH_SIZE)) + +ifneq (${USE_SDRAM},0) +DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \ + plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c + +DDR_PLL4 := 1600 +$(eval $(call add_define,DDR_PLL4)) +endif + +include plat/renesas/rza/soc/a3ul/rz_xspi.mk +include plat/renesas/rza/soc/a3ul/soc.mk diff --git a/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk b/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk new file mode 100644 index 0000000000..b450b1ffa8 --- /dev/null +++ b/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +BOARD := a3ul_smarc_qspi + +APPLOAD ?= RZ_NOFIP +$(eval $(call add_define,APPLOAD)) + +include plat/renesas/rza/common/rz_common.mk + +XSPI0_DEVICE ?= qspiflash_at25 +XSPI_DEVICE_TYPE := QSPI +$(eval $(call add_define_val,XSPI_DEVICE_TYPE,\"${XSPI_DEVICE_TYPE}\")) + +NAND := 0 +RZ_FLASH_SIZE ?= 16777216 # 16MB +$(eval $(call add_define,RZ_FLASH_SIZE)) + +ifneq (${USE_SDRAM},0) +DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \ + plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c + +DDR_PLL4 := 1600 +$(eval $(call add_define,DDR_PLL4)) +endif + +include plat/renesas/rza/soc/a3ul/rz_xspi.mk +include plat/renesas/rza/soc/a3ul/soc.mk diff --git a/plat/renesas/rza/common/aarch64/plat_helpers.S b/plat/renesas/rza/common/aarch64/plat_helpers.S new file mode 100644 index 0000000000..66db9a1ee9 --- /dev/null +++ b/plat/renesas/rza/common/aarch64/plat_helpers.S @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + + .globl platform_mem_init + .globl plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + +func platform_mem_init + ret +endfunc platform_mem_init + +func plat_my_core_pos + mrs x0, mpidr_el1 + lsr x0, x0, #MPIDR_AFF1_SHIFT + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc plat_my_core_pos + +func plat_crash_console_init + mov x0, #1 + ret +endfunc plat_crash_console_init + +func plat_crash_console_putc + ret +endfunc plat_crash_console_putc + +func plat_crash_console_flush + mov x0, #0 + ret +endfunc plat_crash_console_flush diff --git a/plat/renesas/rza/common/bl2_plat_mem_params_desc.c b/plat/renesas/rza/common/bl2_plat_mem_params_desc.c new file mode 100644 index 0000000000..7d1aec02dd --- /dev/null +++ b/plat/renesas/rza/common/bl2_plat_mem_params_desc.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#if (APPLOAD == RZ_NOFIP) + { + .image_id = MAX_IMAGE_IDS, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.spsr = + SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), + .ep_info.pc = BSP_BASE, + .ep_info.args.arg0 = (uintptr_t)PARAMS_BASE, + + SET_STATIC_PARAM_HEAD( + image_info, PARAM_EP, VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +#else + { +#if RZA3 + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2, + entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.spsr = + SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), + .ep_info.pc = BSP_BASE, + .ep_info.args.arg0 = (uintptr_t)PARAMS_BASE, + + SET_STATIC_PARAM_HEAD( + image_info, PARAM_EP, VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + .image_info.image_max_size = BSP_LIMIT - BSP_BASE, + .image_info.image_base = BSP_BASE, + + .next_handoff_image_id = INVALID_IMAGE_ID, +#endif /* RZA3 */ + } +#endif /* (APPLOAD == RZ_NOFIP) */ +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/plat/renesas/rza/common/bl2_plat_setup.c b/plat/renesas/rza/common/bl2_plat_setup.c new file mode 100644 index 0000000000..738d067328 --- /dev/null +++ b/plat/renesas/rza/common/bl2_plat_setup.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static console_t console; + +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return 0; +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + static bl2_to_bl31_params_mem_t *params; + bl_mem_params_node_t *bl_mem_params; + + if (!params) { + params = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; + memset((void *)PARAMS_BASE, 0, sizeof(*params)); + } + + bl_mem_params = get_bl_mem_params_node(image_id); + + switch (image_id) { + case BL32_IMAGE_ID: + memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info, + sizeof(entry_point_info_t)); + break; + case BL33_IMAGE_ID: + memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info, + sizeof(entry_point_info_t)); + break; + default: + /* Do nothing in default case */ + break; + } + + return 0; +} + +void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, + u_register_t arg3, u_register_t arg4) +{ + int ret; + + /* early setup Clock and Reset */ + cpg_early_setup(); + + /* initialize SYC */ + syc_init(PLAT_SYC_INCK_HZ); + + /* initialize Timer */ + generic_delay_timer_init(); + + /* setup PFC */ + pfc_setup(); + + /* setup Clock and Reset */ + cpg_setup(); + + /* initialize console driver */ + ret = console_rza_register(PLAT_SCIF0_BASE, PLAT_UART_INCK_HZ, + PLAT_UART_BARDRATE, &console); + if (!ret) + panic(); + + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH); + + RZA_PRINTF("Initial Program Loader %s\n", RZA_IPL_VERSION_STRING); +} + +void bl2_el3_plat_arch_setup(void) +{ + rza_mmu_pgtbl_cfg_t g_mmu_pagetable_array[] = { + /* vaddress, paddress, size, attribute */ + { 0x00000000, 0x00000000, 0x00200000, + RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, + { 0x00200000, 0x00200000, 0x0FE00000, + RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, + { 0x10000000, 0x10000000, 0x10000000, + RZA_MMU_ATTRIBUTE_DEVICE }, + { 0x20000000, 0x20000000, 0x10000000, + RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, + { 0x30000000, 0x30000000, 0x10000000, + RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, + { 0x40000000, 0x40000000, 0x40000000, + RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, + { 0x80000000, 0x80000000, 0x40000000, + RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, + { 0xC0000000, 0xC0000000, 0x40000000, + RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, + { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + RZA_MMU_ATTRIBUTE_CONFIG_END } + }; + + if (0 != plat_mmu_init(g_mmu_pagetable_array)) { + panic(); + } + plat_mmu_enable(); +} + +void bl2_platform_setup(void) +{ + /* Setup TZC-400, Access Control */ + plat_security_setup(); + +#if USE_SDRAM + /* initialize DDR */ + ddr_setup(); +#endif /* DEBUG_FPGA */ + + rz_io_setup(); + + RZ_RUN_TESTS(); + +#if (APPLOAD == RZ_NOFIP) + rza_load_fsp(); +#endif + rza_print_descs(); +} diff --git a/plat/renesas/rza/common/drivers/auth/auth_mod.c b/plat/renesas/rza/common/drivers/auth/auth_mod.c new file mode 100644 index 0000000000..db101d6947 --- /dev/null +++ b/plat/renesas/rza/common/drivers/auth/auth_mod.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include "../../include/drivers/auth/auth_common.h" +#include "../../include/drivers/auth/sblib/crypto_sblib.h" + +#define return_if_error(rc) \ + do { \ + if (rc != 0) { \ + return rc; \ + } \ + } while (0) + +#define TBBR_COT_GETTER(id) \ + __extension__({ \ + assert((id) < cot_desc_size); \ + cot_desc_ptr[id]; \ + }) + +static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, + const auth_param_type_desc_t *b) +{ + if ((a->type == b->type) && (a->cookie == b->cookie)) { + return 0; + } + return 1; +} + +/* + * This function obtains the requested authentication parameter data from the + * information extracted from the parent image after its authentication. + */ +static int auth_get_param(const auth_param_type_desc_t *param_type_desc, + const auth_img_desc_t *img_desc, void **param, + unsigned int *len) +{ + int i; + + if (img_desc->authenticated_data == NULL) + return 1; + + for (i = 0; i < COT_MAX_VERIFIED_PARAMS; i++) { + if (0 == cmp_auth_param_type_desc( + param_type_desc, + img_desc->authenticated_data[i].type_desc)) { + *param = img_desc->authenticated_data[i].data.ptr; + *len = img_desc->authenticated_data[i].data.len; + return 0; + } + } + + return 1; +} + +/* + * Authenticate an image using Renesas SB-Lib + * + * This function implements 'AUTH_METHOD_SBLIB'. To authenticate an image using + * this method, the image must contain: + * + * - Data to calculate the hash from + * or + * - Data to be signed + * + * The parent image must contain: + * + * - Key Certificate + * - Content Certificate + * + * Key certificate contains the signature and public key to verify itself, + * and the hash value of the public key in the content certificate. + * Content certificate contains the signature and public key to verify itself, + * and an algorithm to authenticate an image. If the image is authenticated + * by matching the hash, content certificate contains the hash of the image. + * If the image is authenticated by digital signature, content certificate + * signature is used to authenticate the certificate and image together. + * + * Renesas SB-Lib authenticates the key certificate, content certificate and + * image together. + * + * Crypto Module is not used because it does not fit the SB-Lib interface. + * + * Return: + * 0 = success, Otherwise = error + */ +static int auth_sblib(const auth_method_param_sblib_t *param, + const auth_img_desc_t *img_desc, void *img, + unsigned int img_len) +{ + const auth_img_desc_t *key_cert_desc, *content_cert_desc; + void *data_ptr, *key_cert_ptr, *content_cert_ptr; + unsigned int data_len, key_cert_len, content_cert_len; + int rc = 0; + + /* Get the content certificate that is the parent of the image */ + content_cert_desc = img_desc->parent; + rc = auth_get_param(param->key_cert, content_cert_desc, + &content_cert_ptr, &content_cert_len); + return_if_error(rc); + + /* Get the key certificate that is the parent of the content certificate */ + key_cert_desc = content_cert_desc->parent; + rc = auth_get_param(param->content_cert, key_cert_desc, &key_cert_ptr, + &key_cert_len); + return_if_error(rc); + + /* Get the data to authenticate from the current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->data, img, + img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Ask Renesas SB-Lib to authenticate this image */ + rc = crypto_sblib_auth(data_ptr, data_len, key_cert_ptr, key_cert_len, + content_cert_ptr, content_cert_len); + + return rc; +} + +/* + * Return the parent id in the output parameter '*parent_id' + * + * Return value: + * 0 = Image has parent, 1 = Image has no parent or parent is authenticated + */ +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id) +{ + const auth_img_desc_t *img_desc = NULL; + + assert(parent_id != NULL); + /* Get the image descriptor */ + img_desc = TBBR_COT_GETTER(img_id); + + /* Check if the image has no parent (ROT) */ + if (img_desc->parent == NULL) { + *parent_id = 0; + return 1; + } + + /* Check if the parent has already been authenticated */ + if (auth_img_flags[img_desc->parent->img_id] & IMG_FLAG_AUTHENTICATED) { + *parent_id = 0; + return 1; + } + + *parent_id = img_desc->parent->img_id; + return 0; +} + +/* + * Initialize the different modules in the authentication framework + */ +void auth_mod_init(void) +{ + /* Check we have a valid CoT registered */ + assert(cot_desc_ptr != NULL); + + /* Renesas SB-Lib */ + crypto_sblib_init(); + + /* Image parser module */ + img_parser_init(); +} + +/* + * Authenticate a certificate/image + * + * Return: 0 = success, Otherwise = error + */ +int auth_mod_verify_img(unsigned int img_id, void *img_ptr, + unsigned int img_len) +{ + const auth_img_desc_t *img_desc = NULL; + const auth_method_desc_t *auth_method = NULL; + void *param_ptr; + unsigned int param_len; + int rc, i; + + /* Get the image descriptor from the chain of trust */ + img_desc = TBBR_COT_GETTER(img_id); + + /* Ask the parser to check the image integrity */ + rc = img_parser_check_integrity(img_desc->img_type, img_ptr, img_len); + return_if_error(rc); + + /* Authenticate the image using the methods indicated in the image descriptor. */ + if (img_desc->img_auth_methods == NULL) + return 1; + for (i = 0; i < AUTH_METHOD_NUM; i++) { + auth_method = &img_desc->img_auth_methods[i]; + switch (auth_method->type) { + case AUTH_METHOD_NONE: + rc = 0; + break; + case AUTH_METHOD_SBLIB: + rc = auth_sblib(&auth_method->param.sblib, img_desc, + img_ptr, img_len); + break; + default: + /* Unknown authentication method */ + rc = 1; + break; + } + return_if_error(rc); + } + + /* Extract the parameters indicated in the image descriptor to + * authenticate the children images + */ + if (img_desc->authenticated_data != NULL) { + for (i = 0; i < COT_MAX_VERIFIED_PARAMS; i++) { + if (img_desc->authenticated_data[i].type_desc == NULL) { + continue; + } + + /* Get the parameter from the image parser module */ + rc = img_parser_get_auth_param( + img_desc->img_type, + img_desc->authenticated_data[i].type_desc, + img_ptr, img_len, ¶m_ptr, ¶m_len); + return_if_error(rc); + + /* Check parameter size */ + if (param_len > + img_desc->authenticated_data[i].data.len) { + return 1; + } + + /* Copy the parameter for later use */ + memcpy((void *)img_desc->authenticated_data[i].data.ptr, + (void *)param_ptr, param_len); + } + } + + /* Mark image as authenticated */ + auth_img_flags[img_desc->img_id] |= IMG_FLAG_AUTHENTICATED; + + return 0; +} diff --git a/plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c b/plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c new file mode 100644 index 0000000000..7dc3d9c0d5 --- /dev/null +++ b/plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include + +#include +#include + +#include "../../../include/drivers/auth/sblib/crypto_sblib.h" +#include "sblib_api_private.h" + +#define SECURE_BOOT_API_ADDR (0x000007F00) + +static sb_secure_boot_api_t secure_boot_api; + +int crypto_sblib_auth(void *data_ptr, size_t len, const void *key_cert, + unsigned int key_cert_len, const void *content_cert, + unsigned int content_cert_len) +{ + sb_ret_t rc; + + assert(secure_boot_api != NULL); + + rc = secure_boot_api(key_cert, key_cert_len, content_cert, + content_cert_len, NULL); + if (SB_RET_SUCCESS != rc) + return CRYPTO_ERR_UNKNOWN; + + return CRYPTO_SUCCESS; +} + +void crypto_sblib_init(void) +{ + secure_boot_api = (sb_secure_boot_api_t)SECURE_BOOT_API_ADDR; +} diff --git a/plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h b/plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h new file mode 100644 index 0000000000..4e8a28759c --- /dev/null +++ b/plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*!***************************************************************************** + * \file : sblib_api_private.h + * \par version : 1.00 + * \par Product Name : Renesas-SB-Lib + * \par Device(s) : Does not depend on specific hardware + * \par Description : This file defines the public macros, types and + * : declarations in used the SB-Lib. + ******************************************************************************/ + +#ifndef SBLIB_API_PRIVATE_H +#define SBLIB_API_PRIVATE_H + +/** SB-Lib return value definition */ +/**\addtogroup group_return_code Return code */ +/*! \{*/ + +/** API succeeded */ +#define SB_RET_SUCCESS ((sb_ret_t)0x55555555UL) + +/** An image of the same version as the current version is input + * (verification completed successfully) + */ +#define SB_RET_SAME_IMAGE_VERSION ((sb_ret_t)0x55005501UL) + +/** A internal failure */ +#define SB_RET_ERR_INTERNAL_FAIL ((sb_ret_t)0xAAAA0000UL) + +/** An invalid argument was entered */ +#define SB_RET_ERR_INVALID_ARG ((sb_ret_t)0xAAAA0001UL) + +/** Unsupported function executed */ +#define SB_RET_ERR_UNSUPPORTED_FUNCTION ((sb_ret_t)0xAAAA0002UL) + +/** Data entered with incorrect alignment */ +#define SB_RET_ERR_INVALID_ALIGNMENT ((sb_ret_t)0xAAAA0003UL) + +/** An invalid magic number is set */ +#define SB_RET_ERR_MANI_INVALID_MAGIC ((sb_ret_t)0xAAAA0100UL) + +/** Unsupported version is set */ +#define SB_RET_ERR_MANI_UNSUPPORTED_VERSION ((sb_ret_t)0xAAAA0101UL) + +/** Out of range TLV Length is set */ +#define SB_RET_ERR_MANI_OUT_OF_RANGE_LEN ((sb_ret_t)0xAAAA0102UL) + +/** Missing required TLV field */ +#define SB_RET_ERR_MANI_TLV_FIELD_ERR ((sb_ret_t)0xAAAA0103UL) + +/** The length exceeding the end of the manifest is specified in length of the TLV field */ +#define SB_RET_ERR_MANI_TLV_INVALID_LEN ((sb_ret_t)0xAAAA0104UL) + +/** An invalid image length is set */ +#define SB_RET_ERR_MANI_INVALID_IMAGE_LEN ((sb_ret_t)0xAAAA0105UL) + +/** There is a wrong combination of signature algorithms */ +#define SB_RET_ERR_MANI_MISMATCH_SIGN_ALGORITHM ((sb_ret_t)0xAAAA0106UL) + +/** An algorithm was specified that the manifest does not support */ +#define SB_RET_ERR_MANI_UNSUPPORTED_ALGORITHM ((sb_ret_t)0xAAAA0107UL) + +/** Cryptographic processing failure */ +#define SB_RET_ERR_CRYPTO_FAIL ((sb_ret_t)0xAAAA0200UL) + +/** Verification failed */ +#define SB_RET_ERR_CRYPTO_AUTH_FAIL ((sb_ret_t)0xAAAA0201UL) + +/** Unsupported algorithm */ +#define SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM ((sb_ret_t)0xAAAA0202UL) + +/** Other resorece is using CryptoIP. */ +#define SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT ((sb_ret_t)0xAAAA0203UL) + +/** Parameter error */ +#define SB_RET_ERR_CRYPTO_PARAM_ERR ((sb_ret_t)0xAAAA0204UL) + +/** CRC mismatch */ +#define SB_RET_ERR_CRC_MISMATCH ((sb_ret_t)0xAAAA0300UL) + +/** Unsupported polynominal */ +#define SB_RET_ERR_CRC_UNSUPPORTED_POLYNOMIAL ((sb_ret_t)0xAAAA0301UL) + +/** Image version lower than the current image version is installed */ +#define SB_RET_ERR_LOWER_IMAGE_VERSION ((sb_ret_t)0xAAAA0400UL) + +/*! \}*/ + +/** Manifest size definition */ +/**\addtogroup group_manifest_size Manifest size */ +/*! \{*/ +#define SB_MANIFEST_LEN_MIN (36UL) /**< Minimum manifest length */ +#define SB_MANIFEST_LEN_MAX (10240UL) /**< Maximum manifest length */ +/*! \}*/ + +/** Reserved WORD size definition */ +/**\addtogroup group_unused_area Reserved WORD size */ +/*! \{*/ + +/** Key Certificate header reserved WORD size */ +#define SB_KEY_CERT_RESERVED_WORD_SIZE (5U) + +/*! \}*/ + +/** SB-Lib return type */ +typedef uint32_t sb_ret_t; + +/** SB-Lib Secure Boot API pointer type */ +typedef sb_ret_t (*sb_secure_boot_api_t)(const uint8_t *const p_key_cert, + const uint32_t key_cert_len_max, + const uint8_t *const p_code_cert, + const uint32_t code_cert_len_max, + const uint8_t *const p_mac_tlv); + +/*!********************************************************* + * \addtogroup SBLIBManifestTypes + * \{*******************************************************/ +/** Key Certificate header structure */ +typedef struct { + /** Magic number unique to KeyCertificate */ + uint32_t magic; + + /** Manifest version */ + uint32_t manifest_version; + + /** KeyCertificate flag (Unused in V.1.00) */ + uint32_t flags; + + /** Unused area */ + uint32_t reserved[SB_KEY_CERT_RESERVED_WORD_SIZE]; +} st_sb_key_cert_header_t; + +/** Code Certificate header structure */ +typedef struct { + /** Magic number unique to CodeCertificate */ + uint32_t magic; + + /** Manifest version */ + uint32_t manifest_version; + + /** CodeCertificate flag */ + uint32_t flags; + + /** Image storage address */ + uint32_t load_addr; + + /** Image expansion destination address */ + uint32_t dest_addr; + + /** Image byte size */ + uint32_t img_len; + + /** Image version */ + uint32_t img_version; + + /** Image build number */ + uint32_t build_num; +} st_sb_code_cert_header_t; +/*! \}*/ + +#endif /* SBLIB_API_PRIVATE_H */ diff --git a/plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c b/plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c new file mode 100644 index 0000000000..ec39b1515b --- /dev/null +++ b/plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "../../../include/drivers/auth/auth_common.h" +#include "sblib_api_private.h" + +#define LIB_NAME "Renesas SB-Lib" + +#define KEY_CERT_HEADER_MAGIC_NUMBER (0x6b657963) +#define CONTENT_CERT_HEADER_MAGIC_NUMBER (0x636f6463) + +/* + * Clear all static temporary variables. + */ +static void clear_temp_vars(void) +{ +#define ZERO_AND_CLEAN(x) \ + do { \ + zeromem(&x, sizeof(x)); \ + clean_dcache_range((uintptr_t) &x, sizeof(x)); \ + } while (0); + +#undef ZERO_AND_CLEAN +} + +static int key_cert_parse(void *img, unsigned int img_len) +{ + return IMG_PARSER_OK; +} + +static int content_cert_parse(void *img, unsigned int img_len) +{ + return IMG_PARSER_OK; +} + +/* Exported functions */ + +static void init(void) +{ + /* Do Nothing */ +} + +/* + * Wrapper for cert_parse() that clears the static variables used by it in case + * of an error. + */ +static int check_integrity(void *img, unsigned int img_len) +{ + int rc; + uint32_t magic; + + if (SB_MANIFEST_LEN_MIN > img_len) + return IMG_PARSER_ERR_FORMAT; + + magic = *(uint32_t *)img; + + switch (magic) { + case KEY_CERT_HEADER_MAGIC_NUMBER: + rc = key_cert_parse(img, img_len); + break; + case CONTENT_CERT_HEADER_MAGIC_NUMBER: + rc = content_cert_parse(img, img_len); + break; + default: + rc = IMG_PARSER_ERR_FORMAT; + break; + } + + if (rc != IMG_PARSER_OK) + clear_temp_vars(); + + return rc; +} + +/* + * Extract an authentication parameter from an SBLib Manifest + */ +static int get_auth_param(const auth_param_type_desc_t *type_desc, void *img, + unsigned int img_len, void **param, + unsigned int *param_len) +{ + int rc = IMG_PARSER_OK; + + switch (type_desc->type) { + case AUTH_PARAM_RAW_DATA: + *param = (void *)img; + *param_len = (unsigned int)img_len; + break; + default: + rc = IMG_PARSER_ERR_NOT_FOUND; + break; + } + + return rc; +} + +REGISTER_IMG_PARSER_LIB(IMG_PLAT, LIB_NAME, init, check_integrity, + get_auth_param); diff --git a/plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c b/plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c new file mode 100644 index 0000000000..365c2e8afd --- /dev/null +++ b/plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include "../../../include/drivers/auth/auth_common.h" +#if USE_TBBR_DEFS +#include +#else +#include +#endif + +#define KEY_CERT_LEN (256) +#define CONTENT_CERT_LEN (512) + +#ifdef IMAGE_BL2 + +static unsigned char soc_fw_key_cert_buf[KEY_CERT_LEN]; +static unsigned char soc_fw_content_cert_buf[CONTENT_CERT_LEN]; + +static unsigned char tos_fw_key_cert_buf[KEY_CERT_LEN]; +static unsigned char tos_fw_content_cert_buf[CONTENT_CERT_LEN]; + +static unsigned char nt_fw_key_cert_buf[KEY_CERT_LEN]; +static unsigned char nt_fw_content_cert_buf[CONTENT_CERT_LEN]; + +static auth_param_type_desc_t key_cert = + AUTH_PARAM_TYPE_DESC(AUTH_PARAM_RAW_DATA, 0); +static auth_param_type_desc_t content_cert = + AUTH_PARAM_TYPE_DESC(AUTH_PARAM_RAW_DATA, 0); +static auth_param_type_desc_t raw_data = + AUTH_PARAM_TYPE_DESC(AUTH_PARAM_RAW_DATA, 0); + +/* + * SoC Firmware + */ +static const auth_img_desc_t soc_fw_key_cert = { + .img_id = SOC_FW_KEY_CERT_ID, + .img_type = IMG_PLAT, + .parent = NULL, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &key_cert, + .data = { .ptr = (void *)soc_fw_key_cert_buf, + .len = (unsigned int)KEY_CERT_LEN } } } +}; + +static const auth_img_desc_t soc_fw_content_cert = { + .img_id = SOC_FW_CONTENT_CERT_ID, + .img_type = IMG_PLAT, + .parent = &soc_fw_key_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &content_cert, + .data = { .ptr = (void *)soc_fw_content_cert_buf, + .len = (unsigned int) + CONTENT_CERT_LEN } } } +}; + +/* + * BL31 + */ +static const auth_img_desc_t bl31_image = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &soc_fw_content_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_SBLIB, + .param.sblib = { .data = &raw_data, + .key_cert = &key_cert, + .content_cert = + &content_cert } } } +}; + +/* + * Trusted OS Firmware + */ +static const auth_img_desc_t trusted_os_fw_key_cert = { + .img_id = TRUSTED_OS_FW_KEY_CERT_ID, + .img_type = IMG_PLAT, + .parent = NULL, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &key_cert, + .data = { .ptr = (void *)tos_fw_key_cert_buf, + .len = (unsigned int)KEY_CERT_LEN } } } +}; + +static const auth_img_desc_t trusted_os_fw_content_cert = { + .img_id = TRUSTED_OS_FW_CONTENT_CERT_ID, + .img_type = IMG_PLAT, + .parent = &trusted_os_fw_key_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &content_cert, + .data = { .ptr = (void *)tos_fw_content_cert_buf, + .len = (unsigned int) + CONTENT_CERT_LEN } } } +}; + +/* + * BL32 + */ +static const auth_img_desc_t bl32_image = { + .img_id = BL32_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &trusted_os_fw_content_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_SBLIB, + .param.sblib = { .data = &raw_data, + .key_cert = &key_cert, + .content_cert = + &content_cert } } } +}; + +/* + * Non-Trusted Firmware + */ +static const auth_img_desc_t non_trusted_fw_key_cert = { + .img_id = NON_TRUSTED_FW_KEY_CERT_ID, + .img_type = IMG_PLAT, + .parent = NULL, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &key_cert, + .data = { .ptr = (void *)nt_fw_key_cert_buf, + .len = (unsigned int)KEY_CERT_LEN } } } +}; + +static const auth_img_desc_t non_trusted_fw_content_cert = { + .img_id = NON_TRUSTED_FW_CONTENT_CERT_ID, + .img_type = IMG_PLAT, + .parent = &non_trusted_fw_key_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_NONE }, + }, + .authenticated_data = + (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) { + [0] = { .type_desc = &content_cert, + .data = { .ptr = (void *)nt_fw_content_cert_buf, + .len = (unsigned int) + CONTENT_CERT_LEN } } } +}; + +/* + * BL33 + */ +static const auth_img_desc_t bl33_image = { + .img_id = BL33_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &non_trusted_fw_content_cert, + .img_auth_methods = + (const auth_method_desc_t[AUTH_METHOD_NUM]) { + [0] = { .type = AUTH_METHOD_SBLIB, + .param.sblib = { .data = &raw_data, + .key_cert = &key_cert, + .content_cert = + &content_cert } } } +}; + +static const auth_img_desc_t *const cot_desc[] = { + [SOC_FW_KEY_CERT_ID] = &soc_fw_key_cert, + [SOC_FW_CONTENT_CERT_ID] = &soc_fw_content_cert, + [BL31_IMAGE_ID] = &bl31_image, + [TRUSTED_OS_FW_KEY_CERT_ID] = &trusted_os_fw_key_cert, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = &trusted_os_fw_content_cert, + [BL32_IMAGE_ID] = &bl32_image, + [NON_TRUSTED_FW_KEY_CERT_ID] = &non_trusted_fw_key_cert, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = &non_trusted_fw_content_cert, + [BL33_IMAGE_ID] = &bl33_image, +}; + +/* Register the CoT in the authentication module */ +REGISTER_COT(cot_desc); + +#endif /* IMAGE_BL2 */ diff --git a/plat/renesas/rza/common/drivers/cpg.c b/plat/renesas/rza/common/drivers/cpg.c new file mode 100644 index 0000000000..eb3c0286c9 --- /dev/null +++ b/plat/renesas/rza/common/drivers/cpg.c @@ -0,0 +1,840 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include + +#define CPG_OFF (0) +#define CPG_ON (1) + +#define CPG_T_CLK (0) +#define CPG_T_RST (1) + +typedef struct { + uintptr_t reg; + uintptr_t mon; + uint32_t val; + uint32_t type; +} CPG_SETUP_DATA; + +typedef struct { + uintptr_t reg; + uint32_t val; +} CPG_REG_SETTING; + +typedef struct { + CPG_REG_SETTING clk1_dat; + CPG_REG_SETTING clk2_dat; + CPG_REG_SETTING stby_dat; +} CPG_PLL_SETDATA_146; + +typedef struct { + CPG_REG_SETTING clk1_dat; + CPG_REG_SETTING clk2_dat; + CPG_REG_SETTING clk3_dat; + CPG_REG_SETTING clk4_dat; + CPG_REG_SETTING clk5_dat; + CPG_REG_SETTING stby_dat; +} CPG_PLL_SETDATA_235; + +typedef struct st_cpg_spi_clk_table { + int frequency; + uint8_t selector; + uint8_t divider; +} cpg_spi_clk_table; + +static cpg_spi_clk_table cpg_xspi_table[] = { + { 533000000, 0, 0 }, /* 533.0MHz */ + { 400000000, 1, 0 }, /* 400.0MHz */ + { 266500000, 0, 1 }, /* 266.5MHz */ + { 200000000, 1, 1 }, /* 200.0MHz */ + { 133250000, 0, 2 }, /* 133.3MHz */ + { 100000000, 1, 2 }, /* 100.0MHz */ + { 66625000, 0, 3 }, /* 66.6MHz */ + { 50000000, 1, 3 }, /* 50.0MHz */ + { 16656250, 0, 4 }, /* 16.7MHz */ + { 12500000, 1, 4 }, /* 12.5MHz */ +}; + +#if USE_SDRAM +static CPG_PLL_SETDATA_146 cpg_pll4_setdata = { +#if (DDR_PLL4 == 1600) + { CPG_PLL4_CLK1, 0xFAE13203 }, + { CPG_PLL4_CLK2, 0x00081000 }, +#elif (DDR_PLL4 == 1333) + { CPG_PLL4_CLK1, 0xA66629C3 }, + { CPG_PLL4_CLK2, 0x00080D00 }, +#else +#error "Unknown Board Type." +#endif + { CPG_PLL4_STBY, 0x00010001 } +}; +#endif + +static CPG_PLL_SETDATA_146 cpg_pll6_setdata = { + { CPG_PLL6_CLK1, 0x00003e83 }, + { CPG_PLL6_CLK2, 0x00082D02 }, + { CPG_PLL6_STBY, 0x00010001 }, /* SSC OFF */ +}; + +#define CPG_PLL2_INDEX (0) +#define CPG_PLL3_INDEX (1) +#define CPG_PLL5_INDEX (2) + +static const CPG_SETUP_DATA early_setup_tbl[] = { + { (uintptr_t)CPG_CLKON_SYC, (uintptr_t)CPG_CLKMON_SYC, 0x00010001, + CPG_T_CLK }, + { (uintptr_t)CPG_RST_SYC, (uintptr_t)CPG_RSTMON_SYC, 0x00010001, + CPG_T_RST } +}; + +static CPG_SETUP_DATA cpg_clk_on_tbl[] = { + { /* CM33 */ + (uintptr_t)CPG_CLKON_CM33, (uintptr_t)CPG_CLKMON_CM33, 0x00030000, + CPG_T_CLK }, + { /* MHU */ + (uintptr_t)CPG_CLKON_MHU, (uintptr_t)CPG_CLKMON_MHU, 0x00010000, + CPG_T_CLK }, + { /* DMAC */ + (uintptr_t)CPG_CLKON_DAMC_REG, (uintptr_t)CPG_CLKMON_DAMC_REG, + 0x00030003, CPG_T_CLK }, + { /* OSTM */ + (uintptr_t)CPG_CLKON_OSTM, (uintptr_t)CPG_CLKMON_OSTM, 0x00060000, + CPG_T_CLK }, + { /* MTU */ + (uintptr_t)CPG_CLKON_MTU, (uintptr_t)CPG_CLKMON_MTU, 0x00010000, + CPG_T_CLK }, + { /* POE3 */ + (uintptr_t)CPG_CLKON_POE3, (uintptr_t)CPG_CLKMON_POE3, 0x00010000, + CPG_T_CLK }, + { /* WDT */ + (uintptr_t)CPG_CLKON_WDT, (uintptr_t)CPG_CLKMON_WDT, 0x00300000, + CPG_T_CLK }, +#if USE_SDRAM + { /* DDR */ + (uintptr_t)CPG_CLKON_DDR, (uintptr_t)CPG_CLKMON_DDR, 0x00030000, + CPG_T_CLK }, +#else + { /* DDR */ + (uintptr_t)CPG_CLKON_DDR, (uintptr_t)CPG_CLKMON_DDR, 0x00030003, + CPG_T_CLK }, +#endif + { /* SDHI */ + (uintptr_t)CPG_CLKON_SDHI, (uintptr_t)CPG_CLKMON_SDHI, +#if RZA3M + 0x000f0000, +#else + 0x00ff0000, +#endif + CPG_T_CLK }, + { /* Image Scaling Unit */ + (uintptr_t)CPG_CLKON_ISU, (uintptr_t)CPG_CLKMON_ISU, 0x00030000, + CPG_T_CLK }, + { /* Camera Data Receive Unit */ + (uintptr_t)CPG_CLKON_CRU, (uintptr_t)CPG_CLKMON_CRU, 0x001f0000, + CPG_T_CLK }, + { /* LCDC */ + (uintptr_t)CPG_CLKON_LCDC, (uintptr_t)CPG_CLKMON_LCDC, 0x00030000, + CPG_T_CLK }, + { /* Serial Sound Interface */ + (uintptr_t)CPG_CLKON_SSI, (uintptr_t)CPG_CLKMON_SSI, 0x00ff0000, + CPG_T_CLK }, + { /* Sampling Rate Converter */ + (uintptr_t)CPG_CLKON_SRC, (uintptr_t)CPG_CLKMON_SRC, 0x00010000, + CPG_T_CLK }, + { /* USB2.0 */ + (uintptr_t)CPG_CLKON_USB, (uintptr_t)CPG_CLKMON_USB, 0x000f0000, + CPG_T_CLK }, + { /* ETHER */ + (uintptr_t)CPG_CLKON_ETH, (uintptr_t)CPG_CLKMON_ETH, 0x00030000, + CPG_T_CLK }, + { /* I2C */ + (uintptr_t)CPG_CLKON_I2C, (uintptr_t)CPG_CLKMON_I2C, 0x000f0000, + CPG_T_CLK }, + { /* SCIF */ + (uintptr_t)CPG_CLKON_SCIF, (uintptr_t)CPG_CLKMON_SCIF, 0x001f0001, + CPG_T_CLK }, + { /* SCI */ + (uintptr_t)CPG_CLKON_SCI, (uintptr_t)CPG_CLKMON_SCI, 0x00030000, + CPG_T_CLK }, + { /* IrDA */ + (uintptr_t)CPG_CLKON_IRDA, (uintptr_t)CPG_CLKMON_IRDA, 0x00010000, + CPG_T_CLK }, + { /* SPI */ + (uintptr_t)CPG_CLKON_RSPI, (uintptr_t)CPG_CLKMON_RSPI, 0x00070000, + CPG_T_CLK }, + { /* CAN */ + (uintptr_t)CPG_CLKON_CANFD, (uintptr_t)CPG_CLKMON_CANFD, 0x00010000, + CPG_T_CLK }, + { /* GPIO */ + (uintptr_t)CPG_CLKON_GPIO, (uintptr_t)CPG_CLKMON_GPIO, 0x00010001, + CPG_T_CLK }, + { /* ADC */ + (uintptr_t)CPG_CLKON_ADC, (uintptr_t)CPG_CLKMON_ADC, 0x00030000, + CPG_T_CLK }, + { /* Thermal Sensor Unit */ + (uintptr_t)CPG_CLKON_TSU, (uintptr_t)CPG_CLKMON_TSU, 0x00010000, + CPG_T_CLK } +}; + +static CPG_SETUP_DATA cpg_reset_tbl[] = { + { /* CM33 */ + (uintptr_t)CPG_RST_CM33, (uintptr_t)CPG_RSTMON_CM33, 0x00070000, + CPG_T_RST }, + { /* MHU */ + (uintptr_t)CPG_RST_MHU, (uintptr_t)CPG_RSTMON_MHU, 0x00010000, + CPG_T_RST }, + { /* DMAC */ + (uintptr_t)CPG_RST_DMAC, (uintptr_t)CPG_RSTMON_DMAC, 0x00030003, + CPG_T_RST }, + { /* OSTM */ + (uintptr_t)CPG_RST_OSTM, (uintptr_t)CPG_RSTMON_OSTM, 0x00060000, + CPG_T_RST }, + { /* MTU */ + (uintptr_t)CPG_RST_MTU, (uintptr_t)CPG_RSTMON_MTU, 0x00010000, + CPG_T_RST }, + { /* POE3 */ + (uintptr_t)CPG_RST_POE3, (uintptr_t)CPG_RSTMON_POE3, 0x00010000, + CPG_T_RST }, + { /* WDT */ + (uintptr_t)CPG_RST_WDT, (uintptr_t)CPG_RSTMON_WDT, 0x00040000, + CPG_T_RST }, +#if USE_SDRAM + { /* DDR */ + (uintptr_t)CPG_RST_DDR, (uintptr_t)CPG_RSTMON_DDR, 0x007F0000, + CPG_T_RST }, +#else + { /* DDR */ + (uintptr_t)CPG_RST_DDR, (uintptr_t)CPG_RSTMON_DDR, 0x007F007F, + CPG_T_RST }, +#endif + { /* SDHI */ + (uintptr_t)CPG_RST_SDHI, (uintptr_t)CPG_RSTMON_SDHI, +#if RZA3M + 0x00010000, +#else + 0x00030000, +#endif + CPG_T_RST }, + { /* Image Scaling Unit */ + (uintptr_t)CPG_RST_ISU, (uintptr_t)CPG_RSTMON_ISU, 0x00030000, + CPG_T_RST }, + { /* Camera Data Receive Unit */ + (uintptr_t)CPG_RST_CRU, (uintptr_t)CPG_RSTMON_CRU, 0x00070000, + CPG_T_RST }, + { /* LCDC */ + (uintptr_t)CPG_RST_LCDC, (uintptr_t)CPG_RSTMON_LCDC, 0x00010000, + CPG_T_RST }, + { /* Serial Sound Interface */ + (uintptr_t)CPG_RST_SSIF, (uintptr_t)CPG_RSTMON_SSIF, 0x000f0000, + CPG_T_RST }, + { /* Sampling Rate Converter */ + (uintptr_t)CPG_RST_SRC, (uintptr_t)CPG_RSTMON_SRC, 0x00010000, + CPG_T_RST }, + { /* USB2.0 */ + (uintptr_t)CPG_RST_USB, (uintptr_t)CPG_RSTMON_USB, 0x000f0000, + CPG_T_RST }, + { /* ETHER */ + (uintptr_t)CPG_RST_ETH, (uintptr_t)CPG_RSTMON_ETH, 0x00030000, + CPG_T_RST }, + { /* I2C */ + (uintptr_t)CPG_RST_I2C, (uintptr_t)CPG_RSTMON_I2C, 0x000f0000, + CPG_T_RST }, + { /* SCIF */ + (uintptr_t)CPG_RST_SCIF, (uintptr_t)CPG_RSTMON_SCIF, 0x001f0001, + CPG_T_RST }, + { /* SCI */ + (uintptr_t)CPG_RST_SCI, (uintptr_t)CPG_RSTMON_SCI, 0x00030000, + CPG_T_RST }, + { /* IrDA */ + (uintptr_t)CPG_RST_IRDA, (uintptr_t)CPG_RSTMON_IRDA, 0x00010000, + CPG_T_RST }, + { /* SPI */ + (uintptr_t)CPG_RST_RSPI, (uintptr_t)CPG_RSTMON_RSPI, 0x00070000, + CPG_T_RST }, + { /* CAN */ + (uintptr_t)CPG_RST_CANFD, (uintptr_t)CPG_RSTMON_CANFD, 0x00030000, + CPG_T_RST }, + { /* GPIO */ + (uintptr_t)CPG_RST_GPIO, (uintptr_t)CPG_RSTMON_GPIO, 0x00070007, + CPG_T_RST }, + { /* ADC */ + (uintptr_t)CPG_RST_ADC, (uintptr_t)CPG_RSTMON_ADC, 0x00030000, + CPG_T_RST }, + { /* Thermal Sensor Unit */ + (uintptr_t)CPG_RST_TSU, (uintptr_t)CPG_RSTMON_TSU, 0x00010000, + CPG_T_RST }, +}; + +static CPG_REG_SETTING cpg_static_select_tbl[] = { + { (uintptr_t)CPG_PL3A_DDIV, 0x01000100 }, + { (uintptr_t)CPG_PL3_SSEL, 0x01000000 }, +}; + +static CPG_REG_SETTING cpg_dynamic_select_tbl[] = { + { (uintptr_t)CPG_PL4_DSEL, 0x00010001 }, +#if RZA3M + { (uintptr_t)CPG_PL2SDHI_DSEL, 0x00010003 }, + { (uintptr_t)CPG_PL2SDHI_DSEL, 0x00010002 }, +#else + { (uintptr_t)CPG_PL2SDHI_DSEL, 0x00110033 }, + { (uintptr_t)CPG_PL2SDHI_DSEL, 0x00110022 }, +#endif +}; + +#define CPG_SEL_PLL1_ON_OFF (0) +#define CPG_SEL_PLL2_1_ON_OFF (1) +#define CPG_SEL_PLL2_2_ON_OFF (2) +#define CPG_SEL_PLL3_1_ON_OFF (3) +#define CPG_SEL_PLL3_2_ON_OFF (4) +#define CPG_SEL_PLL3_3_ON_OFF (5) +#define CPG_SEL_PLL5_1_ON_OFF (6) +#define CPG_SEL_PLL5_3_ON_OFF (7) +#define CPG_SEL_PLL5_4_ON_OFF (8) + +static CPG_REG_SETTING cpg_sel_pll1_on_off[] = { { (uintptr_t)CPG_CLKON_CA55, + 0x00010001 } }; + +static CPG_REG_SETTING cpg_sel_pll2_1_on_off[] = { + { (uintptr_t)CPG_CLKON_ADC, 0x00010001 }, + { (uintptr_t)CPG_CLKON_TSU, 0x00010001 }, +#if RZA3M + { (uintptr_t)CPG_CLKON_SDHI, 0x000f0000 }, +#else + { (uintptr_t)CPG_CLKON_SDHI, 0x00ff0000 }, +#endif +}; + +static CPG_REG_SETTING cpg_sel_pll2_2_on_off[] = { +#if RZA3M + { (uintptr_t)CPG_CLKON_SDHI, 0x000f0000 }, +#else + { (uintptr_t)CPG_CLKON_SDHI, 0x00ff0000 }, +#endif +}; + +static CPG_REG_SETTING cpg_sel_pll3_1_on_off[] = { + { (uintptr_t)CPG_CLKON_AXI_ACPU_BUS, 0x000F000F }, + { (uintptr_t)CPG_CLKON_AXI_COM_BUS, 0x00030003 }, + { (uintptr_t)CPG_CLKON_AXI_DEFAULT_SLV, 0x00010001 }, + { (uintptr_t)CPG_CLKON_AXI_MCPU_BUS, 0x01930193 }, + { (uintptr_t)CPG_CLKON_AXI_TZCDDR, 0x001F001F }, + { (uintptr_t)CPG_CLKON_AXI_VIDEO_BUS, 0x00030003 }, + { (uintptr_t)CPG_CLKON_CA55, 0x001E001E }, + { (uintptr_t)CPG_CLKON_CM33, 0x00010001 }, + { (uintptr_t)CPG_CLKON_CRU, 0x000C000C }, + { (uintptr_t)CPG_CLKON_CST, 0x07FD07FD }, + { (uintptr_t)CPG_CLKON_DAMC_REG, 0x00030003 }, + { (uintptr_t)CPG_CLKON_DDR, 0x00030003 }, + { (uintptr_t)CPG_CLKON_ETH, 0x00030003 }, + { (uintptr_t)CPG_CLKON_GIC600, 0x00010001 }, + { (uintptr_t)CPG_CLKON_IA55, 0x00030003 }, + { (uintptr_t)CPG_CLKON_IM33, 0x00030003 }, + { (uintptr_t)CPG_CLKON_ISU, 0x00030003 }, + { (uintptr_t)CPG_CLKON_JAUTH, 0x00010001 }, + { (uintptr_t)CPG_CLKON_LCDC, 0x00010001 }, + { (uintptr_t)CPG_CLKON_OTP, 0x00020002 }, + { (uintptr_t)CPG_CLKON_PERI_COM, 0x00030003 }, + { (uintptr_t)CPG_CLKON_PERI_CPU, 0x000D000D }, + { (uintptr_t)CPG_CLKON_PERI_DDR, 0x00010001 }, + { (uintptr_t)CPG_CLKON_PERI_VIDEO, 0x00070007 }, + { (uintptr_t)CPG_CLKON_REG0_BUS, 0x00010001 }, + { (uintptr_t)CPG_CLKON_REG1_BUS, 0x00030003 }, + { (uintptr_t)CPG_CLKON_ROM, 0x00010001 }, +#if RZA3M + { (uintptr_t)CPG_CLKON_SDHI, 0x000f0000 }, +#else + { (uintptr_t)CPG_CLKON_SDHI, 0x00ff0000 }, +#endif + { (uintptr_t)CPG_CLKON_SRAM_ACPU, 0x00010001 }, + { (uintptr_t)CPG_CLKON_SRAM_MCPU, 0x00010001 }, + { (uintptr_t)CPG_CLKON_SYSC, 0x00020002 }, + { (uintptr_t)CPG_CLKON_TSIPG, 0x00030003 }, + { (uintptr_t)CPG_CLKON_USB, 0x000F000F } +}; + +static CPG_REG_SETTING cpg_sel_pll3_2_on_off[] = { + { (uintptr_t)CPG_CLKON_CRU, 0x00030003 }, + { (uintptr_t)CPG_CLKON_SPI_MULTI, 0x00030003 }, + { (uintptr_t)CPG_CLKON_AXI_MCPU_BUS, 0x02080208 }, +}; + +static CPG_REG_SETTING cpg_sel_pll3_3_on_off[] = { + { (uintptr_t)CPG_CLKON_SPI_MULTI, 0x00030003 }, + { (uintptr_t)CPG_CLKON_AXI_MCPU_BUS, 0x02080208 }, +}; + +static CPG_REG_SETTING cpg_sel_pll5_1_on_off[] = { + { (uintptr_t)CPG_CLKON_CRU, 0x00100010 }, + { (uintptr_t)CPG_CLKON_LCDC, 0x00020002 } +}; + +static CPG_REG_SETTING cpg_sel_pll5_3_on_off[] = { { (uintptr_t)CPG_CLKON_LCDC, + 0x00020002 } }; + +static CPG_REG_SETTING cpg_sel_pll5_4_on_off[] = { { (uintptr_t)CPG_CLKON_LCDC, + 0x00020002 } }; + +static void cpg_ctrl_clkrst(CPG_SETUP_DATA const *array, uint32_t num) +{ + int i; + uint32_t mask; + uint32_t cmp; + + for (i = 0; i < num; i++, array++) { + mmio_write_32(array->reg, array->val); + + mask = (array->val >> 16) & 0xFFFF; + cmp = array->val & 0xFFFF; + if (array->type == CPG_T_RST) { + cmp = ~(cmp); + } + while ((mmio_read_32(array->mon) & mask) != (cmp & mask)) + ; + } +} + +static void cpg_selector_on_off(uint32_t sel, uint8_t flag) +{ + uint32_t cnt; + uint32_t tbl_num; + CPG_REG_SETTING *ptr; + + switch (sel) { + case CPG_SEL_PLL1_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll1_on_off); + ptr = &cpg_sel_pll1_on_off[0]; + break; + case CPG_SEL_PLL2_1_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll2_1_on_off); + ptr = &cpg_sel_pll2_1_on_off[0]; + break; + case CPG_SEL_PLL2_2_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll2_2_on_off); + ptr = &cpg_sel_pll2_2_on_off[0]; + break; + case CPG_SEL_PLL3_1_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll3_1_on_off); + ptr = &cpg_sel_pll3_1_on_off[0]; + break; + case CPG_SEL_PLL3_2_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll3_2_on_off); + ptr = &cpg_sel_pll3_2_on_off[0]; + break; + case CPG_SEL_PLL3_3_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll3_3_on_off); + ptr = &cpg_sel_pll3_3_on_off[0]; + break; + case CPG_SEL_PLL5_1_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll5_1_on_off); + ptr = &cpg_sel_pll5_1_on_off[0]; + break; + case CPG_SEL_PLL5_3_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll5_3_on_off); + ptr = &cpg_sel_pll5_3_on_off[0]; + break; + case CPG_SEL_PLL5_4_ON_OFF: + tbl_num = ARRAY_SIZE(cpg_sel_pll5_4_on_off); + ptr = &cpg_sel_pll5_4_on_off[0]; + break; + default: + break; + } + + for (cnt = 0; cnt < tbl_num; cnt++) { + if (flag == CPG_ON) { + mmio_write_32(ptr[cnt].reg, + (mmio_read_32(ptr[cnt].reg) | + ptr[cnt].val)); + } else { + mmio_write_32(ptr[cnt].reg, + (ptr[cnt].val & 0xFFFF0000)); + } + } +} + +static void cpg_pll_start_146(CPG_PLL_SETDATA_146 *pdata) +{ + mmio_write_32(pdata->clk1_dat.reg, pdata->clk1_dat.val); + mmio_write_32(pdata->clk2_dat.reg, pdata->clk2_dat.val); + mmio_write_32(pdata->stby_dat.reg, pdata->stby_dat.val); +} + +/* It is assumed that the PLL has stopped by the time this function is executed. */ +static void cpg_pll_setup(void) +{ + uint32_t val = 0; +#if USE_SDRAM + /* PLL4 reset (RESET=0) */ + mmio_write_32(CPG_PLL4_STBY, PLL4_STBY_RESETB_WEN); + + /* PLL4 startup */ + /* PLL4 standby mode transition confirmation */ + do { + val = mmio_read_32(CPG_PLL4_MON); + } while ((val & (PLL4_MON_PLL4_RESETB | PLL4_MON_PLL4_LOCK)) != 0); +#endif + /* PLL6 reset (RESET=0) */ + mmio_write_32(CPG_PLL6_STBY, PLL6_STBY_RESETB_WEN); + + /* PLL6 startup */ + /* PLL6 standby mode transition confirmation */ + do { + val = mmio_read_32(CPG_PLL6_MON); + } while ((val & (PLL6_MON_PLL6_RESETB | PLL6_MON_PLL6_LOCK)) != 0); + +#if USE_SDRAM + /* Set PLL4 to normal mode */ + cpg_pll_start_146(&cpg_pll4_setdata); +#endif + /* Set PLL6 to normal mode */ + cpg_pll_start_146(&cpg_pll6_setdata); + +#if USE_SDRAM + /* PLL4 normal mode transition confirmation */ + do { + val = mmio_read_32(CPG_PLL4_MON); + } while ((val & (PLL4_MON_PLL4_RESETB | PLL4_MON_PLL4_LOCK)) == 0); +#endif +#if !(RZA3M) + /* PLL6 normal mode transition confirmation */ + do { + val = mmio_read_32(CPG_PLL6_MON); + } while ((val & (PLL6_MON_PLL6_RESETB | PLL6_MON_PLL6_LOCK)) == 0); +#endif +} + +static void cpg_div_sel_setup(CPG_REG_SETTING *tbl, uint32_t size) +{ + int cnt; + + for (cnt = 0; cnt < size; cnt++, tbl++) { + mmio_write_32(tbl->reg, tbl->val); + } + +#if USE_SDRAM + /* Wait for completion of settings */ + while (mmio_read_32(CPG_CLKSTATUS) != 0) + ; +#endif +} + +static void cpg_div_sel_static_setup(void) +{ + cpg_div_sel_setup(cpg_static_select_tbl, + ARRAY_SIZE(cpg_static_select_tbl)); +} + +static void cpg_div_sel_dynamic_setup(void) +{ + cpg_div_sel_setup(cpg_dynamic_select_tbl, + ARRAY_SIZE(cpg_dynamic_select_tbl)); +} + +static void cpg_clk_on_setup(void) +{ + cpg_ctrl_clkrst(&cpg_clk_on_tbl[0], ARRAY_SIZE(cpg_clk_on_tbl)); +} + +static void cpg_reset_setup(void) +{ + cpg_ctrl_clkrst(&cpg_reset_tbl[0], ARRAY_SIZE(cpg_reset_tbl)); +} + +void cpg_active_ddr(void (*disable_phy)(void)) +{ +#if RZA3M + /* Assert AXI_PERIDDR.RESTn according to APP006 */ + mmio_write_32(CPG_RST_PERI_DDR, 0x00010000); + while ((mmio_read_32(CPG_RSTMON_PERI_DDR) & 0x00000001) != 0x00000001) + ; +#endif + /* Assert the reset of DDRTOP */ + mmio_write_32(CPG_RST_DDR, 0x005F0000 | (CPG_RST_DDR_OPT_VALUE << 16)); + mmio_write_32(CPG_OTHERFUNC2_REG, 0x00010000); + while ((mmio_read_32(CPG_RSTMON_DDR) & 0x0000005F) != 0x0000005F) + ; + + /* Start the clocks of DDRTOP */ + mmio_write_32(CPG_CLKON_DDR, 0x00030003); + while ((mmio_read_32(CPG_CLKMON_DDR) & 0x00000003) != 0x00000003) + ; + + udelay(1); + +#if RZA3M + /* AXI_PERIDDR.RESTn according to APP006 */ + mmio_write_32(CPG_RST_PERI_DDR, 0x00010001); + while ((mmio_read_32(CPG_RSTMON_PERI_DDR) & 0x00000001) != 0x00000000) + ; +#endif + /* De-assert rst_n */ + mmio_write_32(CPG_OTHERFUNC2_REG, 0x00010001); + + udelay(1); + + /* De-assert PRESETN */ + mmio_write_32(CPG_RST_DDR, 0x00020002); + while ((mmio_read_32(CPG_RSTMON_DDR) & 0x00000002) != 0x00000000) + ; + + udelay(1); + + disable_phy(); + + /* De-assert axiY_ARESETn, regARESETn, reset_n */ + mmio_write_32(CPG_RST_DDR, 0x005D005D | (CPG_RST_DDR_OPT_VALUE << 16) | + CPG_RST_DDR_OPT_VALUE); + while ((mmio_read_32(CPG_RSTMON_DDR) & 0x0000005D) != 0x00000000) + ; + + udelay(1); +} + +void cpg_reset_ddr_mc(void) +{ +#if RZA3M + /* Assert AXI_PERIDDR.RESTn according to APP006 */ + mmio_write_32(CPG_RST_PERI_DDR, 0x00010000); + while ((mmio_read_32(CPG_RSTMON_PERI_DDR) & 0x00000001) != 0x00000001) + ; +#endif + /* Assert rst_n, axiY_ARESETn, regARESETn */ + mmio_write_32(CPG_RST_DDR, 0x005C0000 | (CPG_RST_DDR_OPT_VALUE << 16)); + mmio_write_32(CPG_OTHERFUNC2_REG, 0x00010000); + while ((mmio_read_32(CPG_RSTMON_DDR) & 0x0000005C) != 0x0000005C) + ; + + udelay(1); + +#if RZA3M + /* AXI_PERIDDR.RESTn according to APP006 */ + mmio_write_32(CPG_RST_PERI_DDR, 0x00010001); + while ((mmio_read_32(CPG_RSTMON_PERI_DDR) & 0x00000001) != 0x00000000) + ; +#endif + /* De-assert rst_n */ + mmio_write_32(CPG_OTHERFUNC2_REG, 0x00010001); + + udelay(1); + + /* De-assert axiY_ARESETn, regARESETn */ + mmio_write_32(CPG_RST_DDR, 0x005C005C | (CPG_RST_DDR_OPT_VALUE << 16) | + CPG_RST_DDR_OPT_VALUE); + while ((mmio_read_32(CPG_RSTMON_DDR) & 0x0000005C) != 0x00000000) + ; + + udelay(1); +} + +void cpg_early_setup(void) +{ + cpg_ctrl_clkrst(&early_setup_tbl[0], ARRAY_SIZE(early_setup_tbl)); +} + +void cpg_wdtrst_sel_setup(void) +{ + uint32_t reg; + reg = mmio_read_32(CPG_WDTRST_SEL); + reg |= WDTRST_SEL_WDTRSTSEL0 | WDTRST_SEL_WDTRSTSEL0_WEN; + + mmio_write_32(CPG_WDTRST_SEL, reg); +} + +void cpu_cpg_setup(void) +{ + while ((mmio_read_32(CPG_CLKSTATUS) & CLKSTATUS_DIVPL1_STS) != + 0x00000000) + ; + mmio_write_32(CPG_PL1_DDIV, + PL1_DDIV_DIVPL1_SET_WEN | PL1_DDIV_DIVPL1_SET_1_1); + while ((mmio_read_32(CPG_CLKSTATUS) & CLKSTATUS_DIVPL1_STS) != + 0x00000000) + ; +} + +void cpg_setup(void) +{ + cpu_cpg_setup(); + cpg_selector_on_off(CPG_SEL_PLL3_3_ON_OFF, CPG_OFF); + cpg_div_sel_static_setup(); + cpg_selector_on_off(CPG_SEL_PLL3_3_ON_OFF, CPG_ON); + cpg_pll_setup(); + cpg_clk_on_setup(); + cpg_reset_setup(); + cpg_div_sel_dynamic_setup(); + cpg_wdtrst_sel_setup(); +} + +static int cpg_search_spi_clk_table(int frequency) +{ + int tables = sizeof(cpg_xspi_table) / sizeof(cpg_xspi_table[0]); + for (int i = 0; i < tables; i++) { + if (frequency >= cpg_xspi_table[i].frequency) { + return i; + } + } + return -1; +} + +static int cpg_rsearch_spi_clk_table(uint8_t selector, uint8_t divider) +{ + int tables = sizeof(cpg_xspi_table) / sizeof(cpg_xspi_table[0]); + for (int i = 0; i < tables; i++) { + if (selector == cpg_xspi_table[i].selector && + divider == cpg_xspi_table[i].divider) { + return cpg_xspi_table[i].frequency; + } + } + return -1; +} + +static void wait_until_32(uintptr_t addr, uint32_t mask, uint32_t test) +{ + while ((mmio_read_32(addr) & mask) != test) { + }; +} + +static void cpg_stop_xspi_clock(xspi_clock spi) +{ + int onoff_pos; + uintptr_t clkon_ctrl; + uintptr_t clkmon_ctrl; + switch (spi) { + case XSPI_CLOCK_SPIM: + onoff_pos = 9; + clkon_ctrl = CPG_CLKON_SPI_MULTI; + clkmon_ctrl = CPG_CLKMON_SPI_MULTI; + break; + case XSPI_CLOCK_OCTA: + onoff_pos = 11; + clkon_ctrl = CPG_CLKON_OCTA; + clkmon_ctrl = CPG_CLKMON_OCTA; + break; + default: + ERROR("Not expected value %d passed to %s.", (int)spi, + __func__); + return; + } + + mmio_write_32(clkon_ctrl, 0x00030000); + mmio_write_32(CPG_CLKON_AXI_MCPU_BUS, 0x10000 << onoff_pos); + wait_until_32(CPG_CLKMON_AXI_MCPU_BUS, 1 << onoff_pos, 0); + wait_until_32(clkmon_ctrl, 0x0003, 0); +} + +static void cpg_start_xspi_clock(xspi_clock spi) +{ + int onoff_pos; + uintptr_t clkon_ctrl; + uintptr_t clkmon_ctrl; + switch (spi) { + case XSPI_CLOCK_SPIM: + onoff_pos = 9; + clkon_ctrl = CPG_CLKON_SPI_MULTI; + clkmon_ctrl = CPG_CLKMON_SPI_MULTI; + break; + case XSPI_CLOCK_OCTA: + onoff_pos = 11; + clkon_ctrl = CPG_CLKON_OCTA; + clkmon_ctrl = CPG_CLKMON_OCTA; + break; + default: + ERROR("Not expected value %d passed to %s.", (int)spi, + __func__); + return; + } + + mmio_write_32(clkon_ctrl, 0x0003ffff); + mmio_write_32(CPG_CLKON_AXI_MCPU_BUS, 0x10000 << onoff_pos | 0xffff); + wait_until_32(CPG_CLKMON_AXI_MCPU_BUS, 1 << onoff_pos, 1 << onoff_pos); + wait_until_32(clkmon_ctrl, 0x0003, 0x0003); +} + +int cpg_set_xspi_clock(xspi_clock spi, int frequency_hz) +{ + int seldiv_pos; + int status_pos; + + switch (spi) { + case XSPI_CLOCK_SPIM: + seldiv_pos = 8; + status_pos = 10; + break; + case XSPI_CLOCK_OCTA: + seldiv_pos = 12; + status_pos = 12; + break; + default: + ERROR("Not expected value %d passed to %s.", (int)spi, + __func__); + return -1; + } + + int index = cpg_search_spi_clk_table(frequency_hz); + if (index == -1) + ERROR("Not recognized frequency value %u passed to %s.", + frequency_hz, __func__); + + int prev_sel = (mmio_read_32(CPG_PL3_SSEL) >> seldiv_pos) & 1; + int prev_div = (mmio_read_32(CPG_PL3A_DDIV) >> seldiv_pos) & 7; + + if (prev_sel != cpg_xspi_table[index].selector) { + /* Changing static selector */ + cpg_stop_xspi_clock(spi); + uint32_t sel = cpg_xspi_table[index].selector << seldiv_pos; + sel |= 0x10000 << seldiv_pos; + mmio_write_32(CPG_PL3_SSEL, sel); + cpg_start_xspi_clock(spi); + } + + if (prev_div != cpg_xspi_table[index].divider) { + /* Changing dynamic divider */ + wait_until_32(CPG_CLKSTATUS, 1u << status_pos, 0); + uint32_t div = cpg_xspi_table[index].divider << seldiv_pos; + div |= 0x10000 << seldiv_pos; + mmio_write_32(CPG_PL3A_DDIV, div); + wait_until_32(CPG_CLKSTATUS, 1u << status_pos, 0); + } + + return 0; +} + +int cpg_get_xspi_clock(xspi_clock spi) +{ + uint8_t sel; + uint8_t div; + int seldiv_pos; + + switch (spi) { + case XSPI_CLOCK_SPIM: + seldiv_pos = 8; + break; + case XSPI_CLOCK_OCTA: + seldiv_pos = 12; + break; + default: + ERROR("Not expected value %d passed to %s.", (int)spi, + __func__); + return -1; + } + + sel = (uint8_t)((mmio_read_32(CPG_PL3_SSEL) >> seldiv_pos) & 1); + div = (uint8_t)((mmio_read_32(CPG_PL3A_DDIV) >> seldiv_pos) & 7); + + int frequency = cpg_rsearch_spi_clk_table(sel, div); + if (frequency == -1) + ERROR("CPG register value error (sel=%d, div=%d) in %s", sel, + div, __func__); + + return frequency; +} diff --git a/plat/renesas/rza/common/drivers/ddr/ddr.c b/plat/renesas/rza/common/drivers/ddr/ddr.c new file mode 100644 index 0000000000..7eaae34836 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/ddr.c @@ -0,0 +1,1083 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// include +#include +#include +#include +#include +#include + +#define CEIL(a, div) (((a) + ((div) - 1)) / (div)) +#define _MIN(a, b) ((a) < (b) ? (a) : (b)) +#define _MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define MAX_BYTE_LANES (2U) +#define MAX_BEST_VREF_SAVED (30U) +#define VREF_SETP (1U) + +extern const uint32_t mc_init_tbl[MC_INIT_NUM][2]; +extern const uint32_t mc_odt_pins_tbl[4]; +extern const uint32_t mc_mr1_tbl[2]; +extern const uint32_t mc_mr2_tbl[2]; +extern const uint32_t mc_mr5_tbl[2]; +extern const uint32_t mc_mr6_tbl[2]; +extern const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2]; +extern const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2]; +extern const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2]; +extern const char ddr_an_version[]; + +// prototypes +void ddr_setup(void); +static void disable_phy_clk(void); +static void program_mc1(uint8_t *lp_auto_entry_en); +static void program_phy1(uint32_t sl_lanes, uint32_t byte_lanes); +static void exec_trainingWRLVL(uint32_t sl_lanes); +static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes); +static void setup_vref_training_registers(uint8_t vref_value, uint8_t cs, + uint8_t turn_on_off_vref_training); +static void write_mr(uint8_t cs, uint8_t mrw_sel, uint16_t mrw_data); +static void exec_trainingBITLVL(uint32_t sl_lanes); +static void opt_delay(uint32_t sl_lanes, uint32_t byte_lanes); +static void exec_trainingSL(uint32_t sl_lanes); +static void program_phy2(void); +static void program_mc2(void); + +// main +void ddr_setup(void) +{ + uint32_t sl_lanes, byte_lanes; + uint8_t runBITLVL, runSL, runVREF; + uint8_t lp_auto_entry_en = 0; + uint32_t tmp; + int i; + + RZA_PRINTF("Setup DDR (Rev. %s)\n", ddr_an_version); + // Step2 - Step11 + cpg_active_ddr(disable_phy_clk); + + // Step12 + program_mc1(&lp_auto_entry_en); + + // Step13 + tmp = read_mc_reg(DDRMC_R019); + sl_lanes = ((tmp & 0x1) == 0) ? 3 : 1; + byte_lanes = ((tmp & 0x1) == 0) ? 2 : 1; + tmp = read_mc_reg(DDRMC_R039); + runBITLVL = (tmp >> 20) & 0x1; + runSL = (tmp >> 21) & 0x1; + runVREF = (tmp >> 25) & 0x1; + + // Step14 + program_phy1(sl_lanes, byte_lanes); + + // Step15 + while ((read_phy_reg(DDRPHY_R42) & 0x00000003) != sl_lanes) + ; + + // Step16 + ddr_ctrl_reten_en_n(0); + rmw_mc_reg(DDRMC_R007, 0xFFFFFEFF, 0x00000000); + rmw_mc_reg(DDRMC_R001, 0xFEFFFFFF, 0x01000000); + rmw_mc_reg(DDRMC_R000, 0xFFFFFFFE, 0x00000001); + while ((read_mc_reg(DDRMC_R021) & 0x02000000) != 0x02000000) + ; + rmw_phy_reg(DDRPHY_R74, 0xFFF7FFFF, 0x00080000); + rmw_mc_reg(DDRMC_R029, 0xFF0000FF, 64 << 8); + rmw_mc_reg(DDRMC_R027, 0xE00000FF, 111 << 8); + rmw_mc_reg(DDRMC_R020, 0xFFFFFEFF, 0x00000100); + udelay(1); + rmw_phy_reg(DDRPHY_R74, 0xFFF7FFFF, 0x00000000); + + // Step17 + cpg_reset_ddr_mc(); + ddr_ctrl_reten_en_n(1); + + // Step18-19 + program_mc1(&lp_auto_entry_en); + + // Step20 + for (i = 0; i < ARRAY_SIZE(swizzle_mc_tbl); i++) { + write_mc_reg(swizzle_mc_tbl[i][0], swizzle_mc_tbl[i][1]); + } + for (i = 0; i < ARRAY_SIZE(swizzle_phy_tbl); i++) { + write_phy_reg(swizzle_phy_tbl[i][0], swizzle_phy_tbl[i][1]); + } + + // Step21 + rmw_mc_reg(DDRMC_R000, 0xFFFFFFFE, 0x00000001); + + // Step22 + while ((read_mc_reg(DDRMC_R021) & 0x02000000) != 0x02000000) + ; + + // Step23 + rmw_mc_reg(DDRMC_R023, 0xFDFFFFFF, 0x02000000); + + // Step24 + exec_trainingWRLVL(sl_lanes); + + // Step25 + if (runVREF == 1) + exec_trainingVREF(sl_lanes, byte_lanes); + + // Step26 + if (runBITLVL == 1) + exec_trainingBITLVL(sl_lanes); + + // Step27 + opt_delay(sl_lanes, byte_lanes); + + // Step28 + if (runSL == 1) + exec_trainingSL(sl_lanes); + + // Step29 + program_phy2(); + + // Step30 + program_mc2(); + + // Step31 is skipped because ECC is unused. + + // Step32 + rmw_mc_reg(DDRMC_R006, 0xFFFFFFF0, lp_auto_entry_en & 0xF); +} + +static void disable_phy_clk(void) +{ + // Initialization Step9 + write_phy_reg(DDRPHY_R77, 0x00000200); + write_phy_reg(DDRPHY_R78, 0x00010001); +} + +static void program_mc1(uint8_t *lp_auto_entry_en) +{ + int i; + + // Step1 + for (i = 0; i < ARRAY_SIZE(mc_init_tbl); i++) { + if (mc_init_tbl[i][0] == DDRMC_R006) { + *lp_auto_entry_en = mc_init_tbl[i][1] & 0xF; + write_mc_reg(DDRMC_R006, + mc_init_tbl[i][1] & 0xFFFFFFF0); + } else { + write_mc_reg(mc_init_tbl[i][0], mc_init_tbl[i][1]); + } + } + + // Step2 + rmw_mc_reg(DDRMC_R025, 0xFCFFFFFF, mc_odt_pins_tbl[0] << 24); + rmw_mc_reg(DDRMC_R026, 0xFFFFFCFF, mc_odt_pins_tbl[1] << 8); + rmw_mc_reg(DDRMC_R025, 0xFFFCFFFF, mc_odt_pins_tbl[2] << 16); + rmw_mc_reg(DDRMC_R026, 0xFFFFFFFC, mc_odt_pins_tbl[3] << 0); + + // Step3 + rmw_mc_reg(DDRMC_R009, ~(mc_mr1_tbl[0]), mc_mr1_tbl[1]); + rmw_mc_reg(DDRMC_R011, ~(mc_mr1_tbl[0]), mc_mr1_tbl[1]); + + // Step4 + rmw_mc_reg(DDRMC_R010, ~(mc_mr2_tbl[0]), mc_mr2_tbl[1]); + rmw_mc_reg(DDRMC_R012, ~(mc_mr2_tbl[0]), mc_mr2_tbl[1]); + + // Step5 + rmw_mc_reg(DDRMC_R015, ~(mc_mr5_tbl[0]), mc_mr5_tbl[1]); + rmw_mc_reg(DDRMC_R016, ~(mc_mr5_tbl[0]), mc_mr5_tbl[1]); + + // Step6 + rmw_mc_reg(DDRMC_R017, ~(mc_mr6_tbl[0]), mc_mr6_tbl[1]); + rmw_mc_reg(DDRMC_R018, ~(mc_mr6_tbl[0]), mc_mr6_tbl[1]); + + // Step7 + for (i = 0; i < ARRAY_SIZE(mc_phy_settings_tbl); i++) { + write_mc_reg(mc_phy_settings_tbl[i][0], + mc_phy_settings_tbl[i][1]); + } + + // Step8 is skipped because ECC is unused. +} + +static void program_phy1(uint32_t sl_lanes, uint32_t byte_lanes) +{ + uint16_t dram_clk_period; + uint8_t dram; + uint8_t odt_wr_map_cs0, odt_rd_map_cs0; + uint8_t CL, CWL, AL, PL, RL, WL; + uint32_t mr1, mr1_wl, mr1_wl_mask; + uint32_t mr2, mr2_wl, mr2_wl_mask; + uint8_t clk_drive, dq_dqs_drive, dq_dqs_term, vref_value, vref_ca_value; +#if RZA3M + uint8_t adrctrl_drive; +#endif + uint8_t read_lat, trim_lat; + uint32_t tmp; + int i; + + // Step1 + tmp = read_mc_reg(DDRMC_R039); + dram_clk_period = tmp & 0xFFFF; + dram = (tmp >> 16) & 0xF; + + tmp = read_mc_reg(DDRMC_R025); + odt_wr_map_cs0 = (tmp >> 24) & 0x3; + odt_rd_map_cs0 = (tmp >> 16) & 0x3; + + // Step2 + tmp = read_mc_reg(DDRMC_R002); + CL = (tmp >> 17) & 0x1F; + CWL = (tmp >> 24) & 0x1F; + + tmp = read_mc_reg(DDRMC_R003); + AL = tmp & 0x1F; + PL = (tmp >> 8) & 0xF; + + RL = CL + AL + PL; + WL = CWL + AL + PL; + + // Step3 + mr1 = read_mc_reg(DDRMC_R009) & 0xFFFF; + mr2 = read_mc_reg(DDRMC_R010) & 0xFFFF; + if (dram == 2) { + // DDR4 + mr1_wl_mask = (0x7 << 8) | (0x1 << 7); // 0x78 + mr2_wl_mask = 0x7 << 9; // 0xe0 + switch ((mr2 & mr2_wl_mask) >> 9) { + case 0: + mr1_wl = 0x0; + mr1_wl_mask = 0x0000; + break; + case 1: + mr1_wl = 0x2 << 8; + break; + case 2: + mr1_wl = 0x4 << 8; + break; + case 4: + mr1_wl = 0x6 << 8; + break; + default: + panic(); + } + } else { + // DDR3L, DDR3 + mr1_wl_mask = (0x1 << 9) | (0x1 << 7) | (0x1 << 6) | (0x1 << 2); + mr2_wl_mask = 0x3 << 9; + switch ((mr2 & mr2_wl_mask) >> 9) { + case 0: + mr1_wl = 0x0; + mr1_wl_mask = 0x0000; + break; + case 1: + mr1_wl = (0x0 << 9) | (0x0 << 6) | (0x1 << 2); + break; + case 2: + mr1_wl = (0x0 << 9) | (0x1 << 6) | (0x0 << 2); + break; + default: + panic(); + } + } + mr1_wl |= (mr1 & (0xFFFF ^ mr1_wl_mask)) | (0x1 << 7); + mr2_wl = (mr2 & (0xFFFF ^ mr2_wl_mask)) | (0x0 << 9); + + // Step4 + tmp = read_mc_reg(DDRMC_R040); + clk_drive = tmp & 0xF; + dq_dqs_drive = (tmp >> 4) & 0xF; + dq_dqs_term = (tmp >> 8) & 0xF; +#if RZA3M + adrctrl_drive = (tmp >> 12) & 0xF; +#endif + vref_value = (tmp >> 16) & 0xFF; + vref_ca_value = (tmp >> 24) & 0xFF; + read_lat = (dram == 2 ? 12 : 10) + (CEIL(RL, 2) * 2) - CEIL(WL, 2) + 28; + trim_lat = (dram == 2 ? 11 : 9) + CEIL(RL, 2) - CEIL(WL, 2) + 29; + + // Step5 + tmp = ((WL == 5 ? 0x1 : 0x0) << 16) | 0x00100000; + write_phy_reg(DDRPHY_R77, tmp); + + // Step6 + write_phy_reg(DDRPHY_R05, 0x00000006); + + // Step7 + if (dram == 2) { + // DDR4 + write_phy_reg(DDRPHY_R65, 0x00000009); + } + + // Step8 + write_phy_reg(DDRPHY_R67, (dram == 2 ? 1 : 0) << 27); + write_phy_reg(DDRPHY_R47, (dram == 2 ? 1 : 0) << 24); + + // Step9 + tmp = ((dram == 0 ? 0 : 1) << 15) | + ((dram_clk_period < 1000 ? 1 : 0) << 8) | 0x10004000; + write_phy_reg(DDRPHY_R26, tmp); + + // Step10 +#if RZA3M + write_phy_reg(DDRPHY_R13, + clk_drive | (clk_drive << 4) | (adrctrl_drive << 8) | + (adrctrl_drive << 12) | (dq_dqs_drive << 16) | + (dq_dqs_drive << 20)); +#else + write_phy_reg(DDRPHY_R13, clk_drive | (clk_drive << 4) | + (clk_drive << 8) | (clk_drive << 12) | + (dq_dqs_drive << 16) | + (dq_dqs_drive << 20)); +#endif + + // Step11 + tmp = dq_dqs_term | ((dram == 2) ? 0 : (dq_dqs_term << 4)); + write_phy_reg(DDRPHY_R14, tmp); + + // Step12 + write_phy_reg(DDRPHY_R10, 0x00000000); + + // Step13 + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, 7 * i); + write_phy_reg(DDRPHY_R66, (vref_value << 4) | 0x00000004); + } + + // Step14 + write_phy_reg(DDRPHY_R12, vref_ca_value); + + // Step15 + write_phy_reg(DDRPHY_R61, 0x1A09002D); + + // Step16 + write_phy_reg(DDRPHY_R41, 0x00000000); + + // Step17 + write_phy_reg(DDRPHY_R74, 0x0000001A); + + // Step18 + tmp = ((dram == 2 ? 0 : 1) << 2) | (CEIL(CL, 2) << 4) | + (CEIL(AL, 2) << 8) | (odt_rd_map_cs0 << 16) | + (odt_wr_map_cs0 << 24) | 0x00000001; + write_phy_reg(DDRPHY_R24, tmp); + + // Step19 + tmp = (CEIL(CWL, 2) << 8) | ((((WL % 2) == 0) ? 0 : 1) << 24) | + 0x80000001; + write_phy_reg(DDRPHY_R25, tmp); + + // Step20 + write_phy_reg(DDRPHY_R45, sl_lanes ^ 0x3); + + // Step21 + write_phy_reg(DDRPHY_R64, (trim_lat << 4) | (read_lat << 12)); + + // Step22 + tmp = ((WL % 2) == 0) & 0x1; + write_phy_reg(DDRPHY_R63, tmp); + + // Step23 + write_phy_reg(DDRPHY_R72, 0x00000170); + + // Step24 + write_phy_reg(DDRPHY_R38, mr2_wl | (mr2 << 16)); + + // Step25 + write_phy_reg(DDRPHY_R39, mr1 | (mr1_wl << 16)); + + // Step26 + write_phy_reg(DDRPHY_R27, 0xAC001000); + + // Step27 + udelay(10); + + // Step28 is skipped because dll_mas_dly is unused. + + // Step29 + write_phy_reg(DDRPHY_R44, 0x00000000); + + // Step30 + write_phy_reg(DDRPHY_R43, 0x00000000); + + // Step31 + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, 6 * i); + write_phy_reg(DDRPHY_R30, 9); +#if RZA3M + write_phy_reg(DDRPHY_R32, + 14); //Changed from 10 to 14 according to APP_005 +#else + write_phy_reg(DDRPHY_R32, 10); +#endif + } + + // Step32 + write_phy_reg(DDRPHY_R28, 26 | 0x00000200); + + // Step33 + write_phy_reg(DDRPHY_R29, 0); +#if RZA3M + write_phy_reg(DDRPHY_R57, 29 | 0x00000080); +#else + write_phy_reg(DDRPHY_R57, 26 | 0x00000080); +#endif + + // Step34 + write_phy_reg(DDRPHY_R27, 26 | (0x10 << 8) | 0xAC000000); + + // Step35 + write_phy_reg(DDRPHY_R21, 0x00035076); + + // Step36 + write_phy_reg(DDRPHY_R07, 0x00000032); + + // lpddr4_combo_io_cal + { + // Step37-2 + rmw_phy_reg(DDRPHY_R47, 0xFF800000, 0x00000000); + + // Step37-3 + switch (dram) { + case 0: + tmp = 0x00003200; + break; + case 1: + tmp = 0x00005200; + break; + case 2: + tmp = 0x08009200; + break; + default: + tmp = 0x00000000; + break; + } + write_phy_reg(DDRPHY_R67, tmp); + write_phy_reg(DDRPHY_R46, 0x00000002); + while ((read_phy_reg(DDRPHY_R46) & 0x00000008) != 0x00000008) + ; + + write_phy_reg(DDRPHY_R46, 0x00000000); + udelay(100); + + // Step37-4 + switch (dram) { + case 0: + case 1: + tmp = 0x00041200; + break; + case 2: + tmp = 0x08101300; + break; + default: + tmp = 0x00000000; + break; + } + write_phy_reg(DDRPHY_R67, tmp); + write_phy_reg(DDRPHY_R46, 0x00000001); + while ((read_phy_reg(DDRPHY_R46) & 0x00000004) != 0x00000004) + ; + + rmw_phy_reg(DDRPHY_R46, 0xFFFFFFEF, 0x00000010); + rmw_phy_reg(DDRPHY_R46, 0xFFFFFFEF, 0x00000000); + udelay(1); + } + + // Step38 + rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x00000000); + + // Step39 + rmw_phy_reg(DDRPHY_R78, 0xFFFFF0FE, (sl_lanes << 8)); +} + +static void exec_trainingWRLVL(uint32_t sl_lanes) +{ + uint32_t tmp; + + // Step2 + tmp = read_phy_reg(DDRPHY_R24); + write_phy_reg(DDRPHY_R24, tmp | 0x01000000); + + // Step3 + write_phy_reg(DDRPHY_R37, sl_lanes); + + // Step4 + write_phy_reg(DDRPHY_R31, 0x00010000); + + // Step5 + write_phy_reg(DDRPHY_R18, 0x50200000); + + // Step6 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step7 - Step8 + if (((read_phy_reg(DDRPHY_R36) & sl_lanes) != sl_lanes) || + ((read_phy_reg(DDRPHY_R37) & sl_lanes) != 0)) { + panic(); + } + + // Step9 + write_phy_reg(DDRPHY_R24, tmp); +} + +static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) +{ + uint32_t vref_mid_level_code; + uint32_t vref_training_value; + uint32_t sweep_range; + uint16_t current_vref = 0; + uint32_t best_window_diff_so_far[MAX_BYTE_LANES]; + uint32_t num_best_vref_matches[MAX_BYTE_LANES]; + uint32_t all_best_vref_matches[MAX_BYTE_LANES][MAX_BEST_VREF_SAVED]; + uint8_t window_0, window_1, window_diff; + uint32_t highest_best_vref_val, lowest_best_vref_val; + uint8_t orig_cs_config; + uint32_t tmp; + int i, j; + + // Step2 + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, i); + rmw_phy_reg(DDRPHY_R07, 0xFFFFFFCF, 0x00000010); + } + // Step3 + vref_mid_level_code = (read_mc_reg(DDRMC_R040) >> 16) & 0xFF; + sweep_range = read_mc_reg(DDRMC_R043) & 0xFF; + + // Step4 + for (i = 0; i < byte_lanes; i++) { + best_window_diff_so_far[i] = 255; + num_best_vref_matches[i] = 0; + } + + // Step5 + for (vref_training_value = 0; + vref_training_value < (sweep_range * 2) + 1; + vref_training_value += VREF_SETP) { + // Step5.1 + if (vref_training_value < sweep_range + 1) { + if (vref_mid_level_code < vref_training_value + 2) { + vref_training_value = sweep_range; + continue; + } else { + current_vref = vref_mid_level_code - + vref_training_value; + } + } else { + if ((vref_mid_level_code + vref_training_value - + sweep_range) > 126) { + break; + } else { + current_vref = vref_mid_level_code + + vref_training_value - + sweep_range; + } + } + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, 7 * i); + write_phy_reg(DDRPHY_R66, + (current_vref << 4) | 0x00000001); + } + + // Step5.2 + write_phy_reg(DDRPHY_R18, 0x30800000); + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step5.3 + for (i = 0; i < byte_lanes; i++) { + if (((read_phy_reg(DDRPHY_R59) >> (14 + i)) & 0x1) == + 0x0) { + RZA_PRINTF_INFO( + "PHY side VREF training passed on lane %0d, current_vref = %0d\n", + i, current_vref); + write_phy_reg(DDRPHY_R29, i * 6); + window_0 = read_phy_reg(DDRPHY_R69) & 0x3F; + window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & + 0x3F; + window_diff = (window_0 > window_1) ? + window_0 - window_1 : + window_1 - window_0; + RZA_PRINTF_INFO( + "window_0 = %0d, window_1 = %0d, window_diff = %0d\n", + window_0, window_1, window_diff); + if (window_diff < best_window_diff_so_far[i]) { + best_window_diff_so_far[i] = + window_diff; + all_best_vref_matches[i][0] = + current_vref; + num_best_vref_matches[i] = 1; + RZA_PRINTF_INFO( + "CURRENT BEST VREF PHY side :%d\n", + current_vref); + } else if ((window_diff == + best_window_diff_so_far[i]) && + (num_best_vref_matches[i] < + MAX_BEST_VREF_SAVED)) { + all_best_vref_matches + [i][num_best_vref_matches[i]] = + current_vref; + num_best_vref_matches[i] += 1; + } + } else { + RZA_PRINTF_INFO( + "PHY side VREF training failed lane %d, current_vref = %d\n", + i, current_vref); + } + } + // Step5.4 + } + + // Step6 + for (i = 0; i < byte_lanes; i++) { + highest_best_vref_val = 0x0; + lowest_best_vref_val = 0x7F; + for (j = 0; j < num_best_vref_matches[i]; j++) { + highest_best_vref_val = + _MAX(all_best_vref_matches[i][j], + highest_best_vref_val); + lowest_best_vref_val = _MIN(all_best_vref_matches[i][j], + lowest_best_vref_val); + } + current_vref = (highest_best_vref_val + lowest_best_vref_val) >> + 1; + write_phy_reg(DDRPHY_R29, 7 * i); + write_phy_reg(DDRPHY_R66, current_vref << 4); + } + + // Step7 + write_phy_reg(DDRPHY_R19, 0xFF00FF00); + write_phy_reg(DDRPHY_R20, 0xFF00FF00); + + // Step8 + write_phy_reg(DDRPHY_R18, 0x30800000); + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step9 + tmp = (read_phy_reg(DDRPHY_R59) >> 14) & sl_lanes; + if ((tmp ^ sl_lanes) != sl_lanes) { + panic(); + } + + // Step10 + rmw_phy_reg(DDRPHY_R54, 0xFFFFFF7F, 0x00000080); + + // Step11 + vref_mid_level_code = (read_mc_reg(DDRMC_R043) >> 8) & 0xFF; + sweep_range = (read_mc_reg(DDRMC_R043) >> 16) & 0xFF; + + // Step12 + orig_cs_config = read_phy_reg(DDRPHY_R25) & 0x3; + + // Step13 + setup_vref_training_registers(vref_mid_level_code, sl_lanes, 1); + + // Step14 + rmw_phy_reg(DDRPHY_R66, 0xFFFFFFFE, 0x00000001); + + // Step15 + for (i = 0; i < byte_lanes; i++) { + best_window_diff_so_far[i] = 255; + num_best_vref_matches[i] = 0; + } + + // Step16 + for (vref_training_value = 0; + vref_training_value < (sweep_range * 2) + 1; + vref_training_value += VREF_SETP) { + // Step16.1 + if (vref_training_value < (sweep_range + 1)) { + if (vref_training_value > vref_mid_level_code) { + vref_training_value = sweep_range; + continue; + } else { + current_vref = vref_mid_level_code - + vref_training_value; + } + } else { + if ((vref_mid_level_code + vref_training_value - + sweep_range) <= 73) { + current_vref = vref_mid_level_code + + vref_training_value - + sweep_range; + } else { + break; + } + } + setup_vref_training_registers(current_vref, orig_cs_config, 0); + + // Step16.2 + write_phy_reg(DDRPHY_R18, 0x30500000); + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step16.3 + tmp = (read_phy_reg(DDRPHY_R64) >> 20) & sl_lanes; + for (i = 0; i < byte_lanes; i++) { + if ((tmp ^ sl_lanes) == sl_lanes) { + RZA_PRINTF_INFO( + "VREF training passed during VrefDQ training DRAM side, current_vref = %d\n", + current_vref); + write_phy_reg(DDRPHY_R29, i * 6); + window_0 = read_phy_reg(DDRPHY_R69) & 0x3F; + window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & + 0x3F; + window_diff = (window_0 > window_1) ? + window_0 - window_1 : + window_1 - window_0; + RZA_PRINTF_INFO( + "window_0 = %0d, window_1 = %0d, window_diff = %0d\n", + window_0, window_1, window_diff); + if (window_diff < best_window_diff_so_far[i]) { + best_window_diff_so_far[i] = + window_diff; + all_best_vref_matches[i][0] = + current_vref; + num_best_vref_matches[i] = 1; + RZA_PRINTF_INFO( + "CURRENT BEST VREF DRAM side :%d\n", + current_vref); + } else if ((window_diff == + best_window_diff_so_far[i]) && + (num_best_vref_matches[i] < + MAX_BEST_VREF_SAVED)) { + all_best_vref_matches + [i][num_best_vref_matches[i]] = + current_vref; + num_best_vref_matches[i] += 1; + } + } else { + RZA_PRINTF_INFO( + "VREF training failed during VrefDQ training DRAM side, current_vref = %d\n", + current_vref); + } + } + // Step16.4 + } + + // Step17 + highest_best_vref_val = 0x0; + lowest_best_vref_val = 0x7F; + for (i = 0; i < byte_lanes; i++) { + for (j = 0; j < num_best_vref_matches[i]; j++) { + highest_best_vref_val = + _MAX(all_best_vref_matches[i][j], + highest_best_vref_val); + lowest_best_vref_val = _MIN(all_best_vref_matches[i][j], + lowest_best_vref_val); + } + } + current_vref = (highest_best_vref_val + lowest_best_vref_val) >> 1; + + // Step18 + setup_vref_training_registers(current_vref, sl_lanes, 0); + + // Step19 + rmw_mc_reg(DDRMC_R044, 0xFFFFFF00, current_vref); + + // Step20 + rmw_phy_reg(DDRPHY_R66, 0xFFFFFFFE, 0x00000000); + + // Step21 + setup_vref_training_registers(current_vref, sl_lanes, 2); + + // Step22 + rmw_phy_reg(DDRPHY_R54, 0xFFFFFF7F, 0x00000000); + + // Step23 + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, i); + rmw_phy_reg(DDRPHY_R07, 0xFFFFFFCF, 0x00000030); + } +} + +static void setup_vref_training_registers(uint8_t vref_value, uint8_t cs, + uint8_t turn_on_off_vref_training) +{ + uint8_t vref_op_code; + uint16_t mr; + + // Step1 + if (vref_value > 50) { + vref_op_code = vref_value - 23; + } else { + vref_op_code = vref_value | (1 << 6); + } + + // Step2 + mr = read_mc_reg(DDRMC_R017) & 0xFF00; + write_mr(cs, 6, + mr | (((turn_on_off_vref_training == 2) ? 0 : 1) << 7) | + vref_op_code); + + // Step3 + udelay(1); +} + +static void write_mr(uint8_t cs, uint8_t mrw_sel, uint16_t mrw_data) +{ + uint8_t mrw_cs; + uint8_t mrw_allcs; + + // Step1 + mrw_cs = 0; + if (cs & 0x1) { + rmw_mc_reg(DDRMC_R013, 0xFFFF0000, mrw_data); + mrw_cs = 0; + } + if (cs & 0x2) { + rmw_mc_reg(DDRMC_R014, 0xFFFF0000, mrw_data); + mrw_cs = 1; + } + mrw_allcs = ((cs & 0x3) == 0x3) ? 1 : 0; + + // Step2 + rmw_mc_reg(DDRMC_R008, 0xFC000000, + 0x02800000 | (mrw_allcs << 24) | (mrw_cs << 8) | mrw_sel); + + // Step3 + while ((read_mc_reg(DDRMC_R022) & (1 << 3)) != (1 << 3)) + ; + + // Step4 + rmw_mc_reg(DDRMC_R024, 0xFFFFFFF7, 0x00000008); +} + +static void exec_trainingBITLVL(uint32_t sl_lanes) +{ + uint32_t tmp; + + // Step2 + write_phy_reg(DDRPHY_R62, 0x00000000); + + // Step3 + write_phy_reg(DDRPHY_R19, 0xFF00FF00); + write_phy_reg(DDRPHY_R20, 0xFF00FF00); + + // Step4 + write_phy_reg(DDRPHY_R18, 0x30A00000); + + // Step5 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step6 + tmp = (read_phy_reg(DDRPHY_R59) >> 14) & sl_lanes; + if ((tmp ^ sl_lanes) != sl_lanes) { + panic(); + } + + // Step7 + rmw_phy_reg(DDRPHY_R54, 0xFFFFFF7F, 0x00000080); + + // Step8 + write_phy_reg(DDRPHY_R18, 0x30700000); + + // Step9 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step10 + tmp = (read_phy_reg(DDRPHY_R64) >> 20) & sl_lanes; + if ((tmp ^ sl_lanes) != sl_lanes) { + panic(); + } + + // Step11 + rmw_phy_reg(DDRPHY_R54, 0xFFFFFF7F, 0x00000000); + + // Step12 + write_phy_reg(DDRPHY_R51, 0x00080000); + + // Step13 + write_phy_reg(DDRPHY_R18, 0x11200000); + + // Step14 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step15 + write_phy_reg(DDRPHY_R51, 0x00000000); + + // Step16 + write_phy_reg(DDRPHY_R18, 0x30A00000); + + // Step17 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; +} + +static void opt_delay(uint32_t sl_lanes, uint32_t byte_lanes) +{ + uint32_t tmp; + uint16_t dlls_trim_ca; +#if RZA3M + uint16_t dlls_trim_clk; +#endif + uint16_t dlls_trim_2[MAX_BYTE_LANES]; + uint16_t op_dqs_trim[MAX_BYTE_LANES]; + uint16_t min_WL; + uint16_t min_WD = 128; + int i, j; + + // Step2 + rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x04000000); + + // Step3 + rmw_mc_reg(DDRMC_R004, ~(0x7F << LP_CMD_OFFSET), + (0x00000011 << LP_CMD_OFFSET)); + while (((read_mc_reg(DDRMC_R005) >> 24) & 0x7F) != 0x48) + ; + + // Step4 + write_phy_reg(DDRPHY_R29, 0); +#if RZA3M + dlls_trim_clk = read_phy_reg(DDRPHY_R57) & 0x7F; + dlls_trim_ca = read_phy_reg(DDRPHY_R28) & 0x7F; + if (dlls_trim_clk <= dlls_trim_ca) { + panic(); + } +#else + dlls_trim_ca = read_phy_reg(DDRPHY_R57) & 0x7F; +#endif + min_WL = dlls_trim_ca; + + for (i = 0; i < byte_lanes; i++) { + write_phy_reg(DDRPHY_R29, 6 * i); + dlls_trim_2[i] = read_phy_reg(DDRPHY_R31) & 0x3F; + min_WL = _MIN(min_WL, dlls_trim_2[i]); + + write_phy_reg(DDRPHY_R29, (7 * i) | 0x00000900); + op_dqs_trim[i] = read_phy_reg(DDRPHY_R56) & 0x3F; + min_WD = _MIN(min_WD, op_dqs_trim[i]); + for (j = 0; j < 9; j++) { + write_phy_reg(DDRPHY_R29, (i * 7) | (j << 8)); + tmp = read_phy_reg(DDRPHY_R56) & 0x7F; + tmp = (tmp & 0x40) ? (op_dqs_trim[i] + (tmp & 0x3F)) : + (op_dqs_trim[i] - (tmp & 0x3F)); + min_WD = _MIN(min_WD, tmp); + } + } + + // Step5 +#if RZA3M + tmp = (dlls_trim_clk - min_WL) & 0x7F; +#else + tmp = (dlls_trim_ca - min_WL) & 0x7F; +#endif + write_phy_reg(DDRPHY_R29, 0); + write_phy_reg(DDRPHY_R57, tmp | 0x00000080); +#if RZA3M + tmp = (dlls_trim_ca - min_WL) & 0x7F; +#endif + write_phy_reg(DDRPHY_R28, tmp | 0x00000200); + rmw_phy_reg(DDRPHY_R27, 0xFFFFFF80, tmp); + + for (i = 0; i < byte_lanes; i++) { + tmp = (dlls_trim_2[i] - min_WL) & 0x3F; + write_phy_reg(DDRPHY_R29, 6 * i); + rmw_phy_reg(DDRPHY_R31, 0xFFFFFFC0, tmp); + + write_phy_reg(DDRPHY_R29, (7 * i) | 0x00000900); + tmp = (op_dqs_trim[i] - min_WD) & 0x3F; + rmw_phy_reg(DDRPHY_R56, 0xFFFFFF80, tmp); + } + + // Step6 + rmw_mc_reg(DDRMC_R004, ~(0x7F << LP_CMD_OFFSET), + (0x00000002 << LP_CMD_OFFSET)); + while (((read_mc_reg(DDRMC_R005) >> 24) & 0x7F) != 0x40) + ; + + // Step6 + rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x00000000); + while ((read_phy_reg(DDRPHY_R42) & 0x3) != sl_lanes) + ; +} + +static void exec_trainingSL(uint32_t sl_lanes) +{ + // Step2 + write_phy_reg(DDRPHY_R62, 0x00000001); + + // Step3 + write_phy_reg(DDRPHY_R34, 0x00000010); + + // Step4 + write_phy_reg(DDRPHY_R19, 0x789B3DE0); + write_phy_reg(DDRPHY_R20, 0xF10E4A56); + + // Step5 + write_phy_reg(DDRPHY_R18, 0x11200000); + + // Step6 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step7 + write_phy_reg(DDRPHY_R18, 0x11200000); + + // Step8 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step9 + write_phy_reg(DDRPHY_R18, 0x34200000); + + // Step10 + while ((read_phy_reg(DDRPHY_R18) & 0x10000000) != 0x00000000) + ; + + // Step11 + if ((read_phy_reg(DDRPHY_R18) & sl_lanes) != sl_lanes) { + panic(); + } + + // Step12 + write_phy_reg(DDRPHY_R62, 0x00000003); +} + +static void program_phy2(void) +{ + uint16_t dram_clk_period; + uint32_t tmp, b21, b22, b23; + + // Step1 + tmp = read_mc_reg(DDRMC_R039); + dram_clk_period = tmp & 0xFFFF; + b21 = (tmp >> 21) & 0x1; + b22 = (tmp >> 22) & 0x1; + b23 = (tmp >> 23) & 0x1; + + // Step2 + rmw_phy_reg(DDRPHY_R64, 0xFFFFFFFE, b23); + rmw_phy_reg(DDRPHY_R59, 0xFFFFFFFE, (b23 == 1 ? 0 : b22)); + write_phy_reg(DDRPHY_R55, + (b21 << 24) | + _MIN(1000000000000 / (2 * dram_clk_period * 256), + 0xFFFFFF)); + + // Step3 + rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x04000000); + rmw_phy_reg(DDRPHY_R27, 0xFC0000FF, + _MIN(1000000000000 / (dram_clk_period * 256), 0x3FFFF) + << 8); + rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x00000000); +} + +static void program_mc2(void) +{ + uint8_t main_clk_dly; + uint8_t tphy_rdlat; + uint32_t tmp; + + // Step1 + main_clk_dly = (read_phy_reg(DDRPHY_R21) >> 4) & 0xF; + tmp = (read_mc_reg(DDRMC_R028) >> 24) & 0x7F; + tphy_rdlat = ((main_clk_dly + 1 + 1) * 2) + 2 + ((tmp == 1) ? 2 : 0); + + // Step2 + rmw_mc_reg(DDRMC_R027, 0xFFFFFF80, tphy_rdlat & 0x7F); +} diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c new file mode 100644 index 0000000000..5b3245d3a9 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000266, 0x00000004 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000600, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_mr6_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_phy_settings_tbl[][2] = { { DDRMC_R040, 0x4F7F64A8 }, + { DDRMC_R041, 0x00003C30 }, + { DDRMC_R042, 0x00003C28 }, + { DDRMC_R043, 0x00000000 } }; + +const uint32_t swizzle_mc_tbl[][2] = { + { DDRMC_R030, 0x00000C0B }, { DDRMC_R031, 0x00001C00 }, + { DDRMC_R032, 0x17121500 }, { DDRMC_R033, 0x00140116 }, + { DDRMC_R034, 0x180E1300 }, { DDRMC_R035, 0x0D190F1B }, + { DDRMC_R036, 0x0A021E1A }, { DDRMC_R037, 0x21201F06 }, + { DDRMC_R038, 0x0000001D } +}; + +const uint32_t swizzle_phy_tbl[][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x19160018 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x05021714 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0F1D0307 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0E0D0C08 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x1B040106 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x09150A1A }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E0B1C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c new file mode 100644 index 0000000000..e103f016ff --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, + { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, + { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, + { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c new file mode 100644 index 0000000000..e103f016ff --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, + { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, + { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, + { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c new file mode 100644 index 0000000000..523323fa7b --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x576E08E8 }, + { DDRMC_R041, 0x00003C22 }, + { DDRMC_R042, 0x22227822 }, + { DDRMC_R043, 0x00123312 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00001502 }, { DDRMC_R031, 0x00000A06 }, + { DDRMC_R032, 0x170D1112 }, { DDRMC_R033, 0x1900130B }, + { DDRMC_R034, 0x1F09180C }, { DDRMC_R035, 0x161C0E14 }, + { DDRMC_R036, 0x01101B1A }, { DDRMC_R037, 0x001D051E }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x1B03150E }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x16001706 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D050807 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1901020B }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0F090418 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A0A1D14 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c new file mode 100644 index 0000000000..8084bbf476 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/V2L DDR config generation tool v1.13.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, + { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, + { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, + { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c new file mode 100644 index 0000000000..b431ccb485 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/V2L DDR config generation tool v1.13.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x576E08E8 }, + { DDRMC_R041, 0x00003C22 }, + { DDRMC_R042, 0x22227822 }, + { DDRMC_R043, 0x00123312 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00001502 }, { DDRMC_R031, 0x00000A06 }, + { DDRMC_R032, 0x170D1112 }, { DDRMC_R033, 0x1900130B }, + { DDRMC_R034, 0x1F09180C }, { DDRMC_R035, 0x161C0E14 }, + { DDRMC_R036, 0x01101B1A }, { DDRMC_R037, 0x001D051E }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x1B03150E }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x16001706 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D050807 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1901020B }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0F090418 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A0A1D14 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c new file mode 100644 index 0000000000..7c56f4fcef --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x576E08E8 }, + { DDRMC_R041, 0x00003C22 }, + { DDRMC_R042, 0x22227822 }, + { DDRMC_R043, 0x00123312 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000A02 }, { DDRMC_R031, 0x00000106 }, + { DDRMC_R032, 0x171E120B }, { DDRMC_R033, 0x1800000C }, + { DDRMC_R034, 0x00161C00 }, { DDRMC_R035, 0x0D1F1319 }, + { DDRMC_R036, 0x15101B1A }, { DDRMC_R037, 0x001D0509 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A020419 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x03161701 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D000807 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F0B0518 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x14091506 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D1B0E }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c new file mode 100644 index 0000000000..d926320749 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/V2L DDR config generation tool v1.13.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x576E08E8 }, + { DDRMC_R041, 0x00003C22 }, + { DDRMC_R042, 0x22227822 }, + { DDRMC_R043, 0x00123312 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000A02 }, { DDRMC_R031, 0x00000106 }, + { DDRMC_R032, 0x171E120B }, { DDRMC_R033, 0x1800000C }, + { DDRMC_R034, 0x00161C00 }, { DDRMC_R035, 0x0D1F1319 }, + { DDRMC_R036, 0x15101B1A }, { DDRMC_R037, 0x001D0509 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A020419 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x03161701 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D000807 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F0B0518 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x14091506 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D1B0E }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c new file mode 100644 index 0000000000..9281ec8aa9 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, + { DDRMC_R032, 0x1C191E13 }, { DDRMC_R033, 0x12000A18 }, + { DDRMC_R034, 0x100B1D00 }, { DDRMC_R035, 0x1F0C1B09 }, + { DDRMC_R036, 0x151A1614 }, { DDRMC_R037, 0x000D0E17 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A070E16 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x18140B08 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x00170409 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F030619 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x05020C0D }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A1501 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c new file mode 100644 index 0000000000..d7d27f7fd5 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, + { DDRMC_R032, 0x18171D1C }, { DDRMC_R033, 0x0D000A09 }, + { DDRMC_R034, 0x1F0B1000 }, { DDRMC_R035, 0x1E140E0C }, + { DDRMC_R036, 0x191A121B }, { DDRMC_R037, 0x00131516 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0C050D08 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0A17180B }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x190E0709 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F140206 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x03000416 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A1501 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c new file mode 100644 index 0000000000..b7a57fd36b --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; + +const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x57630BB8 }, + { DDRMC_R041, 0x00002828 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00102611 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, + { DDRMC_R032, 0x1E191117 }, { DDRMC_R033, 0x1D000A16 }, + { DDRMC_R034, 0x000B0D12 }, { DDRMC_R035, 0x1B180C1A }, + { DDRMC_R036, 0x15101C1F }, { DDRMC_R037, 0x00090E13 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A020B0F }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x18050E14 }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x16080603 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x190D0717 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x04090C00 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A1501 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c new file mode 100644 index 0000000000..e9daf72ff2 --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, + 0x00000000 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000266, 0x00000006 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000600, 0x00000000 }; + +const uint32_t mc_mr5_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_mr6_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x4F7F06E8 }, + { DDRMC_R041, 0x00002822 }, + { DDRMC_R042, 0x00003C22 }, + { DDRMC_R043, 0x00000000 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, + { DDRMC_R032, 0x151A2100 }, { DDRMC_R033, 0x00200014 }, + { DDRMC_R034, 0x1F1E1900 }, { DDRMC_R035, 0x000B120C }, + { DDRMC_R036, 0x000A1B17 }, { DDRMC_R037, 0x161D0F13 }, + { DDRMC_R038, 0x0000000D } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x17140B04 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0006070E }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D0A0818 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x19160201 }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x030C150F }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A0905 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } +}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c new file mode 100644 index 0000000000..9fcb87a46d --- /dev/null +++ b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const uint32_t mc_odt_pins_tbl[4] = { 0x00000002, 0x00000001, 0x00000002, + 0x00000001 }; + +const uint32_t mc_mr1_tbl[2] = { 0x00000266, 0x00000206 }; + +const uint32_t mc_mr2_tbl[2] = { 0x00000600, 0x00000200 }; + +const uint32_t mc_mr5_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_mr6_tbl[2] = { 0x00000000, 0x00000000 }; + +const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { + { DDRMC_R040, 0x4F7F01E8 }, + { DDRMC_R041, 0x00007822 }, + { DDRMC_R042, 0x1E1E3C22 }, + { DDRMC_R043, 0x00000000 } +}; + +const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { + { DDRMC_R030, 0x00000A00 }, { DDRMC_R031, 0x00001E00 }, + { DDRMC_R032, 0x1D131500 }, { DDRMC_R033, 0x00001217 }, + { DDRMC_R034, 0x180E2000 }, { DDRMC_R035, 0x0D1F0B1B }, + { DDRMC_R036, 0x021A1400 }, { DDRMC_R037, 0x0C1C0616 }, + { DDRMC_R038, 0x00000000 } +}; + +const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { + { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x19081815 }, + { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0702140B }, + { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x170D0309 }, + { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F00051D }, + { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, + { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0E160106 }, + { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x0A1A1B04 }, + { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E0C1C } +}; diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c b/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c new file mode 100644 index 0000000000..31ddf58bfa --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +static void emmc_little_to_big(uint8_t *p, uint32_t value) +{ + if (p == NULL) + return; + + p[0] = (uint8_t)(value >> 24); + p[1] = (uint8_t)(value >> 16); + p[2] = (uint8_t)(value >> 8); + p[3] = (uint8_t)value; +} + +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) + goto reset; + + /* wait CMDSEQ = 0 */ + while (loop > 0) { + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) + break; /* ready */ + + loop--; + if ((loop == 0) && (retry > 0)) { + udelay(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + +reset: + /* reset */ + SETR_32(SOFT_RST, (GETR_32(SOFT_RST) & (~SOFT_RST_SDRST))); + SETR_32(SOFT_RST, (GETR_32(SOFT_RST) | SOFT_RST_SDRST)); + + /* initialize */ + SETR_32(SD_INFO1, 0x00000000U); + SETR_32(SD_INFO2, SD_INFO2_CLEAR); + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ +} + +static void emmc_read_response(uint32_t *response) +{ + uint8_t *p; + + if (response == NULL) + return; + + /* read response */ + if (mmc_drv_obj.response_length != EMMC_MAX_RESPONSE_LENGTH) { + *response = GETR_32(SD_RSP10); /* [39:8] */ + return; + } + + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p, ((GETR_32(SD_RSP76) << 8) | + (GETR_32(SD_RSP54) >> 24))); /* [127:96] */ + emmc_little_to_big(p + 4, + ((GETR_32(SD_RSP54) << 8) | + (GETR_32(SD_RSP32) >> 24))); /* [95:64] */ + emmc_little_to_big(p + 8, + ((GETR_32(SD_RSP32) << 8) | + (GETR_32(SD_RSP10) >> 24))); /* [63:32] */ + emmc_little_to_big(p + 12, (GETR_32(SD_RSP10) << 8)); +} + +static EMMC_ERROR_CODE emmc_response_check(uint32_t *response, + uint32_t error_mask) +{ + HAL_MEMCARD_RESPONSE_TYPE response_type = + ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & + HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) + return EMMC_ERR_PARAM; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + return EMMC_SUCCESS; + + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) { + /* R1 or R1b */ + mmc_drv_obj.current_state = + (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> + EMMC_R1_STATE_SHIFT); + if ((*response & error_mask) != 0) { + if ((0x80 & *response) != 0) { + ERROR("BL2: emmc SWITCH_ERROR\n"); + } + return EMMC_ERR_CARD_STATUS_BIT; + } + return EMMC_SUCCESS; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R4) { + if ((*response & EMMC_R4_STATUS) != 0) + return EMMC_ERR_CARD_STATUS_BIT; + } + + return EMMC_SUCCESS; +} + +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL, wait = 0; + + dataL = GETR_32(SD_CLK_CTRL); + dataL &= 0x000000FF; + + switch (dataL) { + case 0xFF: + case 0x00: + case 0x01: + case 0x02: + case 0x04: + case 0x08: + case 0x10: + case 0x20: + wait = 10U; + break; + case 0x40: + wait = 20U; + break; + case 0x80: + wait = 30U; + break; + } + + udelay(wait); +} + +static void cmdErrSdInfo2Log(void) +{ + ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2); +} + +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + /* transfer complete interrupt enable */ + SETR_32(DM_CM_INFO1_MASK, + (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); + SETR_32(DM_CM_INFO2_MASK, + (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); + /* BUFF --> FIFO */ + SETR_32(DM_CM_DTRAN_MODE, + (DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH)); + } else { + /* transfer complete interrupt enable */ + SETR_32(DM_CM_INFO1_MASK, + (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); + SETR_32(DM_CM_INFO2_MASK, + (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); + /* FIFO --> BUFF */ + SETR_32(DM_CM_DTRAN_MODE, + (DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH)); + } + SETR_32(DM_DTRAN_ADDR, (((uintptr_t)mmc_drv_obj.buff_address_virtual & + DM_DTRAN_ADDR_WRITE_MASK))); + + SETR_32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); +} + +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) +{ + EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + uint32_t err_not_care_flag = FALSE; + + /* parameter check */ + if (response == NULL) { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & + HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = ((HAL_MEMCARD_COMMAND_TYPE)mmc_drv_obj.cmd_info.cmd & + HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { + /* The interrupt factor flag is observed. */ + emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) + continue; + + switch (state) { + case ESTATE_BEGIN: + /* Busy check */ + if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != + 0) { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, + EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + SETR_32(SD_INFO1, 0x00000000U); + SETR_32(SD_INFO2, SD_INFO2_CLEAR); + SETR_32(SD_INFO1_MASK, SD_INFO1_INFO0); + SETR_32(SD_INFO2_MASK, + (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); + + state = ESTATE_ISSUE_CMD; + /* fallthrough */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg); + /* issue cmd */ + SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.during_cmd_processing = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) { + state = ESTATE_NON_RESP_CMD; + } else { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == + 0) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { + if ((mmc_drv_obj.get_partition_access_flag == + TRUE) && + ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6) != + 0U)) { + err_not_care_flag = TRUE; + rtn_code = EMMC_ERR_CMD_TIMEOUT; + } else { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + } + state = ESTATE_ERROR; + break; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == + 0) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) { + /* R1b */ + SETR_32(SD_INFO2_MASK, + (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); + state = ESTATE_RCV_RESPONSE_BUSY; + } else { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != + 0) { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) { + state = ESTATE_DATA_TRANSFER; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { + /* DMA */ + emmc_data_transfer_dma(); + } else { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == + HAL_MEMCARD_WRITE) { + SETR_32(SD_INFO2_MASK, + (SD_INFO2_BWE | + SD_INFO2_ALL_ERR | + SD_INFO2_CLEAR)); + } else { + SETR_32(SD_INFO2_MASK, + (SD_INFO2_BRE | + SD_INFO2_ALL_ERR | + SD_INFO2_CLEAR)); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } else if (mmc_drv_obj.during_dma_transfer == TRUE) { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } else { + SETR_32(SD_INFO1_MASK, SD_INFO1_INFO2); + SETR_32(SD_INFO2_MASK, + (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { + /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); + SETR_32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); + SETR_32(SD_INFO1, 0x00000000U); + SETR_32(SD_INFO2, SD_INFO2_CLEAR); + + if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0) { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } else { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { + /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); + SETR_32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* fallthrough */ + + case ESTATE_ERROR: + if (err_not_care_flag == TRUE) { + mmc_drv_obj.during_cmd_processing = FALSE; + } else { + emmc_softreset(); + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, + rtn_code); + } + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) { + mmc_drv_obj.during_dma_transfer = FALSE; + } + ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n"); + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_config.h b/plat/renesas/rza/common/drivers/emmc/emmc_config.h new file mode 100644 index 0000000000..16b6b8aa9a --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_config.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_CONFIG_H +#define EMMC_CONFIG_H + +/* RCA */ +#define EMMC_RCA 1UL +/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_RW_DATA_TIMEOUT 0x40UL +/* how many times to try after fail. Don't change. */ +#define EMMC_RETRY_COUNT 0 +#define EMMC_CMD_MAX 60UL /* Don't change. */ + +#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL + +#endif /* EMMC_CONFIG_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_def.h b/plat/renesas/rza/common/drivers/emmc/emmc_def.h new file mode 100644 index 0000000000..46c45745f3 --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_def.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/** + * @file emmc_def.h + * @brief eMMC boot is expecting this header file + * + */ + +#ifndef EMMC_DEF_H +#define EMMC_DEF_H + +#include "emmc_std.h" + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define EMMC_POWER_ON (1U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/** @brief for assembler program + */ +uint32_t _rom_emmc_finalize(void); + +/** @brief eMMC driver API + */ +EMMC_ERROR_CODE emmc_init(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, + uint32_t sector_number, uint32_t count, + uint32_t feature_flags); +EMMC_ERROR_CODE emmc_write_sector(uint32_t *buff_address_virtual, + uint32_t sector_number, uint32_t count, + uint32_t feature_flags); +EMMC_ERROR_CODE emmc_erase_sector(uint32_t *start_address, + uint32_t *end_address); +uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom); + +/** @brief interrupt service + */ +uint32_t emmc_interrupt(void); + +/** @brief DMA + */ + +/** @brief send command API + */ +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, + uint32_t *buff_address_virtual, uint32_t len, + HAL_MEMCARD_OPERATION dir, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/** @brief for error information + */ +void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code); +void emmc_write_error_info_func_no(uint16_t func_no); + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_DEF_H */ +/* ******************************** END ************************************ */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_hal.h b/plat/renesas/rza/common/drivers/emmc/emmc_hal.h new file mode 100644 index 0000000000..0a8551719f --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_hal.h @@ -0,0 +1,535 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_HAL_H +#define EMMC_HAL_H + +/* memory card error/status types */ +#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L +#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L +#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L +#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L +#define HAL_MEMCARD_ERASE_PARAM 0x08000000L +#define HAL_MEMCARD_WP_VIOLATION 0x04000000L +#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L +#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L +#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L +#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L +#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L +#define HAL_MEMCARD_CC_ERROR 0x00100000L +#define HAL_MEMCARD_ERROR 0x00080000L +#define HAL_MEMCARD_UNDERRUN 0x00040000L +#define HAL_MEMCARD_OVERRUN 0x00020000L +#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L +#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L +#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L +#define HAL_MEMCARD_ERASE_RESET 0x00002000L +#define HAL_MEMCARD_CARD_STATE 0x00001E00L +#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L +#define HAL_MEMCARD_APP_CMD 0x00000020L +#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L +#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L +#define HAL_MEMCARD_NO_ERRORS 0x00000000L + +/* Memory card response types */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f + +/* Type of the return value. */ +typedef enum { + HAL_MEMCARD_FAIL = 0U, + HAL_MEMCARD_OK = 1U, + HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /* DMA channel allocation failed */ + HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /* DMA transfer failed */ + HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /* card status non-masked error */ + HAL_MEMCARD_CMD_TIMEOUT = 5U, /* Command timeout occurred */ + HAL_MEMCARD_DATA_TIMEOUT = 6U, /* Data timeout occurred */ + HAL_MEMCARD_CMD_CRC_ERROR = 7U, /* Command CRC error occurred */ + HAL_MEMCARD_DATA_CRC_ERROR = 8U /* Data CRC error occurred */ +} HAL_MEMCARD_RETURN; + +/* memory access operation */ +typedef enum { + HAL_MEMCARD_READ = 0U, /* read */ + HAL_MEMCARD_WRITE = 1U /* write */ +} HAL_MEMCARD_OPERATION; + +/* Type of data width on memorycard bus */ +typedef enum { + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */ + +/* Presence of the memory card */ +typedef enum { + HAL_MEMCARD_CARD_IS_IN = 0U, + HAL_MEMCARD_CARD_IS_OUT = 1U +} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */ + +/* mode of data transfer */ +typedef enum { + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + +/* Memory card response types. */ +typedef enum hal_memcard_response_type { + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + +/* Memory card command types. */ +typedef enum hal_memcard_command_type { + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/* Type of memory card */ +typedef enum hal_memcard_command_card_type { + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/* Memory card application command. */ +typedef enum hal_memcard_command_app_norm { + HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, + HAL_MEMCARD_COMMAND_APP = 0x20000U, + HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + +/* Memory card command codes. */ +typedef enum { +/* class 0 and class 1 */ + /* CMD0 */ + CMD0_GO_IDLE_STATE = + 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC | + (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD1 */ + CMD1_SEND_OP_COND = + 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD2 */ + CMD2_ALL_SEND_CID_MMC = + 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD2_ALL_SEND_CID_SD = + 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD3 */ + CMD3_SET_RELATIVE_ADDR = + 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SEND_RELATIVE_ADDR = + 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD4 */ + CMD4_SET_DSR = + 4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD5 */ + CMD5_SLEEP_AWAKE = + 5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD6 */ + CMD6_SWITCH = + 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD6_SWITCH_FUNC = + 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = + 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + /* CMD7 */ + CMD7_SELECT_CARD = + 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD7(from Disconnected State to Programming State) */ + CMD7_SELECT_CARD_PROG = + 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD7_DESELECT_CARD = + 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD8 */ + CMD8_SEND_EXT_CSD = + 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_IF_COND = + 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD9 */ + CMD9_SEND_CSD = + 9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD10 */ + CMD10_SEND_CID = + 10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD11 */ + CMD11_READ_DAT_UNTIL_STOP = + 11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD12 */ + CMD12_STOP_TRANSMISSION = + 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD12(R1b : write case) */ + CMD12_STOP_TRANSMISSION_WRITE = + 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD13 */ + CMD13_SEND_STATUS = + 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + ACMD13_SD_STATUS = + 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + /* CMD14 */ + CMD14_BUSTEST_R = + 14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD15 */ + CMD15_GO_INACTIVE_STATE = + 15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + +/* class 2 */ + /* CMD16 */ + CMD16_SET_BLOCKLEN = + 16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD17 */ + CMD17_READ_SINGLE_BLOCK = + 17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD18 */ + CMD18_READ_MULTIPLE_BLOCK = + 18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD19 */ + CMD19_BUS_TEST_W = + 19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + +/* class 3 */ + /* CMD20 */ + CMD20_WRITE_DAT_UNTIL_STOP = + 20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD21 */ + CMD21 = 21U, + /* CMD22 */ + CMD22 = 22U, + ACMD22_SEND_NUM_WR_BLOCKS = + 22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + /* CMD23 */ + CMD23_SET_BLOCK_COUNT = + 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + ACMD23_SET_WR_BLK_ERASE_COUNT = + 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + /* CMD24 */ + CMD24_WRITE_BLOCK = + 24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD25 */ + CMD25_WRITE_MULTIPLE_BLOCK = + 25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD26 */ + CMD26_PROGRAM_CID = + 26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD27 */ + CMD27_PROGRAM_CSD = + 27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + +/* class 6 */ + /* CMD28 */ + CMD28_SET_WRITE_PROT = + 28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD29 */ + CMD29_CLR_WRITE_PROT = + 29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD30 */ + CMD30_SEND_WRITE_PROT = + 30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD31 */ + CMD30_SEND_WRITE_PROT_TYPE = + 31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + +/* class 5 */ + /* CMD32 */ + CMD32_ERASE_WR_BLK_START = + 32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD33 */ + CMD33_ERASE_WR_BLK_END = + 33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD34 */ + CMD34 = 34U, + /* CMD35 */ + CMD35_ERASE_GROUP_START = + 35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD36 */ + CMD36_ERASE_GROUP_END = + 36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD37 */ + CMD37 = 37U, + /* CMD38 */ + CMD38_ERASE = + 38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + +/* class 9 */ + /* CMD39 */ + CMD39_FASTIO = + 39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD40 */ + CMD40_GO_IRQSTATE = + 40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD41 */ + CMD41 = 41, + ACMD41_SD_SEND_OP_COND = + 41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + +/* class 7 */ + /* CMD42 */ + CMD42_LOCK_UNLOCK = + 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + ACMD42_SET_CLR_CARD_DETECT = + 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + CMD43 = 43U, /* CMD43 */ + CMD44 = 44U, /* CMD44 */ + CMD45 = 45U, /* CMD45 */ + CMD46 = 46U, /* CMD46 */ + CMD47 = 47U, /* CMD47 */ + CMD48 = 48U, /* CMD48 */ + CMD49 = 49U, /* CMD49 */ + CMD50 = 50U, /* CMD50 */ + CMD51 = 51U, /* CMD51 */ + ACMD51_SEND_SCR = + 51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | + (uint32_t)HAL_MEMCARD_COMMAND_APP, + CMD52 = 52U, /* CMD52 */ + CMD53 = 53U, /* CMD53 */ + CMD54 = 54U, /* CMD54 */ + +/* class 8 */ + /* CMD55 */ + CMD55_APP_CMD = + 55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + /* CMD56 */ + CMD56_GEN_CMD = + 56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | + (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | + (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | + (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, + CMD57 = 57U, /* CMD57 */ + CMD58 = 58U, /* CMD58 */ + CMD59 = 59U, /* CMD59 */ + CMD60 = 60U, /* CMD60 */ + CMD61 = 61U, /* CMD61 */ + CMD62 = 62U, /* CMD62 */ + CMD63 = 63U /* CMD63 */ +} HAL_MEMCARD_COMMAND; + +/* + * Configuration structure from HAL layer. + * + * If some field is not available it should be filled with 0xFF. + * The API version is 32-bit unsigned integer telling the version of the API. + * The integer is divided to four sections which each can be treated as a 8-bit + * unsigned number: + * Bits 31-24 make the most significant part of the version number. This number + * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This + * number changes only, if the API itself changes so much that it is not + * compatible anymore with older releases. + * Bits 23-16 API minor version number. For example API version 2.1 would be + * 0x0201xxxx. + * Bits 15-8 are the number of the year when release is done. The 0 is year + * 2000, 1 is year 2001 and so on + * Bits 7- are the week number when release is done. First full week of the + * year is 1 + * + * Example: let's assume that release 2.1 is done on week 10 year 2008 + * the version will get the value 0x0201080A + */ +typedef struct { + /* + * Version of the chipset API implementation + * + * bits [31:24] API specification major version number.
+ * bits [23:16] API specification minor version number.
+ * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...) + * bits [7:0] API implementation week. + * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E + */ + uint32_t api_version; + + /* maximum block count which can be transferred at once */ + uint32_t max_block_count; + + /* maximum clock frequence in Hz supported by HW */ + uint32_t max_clock_freq; + + /* maximum data bus width supported by HW */ + uint16_t max_data_width; + + /* Is high-speed mode supported by HW (yes=1, no=0) */ + uint8_t hs_mode_supported; + + /* Is memory card removable (yes=1, no=0) */ + uint8_t card_removable; + +} HAL_MEMCARD_HW_CONF; + +/* Configuration structure to HAL layer. */ +typedef struct { + /* how many times to try after fail, for instance sending command */ + uint32_t retries_after_fail; +} HAL_MEMCARD_INIT_CONF; + +#endif /* EMMC_HAL_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_init.c b/plat/renesas/rza/common/drivers/emmc/emmc_init.c new file mode 100644 index 0000000000..49f687f8c4 --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_init.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +st_mmc_base mmc_drv_obj; + +EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode) +{ + if (mode == TRUE) { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } else { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} +static inline void emmc_set_retry_count(uint32_t retry) +{ + mmc_drv_obj.retries_after_fail = retry; +} + +static inline void emmc_set_data_timeout(uint32_t data_timeout) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +static void emmc_memset(uint8_t *buff, uint8_t data, uint32_t cnt) +{ + if (buff == NULL) { + return; + } + + while (cnt > 0) { + *buff++ = data; + cnt--; + } +} + +static void emmc_driver_config(void) +{ + emmc_set_retry_count(EMMC_RETRY_COUNT); + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + +static void emmc_drv_init(void) +{ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); + mmc_drv_obj.card_present = HAL_MEMCARD_CARD_IS_IN; + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result; + + /* + * MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + + /* host controller reset */ + SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ + + return result; +} + +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + /* MMCIF initialize */ + SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + + SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + SETR_32(SD_CLK_CTRL, + 0x00000000U); /* Disable Automatic Control & Clock Output */ + + return EMMC_SUCCESS; +} + +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE result; + + /* initialize mmc driver */ + emmc_drv_init(); + + /* initialize H/W */ + result = emmc_dev_init(); + if (result == EMMC_SUCCESS) { + mmc_drv_obj.initialize = TRUE; + } + + return result; +} + +EMMC_ERROR_CODE emmc_terminate(void) +{ + EMMC_ERROR_CODE result; + + result = emmc_dev_finalize(); + + emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); + + return result; +} + +EMMC_ERROR_CODE emmc_init(void) +{ + EMMC_ERROR_CODE result; + + result = emmc_reset_controller(); + if (result == EMMC_SUCCESS) { + emmc_driver_config(); + } + + return result; +} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c b/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c new file mode 100644 index 0000000000..2c3c67663d --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights + * reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); + +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result; + uint32_t end_bit = BIT20; + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = GETR_32(SD_INFO1); + mmc_drv_obj.error_info.info2 = GETR_32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & + GETR_32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & + GETR_32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = GETR_32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = GETR_32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = GETR_32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = GETR_32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & + GETR_32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & + GETR_32(DM_CM_INFO2_MASK); + + /* ERR SD_INFO2 */ + if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0) { + SETR_32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + SETR_32(SD_INFO1, 0x00000000U); /* interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* PIO Transfer */ + /* BWE/BRE */ + else if (((SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2)) { + /* BWE */ + if (SD_INFO2_BWE & mmc_drv_obj.int_event2) { + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE)); + } + /* BRE */ + else { + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE)); + } + + result = emmc_trans_sector(mmc_drv_obj.buff_address_virtual); + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if (result != EMMC_SUCCESS) { + /* data transfer error */ + emmc_write_error_info(EMMC_FUNCNO_NONE, result); + + /* Panic */ + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); + SETR_32(SD_INFO1, 0x00000000U); + /* interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR); + mmc_drv_obj.force_terminate = TRUE; + } else { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */ + else if ((BIT16 & mmc_drv_obj.dm_event1) != 0) { + SETR_32(DM_CM_INFO1, 0x00000000U); + SETR_32(DM_CM_INFO2, 0x00000000U); + /* interrupt clear */ + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE)); + /* DM_CM_INFO2: DMA-ch0 error occurred */ + if ((BIT16 & mmc_drv_obj.dm_event2) != 0) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + /* wait next interrupt */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */ + else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) { + SETR_32(DM_CM_INFO1, 0x00000000U); + SETR_32(DM_CM_INFO2, 0x00000000U); + /* interrupt clear */ + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE)); + /* DM_CM_INFO2: DMA-ch1 error occurred */ + if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + /* wait next interrupt */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* Response end */ + else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0) { + /* interrupt clear */ + SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO0)); + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0) { + /* interrupt clear */ + SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO2)); + mmc_drv_obj.state_machine_blocking = FALSE; + } else { + /* nothing to do. */ + } + + return (uint32_t)0; +} + +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) +{ + uint32_t length, i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || + (mmc_drv_obj.remain_size == 0)) { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t *)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i = 0; i < (length >> 3); i++) { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + SETR_64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else { + /* Checks when the read data reaches SD_SIZE. */ + /* The BRE bit is cleared at emmc_interrupt function. */ + if (((i % (uint32_t)(EMMC_BLOCK_LENGTH >> + EMMC_BUF_SIZE_SHIFT)) == 0U) && + (i != 0U)) { + /* BRE check */ + while (((GETR_32(SD_INFO2)) & SD_INFO2_BRE) == + 0U) { + /* ERROR check */ + if (((GETR_32(SD_INFO2)) & + SD_INFO2_ALL_ERR) != 0U) { + return EMMC_ERR_TRANSFER; + } + } + /* BRE clear */ + SETR_32(SD_INFO2, (uint32_t)(GETR_32(SD_INFO2) & + ~SD_INFO2_BRE)); + } + *bufPtrLL = GETR_64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_mount.c b/plat/renesas/rza/common/drivers/emmc/emmc_mount.c new file mode 100644 index 0000000000..ff01f7cb1d --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_mount.c @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode); +static EMMC_ERROR_CODE emmc_card_init(void); +static EMMC_ERROR_CODE emmc_high_speed(void); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(uint32_t *freq); +static void emmc_get_partition_access(void); +static void emmc_set_bootpartition(void); + +static void emmc_set_bootpartition(void) +{ + mmc_drv_obj.boot_partition_en = + (EMMC_PARTITION_ID)((mmc_drv_obj.ext_csd_data[179] & + EMMC_BOOT_PARTITION_EN_MASK) >> + EMMC_BOOT_PARTITION_EN_SHIFT); +} + +static EMMC_ERROR_CODE emmc_card_init(void) +{ + int32_t retry; + uint32_t freq = MMC_400KHZ; /* 390KHz */ + EMMC_ERROR_CODE result; + uint32_t result_calc; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || + (mmc_drv_obj.card_power_enable != TRUE) || + ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)) { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0; + mmc_drv_obj.max_freq = MMC_20MHZ; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return EMMC_ERR; + } + + udelay(1000U); /* wait 1ms */ + + /* Get current access partition */ + emmc_get_partition_access(); + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd(0x00000000); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + udelay(200U); /* wait 74clock 390kHz(189.74us) */ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry = 300; retry > 0; retry--) { + result = + emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0) { + break; /* card is ready. exit loop */ + } + udelay(1000U); /* wait 1ms */ + } + + if (retry == 0) { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + switch (mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) { + case EMMC_OCR_ACCESS_MODE_SECT: + mmc_drv_obj.access_mode = TRUE; /* sector mode */ + break; + default: + /* unknown value */ + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000); + mmc_drv_obj.response = + (uint32_t *)(&mmc_drv_obj + .cid_data[0]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* CMD9 (CSD) */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16); + mmc_drv_obj.response = + (uint32_t *)(&mmc_drv_obj + .csd_data[0]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4) { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, + EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* + * card speed check + * Card spec is calculated from TRAN_SPEED(CSD) + */ + result_calc = emmc_calc_tran_speed(&freq); + if (result_calc == 0) { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, + EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + SETR_32(SD_OPTION, + ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | + mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN(512byte) */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* Transfer Data Length */ + SETR_32(SD_SIZE, EMMC_BLOCK_LENGTH); + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, + (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, + HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* + * CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* Set boot partition */ + emmc_set_bootpartition(); + + return EMMC_SUCCESS; +} + +static EMMC_ERROR_CODE emmc_high_speed(void) +{ + uint32_t freq; /* High speed mode clock frequency */ + EMMC_ERROR_CODE result; + uint8_t cardType; + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + emmc_write_error_info(EMMC_FUNCNO_HIGH_SPEED, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* max frequency */ + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0) + freq = MMC_52MHZ; + else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0) + freq = MMC_26MHZ; + else + freq = MMC_20MHZ; + + /* Hi-Speed-mode selection */ + if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = + emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return result; + } + + mmc_drv_obj.hs_timing = TIMING_HIGH_SPEED; /* High-Speed */ + } + + /* set mmc clock */ + mmc_drv_obj.max_freq = freq; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + SETR_32(SD_OPTION, + ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | + mmc_drv_obj.data_timeout)); + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, + mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return result; + } + + return EMMC_SUCCESS; +} + +static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode) +{ + uint32_t value; + + /* busy check */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, + EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) { + /* clock ON */ + value = ((GETR_32(SD_CLK_CTRL) | MMC_SD_CLK_START) & + SD_CLK_WRITE_MASK); + SETR_32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } else { + /* clock OFF */ + value = ((GETR_32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & + SD_CLK_WRITE_MASK); + SETR_32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((width != 8) && (width != 4) && (width != 1)) { + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2); + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, (EMMC_SWITCH_BUS_WIDTH_1 | + (mmc_drv_obj.bus_width << 8))); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch (mmc_drv_obj.bus_width) { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + SETR_32(SD_OPTION, + ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT15)); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + SETR_32(SD_OPTION, (GETR_32(SD_OPTION) & ~(BIT15 | BIT13))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + SETR_32(SD_OPTION, + ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT13)); + break; + default: + goto EXIT; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, + (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, + HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result); + ERROR("BL2: emmc bus_width error end\n"); + return result; +} + +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) +{ + EMMC_ERROR_CODE result; + uint32_t arg; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id = PARTITION_ACCESS(Bit[2:0]) */ + if ((id & ~PARTITION_ID_MASK) != 0) { + emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = + (uint32_t) + mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & PARTITION_ID_MASK) == id) { + result = EMMC_SUCCESS; + } else { + partition_config = + (uint32_t)((partition_config & ~PARTITION_ID_MASK) | + id); + arg = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8); + + result = emmc_set_ext_csd(arg); + } + + return result; +} + +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (GETR_32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); + + switch (clkDiv) { + case 1: + dataL |= 0x000000FFU; + break; /* 1/1 */ + case 2: + dataL |= 0x00000000U; + break; /* 1/2 */ + case 4: + dataL |= 0x00000001U; + break; /* 1/4 */ + case 8: + dataL |= 0x00000002U; + break; /* 1/8 */ + case 16: + dataL |= 0x00000004U; + break; /* 1/16 */ + case 32: + dataL |= 0x00000008U; + break; /* 1/32 */ + case 64: + dataL |= 0x00000010U; + break; /* 1/64 */ + case 128: + dataL |= 0x00000020U; + break; /* 1/128 */ + case 256: + dataL |= 0x00000040U; + break; /* 1/256 */ + case 512: + dataL |= 0x00000080U; + break; /* 1/512 */ + } + + SETR_32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + +static void emmc_get_partition_access(void) +{ + EMMC_ERROR_CODE result; + + SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */ + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, + (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, + HAL_MEMCARD_NOT_DMA); + mmc_drv_obj.get_partition_access_flag = TRUE; + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + mmc_drv_obj.get_partition_access_flag = FALSE; + if (result == EMMC_SUCCESS) { + mmc_drv_obj.partition_access = + (EMMC_PARTITION_ID)(mmc_drv_obj.ext_csd_data[179] & + PARTITION_ID_MASK); + } else if (result == EMMC_ERR_CMD_TIMEOUT) { + mmc_drv_obj.partition_access = PARTITION_ID_BOOT_1; + } else { + emmc_write_error_info(EMMC_FUNCNO_GET_PERTITION_ACCESS, result); + panic(); + } + SETR_32(SD_OPTION, 0x0000C0EEU); /* Initialize */ +} + +static uint32_t emmc_calc_tran_speed(uint32_t *freq) +{ + const uint32_t unit[8] = { + 10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U + }; /* frequency unit (1/10) */ + const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, + 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U }; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + uint32_t max_freq; + uint32_t result; + + /* + * tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + result = 1; + max_freq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] * + mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> + EMMC_TRANSPEED_MULT_SHIFT]; + + if (max_freq == 0) { + result = 0; + } else if (max_freq >= MMC_FREQ_52MHZ) { + *freq = MMC_52MHZ; + } else if (max_freq >= MMC_FREQ_26MHZ) { + *freq = MMC_26MHZ; + } else if (max_freq >= MMC_FREQ_20MHZ) { + *freq = MMC_20MHZ; + } else { + *freq = MMC_400KHZ; + } + + return result; +} + +static uint32_t emmc_set_timeout_register_value(uint32_t freq) +{ + uint32_t timeout_cnt; /* SD_OPTION - Timeout Counter */ + + switch (freq) { + case 1U: + timeout_cnt = 0xE0U; + break; /* SDCLK * 2^27 */ + case 2U: + timeout_cnt = 0xE0U; + break; /* SDCLK * 2^27 */ + case 4U: + timeout_cnt = 0xD0U; + break; /* SDCLK * 2^26 */ + case 8U: + timeout_cnt = 0xC0U; + break; /* SDCLK * 2^25 */ + case 16U: + timeout_cnt = 0xB0U; + break; /* SDCLK * 2^24 */ + case 32U: + timeout_cnt = 0xA0U; + break; /* SDCLK * 2^23 */ + case 64U: + timeout_cnt = 0x90U; + break; /* SDCLK * 2^22 */ + case 128U: + timeout_cnt = 0x80U; + break; /* SDCLK * 2^21 */ + case 256U: + timeout_cnt = 0x70U; + break; /* SDCLK * 2^20 */ + case 512U: + timeout_cnt = 0x70U; + break; /* SDCLK * 2^20 */ + default: + timeout_cnt = 0xE0U; + break; /* SDCLK * 2^27 */ + } + + return timeout_cnt; +} + +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) +{ + EMMC_ERROR_CODE result; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, + (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, + HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + return EMMC_SUCCESS; +} + +EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq) +{ + /* parameter check */ + if (freq == NULL) { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || + (mmc_drv_obj.card_power_enable != TRUE)) { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ((mmc_drv_obj.clock_enable == TRUE) && + (mmc_drv_obj.current_freq == *freq)) { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, + EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || + (mmc_drv_obj.card_power_enable != TRUE) || + ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)) { + emmc_write_error_info(EMMC_FUNCNO_MOUNT, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { + /* nothing to do. */ + } + return result; + } + + /* Switching high speed mode */ + result = emmc_high_speed(); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { + /* nothing to do. */ + } + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8); + if (result != EMMC_SUCCESS) { + emmc_write_error_info_func_no(EMMC_FUNCNO_BUS_WIDTH); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { + /* nothing to do. */ + } + return result; + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_read.c b/plat/renesas/rza/common/drivers/emmc/emmc_read.c new file mode 100644 index 0000000000..03153827d1 --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_read.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b)) +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU + +static EMMC_ERROR_CODE +emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, + uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + EMMC_ERROR_CODE result; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0) || + ((transfer_mode != HAL_MEMCARD_DMA) && + (transfer_mode != HAL_MEMCARD_NOT_DMA))) { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + SETR_32(SD_SECCNT, count); + SETR_32(SD_STOP, 0x00000100); + /* SD_BUF Read/Write DMA Transfer enable */ + SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, + buff_address_virtual, + count << EMMC_SECTOR_SIZE_SHIFT, HAL_MEMCARD_READ, + transfer_mode); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; /* CMD18 error code */ + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + if (transfer_mode == HAL_MEMCARD_NOT_DMA) { + flush_dcache_range((uint64_t)buff_address_virtual, + ((size_t)count << EMMC_SECTOR_SIZE_SHIFT)); + } + + /* ready status check */ + if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0) { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, + EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* state check */ + if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, + EMMC_ERR_CARD_STATE); + return EMMC_ERR_CARD_STATE; + } + + return EMMC_SUCCESS; +} + +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, + uint32_t sector_number, uint32_t count, + uint32_t feature_flags) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result; + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; + + /* parameter check */ + if (count == 0) { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0) { + transfer_mode = HAL_MEMCARD_DMA; + } else { + transfer_mode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0) { + trans_count = MIN_EMMC(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, + sector_number, trans_count, + transfer_mode); + if (result != EMMC_SUCCESS) { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); + sector_number += trans_count; + remain -= trans_count; + } + + return EMMC_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_registers.h b/plat/renesas/rza/common/drivers/emmc/emmc_registers.h new file mode 100644 index 0000000000..0c28bc3626 --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_registers.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_REGISTERS_H +#define EMMC_REGISTERS_H + +/* MMC channel select */ +#define MMC_CH0 (0U) /* SDHI2/MMC0 */ +#define MMC_CH1 (1U) /* SDHI3/MMC1 */ + +#define USE_MMC_CH (MMC_CH0) + +#define BIT0 (0x00000001U) +#define BIT1 (0x00000002U) +#define BIT2 (0x00000004U) +#define BIT3 (0x00000008U) +#define BIT4 (0x00000010U) +#define BIT5 (0x00000020U) +#define BIT6 (0x00000040U) +#define BIT7 (0x00000080U) +#define BIT8 (0x00000100U) +#define BIT9 (0x00000200U) +#define BIT10 (0x00000400U) +#define BIT11 (0x00000800U) +#define BIT12 (0x00001000U) +#define BIT13 (0x00002000U) +#define BIT14 (0x00004000U) +#define BIT15 (0x00008000U) +#define BIT16 (0x00010000U) +#define BIT17 (0x00020000U) +#define BIT18 (0x00040000U) +#define BIT19 (0x00080000U) +#define BIT20 (0x00100000U) +#define BIT21 (0x00200000U) +#define BIT22 (0x00400000U) +#define BIT23 (0x00800000U) +#define BIT24 (0x01000000U) +#define BIT25 (0x02000000U) +#define BIT26 (0x04000000U) +#define BIT27 (0x08000000U) +#define BIT28 (0x10000000U) +#define BIT29 (0x20000000U) +#define BIT30 (0x40000000U) +#define BIT31 (0x80000000U) + + +/* eMMC registers */ +#define MMC0_SD_BASE (0x11C00000U) +#define MMC1_SD_BASE (0x11C10000U) + +#if USE_MMC_CH == MMC_CH0 +#define MMC_SD_BASE (MMC0_SD_BASE) +#else /* USE_MMC_CH == MMC_CH0 */ +#define MMC_SD_BASE (MMC1_SD_BASE) +#endif /* USE_MMC_CH == MMC_CH0 */ + +#define SD_CMD (MMC_SD_BASE + 0x0000U) +#define SD_PORTSEL (MMC_SD_BASE + 0x0008U) +#define SD_ARG (MMC_SD_BASE + 0x0010U) +#define SD_ARG1 (MMC_SD_BASE + 0x0018U) +#define SD_STOP (MMC_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC_SD_BASE + 0x0030U) +#define SD_RSP1 (MMC_SD_BASE + 0x0038U) +#define SD_RSP32 (MMC_SD_BASE + 0x0040U) +#define SD_RSP3 (MMC_SD_BASE + 0x0048U) +#define SD_RSP54 (MMC_SD_BASE + 0x0050U) +#define SD_RSP5 (MMC_SD_BASE + 0x0058U) +#define SD_RSP76 (MMC_SD_BASE + 0x0060U) +#define SD_RSP7 (MMC_SD_BASE + 0x0068U) +#define SD_INFO1 (MMC_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U) +#define SD_SIZE (MMC_SD_BASE + 0x0098U) +#define SD_OPTION (MMC_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC_SD_BASE + 0x00C0U) +#define SDIO_MODE (MMC_SD_BASE + 0x00D0U) +#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U) +#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U) +#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U) +#define SOFT_RST (MMC_SD_BASE + 0x0380U) +#define VERSION (MMC_SD_BASE + 0x0388U) +#define HOST_MODE (MMC_SD_BASE + 0x0390U) +#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U) +#define DM_CM_RST (MMC_SD_BASE + 0x0830U) +#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U) + +/* SD_INFO1 Registers */ +#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */ +#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */ +#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */ +#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */ +#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */ +#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */ +#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */ +#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */ +#define SD_INFO1_INFO2 0x00000004UL /* Access end */ +#define SD_INFO1_INFO0 0x00000001UL /* Response end */ + +/* SD_INFO2 Registers */ +#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */ +#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */ +#define SD_INFO2_SCLKDIVEN 0x00002000UL +#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */ +#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */ +#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */ +#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */ +#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */ +#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */ +#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */ +#define SD_INFO2_ERR2 0x00000004UL /* END Error */ +#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */ +#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */ +#define SD_INFO2_ALL_ERR 0x0000807FUL +#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */ + +/* SOFT_RST */ +#define SOFT_RST_SDRST 0x00000001UL + +/* SD_CLK_CTRL */ +#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL +#define SD_CLK_CTRL_SCLKEN 0x00000100UL +#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL +#define SD_CLOCK_ENABLE 0x00000100UL +#define SD_CLOCK_DISABLE 0x00000000UL +#define SD_CLK_WRITE_MASK 0x000003FFUL +#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL + +/* SD_OPTION */ +#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL + +/* + * MMC Clock Frequency + * (533MHz/4) * 1/x = output clock + */ +#define MMC_CLK_OFF 0UL /* Clock output is disabled */ +#define MMC_400KHZ 512UL /* (533MHz/4) * 1/512 = 260 KHz */ +#define MMC_20MHZ 8UL /* (533MHz/4) * 1/8 = 16.7 MHz Normal speed mode */ +#define MMC_26MHZ 8UL /* (533MHz/4) * 1/8 = 16.7 MHz High speed mode 26Mhz */ +#define MMC_52MHZ 4UL /* (533MHz/4) * 1/4 = 33.3 MHz High speed mode 52Mhz */ +#define MMC_100MHZ 2UL /* (533MHz/4) * 1/2 = 66.6 MHz */ +#define MMC_200MHZ 1UL /* (533MHz/4) * 1/1 = 133.3 MHz */ + +#define MMC_FREQ_52MHZ 52000000UL +#define MMC_FREQ_26MHZ 26000000UL +#define MMC_FREQ_20MHZ 20000000UL + +/* MMC Clock DIV */ +#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ +#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */ +#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */ +#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */ +#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */ +#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */ +#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */ +#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */ +#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */ +#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */ +#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */ + +/* DM_CM_DTRAN_MODE */ +#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */ +#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */ +#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL + +/* CC_EXT_MODE */ +#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */ + +/* DM_CM_INFO_MASK */ +#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL +#define DM_CM_INFO_CH0_ENABLE 0x00010001UL +#define DM_CM_INFO_CH1_ENABLE 0x00020001UL + +/* DM_DTRAN_ADDR */ +#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL + +/* DM_CM_DTRAN_CTRL */ +#define DM_CM_DTRAN_CTRL_START 0x00000001UL + +#endif /* EMMC_REGISTERS_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_std.h b/plat/renesas/rza/common/drivers/emmc/emmc_std.h new file mode 100644 index 0000000000..47d021c9ba --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_std.h @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef EMMC_STD_H +#define EMMC_STD_H + +#include "emmc_hal.h" + +#ifndef FALSE +#define FALSE 0U +#endif +#ifndef TRUE +#define TRUE 1U +#endif + +/* 64bit registers */ +#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) +#define GETR_64(r) (*(volatile uint64_t *)(r)) + +/* 32bit registers */ +#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) +#define GETR_32(r) (*(volatile uint32_t *)(r)) + +/* 16bit registers */ +#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) +#define GETR_16(r) (*(volatile uint16_t *)(r)) + +/* 8bit registers */ +#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) +#define GETR_8(r) (*(volatile uint8_t *)(r)) + +/* CSD register Macros */ +#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) + +#define EMMC_CID_MID() (EMMC_GET_CID(127, 120)) +#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112)) +#define EMMC_CID_OID() (EMMC_GET_CID(111, 104)) +#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88)) +#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56)) +#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48)) +#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16)) +#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8)) +#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1)) + +/* CSD register Macros */ +#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) + +#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126)) +#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122)) +#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112)) +#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104)) +#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96)) +#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84)) +#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80)) +#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79)) +#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78)) +#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77)) +#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76)) +#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62)) +#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59)) +#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56)) +#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53)) +#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50)) +#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47)) +#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42)) +#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37)) +#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32)) +#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31)) +#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29)) +#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26)) +#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22)) +#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21)) +#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16)) +#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15)) +#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14)) +#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13)) +#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12)) +#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10)) +#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8)) +#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1)) + +/* sector access */ +#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 +#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */ +#define EMMC_SECTOR_SIZE 512 +#define EMMC_BLOCK_LENGTH 512 +#define EMMC_BLOCK_LENGTH_DW 128 +#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */ + +/* eMMC specification clock */ +#define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */ +#define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */ +#define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */ +#define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */ +#define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */ + +/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ +typedef enum { + EMMC_ERR = 0, /* unknown error */ + EMMC_SUCCESS, /* OK */ + EMMC_ERR_FROM_DMAC, /* DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT, /* card status error */ + EMMC_ERR_CMD_TIMEOUT, /* command timeout error */ + EMMC_ERR_DATA_TIMEOUT, /* data timeout error */ + EMMC_ERR_CMD_CRC, /* command CRC error */ + EMMC_ERR_DATA_CRC, /* data CRC error */ + EMMC_ERR_PARAM, /* parameter error */ + EMMC_ERR_RESPONSE, /* response error */ + EMMC_ERR_RESPONSE_BUSY, /* response busy error */ + EMMC_ERR_TRANSFER, /* data transfer error */ + EMMC_ERR_READ_SECTOR, /* read sector error */ + EMMC_ERR_WRITE_SECTOR, /* write sector error */ + EMMC_ERR_STATE, /* state error */ + EMMC_ERR_TIMEOUT, /* timeout error */ + EMMC_ERR_ILLEGAL_CARD, /* illegal card */ + EMMC_ERR_CARD_BUSY, /* Busy state */ + EMMC_ERR_CARD_STATE, /* card state error */ + EMMC_ERR_SET_TRACE, /* trace information error */ + EMMC_ERR_FROM_TIMER, /* Timer error */ + EMMC_ERR_FORCE_TERMINATE, /* Force terminate */ + EMMC_ERR_CARD_POWER, /* card power fail */ + EMMC_ERR_ERASE_SECTOR, /* erase sector error */ + EMMC_ERR_INFO2 /* exec cmd error info2 */ +} EMMC_ERROR_CODE; + +/* Function number */ +#define EMMC_FUNCNO_NONE 0U +#define EMMC_FUNCNO_DRIVER_INIT 1U +#define EMMC_FUNCNO_CARD_POWER_ON 2U +#define EMMC_FUNCNO_MOUNT 3U +#define EMMC_FUNCNO_CARD_INIT 4U +#define EMMC_FUNCNO_HIGH_SPEED 5U +#define EMMC_FUNCNO_BUS_WIDTH 6U +#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U +#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U +#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U +#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U +#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U +#define EMMC_FUNCNO_SET_CLOCK 12U +#define EMMC_FUNCNO_EXEC_CMD 13U +#define EMMC_FUNCNO_READ_SECTOR 14U +#define EMMC_FUNCNO_WRITE_SECTOR 15U +#define EMMC_FUNCNO_ERASE_SECTOR 16U +#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U +/* + * Response + * R1 + * Type 'E' bit and bit14(must be 0). ignore bit22 + */ +#define EMMC_R1_ERROR_MASK 0xFDBFE080U +/* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) +#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */ +#define EMMC_R1_READY 0x00000100U /* bit8 */ +#define EMMC_R1_STATE_SHIFT 9 + +/* R4 */ +#define EMMC_R4_RCA_MASK 0xFFFF0000UL +#define EMMC_R4_STATUS 0x00008000UL + +/* CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */ +#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0 +#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT 3 + +/* OCR */ +#define EMMC_HOST_OCR_VALUE 0x40FF8080 +#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L +#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L + +/* EXT_CSD */ +#define EMMC_EXT_CSD_S_CMD_SET 504 +#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241 +#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239 +#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238 +#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235 +#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234 +#define EMMC_EXT_CSD_TRIM_MULT 232 +#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231 +#define EMMC_EXT_CSD_SEC_ERASE_MULT 229 +#define EMMC_EXT_CSD_BOOT_INFO 228 +#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226 +#define EMMC_EXT_CSD_ACC_SIZE 225 +#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224 +#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223 +#define EMMC_EXT_CSD_PEL_WR_SEC_C 222 +#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221 +#define EMMC_EXT_CSD_S_C_VCC 220 +#define EMMC_EXT_CSD_S_C_VCCQ 219 +#define EMMC_EXT_CSD_S_A_TIMEOUT 217 +#define EMMC_EXT_CSD_SEC_COUNT 215 +#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210 +#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209 +#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208 +#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207 +#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206 +#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205 +#define EMMC_EXT_CSD_PWR_CL_26_360 203 +#define EMMC_EXT_CSD_PWR_CL_52_360 202 +#define EMMC_EXT_CSD_PWR_CL_26_195 201 +#define EMMC_EXT_CSD_PWR_CL_52_195 200 +#define EMMC_EXT_CSD_CARD_TYPE 196 +#define EMMC_EXT_CSD_CSD_STRUCTURE 194 +#define EMMC_EXT_CSD_EXT_CSD_REV 192 +#define EMMC_EXT_CSD_CMD_SET 191 +#define EMMC_EXT_CSD_CMD_SET_REV 189 +#define EMMC_EXT_CSD_POWER_CLASS 187 +#define EMMC_EXT_CSD_HS_TIMING 185 +#define EMMC_EXT_CSD_BUS_WIDTH 183 +#define EMMC_EXT_CSD_ERASED_MEM_CONT 181 +#define EMMC_EXT_CSD_PARTITION_CONFIG 179 +#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178 +#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177 +#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175 +#define EMMC_EXT_CSD_BOOT_WP 173 +#define EMMC_EXT_CSD_USER_WP 171 +#define EMMC_EXT_CSD_FW_CONFIG 169 +#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168 +#define EMMC_EXT_CSD_RST_n_FUNCTION 162 +#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160 +#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159 +#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156 +#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155 +#define EMMC_EXT_CSD_GP_SIZE_MULT 154 +#define EMMC_EXT_CSD_ENH_SIZE_MULT 142 +#define EMMC_EXT_CSD_ENH_START_ADDR 139 +#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134 + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01 +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02 +#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04 +#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08 +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e + +/* SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (BIT25 | BIT24) +#define EXTCSD_SET_BITS BIT24 + +#define HS_TIMING_ADD (185 << 16) /* H'b9 */ +#define HS_TIMING_1 (1 << 8) +#define HS_TIMING_HS200 (2 << 8) +#define HS_TIMING_HS400 (3 << 8) + +#define BUS_WIDTH_ADD (183 << 16) /* H'b7 */ +#define BUS_WIDTH_1 (0 << 8) +#define BUS_WIDTH_4 (1 << 8) +#define BUS_WIDTH_8 (2 << 8) +#define BUS_WIDTH_4DDR (5 << 8) +#define BUS_WIDTH_8DDR (6 << 8) + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\ + HS_TIMING_1) /* H'03b90100 */ +#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\ + HS_TIMING_ADD) /* H'03b90000 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ + BUS_WIDTH_1) /* H'03b70000 */ +#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ + BUS_WIDTH_4) /* H'03b70100 */ +#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ + BUS_WIDTH_8) /* H'03b70200 */ +#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ + BUS_WIDTH_4DDR) /* H'03b70500 */ +#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ + BUS_WIDTH_8DDR) /* H'03b70600 */ +/* Partition config = 0x00 */ +#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL + +#define TIMING_HIGH_SPEED 1UL +#define EMMC_BOOT_PARTITION_EN_MASK 0x38U +#define EMMC_BOOT_PARTITION_EN_SHIFT 3U + +/* Bus width */ +#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT +#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT +#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT + +/* for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH 17 +#define EMMC_MAX_CID_LENGTH 16 +#define EMMC_MAX_CSD_LENGTH 16 +#define EMMC_MAX_EXT_CSD_LENGTH 512U +#define EMMC_RES_REG_ALIGNED 4U +#define EMMC_BUF_REG_ALIGNED 8U + +/* TAAC mask */ +#define TAAC_TIME_UNIT_MASK (0x07) +#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) + +/* Partition id */ +typedef enum { + PARTITION_ID_USER = 0x0, /* User Area */ + PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7, /* [2:0] */ +} EMMC_PARTITION_ID; + +/* card state in R1 response [12:9] */ +typedef enum { + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum { + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +} EMMC_INT_STATE; + +/* eMMC boot driver error information */ +typedef struct { + uint16_t num; /* error no */ + uint16_t code; /* error code */ + + volatile uint32_t info1; /* SD_INFO1. (hw dependent) */ + volatile uint32_t info2; /* SD_INFO2. (hw dependent) */ + volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */ + volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */ + volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */ + volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */ +} st_error_info; + +/* Command information */ +typedef struct { + HAL_MEMCARD_COMMAND cmd; /* Command information */ + uint32_t arg; /* argument */ + HAL_MEMCARD_OPERATION dir; /* direction */ + uint32_t hw; /* SD_CMD register value. */ +} st_command_info; + +/* MMC driver base */ +typedef struct { + st_error_info error_info; /* error information */ + st_command_info cmd_info; /* command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /* Dest or Src buff */ + uint32_t *buff_address_physical; /* Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */ + + uint32_t trans_size; /* transfer size for this command */ + uint32_t remain_size; /* remain size for this command */ + uint32_t response_length; /* response length for this command */ + uint32_t sector_size; /* sector_size */ + + /* clock */ + uint32_t base_clock; /* MMC host controller clock */ + /* + * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and + * EXT_CSD. + */ + uint32_t max_freq; + /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */ + uint32_t request_freq; + /* current MMC clock[Hz] (the closest frequency supported by HW) */ + uint32_t current_freq; + + /* state flag */ + /* presence status of the memory card */ + HAL_MEMCARD_PRESENCE_STATUS card_present; + + uint32_t card_power_enable; + uint32_t clock_enable; + /* True : initialize complete. */ + uint32_t initialize; + /* True : sector access, FALSE : byte access */ + uint32_t access_mode; + /* True : mount complete. */ + uint32_t mount; + /* True : selected card. */ + uint32_t selected; + /* 0: DMA, 1:PIO */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; + + /* loaded ISSW image No. ISSW have copy image. */ + uint32_t image_num; + /* card state */ + EMMC_R1_STATE current_state; + /* True : during command processing */ + volatile uint32_t during_cmd_processing; + /* True : during transfer */ + volatile uint32_t during_transfer; + /* True : during transfer (DMA) */ + volatile uint32_t during_dma_transfer; + /* True : occurred DMAC error */ + volatile uint32_t dma_error_flag; + /* force terminate flag */ + volatile uint32_t force_terminate; + /* state machine blocking flag : True or False */ + volatile uint32_t state_machine_blocking; + /* True : get partition access processing */ + volatile uint32_t get_partition_access_flag; + + EMMC_PARTITION_ID boot_partition_en; /* Boot partition */ + EMMC_PARTITION_ID partition_access; /* Current access partition */ + + /* timeout */ + uint32_t hs_timing; + + /* read and write data timeout */ + uint32_t data_timeout; + + /* retry */ + uint32_t retries_after_fail; + + /* interrupt */ + volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /* buffer ptr for executing command. */ + uint32_t r1_card_status; /* R1 response data */ + uint32_t r3_ocr; /* R3 response data */ + uint32_t r4_resp; /* R4 response data */ + uint32_t r5_resp; /* R5 response data */ + + /* True : clock mode is low. (MMC clock = Max26MHz) */ + uint32_t low_clock_mode_enable; + + uint32_t reserved2; + uint32_t reserved3; + uint32_t reserved4; + + /* CSD registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); + /* CID registers (4byte align) */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); + /* EXT CSD registers (8byte align) */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */ + __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED))); + /* Response registers (4byte align) */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); +} st_mmc_base; + +typedef int (*func) (void); + +uint32_t emmc_get_csd_time(void); + +#define MMC_DEBUG +#endif /* EMMC_STD_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_utility.c b/plat/renesas/rza/common/drivers/emmc/emmc_utility.c new file mode 100644 index 0000000000..632ba73c66 --- /dev/null +++ b/plat/renesas/rza/common/drivers/emmc/emmc_utility.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_registers.h" +#include "emmc_std.h" + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = { + 0x00000000, /* CMD0 */ + 0x00000701, /* CMD1 */ + 0x00000002, /* CMD2 */ + 0x00000003, /* CMD3 */ + 0x00000004, /* CMD4 */ + 0x00000505, /* CMD5 */ + 0x00000406, /* CMD6 */ + 0x00000007, /* CMD7 */ + 0x00001C08, /* CMD8 */ + 0x00000009, /* CMD9 */ + 0x0000000A, /* CMD10 */ + 0x00000000, /* reserved */ + 0x0000000C, /* CMD12 */ + 0x0000000D, /* CMD13 */ + 0x00001C0E, /* CMD14 */ + 0x0000000F, /* CMD15 */ + 0x00000010, /* CMD16 */ + 0x00000011, /* CMD17 */ + 0x00007C12, /* CMD18 */ + 0x00000C13, /* CMD19 */ + 0x00000000, 0x00001C15, /* CMD21 */ + 0x00000000, 0x00000017, /* CMD23 */ + 0x00000018, /* CMD24 */ + 0x00006C19, /* CMD25 */ + 0x00000C1A, /* CMD26 */ + 0x0000001B, /* CMD27 */ + 0x0000001C, /* CMD28 */ + 0x0000001D, /* CMD29 */ + 0x0000001E, /* CMD30 */ + 0x00001C1F, /* CMD31 */ + 0x00000000, 0x00000000, 0x00000000, 0x00000423, /* CMD35 */ + 0x00000424, /* CMD36 */ + 0x00000000, 0x00000026, /* CMD38 */ + 0x00000427, /* CMD39 */ + 0x00000428, /* CMD40(send cmd) */ + 0x00000000, 0x0000002A, /* CMD42 */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000C31, 0x00000000, 0x00000000, 0x00000000, + 0x00007C35, 0x00006C36, 0x00000037, /* CMD55 */ + 0x00000038, /* CMD56(Read) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000 +}; + +uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15 - (top >> 3)); + uint32_t index_bottom = (uint32_t)(15 - (bottom >> 3)); + + if (index_top == index_bottom) { + value = data[index_top]; + } else if ((index_top + 1) == index_bottom) { + value = (uint32_t)((data[index_top] << 8) | data[index_bottom]); + } else if ((index_top + 2) == index_bottom) { + value = (uint32_t)((data[index_top] << 16) | + (data[index_top + 1] << 8) | + data[index_top + 2]); + } else { + value = (uint32_t)((data[index_top] << 24) | + (data[index_top + 1] << 16) | + (data[index_top + 2] << 8) | + data[index_top + 3]); + } + + value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); + + return value; +} + +void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code) +{ + mmc_drv_obj.error_info.num = func_no; + mmc_drv_obj.error_info.code = (uint16_t)error_code; + + ERROR("BL2: emmc err:func_no=0x%x code=0x%x\n", func_no, error_code); +} + +void emmc_write_error_info_func_no(uint16_t func_no) +{ + mmc_drv_obj.error_info.num = func_no; + + ERROR("BL2: emmc err:func_no=0x%x\n", func_no); +} + +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = + cmd_reg_hw[cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0; + mmc_drv_obj.remain_size = 0; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6; + + switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, + uint32_t *buff_address_virtual, uint32_t len, + HAL_MEMCARD_OPERATION dir, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) +{ + EMMC_ERROR_CODE result; + uint32_t freq; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* change MMC clock(400KHz) */ + freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + return result; + } + + return EMMC_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/io/io_emmcdrv.c b/plat/renesas/rza/common/drivers/io/io_emmcdrv.c new file mode 100644 index 0000000000..dd14c68ff5 --- /dev/null +++ b/plat/renesas/rza/common/drivers/io/io_emmcdrv.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +#include "emmc_config.h" +#include "emmc_def.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "io_common.h" +#include "io_emmcdrv.h" +#include "io_private.h" + +static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__((unused)), + io_dev_info_t **dev_info); +static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info); + +typedef struct { + uint32_t in_use; + uintptr_t base; + signed long long file_pos; + EMMC_PARTITION_ID partition; +} file_state_t; + +static file_state_t current_file = { 0 }; + +static io_type_t device_type_emmcdrv(void) +{ + return IO_TYPE_MEMMAP; +} + +static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, + signed long long offset) +{ + if (mode != IO_SEEK_SET) { + return IO_FAIL; + } + + ((file_state_t *)entity->info)->file_pos = offset; + + return IO_SUCCESS; +} + +static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp = (file_state_t *)entity->info; + uint32_t first_sector, last_sector, sector_count, emmc_dma = 0; + uint8_t sector_buf[EMMC_SECTOR_SIZE]; + size_t buffer_offset = 0; + int32_t result = IO_SUCCESS; + + first_sector = (fp->base + fp->file_pos) >> EMMC_SECTOR_SIZE_SHIFT; + last_sector = (fp->base + fp->file_pos + length - 1) >> + EMMC_SECTOR_SIZE_SHIFT; + sector_count = last_sector - first_sector + 1; + + NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%llx(%d) len=0x%lx(%d)\n", + buffer, fp->partition, (fp->base + fp->file_pos), first_sector, + length, sector_count); + + // Temporarily disable DMA. + // if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) { + // emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE; + // } + + // first sector + uint32_t first_offset = (fp->base + fp->file_pos) % EMMC_SECTOR_SIZE; + if (0 < first_offset) { + memset(sector_buf, 0x00, EMMC_SECTOR_SIZE); + if (emmc_read_sector((uint32_t *)sector_buf, first_sector, 1, + emmc_dma) != EMMC_SUCCESS) { + result = IO_FAIL; + goto block_read_done; + } else { + buffer_offset = EMMC_SECTOR_SIZE - first_offset; + buffer_offset = (length < buffer_offset) ? + length : + buffer_offset; + + memcpy((uint8_t *)buffer, §or_buf[first_offset], + buffer_offset); + + first_sector++; + sector_count--; + } + } + + // last sector + uint32_t last_offset = + (fp->base + fp->file_pos + length) % EMMC_SECTOR_SIZE; + if (0 < sector_count && 0 < last_offset) { + memset(sector_buf, 0x00, EMMC_SECTOR_SIZE); + if (emmc_read_sector((uint32_t *)sector_buf, last_sector, 1, + emmc_dma) != EMMC_SUCCESS) { + result = IO_FAIL; + goto block_read_done; + } else { + memcpy((uint8_t *)buffer + (length - last_offset), + §or_buf[0], last_offset); + sector_count--; + } + } + + // middle sector + if (0 < sector_count) { + if (emmc_read_sector((uint32_t *)(buffer + buffer_offset), + first_sector, sector_count, + emmc_dma) != EMMC_SUCCESS) { + result = IO_FAIL; + goto block_read_done; + } + } + + *length_read = length; + fp->file_pos += (signed long long)length; +block_read_done: + return result; +} + +static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + const io_drv_spec_t *block_spec = (io_drv_spec_t *)spec; + + if (current_file.in_use != 0U) { + WARN("mmc_block: Only one open spec at a time\n"); + return IO_RESOURCES_EXHAUSTED; + } + + current_file.base = block_spec->offset; + current_file.file_pos = 0; + current_file.in_use = 1; + + current_file.partition = mmc_drv_obj.boot_partition_en; + NOTICE("BL2: eMMC boot from partition %d\n", current_file.partition); + + if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) { + return IO_FAIL; + } + + entity->info = (uintptr_t)¤t_file; + + return IO_SUCCESS; +} + +static int32_t emmcdrv_block_close(io_entity_t *entity) +{ + memset((void *)¤t_file, 0, sizeof(current_file)); + entity->info = 0U; + + return IO_SUCCESS; +} + +static const io_dev_funcs_t emmcdrv_dev_funcs = { .type = &device_type_emmcdrv, + .open = &emmcdrv_block_open, + .seek = &emmcdrv_block_seek, + .size = NULL, + .read = &emmcdrv_block_read, + .write = NULL, + .close = &emmcdrv_block_close, + .dev_init = NULL, + .dev_close = + &emmcdrv_dev_close }; + +static const io_dev_info_t emmcdrv_dev_info = { .funcs = &emmcdrv_dev_funcs, + .info = (uintptr_t)0 }; + +static const io_dev_connector_t emmcdrv_dev_connector = { + &emmcdrv_dev_open, +}; + +static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + *dev_info = (io_dev_info_t *)&emmcdrv_dev_info; + + return IO_SUCCESS; +} + +static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info) +{ + return IO_SUCCESS; +} + +int32_t register_io_dev_emmcdrv(const io_dev_connector_t **dev_con) +{ + int32_t rc; + + rc = io_register_device(&emmcdrv_dev_info); + if (rc == IO_SUCCESS) { + *dev_con = &emmcdrv_dev_connector; + } + + return rc; +} diff --git a/plat/renesas/rza/common/drivers/io/io_emmcdrv.h b/plat/renesas/rza/common/drivers/io/io_emmcdrv.h new file mode 100644 index 0000000000..71c6f515ed --- /dev/null +++ b/plat/renesas/rza/common/drivers/io/io_emmcdrv.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IO_EMMCDRV_H +#define IO_EMMCDRV_H + +struct io_dev_connector; +int32_t register_io_dev_emmcdrv(const io_dev_connector_t **connector); + +#endif /* IO_EMMCDRV_H */ diff --git a/plat/renesas/rza/common/drivers/pfc.c b/plat/renesas/rza/common/drivers/pfc.c new file mode 100644 index 0000000000..8f139ce402 --- /dev/null +++ b/plat/renesas/rza/common/drivers/pfc.c @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include +#include +#include + +static PFC_REGS pfc_mux_reg_tbl[] = { +#if RZA3M + /* P22(sd0) */ + { + { PFC_ON, (uintptr_t)PFC_PMC04, 0x3e }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC04, 0 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH04, + 0x0000010101010101 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD04, + 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR04, 0x0000010101010101 }, /* SR */ + { PFC_ON, (uintptr_t)NULL, 0 } /* IEN */ + }, + /* P6(scif0) */ + { + { PFC_ON, (uintptr_t)PFC_PMC16, 0x3 }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC16, 0x11 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH16, + 0x0000000000000101 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD16, + 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR16, 0x0000000000000101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, +#else /* RZA3M */ + /* P0(sd0) & P0(sd1) */ + { + { PFC_ON, (uintptr_t)PFC_PMC10, 0x0F }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC10, 0x00001111 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH10, + 0x0000000001010101 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD10, + 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR10, 0x0000000001010101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, +#if (DEVICE_TYPE == 1) + /* P6(scif0) */ + { + { PFC_ON, (uintptr_t)PFC_PMC16, 0x18 }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC16, 0x00066000 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH16, + 0x0000000101000000 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD16, + 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR16, 0x0000000101000000 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, +#else + /* P13(scif0) */ + { + { PFC_ON, (uintptr_t)PFC_PMC1D, 0x03 }, /* PMC */ + { PFC_ON, (uintptr_t)PFC_PFC1D, 0x00000011 }, /* PFC */ + { PFC_OFF, (uintptr_t)PFC_IOLH1D, + 0x0000000000000101 }, /* IOLH */ + { PFC_OFF, (uintptr_t)PFC_PUPD1D, + 0x0000000000000000 }, /* PUPD */ + { PFC_OFF, (uintptr_t)PFC_SR1D, 0x0000000000000101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, +#endif +#endif /* RZA3M */ +}; + +static PFC_REGS pfc_qspi_reg_tbl[] = { +#if RZA3M + /* QSPI0 */ + { + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */ + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */ + { PFC_ON, (uintptr_t)PFC_IOLH05, + 0x0000010101010101 }, /* IOLH */ + { PFC_ON, (uintptr_t)PFC_PUPD05, + 0x0000000000000000 }, /* PUPD */ + { PFC_ON, (uintptr_t)PFC_SR05, 0x0000010101010101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, +#else /* RZA3M */ + /* QSPI0 */ + { + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */ + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */ + { PFC_ON, (uintptr_t)PFC_IOLH0A, + 0x0000010101010101 }, /* IOLH */ + { PFC_ON, (uintptr_t)PFC_PUPD0A, + 0x0000000000000000 }, /* PUPD */ + { PFC_ON, (uintptr_t)PFC_SR0A, 0x0000010101010101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, + /* QSPI1 */ + { + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */ + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */ + { PFC_ON, (uintptr_t)PFC_IOLH0B, + 0x0000010101010101 }, /* IOLH */ + { PFC_ON, (uintptr_t)PFC_PUPD0B, + 0x0000000000000000 }, /* PUPD */ + { PFC_ON, (uintptr_t)PFC_SR0B, 0x0000010101010101 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + }, + /* QSPIn */ + { + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PMC */ + { PFC_OFF, (uintptr_t)NULL, 0 }, /* PFC */ + { PFC_ON, (uintptr_t)PFC_IOLH0C, + 0x0000000000000101 }, /* IOLH */ + { PFC_ON, (uintptr_t)PFC_PUPD0C, + 0x0000000000000000 }, /* PUPD */ + { PFC_ON, (uintptr_t)PFC_SR0C, 0x0000000000000000 }, /* SR */ + { PFC_OFF, (uintptr_t)NULL, 0 } /* IEN */ + } +#endif /* RZA3M */ +}; + +static void pfc_mux_setup(void) +{ + int cnt; + int size = ARRAY_SIZE(pfc_mux_reg_tbl); + + for (cnt = 0; cnt < size; cnt++) { + /* PMC */ + if (pfc_mux_reg_tbl[cnt].pmc.flg == PFC_ON) { + mmio_write_8(pfc_mux_reg_tbl[cnt].pmc.reg, + pfc_mux_reg_tbl[cnt].pmc.val); + } + /* IOLH */ + if (pfc_mux_reg_tbl[cnt].iolh.flg == PFC_ON) { + mmio_write_64(pfc_mux_reg_tbl[cnt].iolh.reg, + pfc_mux_reg_tbl[cnt].iolh.val); + } + /* PUPD */ + if (pfc_mux_reg_tbl[cnt].pupd.flg == PFC_ON) { + mmio_write_64(pfc_mux_reg_tbl[cnt].pupd.reg, + pfc_mux_reg_tbl[cnt].pupd.val); + } + /* SR */ + if (pfc_mux_reg_tbl[cnt].sr.flg == PFC_ON) { + mmio_write_64(pfc_mux_reg_tbl[cnt].sr.reg, + pfc_mux_reg_tbl[cnt].sr.val); + } + } + /* multiplexer terminal switching */ + mmio_write_32(PFC_PWPR, 0x0); + mmio_write_32(PFC_PWPR, PWPR_PFCWE); + + for (cnt = 0; cnt < size; cnt++) { + /* PFC */ + if (pfc_mux_reg_tbl[cnt].pfc.flg == PFC_ON) { + mmio_write_32(pfc_mux_reg_tbl[cnt].pfc.reg, + pfc_mux_reg_tbl[cnt].pfc.val); + } + } + + mmio_write_32(PFC_PWPR, 0x0); + mmio_write_32(PFC_PWPR, PWPR_B0Wl); +} + +static void pfc_qspi_setup(void) +{ + int cnt; + int size = ARRAY_SIZE(pfc_qspi_reg_tbl); + + for (cnt = 0; cnt < size; cnt++) { + /* PMC */ + if (pfc_qspi_reg_tbl[cnt].pmc.flg == PFC_ON) { + mmio_write_64(pfc_qspi_reg_tbl[cnt].pmc.reg, + pfc_qspi_reg_tbl[cnt].pmc.val); + } + /* IOLH */ + if (pfc_qspi_reg_tbl[cnt].iolh.flg == PFC_ON) { + mmio_write_64(pfc_qspi_reg_tbl[cnt].iolh.reg, + pfc_qspi_reg_tbl[cnt].iolh.val); + } + /* PUPD */ + if (pfc_qspi_reg_tbl[cnt].pupd.flg == PFC_ON) { + mmio_write_64(pfc_qspi_reg_tbl[cnt].pupd.reg, + pfc_qspi_reg_tbl[cnt].pupd.val); + } + /* SR */ + if (pfc_qspi_reg_tbl[cnt].sr.flg == PFC_ON) { + mmio_write_64(pfc_qspi_reg_tbl[cnt].sr.reg, + pfc_qspi_reg_tbl[cnt].sr.val); + } + } + /* multiplexer terminal switching */ + mmio_write_32(PFC_PWPR, 0x0); + mmio_write_32(PFC_PWPR, PWPR_PFCWE); + for (cnt = 0; cnt < size; cnt++) { + /* SR */ + if (pfc_qspi_reg_tbl[cnt].pfc.flg == PFC_ON) { + mmio_write_64(pfc_qspi_reg_tbl[cnt].pfc.reg, + pfc_qspi_reg_tbl[cnt].pfc.val); + } + } + + mmio_write_32(PFC_PWPR, 0x0); + mmio_write_32(PFC_PWPR, PWPR_B0Wl); +} + +void pfc_setup(void) +{ + pfc_mux_setup(); + pfc_qspi_setup(); +} diff --git a/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c b/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c new file mode 100644 index 0000000000..64b161bc5a --- /dev/null +++ b/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include + +static int rz_mmu_check_tbl(const rza_mmu_pgtbl_cfg_t *config_table); +static void rz_mmu_write_tbl(const rza_mmu_pgtbl_cfg_t *config_table); +static void rz_mmu_write_ttbr0_el3(const uint64_t addr); +static void rz_mmu_write_mair_el3(const uint64_t mair); +static void rz_mmu_write_tcr_el3(const uint64_t tcr); +static uint32_t rz_mmu_get_current_el(void); + +/* MMU allocation area */ +uint64_t __attribute__((section("base_xlat_table"))) + mmu_level1_table[RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; +uint64_t __attribute__((section("xlat_table"), aligned(0x1000))) +mmu_level2_table[RZA_MMU_TABLE_ENTRY * RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; +uint64_t level2_table[RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; + +int plat_mmu_init(const rza_mmu_pgtbl_cfg_t *config_table) +{ + int ret; + int index; + uint64_t mair; + uint64_t tcr; + int t0sz; + uintptr_t virtual_addr_space_size; + + ret = rz_mmu_check_tbl(config_table); + + if (0 == ret) { + /* get the start address for each Level2 MMU table entry */ + for (index = 0; index < RZA_MMU_LEVEL2_TABLE_INDEX_MAX; index++) { + level2_table[index] = + (uint64_t)&mmu_level2_table[RZA_MMU_TABLE_ENTRY * index]; + } + + /* Set the address of the level 2 MMU table in the level 1 MMU table */ + for (index = 0; index < RZA_MMU_LEVEL2_TABLE_INDEX_MAX; index++) { + *((uint64_t *)&mmu_level1_table[index]) = + (level2_table[index] | RZA_MMU_ATTR_NEXT_TBL); + } + + rz_mmu_write_tbl(config_table); + + /* create a pattern of attributes to set in the MAIR register */ + mair = RZA_MMU_MAIR_ATTR_SET(RZA_MMU_ATTR_DEVICE, + RZA_MMU_ATTR_DEVICE_INDEX); + mair |= RZA_MMU_MAIR_ATTR_SET( + RZA_MMU_ATTR_IWBWA_OWBWA_NTR, + RZA_MMU_ATTR_IWBWA_OWBWA_NTR_INDEX); + mair |= RZA_MMU_MAIR_ATTR_SET(RZA_MMU_ATTR_NON_CACHEABLE, + RZA_MMU_ATTR_NON_CACHEABLE_INDEX); + + /* create TTB operation settings to set in TCR register */ + tcr = TCR_EL3_RES1; + + virtual_addr_space_size = (uintptr_t)RZA_MMU_VIRT_SIZE_MAX; + + t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); + + tcr |= (uint64_t)t0sz << TCR_T0SZ_SHIFT; + + /* TTB cache enable */ + tcr |= (TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA); + + /* address range check */ + if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_40_TO_41) != 0U) { + tcr |= TCR_PS_BITS_4TB << TCR_EL3_PS_SHIFT; /* 42bit */ + } else if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_36_TO_39) != 0U) { + tcr |= TCR_PS_BITS_1TB << TCR_EL3_PS_SHIFT; /* 40bit */ + } + /* 36 bits address */ + else if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_32_TO_35) != 0U) { + tcr |= TCR_PS_BITS_64GB << TCR_EL3_PS_SHIFT; /* 36 bit */ + } + /* 32bits address */ + else { + tcr |= TCR_PS_BITS_4GB << TCR_EL3_PS_SHIFT; /* 32 bit */ + } + + __asm__ volatile("tlbi alle3\n"); + + rz_mmu_write_mair_el3(mair); + + rz_mmu_write_tcr_el3(tcr); + + rz_mmu_write_ttbr0_el3(((uint64_t)mmu_level1_table | TTBR_CNP_BIT)); + } + + return ret; +} + +void plat_mmu_enable(void) +{ + /* set MMU and data cache enable, Disable the function to forcibly + * set the execute-never attribute when setting the writable memory + */ + __asm__ volatile(".equ SCTLR_C, (1 << 2)\n" + ".equ SCTLR_M, (1 << 0)\n" + ".equ SCTLR_WXN, (1 << 19)\n" + + "dsb ish\n" + "isb\n" + "mrs x0, SCTLR_EL3\n" + "mov x1, #(SCTLR_C | SCTLR_M)\n" + "orr x0, x0, x1\n" + "bic x0, x0, SCTLR_WXN\n" + "msr SCTLR_EL3, x0\n" + "isb\n" + : + : + : "x0", "x1"); +} + +int rz_mmu_check_tbl(const rza_mmu_pgtbl_cfg_t *config_table) +{ + int ret = 0; + int index; + uint32_t current_el; + + current_el = rz_mmu_get_current_el(); + if (RZA_MMU_CURRENT_EL3 == current_el) { + for (index = 0; ((0 == ret) && (RZA_MMU_ATTRIBUTE_CONFIG_END != + config_table[index].attribute)); + index++) { + if ((config_table[index].vaddress % RZA_MMU_L2_ENTRY_SIZE) != 0) { + ret = -1; + } + + if ((config_table[index].paddress % RZA_MMU_L2_ENTRY_SIZE) != 0) { + ret = -1; + } + + if ((config_table[index].size % RZA_MMU_L2_ENTRY_SIZE) != 0) { + ret = -1; + } + + if (RZA_MMU_PHY_SIZE_MAX < + (uint64_t)(config_table[index].paddress + config_table[index].size)) { + ret = -1; + } + + if (RZA_MMU_VIRT_SIZE_MAX < + (uint64_t)(config_table[index].vaddress + config_table[index].size)) { + ret = -1; + } + } + } else { + ret = -1; + } + + return ret; +} + +void rz_mmu_write_tbl(const rza_mmu_pgtbl_cfg_t *config_table) +{ + int desc; + int num_of_desc; + int ttb_index; + int ttb_num; + int index; + uint64_t *desc_ptr; + uint64_t paddress; + uint64_t ttb_base_ptr; + uint64_t ttb_start_vaddr; + uint64_t attribute; + + for (index = 0; RZA_MMU_ATTRIBUTE_CONFIG_END != config_table[index].attribute; index++) { + /* get target TTB block number + * RZA_MMU_TTB_BLOCK_WIDTH is TTB block width(0x40000000) + */ + ttb_num = config_table[index].vaddress / RZA_MMU_TTB_BLOCK_WIDTH; + /* get target TTB block pointer */ + ttb_base_ptr = (uint64_t)&mmu_level2_table[RZA_MMU_TABLE_ENTRY * ttb_num]; + /* get first virtual address on target TTB block */ + ttb_start_vaddr = RZA_MMU_TTB_BLOCK_WIDTH * ttb_num; + + /* get number of descriptor for setting attribute + * RZA_MMU_L2_ENTRY_SIZE is virtual address entry size per descriptor + */ + num_of_desc = config_table[index].size / RZA_MMU_L2_ENTRY_SIZE; + /* get index of descriptor for setting attribute */ + ttb_index = (config_table[index].vaddress - ttb_start_vaddr) / + RZA_MMU_L2_ENTRY_SIZE; + /* get pointer of descriptor */ + desc_ptr = (uint64_t *)(ttb_base_ptr + (ttb_index * RZA_MMU_TABLE_DESC_SIZE)); + + /* set attribute to descriptor */ + if (RZA_MMU_ATTRIBUTE_ACCESS_FAULT != config_table[index].attribute) { + attribute = (config_table[index].attribute | RZA_MMU_DESC_BLOCK_ENTRY_L12); + paddress = config_table[index].paddress; + for (desc = 0; desc < num_of_desc; desc++) { + *desc_ptr++ = paddress | attribute; + paddress += RZA_MMU_L2_ENTRY_SIZE; + } + } else { + for (desc = 0; desc < num_of_desc; desc++) { + *desc_ptr++ = 0; + } + } + } +} + +void rz_mmu_write_ttbr0_el3(const uint64_t addr) +{ + __asm__ volatile("msr TTBR0_EL3, %0\n" : : "r"(addr) :); +} + +void rz_mmu_write_mair_el3(const uint64_t mair) +{ + __asm__ volatile("msr MAIR_EL3, %0\n" : : "r"(mair) :); +} + +void rz_mmu_write_tcr_el3(const uint64_t tcr) +{ + __asm__ volatile("msr TCR_EL3, %0\n" : : "r"(tcr) :); +} + +uint32_t rz_mmu_get_current_el(void) +{ + uint32_t current_el; + + __asm__ volatile("mrs %0, CurrentEL\n" : "=r"(current_el) : :); + + return current_el; +} diff --git a/plat/renesas/rza/common/drivers/scifa.S b/plat/renesas/rza/common/drivers/scifa.S new file mode 100644 index 0000000000..e430c43e34 --- /dev/null +++ b/plat/renesas/rza/common/drivers/scifa.S @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#define SMR (0x00) +#define BRR (0x02) +#define MDDR (0x02) +#define SCR (0x04) +#define FTDR (0x06) +#define FSR (0x08) +#define FRDR (0x0A) +#define FCR (0x0C) +#define FDR (0x0E) +#define SPTR (0x10) +#define LSR (0x12) +#define SEMR (0x14) +#define FTCR (0x16) + +#define SCR_CKE_MASK (0x03) +#define SCR_CKE_INTERN (0x00) +#define SCR_RE_ON (0x10) +#define SCR_TE_ON (0x20) +#define SCR_INIT (0x00) +#define SCR_READY (SCR_INIT | SCR_RE_ON | SCR_TE_ON) + +#define FCR_RFRST_RST (0x02) +#define FCR_TFRST_RST (0x04) +#define FCR_BASE (0x00) +#define FCR_RST (FCR_BASE | FCR_RFRST_RST | FCR_TFRST_RST) +#define FCR_RUN (FCR_BASE) + +#define SMR_INIT (0x00) + +#define SEMR_NFEN_ON (0x04) +#define SEMR_MDDRS_BRR (0x00) +#define SEMR_MDDRS_MDDR (0x10) +#define SEMR_BRME_ON (0x20) +//#define SEMR_BASE (SEMR_NFEN_ON) +#define SEMR_BASE (0x00) +#define SEMR_BRR (SEMR_BASE | SEMR_MDDRS_BRR) +#define SEMR_MDDR (SEMR_BASE | SEMR_MDDRS_MDDR | SEMR_BRME_ON) + +#define FTCR_TTRGS (0x0080) +#define FTCR_RTRGS (0x8000) + +#define FSR_TDFE_SHIFT (5) +#define FSR_TEND_SHIFT (6) +#define FSR_TEND (1< + +#include +#include +#include +#include +#include +#include +#include + +void spi_multi_setup_device(void) +{ + uint32_t val; + uint8_t read_status; + + mmio_write_32(SPIM_PHYOFFSET1, SPIM_PHYOFFSET1_SET_VALUE); + mmio_write_32(SPIM_PHYOFFSET2, SPIM_PHYOFFSET2_SET_VALUE); + spi_multi_timing_set(); + + /* Set Data read option */ + /* Required when command 0xEB is specified. + * Not required when a command other than is specified, + * but there is no problem in operation. + */ + val = SPIM_DROPR_SET_VALUE; + mmio_write_32(SPIM_DROPR, val); + + read_status = spi_multi_cmd_read(SMCMR_CMD_READ_STATUS_REGISTER_2); + if ((read_status & STATUS_2_QE) == STATUS_2_QE) { + return; + } + /* Write Enable Command */ + spi_multi_cmd_write(SMCMR_CMD_WRITE_ENABLE, SPI_MANUAL_COMMAND_SIZE_0, + 0); + /* Write Status Register-2 Command Quad Enable */ + val = ((STATUS_2_QE | read_status) << SMWDR0_1BYTE_DATA_BIT_SHIFT); + spi_multi_cmd_write(SMCMR_CMD_WRITE_STATUS_REGISTER_2, + SPI_MANUAL_COMMAND_SIZE_8_BIT, val); + /* status 1 BUSY check */ + while (1) { + read_status = + spi_multi_cmd_read(SMCMR_CMD_READ_STATUS_REGISTER_1); + if ((read_status & STATUS_1_BUSY_BIT) == STATUS_1_BUSY) { + udelay(STATUS_BUSY_READ_DELAY_TIME); + continue; + } else { + break; + } + } +} diff --git a/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c b/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c new file mode 100644 index 0000000000..5ff4ce4679 --- /dev/null +++ b/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +void spi_multi_setup_device(void) +{ + /* Do nothing */ +} diff --git a/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c b/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c new file mode 100644 index 0000000000..80a26a375f --- /dev/null +++ b/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include + +void spi_multi_timing_set(void) +{ + /* Timing adjustment register setting */ + mmio_write_32(SPIM_PHYADJ2, 0xA5390000); + mmio_write_32(SPIM_PHYADJ1, 0x80000000); + mmio_write_32(SPIM_PHYADJ2, 0x00008080); + mmio_write_32(SPIM_PHYADJ1, 0x80000022); + mmio_write_32(SPIM_PHYADJ2, 0x00008080); + mmio_write_32(SPIM_PHYADJ1, 0x80000024); + + /* SDR mode serial flash settings */ + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); + + /* Timing adjustment register setting */ + mmio_write_32(SPIM_PHYADJ2, 0x00000030); + mmio_write_32(SPIM_PHYADJ1, 0x80000032); + + dmbsy(); +} + +uint8_t spi_multi_cmd_read(uint8_t command) +{ + uint32_t val; + uint8_t r_status; + + /* SDR mode serial flash settings */ + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); + + /* Set the QSPIn_SSL setting value & Manual Mode */ + mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_MANUAL_SET_VALUE); + + val = command << SMCMR_CMD_BIT_SHIFT; + mmio_write_32(SPIM_SMCMR, val); + + /* Set the Transfer Data size setting value & command output enable */ + val = SMENR_CDE | SPI_MANUAL_COMMAND_SIZE_16_BIT; + mmio_write_32(SPIM_SMENR, val); + + /* Set the SDR transfer & SPI flash mode setting value */ + mmio_write_32(SPIM_SMDRENR, SPIM_SMDRENR_SET_VALUE); + + val = SMCR_SPIE | SMCR_SPIRE; + mmio_write_32(SPIM_SMCR, val); + + /* Wait until the transfer is complete */ + do { + val = mmio_read_32(SPIM_CMNSR); + } while ((val & CMNSR_TEND) == 0); + + val = mmio_read_32(SPIM_SMRDR0); + + r_status = (uint8_t)val; + return r_status; +} + +void spi_multi_cmd_write(uint8_t command, uint8_t size, uint32_t data) +{ + uint32_t val; + + /* SDR mode serial flash settings */ + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); + + /* Set the QSPIn_SSL setting value & Manual Mode */ + mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_MANUAL_SET_VALUE); + + /* Set the Manual Mode Command */ + val = command << SMCMR_CMD_BIT_SHIFT; + mmio_write_32(SPIM_SMCMR, val); + + /* Set the Transfer Data size setting value & command output enable */ + val = SMENR_CDE | size; + mmio_write_32(SPIM_SMENR, val); + + /* Set the write data in Manual mode */ + mmio_write_32(SPIM_SMWDR0, data); + + /* Set the SDR transfer & SPI flash mode setting value */ + mmio_write_32(SPIM_SMDRENR, SPIM_SMDRENR_SET_VALUE); + + /* Set the data transfer enable & data write enable */ + if (size == SPI_MANUAL_COMMAND_SIZE_0) { + val = SMCR_SPIE; + } else { + val = SMCR_SPIE | SMCR_SPIWE; + } + mmio_write_32(SPIM_SMCR, val); + + /* Wait until the transfer is complete */ + do { + val = mmio_read_32(SPIM_CMNSR); + } while ((val & CMNSR_TEND) == 0); +} + +int spi_multi_setup(void) +{ + uint32_t val; + + /* Wait until the transfer is complete */ + do { + val = mmio_read_32(SPIM_CMNSR); + } while ((val & CMNSR_TEND) == 0); + + /* Device-specific settings */ + spi_multi_setup_device(); + /* SDR mode serial flash settings */ + mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); + + /* Read timing setting */ + mmio_write_32(SPIM_PHYOFFSET1, SPIM_PHYOFFSET1_SET_VALUE); + mmio_write_32(SPIM_PHYOFFSET2, SPIM_PHYOFFSET2_SET_VALUE); + + /* Set the QSPIn_SSL setting value */ + mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_EXTREAD_SET_VALUE); + /* Set SSL delay setting value */ + mmio_write_32(SPIM_SSLDR, SPIM_SSLDR_SET_VALUE); + + /* Clear the RBE bit */ + mmio_write_32(SPIM_DRCR, SPIM_DRCR_SET_VALUE); + mmio_read_32(SPIM_DRCR); + + /* Set the data read command */ + mmio_write_32(SPIM_DRCMR, SPIM_DRCMR_SET_VALUE); + + /* Extended external address setting */ + mmio_write_32(SPIM_DREAR, SPIM_DREAR_SET_VALUE); + + /* Set the bit width of command and address output to 1 bit and */ + /* the address size to 4 byte */ + mmio_write_32(SPIM_DRENR, SPIM_DRENR_SET_VALUE); + + /* Dummy cycle setting */ + mmio_write_32(SPIM_DRDMCR, SPIM_DRDMCR_SET_VALUE); + + /* Change to SPI flash mode */ + mmio_write_32(SPIM_DRDRENR, SPIM_DRDRENR_SET_VALUE); + + /* Timing adjustment register setting */ + spi_multi_timing_set(); + + return SPI_MULTI_SUCCESS; +} diff --git a/plat/renesas/rza/common/drivers/syc.c b/plat/renesas/rza/common/drivers/syc.c new file mode 100644 index 0000000000..ceb5aafee8 --- /dev/null +++ b/plat/renesas/rza/common/drivers/syc.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#define SYC_BASE PLAT_SYC_BASE + +static inline void syc_reg_write(uint32_t offset, uint32_t val) +{ + mmio_write_32(SYC_BASE + offset, val); +} + +static inline uint32_t syc_reg_read(uint32_t offset) +{ + return mmio_read_32(SYC_BASE + offset); +} + +static void enable_counter(unsigned int enable) +{ + syc_reg_write(CNTCR_OFF, enable & CNTCR_EN); +} + +void syc_init(unsigned int freq) +{ + syc_reg_write(CNTFID_OFF, freq); + enable_counter(CNTCR_EN); +} + +unsigned int syc_get_freq(void) +{ + return syc_reg_read(CNTFID_OFF); +} diff --git a/plat/renesas/rza/common/drivers/xspi/octa.c b/plat/renesas/rza/common/drivers/xspi/octa.c new file mode 100644 index 0000000000..bac7d51bd6 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspi/octa.c @@ -0,0 +1,1215 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Defaults */ +#define DEFAULT_SPI_FREQUENCY 66666667 +#define RESET_DURATION_US 10 +#define DEFAULT_VOLTAGE_IS_1800MV 1 +#define DEFAULT_CH0_CALIBRATION_OFFSET 0x1C0 +#define DEFAULT_CH1_CALIBRATION_OFFSET 0 + +/* Static function pre-definition */ +static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg); +static int octa_close(xspi_ctrl_t *const ctrl); +static int octa_post_init(xspi_ctrl_t *const ctrl); +static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, + bool is_write); +static int octa_configure_xip(xspi_ctrl_t *const ctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop); +static int octa_start_xip(xspi_ctrl_t *const ctrl); +static int octa_stop_xip(xspi_ctrl_t *const ctrl); +static int octa_run_manual_calibration(xspi_ctrl_t *const ctrl); +static int octa_enable_auto_calibration(xspi_ctrl_t *const ctrl); +static int octa_disable_auto_calibration(xspi_ctrl_t *const ctrl); +static int octa_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz); +static int octa_clean_mmap(xspi_ctrl_t *const ctrl); +static int octa_inv_mmap(xspi_ctrl_t *const ctrl); +static uintptr_t octa_get_mmap_base(xspi_ctrl_t *const ctrl); +static size_t octa_get_mmap_size(xspi_ctrl_t *const ctrl); +static uint32_t octa_get_features(xspi_ctrl_t *const ctrl); + +/* API function table definition */ +const xspi_api_t octa_api = { + .open = octa_open, + .close = octa_close, + .post_init = octa_post_init, + .exec_op = octa_exec_op, + .configure_xip = octa_configure_xip, + .start_xip = octa_start_xip, + .stop_xip = octa_stop_xip, + .run_manual_calibration = octa_run_manual_calibration, + .enable_auto_calibration = octa_enable_auto_calibration, + .disable_auto_calibration = octa_disable_auto_calibration, + .set_frequency = octa_set_frequency, + .clean_mmap = octa_clean_mmap, + .inv_mmap = octa_inv_mmap, + .get_mmap_base = octa_get_mmap_base, + .get_mmap_size = octa_get_mmap_size, + .get_features = octa_get_features, +}; + +/* Preamble pattern (aligned to 16byte boundary) */ +static const uint32_t preamble[4] __aligned(16) = { + 0xFFFF0000, + 0x000800FF, + 0x00FFF700, + 0xF700F708, +}; + +/* Static variables */ +static bool globally_initialised; +static bool post_init_done; +static int spi_clock = DEFAULT_SPI_FREQUENCY; +static bool initialised[2] = { false, false }; +static int freq[2] = { INT_MAX, INT_MAX }; +static bool is_calibrated[2] = { false, false }; + +static const uintptr_t ch0_mmap_base = 0x20000000; +static const size_t ch0_mmap_size = 0x08000000; +static const uintptr_t ch1_mmap_base = 0x28000000; +static const size_t ch1_mmap_size = 0x08000000; + +/* !!! DO NOT TOUCH THESE SETTINGS !!! They are used for doing initialize. */ +static const uint32_t init_octa_dcr_value; +static const uint32_t init_octa_dar_value; +static const uint32_t init_octa_dcsr_value = + 0 | 0u << OCTA_DCSR_ACDA_POS | 0u << OCTA_DCSR_DOPI_POS | + 0u << OCTA_DCSR_ADLEN_POS | 0u << OCTA_DCSR_DAOR_POS | + 0u << OCTA_DCSR_CMDLEN_POS | 0u << OCTA_DCSR_ACDV_POS | + 0u << OCTA_DCSR_DMLEN_POS | 0u << OCTA_DCSR_DALEN_POS; +static const uint32_t init_octa_dsr0_value = + 0 | OCTA_DSR_TYP_NONE >> OCTA_DSR0_DV0TYP_POS | + 0u << OCTA_DSR0_DV0SZ_POS; +static const uint32_t init_octa_dsr1_value = + 0 | OCTA_DSR_TYP_NONE >> OCTA_DSR1_DV1TYP_POS | + 0u << OCTA_DSR1_DV1SZ_POS; +static const uint32_t init_octa_mdtr_value = + 0 | 6u << OCTA_MDTR_DQSEDOPI_POS | 0x50u << OCTA_MDTR_DV1DEL_POS | + 9u << OCTA_MDTR_DQSESOPI_POS | 4u << OCTA_MDTR_DQSERAM_POS | + 0x50u << OCTA_MDTR_DV0DEL_POS; +static const uint32_t init_octa_actr_value = 268435456; +static const uint32_t init_octa_acar0_value; +static const uint32_t init_octa_acar1_value; +static const uint32_t init_octa_drcstr_value = + 0 | 0u << OCTA_DRCSTR_DVRDLO1_POS | 0u << OCTA_DRCSTR_DVRDHI1_POS | + 0u << OCTA_DRCSTR_DVRDCMD1_POS | +#if !RZA3 + 0u << OCTA_DRCSTR_CTR1_POS | 127u << OCTA_DRCSTR_CTRW1_POS | +#endif + 0u << OCTA_DRCSTR_DVRDLO0_POS | 0u << OCTA_DRCSTR_DVRDHI0_POS | + 0u << OCTA_DRCSTR_DVRDCMD0_POS | 1u << OCTA_DRCSTR_CTR0_POS | + 127u << OCTA_DRCSTR_CTRW0_POS; +static const uint32_t init_octa_dwcstr_value = + 0 | 0u << OCTA_DWCSTR_DVWLO1_POS | 0u << OCTA_DWCSTR_DVWHI1_POS | + 0u << OCTA_DWCSTR_DVWCMD1_POS | 0u << OCTA_DWCSTR_DVWLO0_POS | + 0u << OCTA_DWCSTR_DVWHI0_POS | 0u << OCTA_DWCSTR_DVWCMD0_POS; +static const uint32_t init_octa_dcstr_value = 0 | 0u << OCTA_DCSTR_DVSELLO_POS | + 0u << OCTA_DCSTR_DVSELHI_POS | + 0u << OCTA_DCSTR_DVSELCMD_POS; +static const uint32_t init_octa_cdsr_value = + 0 | 1u << OCTA_CDSR_DLFT_POS | 0u << OCTA_CDSR_ACMEME1_POS | + 0u << OCTA_CDSR_ACMEME0_POS | 0u << OCTA_CDSR_DV1PC_POS | + 0u << OCTA_CDSR_DV0PC_POS | + OCTA_CDSR_DVTTYP_SPI << OCTA_CDSR_DV1TTYP_POS | + OCTA_CDSR_DVTTYP_SPI << OCTA_CDSR_DV0TTYP_POS; +static const uint32_t init_octa_mdlr_value = + 0 | 0u << OCTA_MDLR_DV1WDL_POS | 0u << OCTA_MDLR_DV1RDL_POS | + 0u << OCTA_MDLR_DV0WDL_POS | 0u << OCTA_MDLR_DV0RDL_POS; +static const uint32_t init_octa_mrwcr0_value = + 0 | 0u << OCTA_MRWCR0_D0MWCMD1_POS | 0u << OCTA_MRWCR0_D0MWCMD0_POS | + 0u << OCTA_MRWCR0_D0MRCMD1_POS | 0u << OCTA_MRWCR0_D0MRCMD0_POS; +static const uint32_t init_octa_mrwcr1_value = + 0 | 0u << OCTA_MRWCR1_D1MWCMD1_POS | 0u << OCTA_MRWCR1_D1MWCMD0_POS | + 0u << OCTA_MRWCR1_D1MRCMD1_POS | 0u << OCTA_MRWCR1_D1MRCMD0_POS; +static const uint32_t init_octa_mrwcsr_value = + 0 | 0u << OCTA_MRWCSR_MWO1_POS | 0u << OCTA_MRWCSR_MWCL1_POS | + 0u << OCTA_MRWCSR_MWAL1_POS | 0u << OCTA_MRWCSR_MRO1_POS | + 0u << OCTA_MRWCSR_MRCL1_POS | 0u << OCTA_MRWCSR_MRAL1_POS | + 0u << OCTA_MRWCSR_MWO0_POS | 0u << OCTA_MRWCSR_MWCL0_POS | + 0u << OCTA_MRWCSR_MWAL0_POS | 0u << OCTA_MRWCSR_MRO0_POS | + 0u << OCTA_MRWCSR_MRCL0_POS | 0u << OCTA_MRWCSR_MRAL0_POS; + +/* Function definitions */ +static void select_octa(octa_ctrl_t *myctrl, xspi_cfg_t const *const cfg) +{ + if (RZ_XSPI_EXCLUSIVE_SELECTOR) { + /* Check if SPIM selected */ + uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + if ((ipcont_spi_octa & IPCONT_SEL_SPI_OCTA) == + IPCONT_SEL_SPI_OCTA_SPI) { + /* Reset SPIM controller */ + cpg_reset_on(CPG_CLOCK_SPIM); + + /* Stop SPIM clock */ + cpg_clock_off(CPG_CLOCK_SPIM); + } else { + /* Reset the devices connected, required to change the device mode + * from OPI to SPI. + * Otherwise, the octa devices can not initialize by the SPI mode. + */ + mmio_clrbits_32(myctrl->reg_base + OCTA_RSTCNT, + OCTA_RSTCNT_RSTVAL); + } + } + + /* Wait for reset SPI device */ + udelay(RESET_DURATION_US); + + if (RZ_XSPI_FORCE_VOLTAGE_SETTING) { + /* force voltage setting + * Note: This is required if the boot mode is neither 3 nor 4. + */ + uint8_t voltage = DEFAULT_VOLTAGE_IS_1800MV; + mmio_write_8(PFC_QSPI, voltage); + mmio_read_8(PFC_QSPI); + } + + /* Supply OCTA clock */ + cpg_clock_on(CPG_CLOCK_OCTA); + + /* Resume OCTA controller */ + cpg_reset_off(CPG_CLOCK_OCTA); + + if (RZ_XSPI_EXCLUSIVE_SELECTOR) { + /* Select OCTA for SPI controller */ + uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + ipcont_spi_octa &= ~IPCONT_SEL_SPI_OCTA; + ipcont_spi_octa |= IPCONT_SEL_SPI_OCTA_OCTA + << IPCONT_SEL_SPI_OCTA_POS; + mmio_write_32(SYS_IPCONT, ipcont_spi_octa); + mmio_read_32(SYS_IPCONT); + } + + /* De-assert reset line */ + mmio_setbits_32(myctrl->reg_base + OCTA_RSTCNT, OCTA_RSTCNT_RSTVAL); +} + +static void octa_init(octa_ctrl_t *myctrl) +{ + mmio_write_32(myctrl->reg_base + OCTA_DCR, init_octa_dcr_value); + mmio_write_32(myctrl->reg_base + OCTA_DAR, init_octa_dar_value); + mmio_write_32(myctrl->reg_base + OCTA_DCSR, init_octa_dcsr_value); + mmio_write_32(myctrl->reg_base + OCTA_DSR0, init_octa_dsr0_value); + mmio_write_32(myctrl->reg_base + OCTA_DSR1, init_octa_dsr1_value); + mmio_write_32(myctrl->reg_base + OCTA_MDTR, init_octa_mdtr_value); + mmio_write_32(myctrl->reg_base + OCTA_ACTR, init_octa_actr_value); + mmio_write_32(myctrl->reg_base + OCTA_ACAR0, init_octa_acar0_value); + mmio_write_32(myctrl->reg_base + OCTA_ACAR1, init_octa_acar1_value); + mmio_write_32(myctrl->reg_base + OCTA_DRCSTR, init_octa_drcstr_value); + mmio_write_32(myctrl->reg_base + OCTA_DWCSTR, init_octa_dwcstr_value); + mmio_write_32(myctrl->reg_base + OCTA_DCSTR, init_octa_dcstr_value); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, init_octa_cdsr_value); + mmio_write_32(myctrl->reg_base + OCTA_MDLR, init_octa_mdlr_value); + mmio_write_32(myctrl->reg_base + OCTA_MRWCR0, init_octa_mrwcr0_value); + mmio_write_32(myctrl->reg_base + OCTA_MRWCR1, init_octa_mrwcr1_value); + mmio_write_32(myctrl->reg_base + OCTA_MRWCSR, init_octa_mrwcsr_value); +} + +static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) +{ + int result = -1; + assert(ctrl); + assert(cfg); + assert(cfg->channel == 0 || cfg->channel == 1); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + octa_ext_t *ext = (octa_ext_t *)cfg->extend; + assert(cfg->base); + + if (myctrl->opened) + return -1; + + myctrl->reg_base = cfg->base; + myctrl->channel = cfg->channel; + + result = 0; + + if (!globally_initialised) { + /* Initialize IP (once) */ + select_octa(myctrl, cfg); + octa_init(myctrl); + + globally_initialised = true; + } + + /* Initialize MMAP base and initial size */ + size_t mmap_size; + if (myctrl->channel) { + myctrl->mmap_base = ch1_mmap_base; + mmap_size = ch1_mmap_size; + } else { + myctrl->mmap_base = ch0_mmap_base; + mmap_size = ch0_mmap_size; + } + + /* Override size if specified and is smaller */ + if (ext && mmap_size > (size_t)ext->device_size) { + mmap_size = (size_t)ext->device_size; + } + + /* Store mmap size */ + myctrl->mmap_size = mmap_size; + + /* Set device type and calibrate address */ + uint8_t device_type; + if (myctrl->channel) { + device_type = OCTA_DSR_TYP_RAM; + /* Override calibration base if specified */ + uint32_t ch1_calibration_offset = + DEFAULT_CH1_CALIBRATION_OFFSET; + if (ext && ext->calibration_base != UINT32_MAX) { + ch1_calibration_offset = ext->calibration_base; + } + myctrl->calibration_base = ch1_calibration_offset; + mmio_write_32(myctrl->reg_base + OCTA_ACAR1, + myctrl->calibration_base); + } else { + device_type = OCTA_DSR_TYP_FLASH; + /* Override calibration base if specified */ + uint32_t ch0_calibration_offset = + DEFAULT_CH0_CALIBRATION_OFFSET; + if (ext && ext->calibration_base != 0) { + ch0_calibration_offset = ext->calibration_base; + } + myctrl->calibration_base = ch0_calibration_offset; + mmio_write_32(myctrl->reg_base + OCTA_ACAR0, + myctrl->calibration_base); + } + myctrl->device_type = device_type; + + /* Sets DVnSZ only first per channel */ + if (!initialised[myctrl->channel]) { + uint32_t dsr; + if (ext) { + dsr = ext->device_size; + } else { + dsr = mmap_size; + } + + if (myctrl->channel) { + uint32_t aer; + if (dsr <= 8 * 1024 * 1024) + aer = OCTA_AER_LE64MB; + else if (dsr <= 16 * 1024 * 1024) + aer = OCTA_AER_128MB; + else if (dsr <= 32 * 1024 * 1024) + aer = OCTA_AER_256MB; + else + aer = OCTA_AER_512MB; + dsr <<= OCTA_DSR1_DV1SZ_POS; + dsr |= (uint32_t)device_type << OCTA_DSR1_DV1TYP_POS; + mmio_write_32(myctrl->reg_base + OCTA_AER, aer); + mmio_write_32(myctrl->reg_base + OCTA_DSR1, dsr); + } else { + dsr <<= OCTA_DSR0_DV0SZ_POS; + dsr |= (uint32_t)device_type << OCTA_DSR0_DV0TYP_POS; + mmio_write_32(myctrl->reg_base + OCTA_DSR0, dsr); + } + initialised[myctrl->channel] = true; + } + + myctrl->opened = true; + + return result; +} + +static int octa_close(xspi_ctrl_t *const ctrl) +{ + int result = -1; + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + if (myctrl->opened) { + myctrl->opened = false; + result = 0; + } + return result; +} + +static bool octa_check_acmode_ready(bool acmeme, bool is_dopi, int channel) +{ + if (!initialised[channel]) + return true; /* Ignore for empty channel */ + if (!is_dopi) + return true; /* Ignore or SPI/SOPI channel */ + if (!is_calibrated[channel]) + return true; /* Ignore if failed the manual calibration */ + return acmeme; /* On DOPI, Follow acmeme setting */ +} + +static void octa_set_acmode(uint32_t *cdsr) +{ + if (post_init_done) { + bool flag_0, flag_1, acmeme0, acmeme1, is_dopi; + + /* Check if CH0 is ready for enabling ACMODE */ + acmeme0 = (*cdsr & OCTA_CDSR_ACMEME0) != 0; + is_dopi = (*cdsr & OCTA_CDSR_DV0TTYP) == + (OCTA_CDSR_DVTTYP_DOPI << OCTA_CDSR_DV0TTYP_POS); + flag_0 = octa_check_acmode_ready(acmeme0, is_dopi, 0); + + /* Check if CH1 is ready for enabling ACMODE */ + acmeme1 = (*cdsr & OCTA_CDSR_ACMEME1) != 0; + is_dopi = (*cdsr & OCTA_CDSR_DV1TTYP) == + (OCTA_CDSR_DVTTYP_DOPI << OCTA_CDSR_DV1TTYP_POS); + flag_1 = octa_check_acmode_ready(acmeme1, is_dopi, 1); + + /* mask old value */ + *cdsr &= ~OCTA_CDSR_ACMODE; + + /* When both CH0/CH1 are ready for enabling ACMODE and */ + /* either ACMEME0 or ACMEME1 is enabled */ + if (flag_0 && flag_1 && (acmeme0 || acmeme1)) { + *cdsr |= OCTA_CDSR_ACMODE_ENABLE + << OCTA_CDSR_ACMODE_POS; + } + } +} + +static void octa_set_auto_calibration(octa_ctrl_t *myctrl) +{ + uint32_t cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + + /* Set/reset ACMODE */ + octa_set_acmode(&cdsr); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, cdsr & ~OCTA_CDSR_ACMODE); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, cdsr); +} + +static int octa_post_init(xspi_ctrl_t *const ctrl) +{ + int result = 0; + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + + if (!post_init_done) { + post_init_done = true; + octa_set_auto_calibration(myctrl); + } + + return result; +} + +static int octa_test_ddr(xspi_op_t const *const op) +{ + if (!(op->op_is_ddr == op->address_is_ddr)) + return -1; + if (!op->op_is_ddr && !op->address_is_ddr && op->transfer_is_ddr) + return -1; + return 0; +} + +static int octa_test_form(octa_ctrl_t const *const myctrl, + xspi_op_t const *const op) +{ + if (!(myctrl->device_type != OCTA_DSR_TYP_NONE)) + return -1; + if (!((myctrl->device_type == OCTA_DSR_TYP_FLASH && + (op->form == SPI_FORM_8_8_8 || + (op->form == SPI_FORM_1_1_1 && !op->op_is_ddr && + !op->address_is_ddr && !op->transfer_is_ddr))) || + (myctrl->device_type == OCTA_DSR_TYP_RAM && + op->form == SPI_FORM_8_8_8 && op->op_is_ddr && + op->address_is_ddr && op->transfer_is_ddr))) + return -1; + return 0; +} + +static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, + bool is_write) +{ + assert(!!ctrl); + assert(!!op); + int res; + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + res = octa_test_ddr(op); + if (!!res) + return res; + res = octa_test_form(myctrl, op); + if (!!res) + return res; + + assert(op->transfer_size == 0 || op->transfer_size == 1 || + op->transfer_size == 2 || op->transfer_size == 4 || + (op->transfer_size == 3 && op->transfer_is_ddr == false && + is_write == false)); + + uint32_t dcstr; + uint32_t dcsr_clear, dcsr_set; + dcsr_clear = dcsr_set = 0; + uint32_t cdsr_clear, cdsr_set, save_cdsr; + cdsr_clear = cdsr_set = 0; + uint32_t mdtr_clear, mdtr_set, save_mdtr; + mdtr_clear = mdtr_set = 0; + + /* change write flag if no transfer phase required */ + if (op->transfer_size == 0) + is_write = true; + + /* select and check memory type */ + int transfer_type; + int enable_counter; + switch (op->form) { + case SPI_FORM_8_8_8: + if (op->op_is_ddr) { + /* DOPI */ + if (myctrl->device_type == OCTA_DSR_TYP_RAM) { + transfer_type = OCTA_CDSR_DVTTYP_DOPI; + enable_counter = op->dummy_cycles + 1; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSERAM; + mdtr_set |= enable_counter + << OCTA_MDTR_DQSERAM_POS; + } else { + transfer_type = OCTA_CDSR_DVTTYP_DOPI; + enable_counter = op->dummy_cycles + 2; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSEDOPI; + mdtr_set |= enable_counter + << OCTA_MDTR_DQSEDOPI_POS; + } + } else { + /* SOPI */ + transfer_type = OCTA_CDSR_DVTTYP_SOPI; + enable_counter = op->dummy_cycles + 4; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSESOPI; + mdtr_set |= enable_counter << OCTA_MDTR_DQSESOPI_POS; + } + break; + case SPI_FORM_1_1_1: + transfer_type = OCTA_CDSR_DVTTYP_SPI; + break; + default: + ERROR("Unsupported transfer form %d\n", op->form); + return -1; + } + + /* lock channel (not implemented) */ + + /* save shared parameters */ + save_cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + save_mdtr = mmio_read_32(myctrl->reg_base + OCTA_MDTR); + + /* set controller operation parameters */ + mmio_write_32(myctrl->reg_base + OCTA_DCR, (uint32_t)op->op); + mmio_write_32(myctrl->reg_base + OCTA_DAR, op->address); + dcstr = op->slch_value << OCTA_DCSTR_DVSELLO_POS; + dcstr |= op->clsh_value << OCTA_DCSTR_DVSELHI_POS; + dcstr |= op->shsl_value << OCTA_DCSTR_DVSELCMD_POS; + mmio_write_32(myctrl->reg_base + OCTA_DCSTR, dcstr); + cdsr_clear |= OCTA_CDSR_ACMODE; + dcsr_clear |= OCTA_DCSR_ADLEN; + dcsr_set |= op->address_size << OCTA_DCSR_ADLEN_POS; + dcsr_clear |= OCTA_DCSR_CMDLEN; + dcsr_set |= op->op_size << OCTA_DCSR_CMDLEN_POS; + dcsr_clear |= OCTA_DCSR_DMLEN; + dcsr_set |= op->dummy_cycles << OCTA_DCSR_DMLEN_POS; + dcsr_clear |= OCTA_DCSR_DALEN; + /* For 3-byte transfer, modify as 4byte transfer */ + dcsr_set |= (op->transfer_size == 3 ? 4u : op->transfer_size) + << OCTA_DCSR_DALEN_POS; + /* Force data access method */ + dcsr_clear |= OCTA_DCSR_ACDA; + if (op->transfer_flag & XSPI_FLAGS_DATA_ACCESS) { + dcsr_set |= OCTA_DCSR_ACDA; + } + + /* set channel related parameters */ + dcsr_clear |= OCTA_DCSR_ACDV; + dcsr_set |= myctrl->channel << OCTA_DCSR_ACDV_POS; + if (myctrl->channel) { + /* Channel 1 */ + cdsr_clear |= OCTA_CDSR_DV1PC | OCTA_CDSR_DV1TTYP; + cdsr_set |= transfer_type << OCTA_CDSR_DV1TTYP_POS; + } else { + /* Channel 0 */ + cdsr_clear |= OCTA_CDSR_DV0PC | OCTA_CDSR_DV0TTYP; + cdsr_set |= transfer_type << OCTA_CDSR_DV0TTYP_POS; + } + + /* change transfer order */ + dcsr_clear |= OCTA_DCSR_DAOR; + if (~op->transfer_flag & XSPI_FLAGS_SEQUENTIAL_DDR) { + if (op->transfer_is_ddr) { + dcsr_set |= OCTA_DCSR_DAOR; + } + } + /* change SDR mode (DOPI mode with SDR transfer) */ + dcsr_clear |= OCTA_DCSR_DOPI; + if (transfer_type == OCTA_CDSR_DVTTYP_DOPI && !op->transfer_is_ddr) { + dcsr_set |= OCTA_DCSR_DOPI; + } + + mmio_clrsetbits_32(myctrl->reg_base + OCTA_DCSR, dcsr_clear, dcsr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_CDSR, cdsr_clear, cdsr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MDTR, mdtr_clear, mdtr_set); + + if (is_write) { + switch (op->transfer_size) { + case 0: + mmio_write_32(myctrl->reg_base + OCTA_CWNDR, 0); + break; + case 1: + mmio_write_8(myctrl->reg_base + OCTA_CWDR, + *(uint8_t *)op->transfer_buffer); + break; + case 2: + mmio_write_16(myctrl->reg_base + OCTA_CWDR, + *(uint16_t *)op->transfer_buffer); + break; + case 4: + mmio_write_32(myctrl->reg_base + OCTA_CWDR, + *(uint32_t *)op->transfer_buffer); + break; + } + } else { + mmio_read_32(myctrl->reg_base + OCTA_CDSR); + switch (op->transfer_size) { + case 1: + *(uint8_t *)op->transfer_buffer = + mmio_read_8(myctrl->reg_base + OCTA_CRR); + break; + case 2: + *(uint16_t *)op->transfer_buffer = + mmio_read_16(myctrl->reg_base + OCTA_CRR); + break; + case 3: { + uint32_t tmp = + mmio_read_32(myctrl->reg_base + OCTA_CRR); + uint8_t *u8p = (uint8_t *)op->transfer_buffer; + u8p[0] = tmp & 0xff; + u8p[1] = tmp & 0xff00 >> 8; + u8p[2] = tmp & 0xff0000 >> 16; + break; + } + case 4: + *(uint32_t *)op->transfer_buffer = + mmio_read_32(myctrl->reg_base + OCTA_CRR); + break; + } + } + + /* restore shared parameters */ + mmio_write_32(myctrl->reg_base + OCTA_MDTR, save_mdtr); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, save_cdsr); + + /* unlock channel (not implemented) */ + + return 0; +} + +static void octa_configure_xip_ch1(octa_ctrl_t *const myctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop) +{ + uint32_t mdlr_clear, mdlr_set; + mdlr_clear = mdlr_set = 0; + uint32_t mrwcr_clear, mrwcr_set; + mrwcr_clear = mrwcr_set = 0; + uint32_t mrwcsr_clear, mrwcsr_set; + mrwcsr_clear = mrwcsr_set = 0; + + if (rop) { + uint32_t drcstr_clear, drcstr_set; + drcstr_clear = drcstr_set = 0; + drcstr_clear |= OCTA_DRCSTR_DVRDLO1 | OCTA_DRCSTR_DVRDHI1 | + OCTA_DRCSTR_DVRDCMD1; + drcstr_set |= rop->slch_value << OCTA_DRCSTR_DVRDLO1_POS; + drcstr_set |= rop->clsh_value << OCTA_DRCSTR_DVRDHI1_POS; + drcstr_set |= rop->shsl_value << OCTA_DRCSTR_DVRDCMD1_POS; + mdlr_clear |= OCTA_MDLR_DV1RDL; + mdlr_set |= rop->dummy_cycles << OCTA_MDLR_DV1RDL_POS; + mrwcr_clear |= OCTA_MRWCR1_D1MRCMD0 | OCTA_MRWCR1_D1MRCMD1; + mrwcr_set |= (uint32_t)rop->op << OCTA_MRWCR1_D1MRCMD0_POS; + mrwcsr_clear |= OCTA_MRWCSR_MRO1 | OCTA_MRWCSR_MRCL1 | + OCTA_MRWCSR_MRAL1; + if (rop->transfer_is_ddr && + ~rop->transfer_flag & XSPI_FLAGS_SEQUENTIAL_DDR) { + mrwcsr_set |= 1u << OCTA_MRWCSR_MRO1_POS; + } + mrwcsr_set |= rop->op_size << OCTA_MRWCSR_MRCL1_POS; + mrwcsr_set |= rop->address_size << OCTA_MRWCSR_MRAL1_POS; + mmio_clrsetbits_32(myctrl->reg_base + OCTA_DRCSTR, drcstr_clear, + drcstr_set); + } + if (wop) { + uint32_t dwcstr_clear, dwcstr_set; + dwcstr_clear = dwcstr_set = 0; + dwcstr_clear |= OCTA_DWCSTR_DVWLO1 | OCTA_DWCSTR_DVWHI1 | + OCTA_DWCSTR_DVWCMD1; + dwcstr_set |= wop->slch_value << OCTA_DWCSTR_DVWLO1_POS; + dwcstr_set |= wop->clsh_value << OCTA_DWCSTR_DVWHI1_POS; + dwcstr_set |= wop->shsl_value << OCTA_DWCSTR_DVWCMD1_POS; + mdlr_clear |= OCTA_MDLR_DV1WDL; + mdlr_set |= wop->dummy_cycles << OCTA_MDLR_DV1WDL_POS; + mrwcr_clear |= OCTA_MRWCR1_D1MWCMD0 | OCTA_MRWCR1_D1MWCMD1; + mrwcr_set |= (uint32_t)wop->op << OCTA_MRWCR1_D1MWCMD0_POS; + mrwcsr_clear |= OCTA_MRWCSR_MWO1 | OCTA_MRWCSR_MWCL1 | + OCTA_MRWCSR_MWAL1; + if (wop->transfer_is_ddr && + ~wop->transfer_flag & XSPI_FLAGS_SEQUENTIAL_DDR) { + mrwcsr_set |= 1u << OCTA_MRWCSR_MWO1_POS; + } + mrwcsr_set |= wop->op_size << OCTA_MRWCSR_MWCL1_POS; + mrwcsr_set |= wop->address_size << OCTA_MRWCSR_MWAL1_POS; + mmio_clrsetbits_32(myctrl->reg_base + OCTA_DWCSTR, dwcstr_clear, + dwcstr_set); + } + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MDLR, mdlr_clear, mdlr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MRWCR1, mrwcr_clear, + mrwcr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MRWCSR, mrwcsr_clear, + mrwcsr_set); +} + +static void octa_configure_xip_ch0(octa_ctrl_t *const myctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop) +{ + uint32_t mdlr_clear, mdlr_set; + mdlr_clear = mdlr_set = 0; + uint32_t mrwcr_clear, mrwcr_set; + mrwcr_clear = mrwcr_set = 0; + uint32_t mrwcsr_clear, mrwcsr_set; + mrwcsr_clear = mrwcsr_set = 0; + + if (rop) { + uint32_t drcstr_clear, drcstr_set; + drcstr_clear = drcstr_set = 0; + drcstr_clear |= OCTA_DRCSTR_DVRDLO0 | OCTA_DRCSTR_DVRDHI0 | + OCTA_DRCSTR_DVRDCMD0; + drcstr_set |= rop->slch_value << OCTA_DRCSTR_DVRDLO0_POS; + drcstr_set |= rop->clsh_value << OCTA_DRCSTR_DVRDHI0_POS; + drcstr_set |= rop->shsl_value << OCTA_DRCSTR_DVRDCMD0_POS; + mdlr_clear |= OCTA_MDLR_DV0RDL; + mdlr_set |= rop->dummy_cycles << OCTA_MDLR_DV0RDL_POS; + mrwcr_clear |= OCTA_MRWCR0_D0MRCMD0 | OCTA_MRWCR0_D0MRCMD1; + mrwcr_set |= (uint32_t)rop->op << OCTA_MRWCR0_D0MRCMD0_POS; + mrwcsr_clear |= OCTA_MRWCSR_MRO0 | OCTA_MRWCSR_MRCL0 | + OCTA_MRWCSR_MRAL0; + if (rop->transfer_is_ddr && + ~rop->transfer_flag & XSPI_FLAGS_SEQUENTIAL_DDR) { + mrwcsr_set |= 1u << OCTA_MRWCSR_MRO0_POS; + } + mrwcsr_set |= rop->op_size << OCTA_MRWCSR_MRCL0_POS; + mrwcsr_set |= rop->address_size << OCTA_MRWCSR_MRAL0_POS; + mmio_clrsetbits_32(myctrl->reg_base + OCTA_DRCSTR, drcstr_clear, + drcstr_set); + } + if (wop) { + uint32_t dwcstr_clear, dwcstr_set; + dwcstr_clear = dwcstr_set = 0; + dwcstr_clear |= OCTA_DWCSTR_DVWLO0 | OCTA_DWCSTR_DVWHI0 | + OCTA_DWCSTR_DVWCMD0; + dwcstr_set |= wop->slch_value << OCTA_DWCSTR_DVWLO0_POS; + dwcstr_set |= wop->clsh_value << OCTA_DWCSTR_DVWHI0_POS; + dwcstr_set |= wop->shsl_value << OCTA_DWCSTR_DVWCMD0_POS; + mdlr_clear |= OCTA_MDLR_DV0WDL; + mdlr_set |= wop->dummy_cycles << OCTA_MDLR_DV0WDL_POS; + mrwcr_clear |= OCTA_MRWCR0_D0MWCMD0 | OCTA_MRWCR0_D0MWCMD1; + mrwcr_set |= (uint32_t)wop->op << OCTA_MRWCR0_D0MWCMD0_POS; + mrwcsr_clear |= OCTA_MRWCSR_MWO0 | OCTA_MRWCSR_MWCL0 | + OCTA_MRWCSR_MWAL0; + if (wop->transfer_is_ddr && + ~wop->transfer_flag & XSPI_FLAGS_SEQUENTIAL_DDR) { + mrwcsr_set |= 1u << OCTA_MRWCSR_MWO0_POS; + } + mrwcsr_set |= wop->op_size << OCTA_MRWCSR_MWCL0_POS; + mrwcsr_set |= wop->address_size << OCTA_MRWCSR_MWAL0_POS; + mmio_clrsetbits_32(myctrl->reg_base + OCTA_DWCSTR, dwcstr_clear, + dwcstr_set); + } + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MDLR, mdlr_clear, mdlr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MRWCR0, mrwcr_clear, + mrwcr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MRWCSR, mrwcsr_clear, + mrwcsr_set); +} + +static int octa_configure_xip(xspi_ctrl_t *const ctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop) +{ + assert(ctrl); + assert(!!rop || !!wop); + if (!rop && !wop) + return -1; + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + xspi_op_t const *op = NULL; + if (wop) { + op = wop; + octa_test_ddr(wop); + octa_test_form(myctrl, wop); + } + if (rop) { + op = rop; + octa_test_ddr(rop); + octa_test_form(myctrl, rop); + } + if (rop && wop) { + assert(rop->form == wop->form); + assert(rop->op_is_ddr == wop->op_is_ddr && + rop->address_is_ddr == wop->address_is_ddr && + rop->transfer_is_ddr == wop->transfer_is_ddr); + } + + uint32_t cdsr_clear, cdsr_set, mdtr_clear, mdtr_set; + cdsr_clear = cdsr_set = mdtr_clear = mdtr_set = 0; + + int transfer_type; + int enable_counter; + + switch (op->form) { + case SPI_FORM_8_8_8: + if (op->op_is_ddr) { + /* DOPI */ + if (myctrl->device_type == OCTA_DSR_TYP_RAM) { + transfer_type = OCTA_CDSR_DVTTYP_DOPI; + if (rop) { + enable_counter = rop->dummy_cycles + 1; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSERAM; + mdtr_set |= enable_counter + << OCTA_MDTR_DQSERAM_POS; + } + if (myctrl->channel && !RZA3) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR1, 0); + } else if (!myctrl->channel) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR0, 0); + } + } else { + transfer_type = OCTA_CDSR_DVTTYP_DOPI; + if (rop) { + enable_counter = rop->dummy_cycles + 2; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSEDOPI; + mdtr_set |= enable_counter + << OCTA_MDTR_DQSEDOPI_POS; + } + if (myctrl->channel && !RZA3) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR1, + OCTA_DRCSTR_CTR1); + } else if (!myctrl->channel) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR0, + OCTA_DRCSTR_CTR0); + } + } + } else { + /* SOPI */ + transfer_type = OCTA_CDSR_DVTTYP_SOPI; + if (rop) { + enable_counter = rop->dummy_cycles + 4; + if (enable_counter > 15) + enable_counter = 15; + mdtr_clear |= OCTA_MDTR_DQSESOPI; + mdtr_set |= enable_counter + << OCTA_MDTR_DQSESOPI_POS; + } + if (myctrl->channel && !RZA3) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR1, 0); + } else if (!myctrl->channel) { + mmio_clrsetbits_32(myctrl->reg_base + + OCTA_DRCSTR, + OCTA_DRCSTR_CTR0, 0); + } + } + break; + case SPI_FORM_1_1_1: + transfer_type = OCTA_CDSR_DVTTYP_SPI; + break; + default: + ERROR("Unsupported transfer form %d\n", rop->form); + return -1; + } + + if (myctrl->channel) { + octa_configure_xip_ch1(myctrl, rop, wop); + cdsr_clear |= OCTA_CDSR_DV1TTYP; + cdsr_set |= transfer_type << OCTA_CDSR_DV1TTYP_POS; + cdsr_clear |= OCTA_CDSR_DV1PC; + } else { + octa_configure_xip_ch0(myctrl, rop, wop); + cdsr_clear |= OCTA_CDSR_DV0TTYP; + cdsr_set |= transfer_type << OCTA_CDSR_DV0TTYP_POS; + cdsr_clear |= OCTA_CDSR_DV0PC; + } + + mmio_clrsetbits_32(myctrl->reg_base + OCTA_MDTR, mdtr_clear, mdtr_set); + mmio_clrsetbits_32(myctrl->reg_base + OCTA_CDSR, cdsr_clear, cdsr_set); + + return 0; +} + +static int octa_start_xip(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + /* Flush write buffer for OCTA controller register space */ + mmio_read_32(myctrl->reg_base + OCTA_DCR); + /* Invalidate cache */ + inv_dcache_range(myctrl->mmap_base, myctrl->mmap_size); + + return 0; +} + +static int octa_stop_xip(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + /* Clean cache */ + clean_dcache_range(myctrl->mmap_base, myctrl->mmap_size); + + return 0; +} + +#define DELAY_LEVELS 16 +static int get_ok_area_start(bool *p_s_ok_ng_result) +{ + int index; /**< loop counter */ + int index_start = -1; + + /* detect ok area index start */ + for (index = 0; index < DELAY_LEVELS; index++) { + if (p_s_ok_ng_result[index]) { + index_start = index; + break; + } + } + return index_start; +} + +static int get_ok_area_count(bool *p_s_ok_ng_result, int index_start) +{ + int index; /**< loop counter */ + int ok_cnt = 0; + + /* count number of ok */ + for (index = index_start; index < DELAY_LEVELS; index++) { + if (p_s_ok_ng_result[index]) { + ok_cnt++; + } else { + break; + } + } + return ok_cnt; +} + +static int octa_manual_calibration_common(octa_ctrl_t *myctrl) +{ + volatile uint32_t *p_preamble; + int judge_result; + int i; + int index; /**< loop counter */ + int index_start = -1; + int ok_cnt = 0; + bool is_ok[DELAY_LEVELS]; + + uint32_t mdtr = mmio_read_32(myctrl->reg_base + OCTA_MDTR); + uint32_t mdtr_save = mdtr; + int mdtr_pos; + if (myctrl->channel) { + mdtr &= ~OCTA_MDTR_DV1DEL; + mdtr_pos = OCTA_MDTR_DV1DEL_POS; + } else { + mdtr &= ~OCTA_MDTR_DV0DEL; + mdtr_pos = OCTA_MDTR_DV0DEL_POS; + } + + /* detect ok/ng area */ + uintptr_t offset = (uintptr_t)myctrl->calibration_base; + offset += myctrl->mmap_base; + p_preamble = (uint32_t *)offset; + for (index = 0; index < DELAY_LEVELS; index++) { + /* Set DQS delay value */ + mmio_write_32(myctrl->reg_base + OCTA_MDTR, + mdtr | (index * 256 / DELAY_LEVELS) << mdtr_pos); + mmio_read_32(myctrl->reg_base + OCTA_MDTR); + + /* Read preamble data and test */ + judge_result = 0; + + inv_dcache_range((uintptr_t)p_preamble, 16); + for (i = 0; i < 4; i++) { + if (preamble[i] != p_preamble[i]) { + judge_result = 1; + break; + } + } + + /* Store the judgement result in the table */ + if (0 == judge_result) { + is_ok[index] = true; + } else { /* Continuous OK region */ + is_ok[index] = false; + } + } + + /* Search for the start index of the OK area */ + index_start = get_ok_area_start(is_ok); + if ((-1) == index_start) { + /* restore old value */ + mmio_write_32(myctrl->reg_base + OCTA_MDTR, mdtr_save); + mmio_read_32(myctrl->reg_base + OCTA_MDTR); + return -1; /* OK area not found */ + } + + /* Find the number of OK areas */ + ok_cnt = get_ok_area_count(is_ok, index_start); + + if (3 < ok_cnt) { + /* Set DQS delay value */ + uint32_t delay = + (index_start + (ok_cnt >> 1)) * (256 / DELAY_LEVELS); + mmio_write_32(myctrl->reg_base + OCTA_MDTR, + mdtr | delay << mdtr_pos); + mmio_read_32(myctrl->reg_base + OCTA_MDTR); + return 0; + } else { + /* restore old value */ + mmio_write_32(myctrl->reg_base + OCTA_MDTR, mdtr_save); + mmio_read_32(myctrl->reg_base + OCTA_MDTR); + return -1; + } +} + +static void octa_write_preamble_pattern(octa_ctrl_t *myctrl) +{ + const uint32_t *pattern = &preamble[0]; + uintptr_t wp = myctrl->mmap_base; + wp += (uintptr_t)myctrl->calibration_base; + volatile uint32_t *w_pattern = (uint32_t *)wp; + *w_pattern++ = *pattern++; + *w_pattern++ = *pattern++; + *w_pattern++ = *pattern++; + *w_pattern++ = *pattern++; + clean_dcache_range(wp, 16); +} + +static int octa_manual_calibration_ch0(octa_ctrl_t *myctrl) +{ + int result; + static bool is_prepared; + uint32_t cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + uint32_t ch0_transfer_type = (cdsr & OCTA_CDSR_DV0TTYP) >> + OCTA_CDSR_DV0TTYP_POS; + if (ch0_transfer_type != OCTA_CDSR_DVTTYP_DOPI) + return 0; + if (!is_prepared) { + uint32_t dsr0 = mmio_read_32(myctrl->reg_base + OCTA_DSR0); + uint32_t ch0_device_type = (dsr0 & OCTA_DSR0_DV0TYP) >> + OCTA_DSR0_DV0TYP_POS; + if (ch0_device_type == OCTA_DSR_TYP_RAM) { + octa_write_preamble_pattern(myctrl); + } + is_prepared = true; + } + if (octa_manual_calibration_common(myctrl) < 0) { + ERROR("octa.c:%s Fail on manual calibration\n", __func__); + result = -1; + } else { + is_calibrated[0] = true; + result = 0; + } + return result; +} + +static int octa_manual_calibration_ch1(octa_ctrl_t *myctrl) +{ + int result; + static bool is_prepared; + uint32_t cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + uint32_t ch1_transfer_type = (cdsr & OCTA_CDSR_DV1TTYP) >> + OCTA_CDSR_DV1TTYP_POS; + if (ch1_transfer_type != OCTA_CDSR_DVTTYP_DOPI) + return 0; + if (!is_prepared) { + uint32_t dsr1 = mmio_read_32(myctrl->reg_base + OCTA_DSR1); + uint32_t ch1_device_type = (dsr1 & OCTA_DSR1_DV1TYP) >> + OCTA_DSR1_DV1TYP_POS; + if (ch1_device_type == OCTA_DSR_TYP_RAM) { + octa_write_preamble_pattern(myctrl); + } + is_prepared = true; + } + if (octa_manual_calibration_common(myctrl) < 0) { + ERROR("octa.c:%s Fail on manual calibration\n", __func__); + result = -1; + } else { + is_calibrated[1] = true; + result = 0; + } + return result; +} + +static int octa_run_manual_calibration(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + int result; + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + if (myctrl->channel) { + /* Channel 1 */ + result = octa_manual_calibration_ch1(myctrl); + } else { + /* Channel 0 */ + result = octa_manual_calibration_ch0(myctrl); + } + + return result; +} + +static int octa_enable_auto_calibration(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + uint32_t cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + bool en; + + /* Check condition per channel and set/reset ACMEME */ + if (myctrl->channel) { + en = is_calibrated[1] && + (cdsr & OCTA_CDSR_DV1TTYP) == + (OCTA_CDSR_DVTTYP_DOPI << OCTA_CDSR_DV1TTYP_POS); + if (en) + cdsr |= OCTA_CDSR_ACMEME1; + else + cdsr &= ~OCTA_CDSR_ACMEME1; + } else { + en = is_calibrated[0] && + (cdsr & OCTA_CDSR_DV0TTYP) == + (OCTA_CDSR_DVTTYP_DOPI << OCTA_CDSR_DV0TTYP_POS); + if (en) + cdsr |= OCTA_CDSR_ACMEME0; + else + cdsr &= ~OCTA_CDSR_ACMEME0; + } + + /* Set/reset ACMODE */ + octa_set_acmode(&cdsr); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, cdsr & ~OCTA_CDSR_ACMODE); + mmio_write_32(myctrl->reg_base + OCTA_CDSR, cdsr); + + return 0; +} + +static int octa_disable_auto_calibration(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + uint32_t cdsr = mmio_read_32(myctrl->reg_base + OCTA_CDSR); + + /* Reset ACMEMEn */ + if (myctrl->channel) { + cdsr &= ~OCTA_CDSR_ACMEME1; + } else { + cdsr &= ~OCTA_CDSR_ACMEME0; + } + + /* Reset ACMODE */ + cdsr &= ~OCTA_CDSR_ACMODE; + mmio_write_32(myctrl->reg_base + OCTA_CDSR, cdsr); + + return 0; +} + +static int octa_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz) +{ + assert(ctrl); + assert(frequency_hz > 0); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + + freq[myctrl->channel] = frequency_hz; + int freq_request; + + freq_request = freq[0]; + if (freq_request > freq[1]) + freq_request = freq[1]; + + int result = cpg_set_xspi_clock(XSPI_CLOCK_OCTA, freq_request * 4); + if (result != 0) + return result; + int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_OCTA); + if (actual_freq == -1) + return -1; + spi_clock = actual_freq / 4; + + return 0; +} + +static int octa_clean_mmap(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + clean_dcache_range(myctrl->mmap_base, myctrl->mmap_size); + + return 0; +} + +static int octa_inv_mmap(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + inv_dcache_range(myctrl->mmap_base, myctrl->mmap_size); + + return 0; +} + +static uintptr_t octa_get_mmap_base(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + return myctrl->mmap_base; +} + +static size_t octa_get_mmap_size(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + return myctrl->mmap_size; +} + +static uint32_t octa_get_features(xspi_ctrl_t *const ctrl) +{ + (void)ctrl; + uint32_t features = 0; + features |= XSPI_FEATURE_FORM888; + features |= XSPI_FEATURE_DDR; + features |= XSPI_FEATURE_DDROP; + features |= XSPI_FEATURE_XIP_READ; + features |= XSPI_FEATURE_XIP_WRITE; + + return features; +} diff --git a/plat/renesas/rza/common/drivers/xspi/spim.c b/plat/renesas/rza/common/drivers/xspi/spim.c new file mode 100644 index 0000000000..1884e5864e --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspi/spim.c @@ -0,0 +1,1231 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Defaults */ +#define DEFAULT_SPI_FREQUENCY 66666667 +#define RESET_DURATION_US 10 +#define DEFAULT_VOLTAGE_IS_1800MV 1 + +/* Static function pre-definition */ +static int spim_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg); +static int spim_close(xspi_ctrl_t *const ctrl); +static int spim_post_init(xspi_ctrl_t *const ctrl); +static int spim_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, + bool is_write); +static int spim_configure_xip(xspi_ctrl_t *const ctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop); +static int spim_start_xip(xspi_ctrl_t *const ctrl); +static int spim_stop_xip(xspi_ctrl_t *const ctrl); +static int spim_run_manual_calibration(xspi_ctrl_t *const ctrl); +static int spim_enable_auto_calibration(xspi_ctrl_t *const ctrl); +static int spim_disable_auto_calibration(xspi_ctrl_t *const ctrl); +static int spim_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz); +static int spim_clean_mmap(xspi_ctrl_t *const ctrl); +static int spim_inv_mmap(xspi_ctrl_t *const ctrl); +static uintptr_t spim_get_mmap_base(xspi_ctrl_t *const ctrl); +static size_t spim_get_mmap_size(xspi_ctrl_t *const ctrl); +static uint32_t spim_get_features(xspi_ctrl_t *const ctrl); + +/* API function table definition */ +const xspi_api_t spim_api = { + .open = spim_open, + .close = spim_close, + .post_init = spim_post_init, + .exec_op = spim_exec_op, + .configure_xip = spim_configure_xip, + .start_xip = spim_start_xip, + .stop_xip = spim_stop_xip, + .run_manual_calibration = spim_run_manual_calibration, + .enable_auto_calibration = spim_enable_auto_calibration, + .disable_auto_calibration = spim_disable_auto_calibration, + .set_frequency = spim_set_frequency, + .clean_mmap = spim_clean_mmap, + .inv_mmap = spim_inv_mmap, + .get_mmap_base = spim_get_mmap_base, + .get_mmap_size = spim_get_mmap_size, + .get_features = spim_get_features, +}; + +/* Static variables */ +static bool globally_initialised; +static int spi_clock = DEFAULT_SPI_FREQUENCY; + +/* Function definitions */ +static void wait_until_32(uintptr_t addr, uint32_t mask, uint32_t data) +{ + while ((mmio_read_32(addr) & mask) != data) { + }; +} + +static void select_spim(spim_ctrl_t *myctrl, xspi_cfg_t const *const cfg) +{ + if (RZ_XSPI_EXCLUSIVE_SELECTOR) { + /* Check if OCTA selected */ + uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + if ((ipcont_spi_octa & IPCONT_SEL_SPI_OCTA) == + IPCONT_SEL_SPI_OCTA_OCTA) { + /* Reset the OCTA controller and the devices connected, + * required to change the device mode from OPI to SPI. + * Otherwise, the octa devices can not communicate with the SPIM controller. + */ + /* Assert reset line */ + mmio_clrbits_32(myctrl->reg_base + OCTA_RSTCNT, + OCTA_RSTCNT_RSTVAL); + + /* Reset OCTA controller */ + cpg_reset_on(CPG_CLOCK_OCTA); + + /* Stop OCTA clock */ + cpg_clock_off(CPG_CLOCK_OCTA); + } + } + + /* Wait for reset SPI device */ + udelay(RESET_DURATION_US); + + if (RZ_XSPI_FORCE_VOLTAGE_SETTING) { + /* force voltage setting + * Note: This is required if the boot mode is neither 3 nor 4. + */ + uint8_t voltage = DEFAULT_VOLTAGE_IS_1800MV; + if (cfg->extend) { + const spim_ext_t *ext = (const spim_ext_t *)cfg->extend; + if (ext->voltage_is_3300mv) + voltage = 0; + } + mmio_write_8(PFC_QSPI, voltage); + mmio_read_8(PFC_QSPI); + } + + /* Supply SPIM clock (currently not implemented) */ + cpg_clock_on(CPG_CLOCK_SPIM); + + /* Resume SPIM controller (currently not implemented) */ + cpg_reset_off(CPG_CLOCK_SPIM); + + if (RZ_XSPI_EXCLUSIVE_SELECTOR) { + /* Select SPIM for SPI controller */ + uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + ipcont_spi_octa &= ~IPCONT_SEL_SPI_OCTA; + ipcont_spi_octa |= IPCONT_SEL_SPI_OCTA_SPI + << IPCONT_SEL_SPI_OCTA_POS; + mmio_write_32(SYS_IPCONT, ipcont_spi_octa); + mmio_read_32(SYS_IPCONT); + } +} + +static void test_tend(const spim_ctrl_t *myctrl) +{ + wait_until_32(myctrl->reg_base + SPIM_CMNSR, SPIM_CMNSR_TEND, + SPIM_CMNSR_TEND); +} + +static void spim_init_phy(const spim_ctrl_t *myctrl) +{ + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ2, 0xa5390000); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ1, 0x80000000); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ2, 0x00008080); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ1, 0x80000022); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ2, 0x00008080); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ1, 0x80000024); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ2, 0x00000030); + mmio_write_32(myctrl->reg_base + SPIM_PHYADJ1, 0x80000032); +} + +static const uint32_t cmncr_init_mask = SPIM_CMNCR_BSZ | SPIM_CMNCR_IO0FV | + SPIM_CMNCR_IO2FV | SPIM_CMNCR_IO3FV | + SPIM_CMNCR_MOIIO0 | SPIM_CMNCR_MOIIO1 | + SPIM_CMNCR_MOIIO2 | SPIM_CMNCR_MOIIO3; +/* IOn maintained as Hi-Z at idle + * IO0 Value sets Hi-Z while dummy and 1-bit read transfer phase + * IO2/IO3 Value sets high while 1-bit command/address/additional-data phase + */ +static const uint32_t cmncr_init_value = + 1u << SPIM_CMNCR_MD_POS | SPIM_CMNCR_BSZ_SINGLE << SPIM_CMNCR_BSZ_POS | + SPIM_CMNCR_IO_HIZ << SPIM_CMNCR_IO0FV_POS | + SPIM_CMNCR_IO_HIGH << SPIM_CMNCR_IO2FV_POS | + SPIM_CMNCR_IO_HIGH << SPIM_CMNCR_IO3FV_POS | + SPIM_CMNCR_IO_HIZ << SPIM_CMNCR_MOIIO0_POS | + SPIM_CMNCR_IO_HIZ << SPIM_CMNCR_MOIIO1_POS | + SPIM_CMNCR_IO_HIZ << SPIM_CMNCR_MOIIO2_POS | + SPIM_CMNCR_IO_HIZ << SPIM_CMNCR_MOIIO3_POS; + +static const uint32_t ssldr_init_mask = SPIM_SSLDR_SCKDL | SPIM_SSLDR_SLNDL | + SPIM_SSLDR_SPNDL; +static const uint32_t ssldr_init_value = 0u << SPIM_SSLDR_SCKDL_POS | + 0u << SPIM_SSLDR_SLNDL_POS | + 0u << SPIM_SSLDR_SPNDL_POS; + +static const uint32_t drcr_init_mask = SPIM_DRCR_RBURST | SPIM_DRCR_RCF | + SPIM_DRCR_RBE | SPIM_DRCR_SSLE; +static const uint32_t drcr_init_value = + 7u << SPIM_DRCR_RBURST_POS | 1u << SPIM_DRCR_RCF_POS | + 1u << SPIM_DRCR_RBE_POS | 1u << SPIM_DRCR_SSLE_POS; + +static const uint32_t drear_init_mask = SPIM_DREAR_EAC | SPIM_DREAR_EAV; +static const uint32_t drear_init_value = 3u << SPIM_DREAR_EAC_POS | + 0u << SPIM_DREAR_EAV_POS; + +static const uint32_t drdrenr_init_mask = + SPIM_DRDRENR_HYPE | SPIM_DRDRENR_ADDRE | SPIM_DRDRENR_OPDRE | + SPIM_DRDRENR_DRDRE; +static const uint32_t drdrenr_init_value = + 0u << SPIM_DRDRENR_HYPE_POS | 0u << SPIM_DRDRENR_ADDRE_POS | + 0u << SPIM_DRDRENR_OPDRE_POS | 0u << SPIM_DRDRENR_DRDRE_POS; + +static const uint32_t phycnt_init_mask = + SPIM_PHYCNT_ALT_ALIGN | SPIM_PHYCNT_CAL | SPIM_PHYCNT_CKSEL | + SPIM_PHYCNT_EXDS | SPIM_PHYCNT_HS | SPIM_PHYCNT_OCT | SPIM_PHYCNT_OCTA | + SPIM_PHYCNT_PHYMEM | SPIM_PHYCNT_WBUF2 | SPIM_PHYCNT_WBUF; +static const uint32_t phycnt_init_value = + 0u << SPIM_PHYCNT_ALT_ALIGN_POS | 0u << SPIM_PHYCNT_CAL_POS | + 3u << SPIM_PHYCNT_CKSEL_POS | 0u << SPIM_PHYCNT_EXDS_POS | + 0u << SPIM_PHYCNT_HS_POS | 0u << SPIM_PHYCNT_OCT_POS | + 0u << SPIM_PHYCNT_OCTA_POS | 0u << SPIM_PHYCNT_PHYMEM_POS | + 0u << SPIM_PHYCNT_WBUF2_POS | 0u << SPIM_PHYCNT_WBUF_POS; + +static const uint32_t phyoffset1_init_mask = SPIM_PHYOFFSET1_DDRTMG; +static const uint32_t phyoffset1_init_value = SPIM_PHYOFFSET1_SDR + << SPIM_PHYOFFSET1_DDRTMG_POS; + +static const uint32_t phyoffset2_init_mask = SPIM_PHYOFFSET2_OCTTMG; +static const uint32_t phyoffset2_init_value = SPIM_PHYOFFSET2_SPI + << SPIM_PHYOFFSET2_OCTTMG_POS; + +static void spim_ip_init(spim_ctrl_t *myctrl) +{ + cpg_set_xspi_clock(XSPI_CLOCK_SPIM, spi_clock * 4); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_CMNCR, cmncr_init_mask, + cmncr_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SSLDR, ssldr_init_mask, + ssldr_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_DRCR, drcr_init_mask, + drcr_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_DREAR, drear_init_mask, + drear_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_DRDRENR, drdrenr_init_mask, + drdrenr_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYCNT, phycnt_init_mask, + phycnt_init_value | SPIM_PHYCNT_CAL); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYOFFSET1, + phyoffset1_init_mask, phyoffset1_init_value); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYOFFSET2, + phyoffset2_init_mask, phyoffset2_init_value); + spim_init_phy(myctrl); +} + +static int spim_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) +{ + int result = -1; + assert(ctrl); + assert(cfg); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + + if (myctrl->opened) + return -1; + + myctrl->reg_base = cfg->base; + myctrl->mmap_base = 0x20000000; + myctrl->mmap_size = 0x10000000; + assert(myctrl->reg_base); + + if (!globally_initialised) { + select_spim(myctrl, cfg); + spim_ip_init(myctrl); + + globally_initialised = true; + } + + result = 0; + myctrl->opened = true; + + return result; +} + +static int spim_close(xspi_ctrl_t *const ctrl) +{ + int result = -1; + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + if (myctrl->opened) { + myctrl->opened = false; + result = 0; + } + return result; +} + +static int spim_post_init(xspi_ctrl_t *const ctrl) +{ + int result = 0; + return result; +} + +static uint32_t spim_cmncr_set(uint8_t mask, uint8_t value, int pos) +{ + int moiionpos = -1; + int ionfvpos = -1; + uint32_t cmncr_set = 0; + uint32_t moiio = 0; + uint32_t ionfv = 0; + + switch (pos) { + case 1: + moiionpos = SPIM_CMNCR_MOIIO1_POS; + break; + case 2: + moiionpos = SPIM_CMNCR_MOIIO2_POS; + ionfvpos = SPIM_CMNCR_IO2FV_POS; + break; + case 3: + moiionpos = SPIM_CMNCR_MOIIO3_POS; + ionfvpos = SPIM_CMNCR_IO3FV_POS; + break; + } + + if (mask & (1 << pos)) { + moiio = value & 1 << pos ? SPIM_CMNCR_IO_HIGH : + SPIM_CMNCR_IO_LOW; + ionfv = SPIM_CMNCR_IO_KEEP; + } else { + moiio = SPIM_CMNCR_IO_HIZ; + ionfv = SPIM_CMNCR_IO_HIZ; + } + + if (moiionpos >= 0) + cmncr_set |= moiio << moiionpos; + if (ionfvpos >= 0) + cmncr_set |= ionfv << ionfvpos; + + return cmncr_set; +} + +static void spim_set_idlelevel(spim_ctrl_t *const myctrl, + const xspi_op_t *const op) +{ + static const uint32_t cmncr_mask = + SPIM_CMNCR_IO2FV | SPIM_CMNCR_IO3FV | SPIM_CMNCR_MOIIO1 | + SPIM_CMNCR_MOIIO2 | SPIM_CMNCR_MOIIO3; + + uint32_t cmncr_set = 0; + + cmncr_set |= spim_cmncr_set(op->force_idle_level_mask, + op->force_idle_level_value, 1); + cmncr_set |= spim_cmncr_set(op->force_idle_level_mask, + op->force_idle_level_value, 2); + cmncr_set |= spim_cmncr_set(op->force_idle_level_mask, + op->force_idle_level_value, 3); + + mmio_clrsetbits_32(myctrl->reg_base + SPIM_CMNCR, cmncr_mask, + cmncr_set); +} + +static int spim_reduce_frequency(spim_ctrl_t *const ctrl) +{ + int old_freq = spi_clock; + assert(ctrl); + if (spi_clock > RZ_SPIM_SDR_FREQ_LIMIT) { + spi_clock = RZ_SPIM_SDR_FREQ_LIMIT; + } else { + /* We do not need to reduce the current SPI frequency */ + return 0; + } + + int result = cpg_set_xspi_clock(XSPI_CLOCK_SPIM, spi_clock * 4 + 1); + if (result != 0) { + return result; + } + + int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_SPIM); + if (actual_freq == -1) + return -1; + spi_clock = actual_freq / 4; + + INFO("SPIM: Reduces the SPI frequency from %d to %d.\n", old_freq, + spi_clock); + + return 0; +} + +static void spim_start_xip_internal(spim_ctrl_t *const ctrl) +{ + spim_reduce_frequency(ctrl); + mmio_clrbits_32(ctrl->reg_base + SPIM_CMNCR, SPIM_CMNCR_MD); + mmio_read_32(ctrl->reg_base + SPIM_CMNCR); +} + +static void test_sslf(spim_ctrl_t *myctrl) +{ + wait_until_32(myctrl->reg_base + SPIM_CMNSR, SPIM_CMNSR_SSLF, 0); +} + +static int spim_stop_xip_internal(spim_ctrl_t *myctrl) +{ + int result = 0; + uint32_t drcr = mmio_read_32(myctrl->reg_base + SPIM_DRCR); + if ((drcr & (SPIM_DRCR_RBE | SPIM_DRCR_SSLE)) == + (SPIM_DRCR_RBE | SPIM_DRCR_SSLE)) { + /* Set SSLN and wait for sslf */ + mmio_write_32(myctrl->reg_base + SPIM_DRCR, + drcr | SPIM_DRCR_SSLN); + test_sslf(myctrl); + } + test_tend(myctrl); + + /* Set MD bit */ + mmio_setbits_32(myctrl->reg_base + SPIM_CMNCR, SPIM_CMNCR_MD); + + return result; +} + +static bool spim_stop_xip_temporarily(spim_ctrl_t *myctrl) +{ + /* Stop XIP and return previous state*/ + bool state = + !(mmio_read_32(myctrl->reg_base + SPIM_CMNCR) & SPIM_CMNCR_MD); + spim_stop_xip_internal(myctrl); + return state; +} + +static const uint32_t smcmr_clearmask = SPIM_SMCMR_CMD | SPIM_SMCMR_OCMD; + +static const uint32_t smenr_clearmask = + SPIM_SMENR_ADB | SPIM_SMENR_ADE | SPIM_SMENR_CDB | SPIM_SMENR_CDE | + SPIM_SMENR_DME | SPIM_SMENR_SPIDB | SPIM_SMENR_OCDB | SPIM_SMENR_OCDE | + SPIM_SMENR_OPDB | SPIM_SMENR_OPDE | SPIM_SMENR_SPIDE; + +static const uint32_t smdrenr_clearmask = + SPIM_SMDRENR_ADDRE | SPIM_SMDRENR_DRDRE | SPIM_SMDRENR_HYPE | + SPIM_SMDRENR_OPDRE; + +static const uint32_t smdmcr_clearmask = SPIM_SMDMCR_DMCYC; + +static const uint32_t ssldr_clearmask = SPIM_SSLDR_SCKDL | SPIM_SSLDR_SLNDL | + SPIM_SSLDR_SPNDL; + +/* SMENR value for 1-1-1 command */ +static const uint32_t smenr_form_111 = + SPIM_SMENR_DB_1BIT << SPIM_SMENR_CDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_OCDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_ADB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_OPDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_SPIDB_POS; + +/* SMENR value for 1-1-4 command */ +static const uint32_t smenr_form_114 = + SPIM_SMENR_DB_1BIT << SPIM_SMENR_CDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_OCDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_ADB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_OPDB_POS | + SPIM_SMENR_DB_4BIT << SPIM_SMENR_SPIDB_POS; + +/* SMENR value for 1-4-4 command */ +static const uint32_t smenr_form_144 = + SPIM_SMENR_DB_1BIT << SPIM_SMENR_CDB_POS | + SPIM_SMENR_DB_1BIT << SPIM_SMENR_OCDB_POS | + SPIM_SMENR_DB_4BIT << SPIM_SMENR_ADB_POS | + SPIM_SMENR_DB_4BIT << SPIM_SMENR_OPDB_POS | + SPIM_SMENR_DB_4BIT << SPIM_SMENR_SPIDB_POS; + +/* SMENR value for no opcode */ +static const uint32_t smenr_op_none = 0u << SPIM_SMENR_CDE_POS | + 0u << SPIM_SMENR_OCDE_POS; + +/* SMENR value for 1-byte opcode */ +static const uint32_t smenr_op_1byte = 1u << SPIM_SMENR_CDE_POS | + 0u << SPIM_SMENR_OCDE_POS; + +/* SMENR value for 2-byte opcode */ +static const uint32_t smenr_op_2byte = 1u << SPIM_SMENR_CDE_POS | + 1u << SPIM_SMENR_OCDE_POS; + +/* SMENR value for no address */ +static const uint32_t smenr_addr_none = SPIM_SMENR_ADE_NONE + << SPIM_SMENR_ADE_POS; + +/* SMENR value for 3-byte address */ +static const uint32_t smenr_addr_3byte = SPIM_SMENR_ADE_3BYTE + << SPIM_SMENR_ADE_POS; + +/* SMENR value for 4-byte address */ +static const uint32_t smenr_addr_4byte = SPIM_SMENR_ADE_4BYTE + << SPIM_SMENR_ADE_POS; + +/* SMENR value for no additional data */ +static const uint32_t smenr_additional_none = SPIM_SMENR_OPDE_NONE + << SPIM_SMENR_OPDE_POS; + +/* SMENR value for 1-byte additional data */ +static const uint32_t smenr_additional_1byte = SPIM_SMENR_OPDE_1BYTE + << SPIM_SMENR_OPDE_POS; + +/* SMENR value for 2-byte additional data */ +static const uint32_t smenr_additional_2byte = SPIM_SMENR_OPDE_2BYTE + << SPIM_SMENR_OPDE_POS; + +/* SMENR value for 3-byte additional data */ +static const uint32_t smenr_additional_3byte = SPIM_SMENR_OPDE_3BYTE + << SPIM_SMENR_OPDE_POS; + +/* SMENR value for 4-byte additional data */ +static const uint32_t smenr_additional_4byte = SPIM_SMENR_OPDE_4BYTE + << SPIM_SMENR_OPDE_POS; + +static void send_256(spim_ctrl_t *myctrl, xspi_transfer_form_t form, + uintptr_t buffer, uint32_t smenr) +{ + /* Use wbuffer for transfer */ + mmio_setbits_32(myctrl->reg_base + SPIM_DRCR, SPIM_DRCR_RCF); + mmio_setbits_32(myctrl->reg_base + SPIM_PHYCNT, + SPIM_PHYCNT_WBUF2 | SPIM_PHYCNT_WBUF | SPIM_PHYCNT_CAL); + if (form == SPI_FORM_1_1_4 || form == SPI_FORM_1_4_4) { + uint32_t phyoffset2_msk = SPIM_PHYOFFSET2_OCTTMG; + uint32_t phyoffset2_set = SPIM_PHYOFFSET2_SPI_WBUF + << SPIM_PHYOFFSET2_OCTTMG_POS; + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYOFFSET2, + phyoffset2_msk, phyoffset2_set); + } + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_LONG + << SPIM_SMENR_SPIDE_POS)); + /* Write data to buffer */ + for (int bytes = 0; bytes < 256; bytes += 8) { + mmio_write_64(myctrl->reg_base + SPIM_BUFFER + bytes, + *(uint64_t *)(buffer + bytes)); + } +} + +static void send_4(spim_ctrl_t *myctrl, uintptr_t buffer, uint32_t smenr) +{ + /* Set SPIDE */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_LONG + << SPIM_SMENR_SPIDE_POS)); + /* Write data to SMWDR */ + mmio_write_32(myctrl->reg_base + SPIM_SMWDR0, *(uint32_t *)buffer); +} + +static void send_2(spim_ctrl_t *myctrl, uintptr_t buffer, uint32_t smenr) +{ + /* Set SPIDE */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_WORD + << SPIM_SMENR_SPIDE_POS)); + /* Write data to SMWDR */ + mmio_write_16(myctrl->reg_base + SPIM_SMWDR0, *(uint16_t *)buffer); +} + +static void send_1(spim_ctrl_t *myctrl, uintptr_t buffer, uint32_t smenr) +{ + /* Set SPIDE */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_BYTE + << SPIM_SMENR_SPIDE_POS)); + /* Write data to SMWDR */ + mmio_write_8(myctrl->reg_base + SPIM_SMWDR0, *(uint8_t *)buffer); +} + +static void receive(spim_ctrl_t *myctrl, uintptr_t buffer, uint32_t smenr) +{ + /* Set SPIDE */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_LONG + << SPIM_SMENR_SPIDE_POS)); +} + +static void no_data(spim_ctrl_t *myctrl, uintptr_t buffer, uint32_t smenr) +{ + /* No transfer data */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMENR, smenr_clearmask, + smenr | (SPIM_SMENR_SPIDE_NONE + << SPIM_SMENR_SPIDE_POS)); +} + +static int spim_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, + bool is_write) +{ + /* Check parameters */ + assert(ctrl); + assert(op); + assert(op->transfer_size == 0 || + (op->transfer_size && op->transfer_buffer)); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + bool is_xip; + + switch (op->form) { + case SPI_FORM_1_1_1: + case SPI_FORM_1_1_4: + case SPI_FORM_1_4_4: + break; + default: + ERROR("Unsupported transfer form %d\n", op->form); + return -1; + } + + /* Save XIP state and stop XIP */ + is_xip = spim_stop_xip_temporarily(myctrl); + + /* Reduce freq for MPU's AC characteristics */ + spim_reduce_frequency(ctrl); + + /* Wait for transaction end */ + test_tend(myctrl); + + /* Change I/O level while idle state */ + spim_set_idlelevel(myctrl, op); + + /* Create values to write the registers */ + uint32_t smcmr_set = 0; + uint32_t smenr_set = 0; + uint32_t smdrenr_set = 0; + uint32_t smopr = 0; + uint32_t smadr = op->address; + uint32_t smdmcr_set = 0; + uint32_t ssldr_set = 0; + uint32_t save_ssldr = mmio_read_32(myctrl->reg_base + SPIM_SSLDR); + uint32_t save_phyoffset1 = + mmio_read_32(myctrl->reg_base + SPIM_PHYOFFSET1); + uint32_t save_phyoffset2 = + mmio_read_32(myctrl->reg_base + SPIM_PHYOFFSET2); + uint32_t save_phycnt = mmio_read_32(myctrl->reg_base + SPIM_PHYCNT); + + /* Command form */ + switch (op->form) { + case SPI_FORM_1_1_1: + smenr_set |= smenr_form_111; + break; + case SPI_FORM_1_1_4: + smenr_set |= smenr_form_114; + break; + case SPI_FORM_1_4_4: + smenr_set |= smenr_form_144; + break; + default: + ERROR("Unsupported transfer form %d\n", op->form); + return -1; + } + + /* Opcode */ + switch (op->op_size) { + case 0: + smenr_set |= smenr_op_none; + break; + case 1: + smenr_set |= smenr_op_1byte; + smcmr_set |= (op->op & 0xff) << SPIM_SMCMR_CMD_POS; + break; + case 2: + smenr_set |= smenr_op_2byte; + smcmr_set |= (op->op & 0xff) << SPIM_SMCMR_OCMD_POS; + smcmr_set |= (op->op & 0xff00) >> 8 << SPIM_SMCMR_CMD_POS; + break; + default: + ERROR("Unsupported op size %d\n", op->op_size); + return -1; + } + + /* Address */ + switch (op->address_size) { + case 0: + smenr_set |= smenr_addr_none; + break; + case 3: + smenr_set |= smenr_addr_3byte; + break; + case 4: + smenr_set |= smenr_addr_4byte; + break; + default: + ERROR("Unsupported address size %d\n", op->address_size); + return -1; + } + + /* Additional data */ + switch (op->additional_size) { + case 0: + smenr_set |= smenr_additional_none; + break; + case 1: + smenr_set |= smenr_additional_1byte; + smopr = (op->additional_value & 0xff) << SPIM_SMOPR_OPD3_POS; + break; + case 2: + smenr_set |= smenr_additional_2byte; + smopr = (op->additional_value & 0xff) << SPIM_SMOPR_OPD2_POS; + smopr |= (op->additional_value & 0xff00) >> + 8 << SPIM_SMOPR_OPD3_POS; + break; + case 3: + smenr_set |= smenr_additional_3byte; + smopr = (op->additional_value & 0xff) << SPIM_SMOPR_OPD1_POS; + smopr |= (op->additional_value & 0xff00) >> + 8 << SPIM_SMOPR_OPD2_POS; + smopr |= (op->additional_value & 0xff0000) >> + 16 << SPIM_SMOPR_OPD3_POS; + break; + case 4: + smenr_set |= smenr_additional_4byte; + smopr = (op->additional_value & 0xff) << SPIM_SMOPR_OPD0_POS; + smopr |= (op->additional_value & 0xff00) >> + 8 << SPIM_SMOPR_OPD1_POS; + smopr |= (op->additional_value & 0xff0000) >> + 16 << SPIM_SMOPR_OPD2_POS; + smopr |= (op->additional_value & 0xff000000) >> + 24 << SPIM_SMOPR_OPD3_POS; + break; + default: + ERROR("Unsupported additional size %d\n", op->additional_size); + return -1; + } + + /* Dummy cycle */ + if (op->dummy_cycles == 0) { + smenr_set |= 0u << SPIM_SMENR_DME_POS; + smdmcr_set |= 0u << SPIM_SMDMCR_DMCYC_POS; + } else if (op->dummy_cycles == 1 || op->dummy_cycles > 20) { + ERROR("Unsupported dummy cycle count %d\n", op->dummy_cycles); + return -1; + } else { + smenr_set |= 1u << SPIM_SMENR_DME_POS; + smdmcr_set |= (op->dummy_cycles - 1) << SPIM_SMDMCR_DMCYC_POS; + } + + /* PHYOFFSET1 setting */ + uint32_t phyoffset1_msk = SPIM_PHYOFFSET1_DDRTMG; + uint32_t phyoffset1_set; + phyoffset1_set = SPIM_PHYOFFSET1_SDR << SPIM_PHYOFFSET1_DDRTMG_POS; + + /* PHYCNT setting */ + uint32_t phycnt_msk = SPIM_PHYCNT_PHYMEM; + uint32_t phycnt_set; + phycnt_set = SPIM_PHYCNT_SDR << SPIM_PHYCNT_PHYMEM_POS; + + /* SLCH (SSL assert to CLK high) */ + if (op->slch_value < 8) { + ssldr_set |= op->slch_value << SPIM_SSLDR_SCKDL_POS; + } else { + ERROR("Unsupported slch_value %d\n", op->slch_value); + return -1; + } + + /* CLSH (CLK low tp SSL negative) */ + if (op->clsh_value < 8) { + ssldr_set |= op->clsh_value << SPIM_SSLDR_SLNDL_POS; + } else { + ERROR("Unsupported clsh_value %d\n", op->clsh_value); + return -1; + } + + /* SHSL (SSL negative to SSL assert) */ + if (op->shsl_value < 8) { + ssldr_set |= op->shsl_value << SPIM_SSLDR_SPNDL_POS; + } else { + ERROR("Unsupported shsl_value %d\n", op->shsl_value); + return -1; + } + + /* Write the register */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMCMR, smcmr_clearmask, + smcmr_set); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMDRENR, smdrenr_clearmask, + smdrenr_set); + mmio_write_32(myctrl->reg_base + SPIM_SMADR, smadr); + mmio_write_32(myctrl->reg_base + SPIM_SMOPR, smopr); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SMDMCR, smdmcr_clearmask, + smdmcr_set); + mmio_write_32(myctrl->reg_base + SPIM_SSLDR, + (save_ssldr & ~ssldr_clearmask) | ssldr_set); + mmio_write_32(myctrl->reg_base + SPIM_PHYOFFSET1, + (save_phyoffset1 & ~phyoffset1_msk) | phyoffset1_set); + mmio_write_32(myctrl->reg_base + SPIM_PHYCNT, + (save_phycnt & ~phycnt_msk) | phycnt_set | + SPIM_PHYCNT_CAL); + + int64_t remain = (int64_t)op->transfer_size; + uintptr_t buffer = (uintptr_t)op->transfer_buffer; + uint32_t smcr; + + /* Enable transmit */ + if (is_write && remain) + smcr = SPIM_SMCR_SPIWE | SPIM_SMCR_SPIE; + else if (remain) + smcr = SPIM_SMCR_SPIRE | SPIM_SMCR_SPIE; + else + smcr = SPIM_SMCR_SPIE; + + do { + uint32_t xfer_count; + + /* Block size per single transfer */ + if (is_write && remain >= 256) { + send_256(myctrl, op->form, buffer, smenr_set); + xfer_count = 256; + } else if (is_write && remain >= 4) { + send_4(myctrl, buffer, smenr_set); + xfer_count = 4; + } else if (is_write && remain >= 2) { + send_2(myctrl, buffer, smenr_set); + xfer_count = 2; + } else if (is_write && remain) { + send_1(myctrl, buffer, smenr_set); + xfer_count = 1; + } else if (remain) { + receive(myctrl, buffer, smenr_set); + xfer_count = 4; + } else { + no_data(myctrl, buffer, smenr_set); + xfer_count = 0; + } + + /* Set SSLKP if transaction is remained and write transfer */ + if (is_write && remain > xfer_count) { + smcr |= SPIM_SMCR_SSLKP; + } else { + smcr &= ~SPIM_SMCR_SSLKP; + } + + /* Exec transaction */ + mmio_write_32(myctrl->reg_base + SPIM_SMCR, smcr); + test_tend(myctrl); + + /* Store received data */ + if (!is_write && remain) { + uint32_t smrdr = + mmio_read_32(myctrl->reg_base + SPIM_SMRDR0); + if (remain > 3) { + *(uint32_t *)buffer = smrdr; + } else { + *(uint8_t *)buffer = (smrdr >> 24) & 255; + if (remain > 1) + *(uint8_t *)(buffer + 1) = + (smrdr >> 16) & 255; + if (remain > 2) + *(uint8_t *)(buffer + 2) = + (smrdr >> 8) & 255; + } + } + remain -= xfer_count; + buffer += xfer_count; + + /* Clear write buffer flag and restore OCTTMG */ + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYCNT, + SPIM_PHYCNT_WBUF2 | SPIM_PHYCNT_WBUF, + SPIM_PHYCNT_CAL); + mmio_write_32(myctrl->reg_base + SPIM_PHYOFFSET2, + save_phyoffset2); + + if (remain > 0) { + if (!is_write) { + /* Increment address */ + smadr += xfer_count; + mmio_write_32(myctrl->reg_base + SPIM_SMADR, + smadr); + } else { + /* Clear enabler bits for continuous write access */ + smenr_set &= + ~(SPIM_SMENR_DME | SPIM_SMENR_CDE | + SPIM_SMENR_OCDE | SPIM_SMENR_ADE | + SPIM_SMENR_OPDE); + } + } + } while (remain > 0); + + /* Resume regs */ + mmio_write_32(myctrl->reg_base + SPIM_SSLDR, save_ssldr); + mmio_write_32(myctrl->reg_base + SPIM_PHYCNT, + save_phycnt | SPIM_PHYCNT_CAL); + mmio_write_32(myctrl->reg_base + SPIM_PHYOFFSET1, save_phyoffset1); + + if (is_xip) { + /* Resume XIP state */ + spim_start_xip_internal(ctrl); + } + + return 0; +} + +static const uint32_t drcmr_clearmask = SPIM_DRCMR_CMD | SPIM_DRCMR_OCMD; + +static const uint32_t drenr_clearmask = + SPIM_DRENR_ADB | SPIM_DRENR_ADE | SPIM_DRENR_CDB | SPIM_DRENR_CDE | + SPIM_DRENR_DME | SPIM_DRENR_DRDB | SPIM_DRENR_OCDB | SPIM_DRENR_OCDE | + SPIM_DRENR_OPDB | SPIM_DRENR_OPDE; + +static const uint32_t drdrenr_clearmask = + SPIM_DRDRENR_ADDRE | SPIM_DRDRENR_DRDRE | SPIM_DRDRENR_HYPE | + SPIM_DRDRENR_OPDRE; + +static const uint32_t drdmcr_clearmask = SPIM_DRDMCR_DMCYC; + +/* DRENR value for 1-1-1 command */ +static const uint32_t drenr_form_111 = + SPIM_DRENR_DB_1BIT << SPIM_DRENR_CDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_OCDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_ADB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_OPDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_DRDB_POS; + +/* DRENR value for 1-1-4 command */ +static const uint32_t drenr_form_114 = + SPIM_DRENR_DB_1BIT << SPIM_DRENR_CDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_OCDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_ADB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_OPDB_POS | + SPIM_DRENR_DB_4BIT << SPIM_DRENR_DRDB_POS; + +/* DRENR value for 1-4-4 command */ +static const uint32_t drenr_form_144 = + SPIM_DRENR_DB_1BIT << SPIM_DRENR_CDB_POS | + SPIM_DRENR_DB_1BIT << SPIM_DRENR_OCDB_POS | + SPIM_DRENR_DB_4BIT << SPIM_DRENR_ADB_POS | + SPIM_DRENR_DB_4BIT << SPIM_DRENR_OPDB_POS | + SPIM_DRENR_DB_4BIT << SPIM_DRENR_DRDB_POS; + +/* DRENR value for no opcode */ +static const uint32_t drenr_op_none = 0u << SPIM_DRENR_CDE_POS | + 0u << SPIM_DRENR_OCDE_POS; + +/* DRENR value for 1-byte opcode */ +static const uint32_t drenr_op_1byte = 1u << SPIM_DRENR_CDE_POS | + 0u << SPIM_DRENR_OCDE_POS; + +/* DRENR value for 2-byte opcode */ +static const uint32_t drenr_op_2byte = 1u << SPIM_DRENR_CDE_POS | + 1u << SPIM_DRENR_OCDE_POS; + +/* DRENR value for no address */ +static const uint32_t drenr_addr_none = SPIM_DRENR_ADE_NONE + << SPIM_DRENR_ADE_POS; + +/* DRENR value for 3-byte address */ +static const uint32_t drenr_addr_3byte = SPIM_DRENR_ADE_3BYTE + << SPIM_DRENR_ADE_POS; + +/* DRENR value for 4-byte address */ +static const uint32_t drenr_addr_4byte = SPIM_DRENR_ADE_4BYTE + << SPIM_DRENR_ADE_POS; + +/* DRENR value for no additional data */ +static const uint32_t drenr_additional_none = SPIM_DRENR_OPDE_NONE + << SPIM_DRENR_OPDE_POS; + +/* DRENR value for 1-byte additional data */ +static const uint32_t drenr_additional_1byte = SPIM_DRENR_OPDE_1BYTE + << SPIM_DRENR_OPDE_POS; + +/* DRENR value for 2-byte additional data */ +static const uint32_t drenr_additional_2byte = SPIM_DRENR_OPDE_2BYTE + << SPIM_DRENR_OPDE_POS; + +/* DRENR value for 3-byte additional data */ +static const uint32_t drenr_additional_3byte = SPIM_DRENR_OPDE_3BYTE + << SPIM_DRENR_OPDE_POS; + +/* DRENR value for 4-byte additional data */ +static const uint32_t drenr_additional_4byte = SPIM_DRENR_OPDE_4BYTE + << SPIM_DRENR_OPDE_POS; + +static int spim_configure_xip(xspi_ctrl_t *const ctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop) +{ + assert(ctrl); + if (!rop) + return -1; + if (wop) + return -1; + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + + uint32_t drcmr = mmio_read_32(myctrl->reg_base + SPIM_DRCMR); + uint32_t drenr = mmio_read_32(myctrl->reg_base + SPIM_DRENR); + uint32_t drdrenr = mmio_read_32(myctrl->reg_base + SPIM_DRDRENR); + uint32_t dropr = 0; + uint32_t drdmcr = mmio_read_32(myctrl->reg_base + SPIM_DRDMCR); + uint32_t ssldr_clear = 0; + uint32_t ssldr_set = 0; + uint32_t phyoffset1_msk = SPIM_PHYOFFSET1_DDRTMG; + uint32_t phyoffset1_set = 0; + uint32_t phyoffset2_msk = SPIM_PHYOFFSET2_OCTTMG; + uint32_t phyoffset2_set = SPIM_PHYOFFSET2_SPI + << SPIM_PHYOFFSET2_OCTTMG_POS; + uint32_t phycnt_msk = SPIM_PHYCNT_PHYMEM; + uint32_t phycnt_set = 0; + + /* Change I/O level while idle state */ + spim_set_idlelevel(myctrl, rop); + + drenr &= ~drenr_clearmask; + drcmr &= ~drcmr_clearmask; + drdrenr &= ~drdrenr_clearmask; + drdmcr &= ~drdmcr_clearmask; + + /* Command form */ + switch (rop->form) { + case SPI_FORM_1_1_1: + drenr |= drenr_form_111; + break; + case SPI_FORM_1_1_4: + drenr |= drenr_form_114; + break; + case SPI_FORM_1_4_4: + drenr |= drenr_form_144; + break; + default: + ERROR("Unsupported transfer form %d for rop\n", rop->form); + return -1; + } + + /* Opcode */ + switch (rop->op_size) { + case 0: + drenr |= drenr_op_none; + break; + case 1: + drenr |= drenr_op_1byte; + drcmr |= (rop->op & 0xff) << SPIM_DRCMR_CMD_POS; + break; + case 2: + drenr |= drenr_op_2byte; + drcmr |= (rop->op & 0xff) << SPIM_DRCMR_OCMD_POS; + drcmr |= (rop->op & 0xff00) >> 8 << SPIM_DRCMR_CMD_POS; + break; + default: + ERROR("Unsupported op size %d for rop\n", rop->op_size); + return -1; + } + + /* Address */ + switch (rop->address_size) { + case 0: + drenr |= drenr_addr_none; + break; + case 3: + drenr |= drenr_addr_3byte; + break; + case 4: + drenr |= drenr_addr_4byte; + break; + default: + ERROR("Unsupported address size %d for rop\n", + rop->address_size); + return -1; + } + + /* Additional data */ + switch (rop->additional_size) { + case 0: + drenr |= drenr_additional_none; + break; + case 1: + drenr |= drenr_additional_1byte; + dropr |= (rop->additional_value & 0xff) << SPIM_DROPR_OPD3_POS; + break; + case 2: + drenr |= drenr_additional_2byte; + dropr |= (rop->additional_value & 0xff) << SPIM_DROPR_OPD2_POS; + dropr |= (rop->additional_value & 0xff00) >> + 8 << SPIM_DROPR_OPD3_POS; + break; + case 3: + drenr |= drenr_additional_3byte; + dropr |= (rop->additional_value & 0xff) << SPIM_DROPR_OPD1_POS; + dropr |= (rop->additional_value & 0xff00) >> + 8 << SPIM_DROPR_OPD2_POS; + dropr |= (rop->additional_value & 0xff0000) >> + 16 << SPIM_DROPR_OPD3_POS; + break; + case 4: + drenr |= drenr_additional_4byte; + dropr |= (rop->additional_value & 0xff) << SPIM_DROPR_OPD0_POS; + dropr |= (rop->additional_value & 0xff00) >> + 8 << SPIM_DROPR_OPD1_POS; + dropr |= (rop->additional_value & 0xff0000) >> + 16 << SPIM_DROPR_OPD2_POS; + dropr |= (rop->additional_value & 0xff000000) >> + 24 << SPIM_DROPR_OPD3_POS; + break; + default: + ERROR("Unsupported additional size %d for rop\n", + rop->additional_size); + return -1; + } + + /* Dummy cycle */ + if (rop->dummy_cycles == 0) { + drenr |= 0u << SPIM_DRENR_DME_POS; + drdmcr |= 0u << SPIM_DRDMCR_DMCYC_POS; + } else if (rop->dummy_cycles == 1 || rop->dummy_cycles > 20) { + ERROR("Unsupported dummy cycle count %d for rop\n", + rop->dummy_cycles); + return -1; + } else { + drenr |= 1u << SPIM_DRENR_DME_POS; + drdmcr |= (rop->dummy_cycles - 1) << SPIM_DRDMCR_DMCYC_POS; + } + + /* Set operation timing for PHYOFFSET1 */ + phyoffset1_set = SPIM_PHYOFFSET1_SDR << SPIM_PHYOFFSET1_DDRTMG_POS; + + /* Set data transfer mode for PHYCNT */ + phycnt_set = SPIM_PHYCNT_SDR << SPIM_PHYCNT_PHYMEM_POS; + + /* SLCH (SSL assert to CLK high) */ + if (rop->slch_value < 8) { + ssldr_clear |= SPIM_SSLDR_SCKDL; + ssldr_set |= rop->slch_value << SPIM_SSLDR_SCKDL_POS; + } else { + ERROR("Unsupported slch_value %d for rop\n", rop->slch_value); + return -1; + } + + /* CLSH (CLK low tp SSL negative) */ + if (rop->clsh_value < 8) { + ssldr_clear |= SPIM_SSLDR_SLNDL; + ssldr_set |= rop->clsh_value << SPIM_SSLDR_SLNDL_POS; + } else { + ERROR("Unsupported clsh_value %d for rop\n", rop->clsh_value); + return -1; + } + + /* SHSL (SSL negative to SSL assert) */ + if (rop->shsl_value < 8) { + ssldr_clear |= SPIM_SSLDR_SPNDL; + ssldr_set |= rop->shsl_value << SPIM_SSLDR_SPNDL_POS; + } else { + ERROR("Unsupported shsl_value %d for rop\n", rop->shsl_value); + return -1; + } + + /* Write the register */ + mmio_write_32(myctrl->reg_base + SPIM_DRCMR, drcmr); + mmio_write_32(myctrl->reg_base + SPIM_DRENR, drenr); + mmio_write_32(myctrl->reg_base + SPIM_DRDRENR, drdrenr); + mmio_write_32(myctrl->reg_base + SPIM_DROPR, dropr); + mmio_write_32(myctrl->reg_base + SPIM_DRDMCR, drdmcr); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_SSLDR, ssldr_clear, + ssldr_set); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYOFFSET1, phyoffset1_msk, + phyoffset1_set); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYOFFSET2, phyoffset2_msk, + phyoffset2_set); + mmio_clrsetbits_32(myctrl->reg_base + SPIM_PHYCNT, phycnt_msk, + phycnt_set | SPIM_PHYCNT_CAL); + + /* Reduce the SPI freq. */ + spim_reduce_frequency(ctrl); + + return 0; +} + +static int spim_start_xip(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + mmio_setbits_32(myctrl->reg_base + SPIM_DRCR, SPIM_DRCR_RCF); + spim_start_xip_internal(myctrl); + spim_inv_mmap(ctrl); + + return 0; +} + +static int spim_stop_xip(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return spim_stop_xip_internal(myctrl); +} + +static int spim_run_manual_calibration(xspi_ctrl_t *const ctrl) +{ + return -1; +} + +static int spim_enable_auto_calibration(xspi_ctrl_t *const ctrl) +{ + return -1; +} + +static int spim_disable_auto_calibration(xspi_ctrl_t *const ctrl) +{ + return -1; +} + +static int spim_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz) +{ + assert(ctrl); + + int result = cpg_set_xspi_clock(XSPI_CLOCK_SPIM, frequency_hz * 4 + 1); + if (result != 0) + return result; + int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_SPIM); + if (actual_freq == -1) + return -1; + actual_freq = actual_freq / 4; + if (frequency_hz != actual_freq) { + INFO("SPIM: Reduces the SPI frequency from requested %d to %d.\n", + frequency_hz, actual_freq); + } + spi_clock = actual_freq; + + return 0; +} + +static int spim_clean_mmap(xspi_ctrl_t *const ctrl) +{ + return 0; +} + +static int spim_inv_mmap(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + inv_dcache_range(myctrl->mmap_base, myctrl->mmap_size); + + return 0; +} + +static uintptr_t spim_get_mmap_base(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return myctrl->mmap_base; +} + +static size_t spim_get_mmap_size(xspi_ctrl_t *const ctrl) +{ + assert(ctrl); + spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return myctrl->mmap_size; +} + +static uint32_t spim_get_features(xspi_ctrl_t *const ctrl) +{ + (void)ctrl; + uint32_t features = 0; + features |= XSPI_FEATURE_FORM114; + features |= XSPI_FEATURE_FORM144; + features |= XSPI_FEATURE_XIP_READ; + + return features; +} diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c new file mode 100644 index 0000000000..615a9fef97 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c @@ -0,0 +1,518 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include "octaflash_mx66uw_api.h" + +/* Defaults */ +#define DEFAULT_SPI_FREQUENCY 100000000 +#define SPI_POST_RESET_WAIT 50 + +/* Static function pre-definition */ +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg); +static int flash_close(xspidevice_ctrl_t *ctrl); +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write); +static int flash_enter_xip(xspidevice_ctrl_t *ctrl); +static int flash_exit_xip(xspidevice_ctrl_t *ctrl); +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info); +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length); +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length); +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length); +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl); + +/* API function table definition */ +const xspidevice_api_t octaflash_mx66uw_api = { + .open = flash_open, + .close = flash_close, + .exec_op = flash_exec_op, + .enter_xip = flash_enter_xip, + .exit_xip = flash_exit_xip, + .get_info = flash_get_info, + .read = flash_read, + .write = flash_write, + .erase = flash_erase, + .get_write_status = flash_get_write_status, +}; + +/* Access timing parameters : 100MHz + * DRCSTR : DVRDLO0=0, DVRDHI0=5, DVRDCMD0=1, CTR0=0, CTRW0=0 + * DWCSTR : DVWLO0=0, DVWHI0=0, DVWCMD0=1 + * DCSTR : DVSELLO=0, DVSELHI=5, DVSELCMD=1 + */ + +/* Static variables */ +static int spi_frequency = DEFAULT_SPI_FREQUENCY + 1; + +/* Flash Commands */ +/* Write Enable (SPI) */ +static const xspi_op_t op_write_enable_spi = { .form = SPI_FORM_1_1_1, + .op = 0x06, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Write Enable (DOPI) */ +static const xspi_op_t op_write_enable_dopi = { .form = SPI_FORM_8_8_8, + .op = 0x06F9, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Read Status Register (SPI) */ +static const xspi_op_t op_read_status_spi = { .form = SPI_FORM_1_1_1, + .op = 0x05, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Read Status Register - 1 (DOPI) */ +static const xspi_op_t op_read_status_dopi = { .form = SPI_FORM_8_8_8, + .op = 0x05FA, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 4, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Write Configuration Register2 (SPI) */ +static const xspi_op_t op_write_config2_spi = { .form = SPI_FORM_1_1_1, + .op = 0x72, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Read Command = 8 I/O DT Read (EEh/11h) */ +static const xspi_op_t rop = { .form = SPI_FORM_8_8_8, + .op = 0xee11, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 10, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Page Program 4B (DOPI) */ +static const xspi_op_t op_page_program_dopi = { .form = SPI_FORM_8_8_8, + .op = 0x12ED, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Erase 4k (DOPI) */ +static const xspi_op_t op_erase_4k_dopi = { .form = SPI_FORM_8_8_8, + .op = 0x21DE, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Erase 64k (DOPI) */ +static const xspi_op_t op_erase_64k_dopi = { .form = SPI_FORM_8_8_8, + .op = 0xDC23, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Function definitions */ +static int flash_write_enable_spi(octaflash_mx66uw_ctrl_t *myctrl) +{ + const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable_spi, false); +} + +static int flash_write_enable_dopi(octaflash_mx66uw_ctrl_t *myctrl) +{ + const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable_dopi, false); +} + +static int flash_read_status_register_spi(octaflash_mx66uw_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t status; + xspi_op_t op = op_read_status_spi; + op.transfer_buffer = &status; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result) + return result; + return (int)status; +} + +static int flash_read_status_register_dopi(octaflash_mx66uw_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + uint8_t status; + xspi_op_t op = op_read_status_dopi; + op.transfer_buffer = &status; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result) + return result; + return (int)status; +} + +static int flash_write_config_register2_spi(octaflash_mx66uw_ctrl_t *myctrl, + uint32_t add, uint8_t data) +{ + const xspi_instance_t *xspi = myctrl->xspi; + xspi_op_t op = op_write_config2_spi; + op.address = add; + op.transfer_buffer = &data; + return xspi->api->exec_op(xspi->ctrl, &op, true); +} + +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) +{ + assert(ctrl); + assert(cfg); + int result; + enum xspidevice_write_status ws; + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = cfg->xspi; + + if (myctrl->opened) + return -1; + + myctrl->xspi = xspi; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (result == 0) { + xspi->api->set_frequency(xspi->ctrl, spi_frequency); + if (false) + flash_read_status_register_spi( + myctrl); /* Avoiding build error */ + udelay(SPI_POST_RESET_WAIT); + flash_write_enable_spi(myctrl); + flash_write_config_register2_spi(myctrl, 0x00000300, 5); + + flash_write_enable_spi(myctrl); + flash_write_config_register2_spi(myctrl, 0x00000000, 2); + + do { + ws = flash_get_write_status(ctrl); + } while (ws == WRITE_STATUS_IN_PROGRESS); + + myctrl->opened = true; + } + + return result; +} + +static int flash_close(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result = -1; + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { + result = xspi->api->close(xspi->ctrl); + myctrl->opened = false; + } + return result; +} + +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write) +{ + assert(ctrl); + assert(op); + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->exec_op(xspi->ctrl, op, is_write); +} + +static int flash_enter_xip(xspidevice_ctrl_t *ctrl) +{ + int result = -1; + assert(ctrl); + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + result = xspi->api->configure_xip(xspi->ctrl, &rop, NULL); + if (result == 0) { + result = xspi->api->run_manual_calibration(xspi->ctrl); + result = xspi->api->start_xip(xspi->ctrl); + } + + return result; +} + +static int flash_exit_xip(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->stop_xip(xspi->ctrl); +} + +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info) +{ + assert(ctrl); + assert(info); + info->capacity = 0; + strlcpy(info->device_vendor, "Macronix", sizeof(info->device_vendor)); + strlcpy(info->device_product, "MX66UW", sizeof(info->device_product)); + return 0; +} + +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length) +{ + assert(ctrl); + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); + + return 0; +} + +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length) +{ + int result = 0; + if (RZ_XSPIFLASH_DISABLE_WRITE) { + result = -1; + } else { + assert(ctrl); + octaflash_mx66uw_ctrl_t *myctrl = + (octaflash_mx66uw_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + uintptr_t tmp_buffer = (uintptr_t)buffer; + xspi_op_t op = op_page_program_dopi; + + /* Stop XIP mode */ + xspi->api->stop_xip(xspi->ctrl); + + /* Stop Auto Calibration */ + xspi->api->disable_auto_calibration(xspi->ctrl); + + while (length && !result) { + /* Wait for previous command finished */ + enum xspidevice_write_status ws; + do { + ws = flash_get_write_status(ctrl); + } while (ws == WRITE_STATUS_IN_PROGRESS); + if (ws != WRITE_STATUS_OK) { + /* Error on previous command */ + result = -1; + break; + } + result = flash_write_enable_dopi(myctrl); + if (result) + break; + + op.transfer_buffer = (void *)tmp_buffer; + op.address = address; + if (length > 4) + op.transfer_size = 4; + else + op.transfer_size = length; + + /* Execute page program */ + result = xspi->api->exec_op(xspi->ctrl, &op, true); + + /* Move pointer */ + address += op.transfer_size; + tmp_buffer += op.transfer_size; + length -= op.transfer_size; + } + + /* Restart Auto Calibration */ + xspi->api->enable_auto_calibration(xspi->ctrl); + + xspi->api->start_xip(xspi->ctrl); + + /* Invalidate dcache */ + xspi->api->inv_mmap(xspi->ctrl); + } + + return result; +} + +static int flash_erase_4k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) +{ + xspi_op_t op = op_erase_4k_dopi; + op.address = address; + return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); +} + +static int flash_erase_64k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) +{ + xspi_op_t op = op_erase_64k_dopi; + op.address = address; + return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); +} + +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) +{ + int result; + if (RZ_XSPIFLASH_DISABLE_WRITE) { + result = -1; + } else { + assert(ctrl); + assert((address & 4095) == 0); + assert(length > 4095); + size_t over = address + length; + octaflash_mx66uw_ctrl_t *myctrl = + (octaflash_mx66uw_ctrl_t *)ctrl; + + do { + /* Wait for previous command finished */ + enum xspidevice_write_status ws; + do { + ws = flash_get_write_status(ctrl); + } while (ws == WRITE_STATUS_IN_PROGRESS); + if (ws != WRITE_STATUS_OK) { + /* Error on previous command */ + return -1; + } + result = flash_write_enable_dopi(myctrl); + if (result) + return result; + + /* Select erase size */ + if (!(address & 0xffff) && length >= 65536) { + /* 64K boundary */ + result = flash_erase_64k(myctrl, address); + address += 65536; + length -= 65536; + } else { + /* 4K boundary */ + result = flash_erase_4k(myctrl, address); + address += 4096; + length -= 4096; + } + + if (result) + return result; + } while (address < over); + } + + return result; +} + +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result; + octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; + + /* Read Status Register - 1 */ + result = flash_read_status_register_dopi(myctrl); + if (result < 0) + return WRITE_STATUS_FAIL; + if (result & 1) + return WRITE_STATUS_IN_PROGRESS; + return WRITE_STATUS_OK; +} diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h new file mode 100644 index 0000000000..69f7d2870f --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _OCTAFLASH_MX66UW_API_H_ +#define _OCTAFLASH_MX66UW_API_H_ +#include +#include + +#include "xspidevice_api.h" + +/** xSPI device control structure */ +typedef struct st_octaflash_mx66uw_ctrl { + bool opened; + const xspi_instance_t *xspi; +} octaflash_mx66uw_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_octaflash_mx66uw_ext { + /* No additional configurations */ +} octaflash_mx66uw_ext_t; + +extern const xspidevice_api_t octaflash_mx66uw_api; + +#endif /* _OCTAFLASH_MX66UW_API_H_ */ diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk new file mode 100644 index 0000000000..a1d8fe3832 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := octaflash_mx66uw +PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) +RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h +RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ + plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c new file mode 100644 index 0000000000..e38fcbe904 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include "octaram_apsxx_api.h" + +/* Defaults */ +#define DEFAULT_SPI_FREQUENCY 100000000 +#define SPI_POST_RESET_WAIT 2 + +/* Static function pre-definition */ +static int octaram_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg); +static int octaram_close(xspidevice_ctrl_t *ctrl); +static int octaram_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write); +static int octaram_enter_xip(xspidevice_ctrl_t *ctrl); +static int octaram_exit_xip(xspidevice_ctrl_t *ctrl); +static int octaram_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info); +static int octaram_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length); +static int octaram_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length); +static int octaram_erase(xspidevice_ctrl_t *ctrl, size_t address, + size_t length); +static enum xspidevice_write_status +octaram_get_write_status(xspidevice_ctrl_t *ctrl); + +/* API function table definition */ +const xspidevice_api_t octaram_apsxx_api = { + .open = octaram_open, + .close = octaram_close, + .exec_op = octaram_exec_op, + .enter_xip = octaram_enter_xip, + .exit_xip = octaram_exit_xip, + .get_info = octaram_get_info, + .read = octaram_read, + .write = octaram_write, + .erase = octaram_erase, + .get_write_status = octaram_get_write_status, +}; + +/* Access timing parameters : 100MHz + * DRCSTR : DVRDLO1=0, DVRDHI1=5, DVRDCMD1=1 + * DWCSTR : DVWLO1=0, DVWHI1=0, DVWCMD1=1 + * DCSTR : DVSELLO=0, DVSELHI=5, DVSELCMD=1 + */ + +/* Static variables */ +static int spi_frequency = DEFAULT_SPI_FREQUENCY + 1; + +/*** Operational Commands ***/ +/* Write Mode Register */ +static const xspi_op_t op_write_mode = { .form = SPI_FORM_8_8_8, + .op = 0x4000, + .op_size = 2, + .op_is_ddr = true, + .address = 0x00040000, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 2, + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 }; + +/* Read Command = Sync Read (80/xxh) */ +static const xspi_op_t rop = { .form = SPI_FORM_8_8_8, + .op = 0x8000, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 4, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 5, + .shsl_value = 1 }; + +/* Write Command = Sync Write (00/xxh) */ +static const xspi_op_t wop = { .form = SPI_FORM_8_8_8, + .op = 0x0000, + .op_size = 2, + .op_is_ddr = true, + .address = 0, + .address_is_ddr = true, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 4, + .transfer_buffer = NULL, + .transfer_is_ddr = true, + .transfer_size = 0, + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 }; + +/* Function definitions */ +static int octaram_write_mode_register(octaram_apsxx_ctrl_t *myctrl, + uint16_t data) +{ + const xspi_instance_t *xspi = myctrl->xspi; + xspi_op_t op = op_write_mode; + op.transfer_buffer = &data; + return xspi->api->exec_op(xspi->ctrl, &op, true); +} + +static int octaram_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) +{ + assert(ctrl); + assert(cfg); + int result; + octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; + const xspi_instance_t *xspi = cfg->xspi; + + if (myctrl->opened) + return -1; + + myctrl->xspi = xspi; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (result == 0) { + xspi->api->set_frequency(xspi->ctrl, spi_frequency); + udelay(SPI_POST_RESET_WAIT); + octaram_write_mode_register(myctrl, 0xF011); + /* [15] Deep Power Down Enable = 1 : Normal Operation + * [14:12] Drive Strength = 111 : 25ohms 010 + * [11:8] Reserved = 0000 + * [7:4] Latency Code = 0001 : 4 clocks + * [3] Latency Type = 0 : Variable Latency + * [2] Burst Type = 0 : Wrapped + * [1:0] Burst Length = 01 : 64 bytes + */ + myctrl->opened = true; + } + + return result; +} + +static int octaram_close(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result = -1; + octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { + result = xspi->api->close(xspi->ctrl); + myctrl->opened = false; + } + return result; +} + +static int octaram_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write) +{ + assert(ctrl); + assert(op); + octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->exec_op(xspi->ctrl, op, is_write); +} + +static int octaram_enter_xip(xspidevice_ctrl_t *ctrl) +{ + int result = -1; + assert(ctrl); + octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + result = xspi->api->configure_xip(xspi->ctrl, &rop, &wop); + if (result == 0) { + result = xspi->api->run_manual_calibration(xspi->ctrl); + result = xspi->api->start_xip(xspi->ctrl); + } + + return result; +} + +static int octaram_exit_xip(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->stop_xip(xspi->ctrl); +} + +static int octaram_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info) +{ + assert(ctrl); + assert(info); + info->capacity = 0; + strlcpy(info->device_vendor, "APMemory", sizeof(info->device_vendor)); + strlcpy(info->device_product, "APSx", sizeof(info->device_product)); + return 0; +} + +static int octaram_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length) +{ + return -1; +} + +static int octaram_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length) +{ + return -1; +} + +static int octaram_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) +{ + return -1; +} + +static enum xspidevice_write_status +octaram_get_write_status(xspidevice_ctrl_t *ctrl) +{ + return -1; +} diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h new file mode 100644 index 0000000000..81e9a67fa5 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _OCTARAM_APSXX_API_H_ +#define _OCTARAM_APSXX_API_H_ +#include +#include + +#include "xspidevice_api.h" + +/** xSPI device control structure */ +typedef struct st_octaram_apsxx_ctrl { + bool opened; + const xspi_instance_t *xspi; +} octaram_apsxx_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_octaram_apsxx_ext { + /* No additional configurations */ +} octaram_apsxx_ext_t; + +extern const xspidevice_api_t octaram_apsxx_api; + +#endif /* _OCTARAM_APSXX_API_H_ */ diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk new file mode 100644 index 0000000000..01345e2036 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := octaram_apsxx +PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) +RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h +RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ + plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c new file mode 100644 index 0000000000..c794e6c91e --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include "qspiflash_at25_api.h" + +/* Defaults */ +#define DEFAULT_SPI_FREQUENCY 66666667 +#define SPI_POST_RESET_WAIT 50 + +/* Static function pre-definition */ +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg); +static int flash_close(xspidevice_ctrl_t *ctrl); +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write); +static int flash_enter_xip(xspidevice_ctrl_t *ctrl); +static int flash_exit_xip(xspidevice_ctrl_t *ctrl); +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info); +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length); +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length); +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length); +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl); + +/* API function table definition */ +const xspidevice_api_t qspiflash_at25_api = { + .open = flash_open, + .close = flash_close, + .exec_op = flash_exec_op, + .enter_xip = flash_enter_xip, + .exit_xip = flash_exit_xip, + .get_info = flash_get_info, + .read = flash_read, + .write = flash_write, + .erase = flash_erase, + .get_write_status = flash_get_write_status, +}; + +/* Static variables */ +static int spi_frequency = DEFAULT_SPI_FREQUENCY; +static const uint8_t status2_srp1 = 0x01; +static const uint8_t status2_qe = 0x02; + +/*** Flash Commands ***/ +/* Write Enable */ +static const xspi_op_t op_write_enable = { + .form = SPI_FORM_1_1_1, + .op = 0x06, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Read Status Register - 1 */ +static const xspi_op_t op_read_status1 = { + .form = SPI_FORM_1_1_1, + .op = 0x05, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Read Status Register - 2 */ +static const xspi_op_t op_read_status2 = { + .form = SPI_FORM_1_1_1, + .op = 0x35, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Write Status Register - 2 */ +static const xspi_op_t op_write_status2 = { + .form = SPI_FORM_1_1_1, + .op = 0x31, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Read Command = Fast Read Quad I/O (EBh) */ +static const xspi_op_t rop = { + .form = SPI_FORM_1_4_4, + .op = 0xeb, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 3, + .additional_value = 0x55555555, + .additional_size = 1, + .dummy_cycles = 4, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Quad Page Program */ +static const xspi_op_t op_page_program = { + .form = SPI_FORM_1_4_4, + .op = 0x33, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 3, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Erase 4k */ +static const xspi_op_t op_erase_4k = { + .form = SPI_FORM_1_1_1, + .op = 0x20, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 3, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Erase 32k */ +static const xspi_op_t op_erase_32k = { + .form = SPI_FORM_1_1_1, + .op = 0x52, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 3, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Erase 64k */ +static const xspi_op_t op_erase_64k = { + .form = SPI_FORM_1_1_1, + .op = 0xD8, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 3, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLD pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLD pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 6 +}; + +/* Function definitions */ +static int flash_write_enable(qspiflash_at25_ctrl_t *myctrl) +{ + const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable, false); +} + +static int flash_read_status_register1(qspiflash_at25_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t status; + xspi_op_t op = op_read_status1; + op.transfer_buffer = &status; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result) + return result; + return (int)status; +} + +static int flash_read_status_register2(qspiflash_at25_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t status; + xspi_op_t op = op_read_status2; + op.transfer_buffer = &status; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result) + return result; + return (int)status; +} + +static int flash_write_status_register2(qspiflash_at25_ctrl_t *myctrl, + uint8_t status) +{ + const xspi_instance_t *xspi = myctrl->xspi; + xspi_op_t op = op_write_status2; + op.transfer_buffer = &status; + return xspi->api->exec_op(xspi->ctrl, &op, true); +} + +static int flash_set_qe(qspiflash_at25_ctrl_t *myctrl) +{ + int result; + result = flash_read_status_register2(myctrl); + if (result < 0) + return result; + uint8_t sr2 = (uint8_t)result; + + /* Check if QE is set or not */ + if (sr2 & status2_qe) + return 0; + + /* Check if SRP1 is set or not : If set, can not set QE bit */ + if (sr2 & status2_srp1) + return -1; + + /* Set QE bit */ + result = flash_write_enable(myctrl); + if (result < 0) + return result; + sr2 |= status2_qe; + return flash_write_status_register2(myctrl, sr2); +} + +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) +{ + assert(ctrl); + assert(cfg); + int result; + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = cfg->xspi; + + if (myctrl->opened) + return -1; + + myctrl->xspi = xspi; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (result == 0) { + result = xspi->api->set_frequency(xspi->ctrl, spi_frequency); + udelay(SPI_POST_RESET_WAIT); + } + if (result == 0) { + result = flash_set_qe(myctrl); + } + if (result == 0) { + myctrl->opened = true; + } else { + xspi->api->close(xspi->ctrl); + } + + return result; +} +static int flash_close(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result = -1; + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { + result = xspi->api->close(xspi->ctrl); + myctrl->opened = false; + } + return result; +} +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write) +{ + assert(ctrl); + assert(op); + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->exec_op(xspi->ctrl, op, is_write); +} + +static int flash_enter_xip(xspidevice_ctrl_t *ctrl) +{ + int result = -1; + assert(ctrl); + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + result = xspi->api->configure_xip(xspi->ctrl, &rop, NULL); + if (result == 0) { + result = xspi->api->set_frequency(xspi->ctrl, spi_frequency); + } + if (result == 0) { + result = xspi->api->start_xip(xspi->ctrl); + } + + return result; +} +static int flash_exit_xip(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->stop_xip(xspi->ctrl); +} +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info) +{ + assert(ctrl); + assert(info); + info->capacity = 0; + info->minimum_erase_size = 0; + + strlcpy(info->device_vendor, "Renesas", sizeof(info->device_vendor)); + strlcpy(info->device_product, "AT25x", sizeof(info->device_product)); + return 0; +} +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length) +{ + assert(ctrl); + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); + + return 0; +} + +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length) +{ + int result = 0; + if (RZ_XSPIFLASH_DISABLE_WRITE) { + result = -1; + } else { + assert(ctrl); + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + uintptr_t tmp_buffer = (uintptr_t)buffer; + xspi_op_t op = op_page_program; + + /* Stop XIP mode */ + xspi->api->stop_xip(xspi->ctrl); + + while (length && !result) { + /* Wait for previous command finished */ + enum xspidevice_write_status ws; + do { + ws = flash_get_write_status(ctrl); + } while (ws == WRITE_STATUS_IN_PROGRESS); + if (ws != WRITE_STATUS_OK) { + /* Error on previous command */ + result = -1; + break; + } + result = flash_write_enable(myctrl); + if (result) + break; + + op.transfer_buffer = (void *)tmp_buffer; + op.address = address; + if (length > 256) + op.transfer_size = 256; + else + op.transfer_size = length; + + /* Execute page program */ + result = xspi->api->exec_op(xspi->ctrl, &op, true); + + /* Move pointer */ + address += op.transfer_size; + tmp_buffer += op.transfer_size; + length -= op.transfer_size; + } + + xspi->api->start_xip(xspi->ctrl); + + /* Invalidate dcache */ + xspi->api->inv_mmap(xspi->ctrl); + } + + return result; +} + +static int flash_erase_4k(qspiflash_at25_ctrl_t *myctrl, size_t address) +{ + xspi_op_t op = op_erase_4k; + op.address = address; + return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); +} + +static int flash_erase_32k(qspiflash_at25_ctrl_t *myctrl, size_t address) +{ + xspi_op_t op = op_erase_32k; + op.address = address; + return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); +} + +static int flash_erase_64k(qspiflash_at25_ctrl_t *myctrl, size_t address) +{ + xspi_op_t op = op_erase_64k; + op.address = address; + return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); +} + +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) +{ + int result; + if (RZ_XSPIFLASH_DISABLE_WRITE) { + result = -1; + } else { + assert(ctrl); + assert((address & 4095) == 0); + assert(length > 4095); + size_t over = address + length; + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + + do { + /* Wait for previous command finished */ + enum xspidevice_write_status ws; + do { + ws = flash_get_write_status(ctrl); + } while (ws == WRITE_STATUS_IN_PROGRESS); + if (ws != WRITE_STATUS_OK) { + /* Error on previous command */ + return -1; + } + result = flash_write_enable(myctrl); + if (result) + return result; + + /* Select erase size */ + if (!(address & 0xffff) && length >= 65536) { + /* 64K boundary */ + result = flash_erase_64k(myctrl, address); + address += 65536; + length -= 65536; + } else if (!(address & 0x7fff) && length >= 32768) { + /* 32K boundary */ + result = flash_erase_32k(myctrl, address); + address += 32768; + length -= 32768; + } else { + /* 4K boundary */ + result = flash_erase_4k(myctrl, address); + address += 4096; + length -= 4096; + } + + if (result) + return result; + } while (address < over); + } + + return result; +} + +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result; + qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; + + /* Read Status Register - 1 */ + result = flash_read_status_register1(myctrl); + if (result < 0) + return WRITE_STATUS_FAIL; + if (result & 1) + return WRITE_STATUS_IN_PROGRESS; + return WRITE_STATUS_OK; +} diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h new file mode 100644 index 0000000000..a094017a71 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _QSPIFLASH_AT25_API_H_ +#define _QSPIFLASH_AT25_API_H_ +#include +#include + +#include "xspidevice_api.h" + +/** xSPI device control structure */ +typedef struct st_qspiflash_at25_ctrl { + bool opened; + const xspi_instance_t *xspi; +} qspiflash_at25_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_qspiflash_at25_ext { + /* No additional configurations */ +} qspiflash_at25_ext_t; + +extern const xspidevice_api_t qspiflash_at25_api; + +#endif /* _QSPIFLASH_AT25_API_H_ */ diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk new file mode 100644 index 0000000000..7352fd8c08 --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := qspiflash_at25 +PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) +RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h +RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ + plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c new file mode 100644 index 0000000000..ddf2dd1dfe --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c @@ -0,0 +1,764 @@ +/* + * Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include + +#include "errno.h" +#include "lib/mmio.h" +#include "pfc_regs.h" +#include "qspiflash_mx25l25645g_api.h" + +/* Defaults */ +static const bool DEFAULT_PBE_ENABLE; +static const uint32_t DEFAULT_TIMEOUT = 1000; /* usec */ +static const uint32_t DEFAULT_SPI_FREQUENCY = 66666666U; +static const e_read_mode_t DEFAULT_READ_MODE = READ_MODE_QUAD; +static const e_dummy_cycles_t DEFAULT_DUMMY_CYCLES = DUMMY_CYCLES_6; +static const e_burst_read_wrap_depth_t DEFAULT_BURST_READ_WRAP_DEPTH = + BURST_READ_WRAP_DISABLE; +static const e_output_driver_strength_t DEFAULT_OUTPUT_DRIVER_STRENGTH = + OUTPUT_DRIVER_STRENGTH_30_OHMS; + +static const uint32_t SPI_POST_RESET_WAIT = 50; /* usec */ +static const uint32_t FLASH_RESET_RECOVERY_WAIT = 40; /* usec */ +static const uint32_t MAX_FLASH_UNLOCK_RETRIES = 3; + +static const uintptr_t WP_IO2_PIN_PORT_ADDR = PFC_P05; +static const uintptr_t WP_IO2_PIN_PORT_MODE_ADDR = PFC_PMC05; +static const uint32_t WP_IO2_PIN_BIT = BIT(3); + +/* Static function pre-definition */ +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg); +static int flash_close(xspidevice_ctrl_t *ctrl); +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write); +static int flash_enter_xip(xspidevice_ctrl_t *ctrl); +static int flash_exit_xip(xspidevice_ctrl_t *ctrl); +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info); +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length); +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length); +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length); +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl); + +/* API function table definition */ +const xspidevice_api_t qspiflash_mx25l25645g_api = { + .open = flash_open, + .close = flash_close, + .exec_op = flash_exec_op, + .enter_xip = flash_enter_xip, + .exit_xip = flash_exit_xip, + .get_info = flash_get_info, + .read = flash_read, + .write = flash_write, + .erase = flash_erase, + .get_write_status = flash_get_write_status, +}; + +/* Static variables */ +static const int spi_frequency = DEFAULT_SPI_FREQUENCY + 1; + +/*** Flash Commands ***/ +/* Write Enable */ +static const xspi_op_t op_write_enable = { + .form = SPI_FORM_1_1_1, + .op = 0x06, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Read Manufacturer ID */ +static const xspi_op_t op_read_id = { + .form = SPI_FORM_1_1_1, + .op = 0x9f, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Read Status Register */ +static const xspi_op_t op_read_status = { + .form = SPI_FORM_1_1_1, + .op = 0x05, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Read Configuration Register */ +static const xspi_op_t op_read_configuraton = { + .form = SPI_FORM_1_1_1, + .op = 0x15, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Write Status/Configuration Register */ +static const xspi_op_t op_write_sr = { + .form = SPI_FORM_1_1_1, + .op = 0x01, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 2, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* RSTEN (Reset Enable) */ +static const xspi_op_t op_reset_enable = { + .form = SPI_FORM_1_1_1, + .op = 0x66, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* RST (Reset) */ +static const xspi_op_t op_reset = { + .form = SPI_FORM_1_1_1, + .op = 0x99, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Burst Read */ +static const xspi_op_t op_burst_read = { + .form = SPI_FORM_1_1_1, + .op = 0xc0, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 0, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 0, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 1, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* FASTREAD4B (Fast Read Mode with 4 Byte Address, 1-1-1) */ +static const xspi_op_t op_fast_read = { + .form = SPI_FORM_1_1_1, + .op = 0x0c, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = 8, /* cannot change */ + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* 4READ4B (4x I/O Read Mode with 4 Byte Address, 1-4-4) */ +static const xspi_op_t op_quad_io_read = { + .form = SPI_FORM_1_4_4, + .op = 0xec, + .op_size = 1, + .op_is_ddr = false, + .address = 0, + .address_is_ddr = false, + .address_size = 4, + .additional_value = 0, + .additional_size = 0, + .dummy_cycles = (uint8_t)DEFAULT_DUMMY_CYCLES, + .transfer_buffer = NULL, + .transfer_is_ddr = false, + .transfer_size = 0, + .force_idle_level_mask = 0x08, // Keep IO3/HOLDorRESET pin to High + .force_idle_level_value = 0x08, // Keep IO3/HOLDorRESET pin to High + .slch_value = 0, + .clsh_value = 0, + .shsl_value = 1 +}; + +/* Function definitions */ +static int flash_write_enable(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + const xspi_instance_t *xspi = myctrl->xspi; + int timeout = DEFAULT_TIMEOUT; + enum xspidevice_write_status status = WRITE_STATUS_DISABLED; + while ((status != WRITE_STATUS_OK) && (timeout > 0)) { + xspi->api->exec_op(xspi->ctrl, &op_write_enable, false); + status = flash_get_write_status(myctrl); + timeout--; + udelay(1); + } + if (timeout == 0) { + ERROR("Timeout on write enable, status: %d\n", status); + return -1; + } + if (status != WRITE_STATUS_OK) { + ERROR("Write enable failed\n"); + return -1; + } + return 0; +} + +static int flash_check_manufacturer_id(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t id[3]; + xspi_op_t op = op_read_id; + op.transfer_buffer = id; + op.transfer_size = 3; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result < 0) + return result; + const uint16_t device_id = (id[1] << 8) | id[2]; + if ((id[0] != MANUFACTURER_ID) || (device_id != DEVICE_ID)) { + ERROR("Flash device not found\n"); + VERBOSE("Manufacturer ID: 0x%02x, Device ID: 0x%04x\n", id[0], + device_id); + return -1; + } + + return 0; +} + +static uint8_t flash_read_status_register(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t status; + xspi_op_t op = op_read_status; + op.transfer_buffer = &status; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result < 0) { + ERROR("Failed to read status register\n"); + panic(); + } + return status; +} + +static uint8_t +flash_read_configuration_register(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + int result; + const xspi_instance_t *xspi = myctrl->xspi; + + uint8_t configuration; + xspi_op_t op = op_read_configuraton; + op.transfer_buffer = &configuration; + result = xspi->api->exec_op(xspi->ctrl, &op, false); + if (result < 0) { + ERROR("Failed to read configuration register\n"); + panic(); + } + return configuration; +} + +static int flash_wait_for_write_complete(qspiflash_mx25l25645g_ctrl_t *myctrl, + uint32_t timeout /* usec */) +{ + assert(myctrl); + assert(timeout > 0); + + uint8_t status = 0; + do { + status = flash_read_status_register(myctrl); + timeout--; + udelay(1); + } while ((status & BIT(0)) != 0 && timeout > 0); + + if (timeout == 0) { + ERROR("Timeout after write operation, status: %d\n", status); + return -1; + } + + return 0; +} + +static int flash_reset(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + const xspi_instance_t *xspi = myctrl->xspi; + flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + + /* Reset Enable */ + int result = xspi->api->exec_op(xspi->ctrl, &op_reset_enable, false); + if (result < 0) + return result; + + /* Reset */ + result = xspi->api->exec_op(xspi->ctrl, &op_reset, false); + if (result < 0) + return result; + + udelay(FLASH_RESET_RECOVERY_WAIT); + + return result; +} + +static int flash_prepare_unlock(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + /* Set WP#SIO2 as GPIO */ + mmio_write_8(WP_IO2_PIN_PORT_MODE_ADDR, + mmio_read_8(WP_IO2_PIN_PORT_MODE_ADDR) & ~WP_IO2_PIN_BIT); + /* Set WP#SIO2 to high */ + mmio_write_8(WP_IO2_PIN_PORT_ADDR, + mmio_read_8(WP_IO2_PIN_PORT_ADDR) | WP_IO2_PIN_BIT); + + /* Check if WP#SIO2 is high */ + if ((mmio_read_8(WP_IO2_PIN_PORT_ADDR) & WP_IO2_PIN_BIT) == 0) { + ERROR("Failed to pull up WP#SIO2\n"); + return -1; + } + return 0; +} + +static int flash_finish_unlock(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + /* Set WP#SIO2 as peripheral */ + mmio_write_8(WP_IO2_PIN_PORT_MODE_ADDR, + mmio_read_8(WP_IO2_PIN_PORT_MODE_ADDR) | WP_IO2_PIN_BIT); + return 0; +} + +static void flash_hw_protect_unlock(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + VERBOSE("Trying to unlock the flash HW protection\n"); + + int result = flash_reset(myctrl); + if (result < 0) { + ERROR("Failed to reset the flash while unlocking HW protection\n"); + goto err; + } + + /* Write enable */ + result = flash_write_enable(myctrl); + if (result < 0) { + ERROR("Failed to enable write while unlocking HW protection\n"); + goto err; + } + + const xspi_instance_t *xspi = myctrl->xspi; + + if (flash_prepare_unlock(myctrl) < 0) + goto err; + + xspi_op_t op = op_write_sr; + uint8_t status_configuration_register[2] = { + 0, /* Status Register, ensure the SRWD(bit7) is 0 */ + 0, + }; + op.transfer_buffer = (void *)&status_configuration_register; + result = xspi->api->exec_op(xspi->ctrl, &op, true); + if (result < 0) + goto err; + + result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + if (result < 0) + goto err; + + /* Verify if the status register is written correctly */ + uint8_t status = flash_read_status_register(myctrl); + if ((status & 0x80) != 0) + goto err; + + if (flash_finish_unlock(myctrl) < 0) + goto err; + + VERBOSE("Flash HW protection is unlocked\n"); + + return; + +err: + ERROR("Failed to unlock the flash\n"); + panic(); +} + +static int flash_init(qspiflash_mx25l25645g_ctrl_t *myctrl) +{ + if (flash_check_manufacturer_id(myctrl) != 0) + return -1; + + const xspi_instance_t *xspi = myctrl->xspi; + + int result = flash_reset(myctrl); + if (result < 0) + return result; + + /* Write enable */ + result = flash_write_enable(myctrl); + if (result < 0) + return result; + + /* Determine status_register */ + uint8_t status_register = 0; + if (DEFAULT_READ_MODE == READ_MODE_QUAD) { + status_register = 1u << 6; /* QE (Quad Enable) : Enable */ + } + + /* Determine configuration_register */ + uint8_t configuration_register = 0; + if (DEFAULT_READ_MODE == READ_MODE_QUAD) { + switch (DEFAULT_DUMMY_CYCLES) { + case DUMMY_CYCLES_4: + configuration_register = 1u << 6; + break; + case DUMMY_CYCLES_8: + configuration_register = 2u << 6; + break; + case DUMMY_CYCLES_10: + configuration_register = 3u << 6; + break; + case DUMMY_CYCLES_6: + default: + configuration_register = + 0u << 6; /* Default: 6 dummy cycles */ + break; + } + } else { + if (DEFAULT_DUMMY_CYCLES != DUMMY_CYCLES_8) { + ERROR("Only dummy cycles 8 is supported for normal read mode\n"); + return -1; /* Only dummy cycles 8 is supported for normal read mode */ + } + + configuration_register = 0u << 6; /* DC[1:0] */ + } + + if (DEFAULT_PBE_ENABLE) { + configuration_register |= 1u + << 4; /* PBE (Preamble Bit Enable) */ + } + configuration_register |= DEFAULT_OUTPUT_DRIVER_STRENGTH + << 0; /* ODS[1:0] */ + + /* Write configuration register */ + xspi_op_t op = op_write_sr; + uint8_t status_configuration_register[2] = { status_register, + configuration_register }; + op.transfer_buffer = (void *)&status_configuration_register; + result = xspi->api->exec_op(xspi->ctrl, &op, true); + if (result < 0) + return result; + + result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + if (result < 0) + return result; + + /* Verify if the status register is written correctly */ + uint8_t status = flash_read_status_register(myctrl); + if (status != status_register) { + if ((status & 0x80) != 0) { + WARN("Flash is in Hardware Protection Mode\n"); + return -EAGAIN; + } + ERROR("Failed to write status register\n"); + return -1; + } + + /* Verify if the configuration register is written correctly */ + uint8_t configuration = flash_read_configuration_register(myctrl); + if (configuration != configuration_register) { + ERROR("Failed to write configuration register\n"); + return -1; + } + + return result; +} + +static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) +{ + assert(ctrl); + assert(cfg); + int result; + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + const xspi_instance_t *xspi = cfg->xspi; + + if (myctrl->opened) + return -EBUSY; + + myctrl->xspi = xspi; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (result == 0) { + result = xspi->api->set_frequency(xspi->ctrl, spi_frequency); + } + if (result == 0) { + udelay(SPI_POST_RESET_WAIT); + + uint32_t retries = 0; + do { + retries++; + if (retries >= MAX_FLASH_UNLOCK_RETRIES) + break; + + result = flash_init(myctrl); + if (result == -EAGAIN) + flash_hw_protect_unlock(myctrl); + } while (result == -EAGAIN); + + if (result == 0) { + myctrl->opened = true; + } else { + xspi->api->close(xspi->ctrl); + } + } + + return result; +} + +static int flash_close(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + int result = -1; + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { + result = xspi->api->close(xspi->ctrl); + myctrl->opened = false; + } + + return result; +} + +static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write) +{ + assert(ctrl); + assert(op); + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + return xspi->api->exec_op(xspi->ctrl, op, is_write); +} + +static int flash_enter_xip(xspidevice_ctrl_t *ctrl) +{ + int result = -1; + assert(ctrl); + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + result = flash_write_enable(myctrl); + if (result < 0) + return result; + + xspi_op_t op = op_burst_read; + uint8_t wrap_depth = DEFAULT_BURST_READ_WRAP_DEPTH; + op.transfer_buffer = (void *)&wrap_depth; + result = xspi->api->exec_op(xspi->ctrl, &op, true); + + result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + if (result < 0) + return result; + + if (DEFAULT_READ_MODE == READ_MODE_QUAD) { + result = xspi->api->configure_xip(xspi->ctrl, &op_quad_io_read, + NULL); + } else { + result = xspi->api->configure_xip(xspi->ctrl, &op_fast_read, + NULL); + } + + if (result < 0) + return result; + + result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + if (result < 0) + return result; + + result = xspi->api->set_frequency(xspi->ctrl, spi_frequency); + if (result < 0) + return result; + + result = xspi->api->start_xip(xspi->ctrl); + + return result; +} +static int flash_exit_xip(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + + xspi_op_t op = op_burst_read; + uint8_t wrap_depth = BURST_READ_WRAP_DISABLE; + op.transfer_buffer = (void *)&wrap_depth; + const xspi_instance_t *xspi = myctrl->xspi; + int result = xspi->api->exec_op(xspi->ctrl, &op, true); + + result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); + if (result < 0) + return result; + + return xspi->api->stop_xip(xspi->ctrl); +} +static int flash_get_info(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info) +{ + assert(ctrl); + assert(info); + info->capacity = 0; + info->minimum_erase_size = 0; + + strlcpy(info->device_vendor, "Macronix", sizeof(info->device_vendor)); + strlcpy(info->device_product, "MX25L25645G", + sizeof(info->device_product)); + return 0; +} +static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length) +{ + assert(ctrl); + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + const xspi_instance_t *xspi = myctrl->xspi; + + uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); + + return 0; +} + +static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length) +{ + /* Not supported */ + return -1; +} + +static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) +{ + /* Not supported */ + return -1; +} + +static enum xspidevice_write_status +flash_get_write_status(xspidevice_ctrl_t *ctrl) +{ + assert(ctrl); + qspiflash_mx25l25645g_ctrl_t *myctrl = + (qspiflash_mx25l25645g_ctrl_t *)ctrl; + + /* Read Flag Status Register */ + uint8_t result = flash_read_status_register(myctrl); + if ((result & BIT(0)) != 0) + return WRITE_STATUS_IN_PROGRESS; + if ((result & BIT(1)) == 0) + return WRITE_STATUS_DISABLED; + + return WRITE_STATUS_OK; +} diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h new file mode 100644 index 0000000000..3e4e556e0a --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _QSPIFLASH_MX25L25645G_API_H_ +#define _QSPIFLASH_MX25L25645G_API_H_ +#include +#include + +#include "xspidevice_api.h" + +enum flash_id { + MEMORY_DENSITY_128Mbit = 0x18, + MEMORY_DENSITY_256Mbit = 0x19, + MANUFACTURER_ID = 0xC2, + MEMORY_TYPE = 0x20, + MEMORY_DENSITY = MEMORY_DENSITY_256Mbit, + DEVICE_ID = (MEMORY_DENSITY << 8) | MEMORY_TYPE, +}; + +typedef enum { + BURST_READ_WRAP_8_BYTES = 0x00, + BURST_READ_WRAP_16_BYTES = 0x01, + BURST_READ_WRAP_32_BYTES = 0x02, + BURST_READ_WRAP_64_BYTES = 0x03, + BURST_READ_WRAP_DISABLE = 0x1F, +} e_burst_read_wrap_depth_t; + +typedef enum { + OUTPUT_DRIVER_STRENGTH_30_OHMS = 0x00, + OUTPUT_DRIVER_STRENGTH_45_OHMS = 0x01, + OUTPUT_DRIVER_STRENGTH_90_OHMS = 0x02, + OUTPUT_DRIVER_STRENGTH_15_OHMS = 0x03, +} e_output_driver_strength_t; + +typedef enum { + DUMMY_CYCLES_4 = 4, + DUMMY_CYCLES_6 = 6, + DUMMY_CYCLES_8 = 8, + DUMMY_CYCLES_10 = 10, +} e_dummy_cycles_t; + +typedef enum { + READ_MODE_NORMAL, + READ_MODE_QUAD, +} e_read_mode_t; + +/** xSPI device control structure */ +typedef struct st_qspiflash_mx25l25645g_ctrl { + bool opened; + const xspi_instance_t *xspi; +} qspiflash_mx25l25645g_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_qspiflash_mx25l25645g_ext { + /* No additional configurations */ +} qspiflash_mx25l25645g_ext_t; + +extern const xspidevice_api_t qspiflash_mx25l25645g_api; + +#endif /* _QSPIFLASH_MX25L25645G_API_H_ */ diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk new file mode 100644 index 0000000000..f4092bcc3a --- /dev/null +++ b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := qspiflash_mx25l25645g +PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) +RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h +RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ + plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/include/cpg.h b/plat/renesas/rza/common/include/cpg.h new file mode 100644 index 0000000000..575d39693b --- /dev/null +++ b/plat/renesas/rza/common/include/cpg.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CPG_H__ +#define __CPG_H__ +#include + +#include "cpg_regs.h" + +typedef enum { + XSPI_CLOCK_SPIM, + XSPI_CLOCK_OCTA, +} xspi_clock; + +typedef enum clock_id_t { + CPG_CLOCK_SPIM = 20, + CPG_CLOCK_OCTA = 61, +} clock_id; + +static inline void cpg_clock_onoff(int clkid, uint32_t mask, uint32_t val) +{ + val = mask * (val & 1); + mmio_write_32(CPG_CLKON_CA55 + clkid * 4, (mask << 16) + val); + while ((mmio_read_32(CPG_CLKMON_CA55 + clkid * 4) & mask) != val) + ; +} + +static inline void cpg_reset_onoff(int clkid, uint32_t mask, uint32_t val) +{ + val = mask * (val & 1); + mmio_write_32(CPG_RST_CA55 + clkid * 4, (mask << 16) + (val ^ 0xffff)); + while ((mmio_read_32(CPG_RSTMON_CA55 + clkid * 4) & mask) != val) + ; +} + +#define CPG_CLKRSTONOFF_START(id) switch (id) { +#define CPG_CLKRSTONOFF_END(a) } +#define CPG_CLKON_DEF(id, mask) CPG_CLKONOFF_DEF(id, mask, 1) +#define CPG_CLKOFF_DEF(id, mask) CPG_CLKONOFF_DEF(id, mask, 0) +#define CPG_CLKONOFF_DEF(id, mask, value) \ + case id: \ + cpg_clock_onoff(id, mask, value); \ + break; +#define CPG_RSTON_DEF(id, mask) CPG_RSTONOFF_DEF(id, mask, 1) +#define CPG_RSTOFF_DEF(id, mask) CPG_RSTONOFF_DEF(id, mask, 0) +#define CPG_RSTONOFF_DEF(id, mask, value) \ + case id: \ + cpg_reset_onoff(id, mask, value); \ + break; + +static inline void cpg_clock_on(enum clock_id_t clkid) +{ + CPG_CLKRSTONOFF_START(clkid); + CPG_CLKON_DEF(CPG_CLOCK_SPIM, 3); + CPG_CLKON_DEF(CPG_CLOCK_OCTA, 3); + CPG_CLKRSTONOFF_END(); +} + +static inline void cpg_clock_off(enum clock_id_t clkid) +{ + CPG_CLKRSTONOFF_START(clkid); + CPG_CLKOFF_DEF(CPG_CLOCK_SPIM, 3); + CPG_CLKOFF_DEF(CPG_CLOCK_OCTA, 3); + CPG_CLKRSTONOFF_END(); +} + +static inline void cpg_reset_on(enum clock_id_t clkid) +{ + CPG_CLKRSTONOFF_START(clkid); + CPG_RSTON_DEF(CPG_CLOCK_SPIM, 1); + CPG_RSTON_DEF(CPG_CLOCK_OCTA, 1); + CPG_CLKRSTONOFF_END(); +} + +static inline void cpg_reset_off(enum clock_id_t clkid) +{ + CPG_CLKRSTONOFF_START(clkid); + CPG_RSTOFF_DEF(CPG_CLOCK_SPIM, 1); + CPG_RSTOFF_DEF(CPG_CLOCK_OCTA, 1); + CPG_CLKRSTONOFF_END(); +} + +void cpg_early_setup(void); +void cpg_setup(void); +void cpg_active_ddr(void (*disable_phy)(void)); +void cpg_reset_ddr_mc(void); +int cpg_set_xspi_clock(xspi_clock spi, int frequency_hz); +int cpg_get_xspi_clock(xspi_clock spi); + +#endif /* __CPG_H__ */ diff --git a/plat/renesas/rza/common/include/cpg_regs.h b/plat/renesas/rza/common/include/cpg_regs.h new file mode 100644 index 0000000000..f43d1fd45e --- /dev/null +++ b/plat/renesas/rza/common/include/cpg_regs.h @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CPG_REGS_H__ +#define __CPG_REGS_H__ + +#define CPG_BASE (0x11010000) /* CPG base address */ + +#define CPG_PLL1_STBY (CPG_BASE + 0x0000) /* PLL1 (SSCG) standby control register */ +#define CPG_PLL1_CLK1 (CPG_BASE + 0x0004) /* PLL1 (SSCG) output clock setting register 1 */ +#define CPG_PLL1_CLK2 (CPG_BASE + 0x0008) /* PLL1 (SSCG) output clock setting register 2 */ +#define CPG_PLL1_MON (CPG_BASE + 0x000C) /* PLL1 (SSCG) monitor register */ +#define CPG_PLL4_STBY (CPG_BASE + 0x0010) /* PLL4 (SSCG) standby control register */ +#define CPG_PLL4_CLK1 (CPG_BASE + 0x0014) /* PLL4 (SSCG) output clock setting register 1 */ +#define CPG_PLL4_CLK2 (CPG_BASE + 0x0018) /* PLL4 (SSCG) output clock setting register 2 */ +#define CPG_PLL4_MON (CPG_BASE + 0x001C) /* PLL4 (SSCG) monitor register */ +#define CPG_PLL6_STBY (CPG_BASE + 0x0020) /* PLL6 (SSCG) standby control register */ +#define CPG_PLL6_CLK1 (CPG_BASE + 0x0024) /* PLL6 (SSCG) output clock setting register 1 */ +#define CPG_PLL6_CLK2 (CPG_BASE + 0x0028) /* PLL6 (SSCG) output clock setting register 2 */ +#define CPG_PLL6_MON (CPG_BASE + 0x002C) /* PLL6 (SSCG) monitor register */ +#define CPG_PLL1_SETTING (CPG_BASE + 0x0040) /* PLL1_SEL_SETTING */ +#define CPG_OTPPLL0_MON (CPG_BASE + 0x0044) /* OTP_OTPPLL0 monitor register */ +#define CPG_OTPPLL1_MON (CPG_BASE + 0x0048) /* OTP_OTPPLL1 monitor register */ +#define CPG_OTPPLL2_MON (CPG_BASE + 0x004C) /* OTP_OTPPLL2 monitor register */ + +#define CPG_PLL2_STBY (CPG_BASE + 0x0100) /* PLL2 (SSCG) standby control register */ +#define CPG_PLL2_CLK1 (CPG_BASE + 0x0104) /* PLL2 (SSCG) output clock setting register 1 */ +#define CPG_PLL2_CLK2 (CPG_BASE + 0x0108) /* PLL2 (SSCG) output clock setting register 2 */ +#define CPG_PLL2_CLK3 (CPG_BASE + 0x010C) /* PLL2 (SSCG) output clock setting register 3 */ +#define CPG_PLL2_CLK4 (CPG_BASE + 0x0110) /* PLL2 (SSCG) output clock setting register 4 */ +#define CPG_PLL2_CLK5 (CPG_BASE + 0x0114) /* PLL2 (SSCG) output clock setting register 5 */ +#define CPG_PLL2_CLK6 (CPG_BASE + 0x0118) /* PLL2 (SSCG) output clock setting register 6 */ +#define CPG_PLL2_MON (CPG_BASE + 0x011C) /* PLL2 (SSCG) monitor register */ +#define CPG_PLL3_STBY (CPG_BASE + 0x0120) /* PLL3 (SSCG) standby control register */ +#define CPG_PLL3_CLK1 (CPG_BASE + 0x0124) /* PLL3 (SSCG) output clock setting register 1 */ +#define CPG_PLL3_CLK2 (CPG_BASE + 0x0128) /* PLL3 (SSCG) output clock setting register 2 */ +#define CPG_PLL3_CLK3 (CPG_BASE + 0x012C) /* PLL3 (SSCG) output clock setting register 3 */ +#define CPG_PLL3_CLK4 (CPG_BASE + 0x0130) /* PLL3 (SSCG) output clock setting register 4 */ +#define CPG_PLL3_CLK5 (CPG_BASE + 0x0134) /* PLL3 (SSCG) output clock setting register 5 */ +#define CPG_PLL3_MON (CPG_BASE + 0x013C) /* PLL3 (SSCG) monitor register */ +#define CPG_PLL5_STBY (CPG_BASE + 0x0140) /* PLL5 (SSCG) standby control register */ +#define CPG_PLL5_CLK1 (CPG_BASE + 0x0144) /* PLL5 (SSCG) output clock setting register 1 */ +#define CPG_PLL5_CLK2 (CPG_BASE + 0x0148) /* PLL5 (SSCG) output clock setting register 2 */ +#define CPG_PLL5_CLK3 (CPG_BASE + 0x014C) /* PLL5 (SSCG) output clock setting register 3 */ +#define CPG_PLL5_CLK4 (CPG_BASE + 0x0150) /* PLL5 (SSCG) output clock setting register 4 */ +#define CPG_PLL5_CLK5 (CPG_BASE + 0x0154) /* PLL5 (SSCG) output clock setting register 5 */ +#define CPG_PLL5_MON (CPG_BASE + 0x015C) /* PLL5 (SSCG) monitor register */ + +#define CPG_PL1_DDIV (CPG_BASE + 0x0200) /* Division ratio setting register */ +#define CPG_PL2_DDIV (CPG_BASE + 0x0204) /* Division ratio setting register */ +#define CPG_PL3A_DDIV (CPG_BASE + 0x0208) /* Division ratio setting register */ +#define CPG_PL3B_DDIV (CPG_BASE + 0x020C) /* Division ratio setting register */ +#define CPG_PL6_DDIV (CPG_BASE + 0x0210) /* Division ratio setting register */ + +#define CPG_PL2SDHI_DSEL (CPG_BASE + 0x0218) /* Source clock setting register */ +#define CPG_PL4_DSEL (CPG_BASE + 0x021C) /* Source clock setting register */ +#define CPG_CLKSTATUS (CPG_BASE + 0x0280) /* CLK status register */ + +#define CPG_PL1_CA55_SSEL (CPG_BASE + 0x0400) /* Source clock setting register */ +#define CPG_PL2_SSEL (CPG_BASE + 0x0404) /* Source clock setting register */ +#define CPG_PL3_SSEL (CPG_BASE + 0x0408) /* Source clock setting register */ +#define CPG_PL5_SSEL (CPG_BASE + 0x0410) /* Source clock setting register */ +#define CPG_PL6_SSEL (CPG_BASE + 0x0414) /* Source clock setting register */ +#define CPG_PL6_ETH_SSEL (CPG_BASE + 0x0418) /* Source clock setting register */ +#define CPG_PL5_SDIV (CPG_BASE + 0x0420) /* Division ratio setting register */ + +#define CPG_CLKON_CA55 (CPG_BASE + 0x0500) /* Clock ON/OFF register CA55 */ +#define CPG_CLKON_CM33 (CPG_BASE + 0x0504) /* Clock ON/OFF register CM33 */ +#define CPG_CLKON_SRAM_ACPU (CPG_BASE + 0x0508) /* Clock ON/OFF register SRAM_ACPU */ +#define CPG_CLKON_SRAM_MCPU (CPG_BASE + 0x050C) /* Clock ON/OFF register SRAM_MCPU */ +#define CPG_CLKON_ROM (CPG_BASE + 0x0510) /* Clock ON/OFF register ROM */ +#define CPG_CLKON_GIC600 (CPG_BASE + 0x0514) /* Clock ON/OFF register GIC600 */ +#define CPG_CLKON_IA55 (CPG_BASE + 0x0518) /* Clock ON/OFF register IA55 */ +#define CPG_CLKON_IM33 (CPG_BASE + 0x051C) /* Clock ON/OFF register IM33 */ +#define CPG_CLKON_MHU (CPG_BASE + 0x0520) /* Clock ON/OFF register MHU */ +#define CPG_CLKON_CST (CPG_BASE + 0x0524) /* Clock ON/OFF register CST */ +#define CPG_CLKON_SYC (CPG_BASE + 0x0528) /* Clock ON/OFF register SYC */ +#define CPG_CLKON_DAMC_REG (CPG_BASE + 0x052C) /* Clock ON/OFF register DAMC_REG */ +#define CPG_CLKON_SYSC (CPG_BASE + 0x0530) /* Clock ON/OFF register SYSC */ +#define CPG_CLKON_OSTM (CPG_BASE + 0x0534) /* Clock ON/OFF register OSTM */ +#define CPG_CLKON_MTU (CPG_BASE + 0x0538) /* Clock ON/OFF register MTU */ +#define CPG_CLKON_POE3 (CPG_BASE + 0x053C) /* Clock ON/OFF register POE3 */ +#define CPG_CLKON_WDT (CPG_BASE + 0x0548) /* Clock ON/OFF register WDT */ +#define CPG_CLKON_DDR (CPG_BASE + 0x054C) /* Clock ON/OFF register DDR */ +#define CPG_CLKON_SPI_MULTI (CPG_BASE + 0x0550) /* Clock ON/OFF register SPI_MULTI */ +#define CPG_CLKON_SDHI (CPG_BASE + 0x0554) /* Clock ON/OFF register SDHI */ +#define CPG_CLKON_ISU (CPG_BASE + 0x055C) /* Clock ON/OFF register ISU */ +#define CPG_CLKON_CRU (CPG_BASE + 0x0564) /* Clock ON/OFF register CRU */ +#define CPG_CLKON_MIPI_DSI (CPG_BASE + 0x0568) /* Clock ON/OFF register MIPI_DSI */ +#define CPG_CLKON_LCDC (CPG_BASE + 0x056C) /* Clock ON/OFF register LCDC */ +#define CPG_CLKON_SSI (CPG_BASE + 0x0570) /* Clock ON/OFF register SSI */ +#define CPG_CLKON_SRC (CPG_BASE + 0x0574) /* Clock ON/OFF register SRC */ +#define CPG_CLKON_USB (CPG_BASE + 0x0578) /* Clock ON/OFF register USB */ +#define CPG_CLKON_ETH (CPG_BASE + 0x057C) /* Clock ON/OFF register ETH */ +#define CPG_CLKON_I2C (CPG_BASE + 0x0580) /* Clock ON/OFF register I2C */ +#define CPG_CLKON_SCIF (CPG_BASE + 0x0584) /* Clock ON/OFF register SCIF */ +#define CPG_CLKON_SCI (CPG_BASE + 0x0588) /* Clock ON/OFF register SCI */ +#define CPG_CLKON_IRDA (CPG_BASE + 0x058C) /* Clock ON/OFF register IRDA */ +#define CPG_CLKON_RSPI (CPG_BASE + 0x0590) /* Clock ON/OFF register RSPI */ +#define CPG_CLKON_CANFD (CPG_BASE + 0x0594) /* Clock ON/OFF register CANFD */ +#define CPG_CLKON_GPIO (CPG_BASE + 0x0598) /* Clock ON/OFF register GPIO */ +#define CPG_CLKON_TSIPG (CPG_BASE + 0x059C) /* Clock ON/OFF register TSIPG */ +#define CPG_CLKON_JAUTH (CPG_BASE + 0x05A0) /* Clock ON/OFF register JAUTH */ +#define CPG_CLKON_OTP (CPG_BASE + 0x05A4) /* Clock ON/OFF register OTP */ +#define CPG_CLKON_ADC (CPG_BASE + 0x05A8) /* Clock ON/OFF register ADC */ +#define CPG_CLKON_TSU (CPG_BASE + 0x05AC) /* Clock ON/OFF register TSU */ +#define CPG_CLKON_BBGU (CPG_BASE + 0x05B0) /* Clock ON/OFF register BBGU */ +#define CPG_CLKON_AXI_ACPU_BUS (CPG_BASE + 0x05B4) /* Clock ON/OFF register AXI_ACPU_BUS */ +#define CPG_CLKON_AXI_MCPU_BUS (CPG_BASE + 0x05B8) /* Clock ON/OFF register AXI_MCPU_BUS */ +#define CPG_CLKON_AXI_COM_BUS (CPG_BASE + 0x05BC) /* Clock ON/OFF register AXI_COM_BUS */ +#define CPG_CLKON_AXI_VIDEO_BUS (CPG_BASE + 0x05C0) /* Clock ON/OFF register AXI_VIDEO_BUS */ +#define CPG_CLKON_PERI_COM (CPG_BASE + 0x05C4) /* Clock ON/OFF register PERI_COM */ +#define CPG_CLKON_REG1_BUS (CPG_BASE + 0x05C8) /* Clock ON/OFF register REG1_BUS */ +#define CPG_CLKON_REG0_BUS (CPG_BASE + 0x05CC) /* Clock ON/OFF register REG0_BUS */ +#define CPG_CLKON_PERI_CPU (CPG_BASE + 0x05D0) /* Clock ON/OFF register PERI_CPU */ +#define CPG_CLKON_PERI_VIDEO (CPG_BASE + 0x05D4) /* Clock ON/OFF register PERI_VIDEO */ +#define CPG_CLKON_PERI_DDR (CPG_BASE + 0x05D8) /* Clock ON/OFF register PERI_DDR */ +#define CPG_CLKON_AXI_TZCDDR (CPG_BASE + 0x05DC) /* Clock ON/OFF register AXI_TZCDDR */ +#define CPG_CLKON_MTGPGS (CPG_BASE + 0x05E0) /* Clock ON/OFF register MTGPGS */ +#define CPG_CLKON_AXI_DEFAULT_SLV (CPG_BASE + 0x05E4) /* Clock ON/OFF register AXI_DEFAULT_SLV */ +#define CPG_CLKON_OCTA (CPG_BASE + 0x05F4) /* Clock ON/OFF register OCTA */ + +#define CPG_CLKMON_CA55 (CPG_BASE + 0x0680) /* Clock monitor register CA55 */ +#define CPG_CLKMON_CM33 (CPG_BASE + 0x0684) /* Clock monitor register CM33 */ +#define CPG_CLKMON_SRAM_ACPU (CPG_BASE + 0x0688) /* Clock monitor register SRAM_ACPU */ +#define CPG_CLKMON_SRAM_MCPU (CPG_BASE + 0x068C) /* Clock monitor register SRAM_MCPU */ +#define CPG_CLKMON_ROM (CPG_BASE + 0x0690) /* Clock monitor register ROM */ +#define CPG_CLKMON_GIC600 (CPG_BASE + 0x0694) /* Clock monitor register GIC600 */ +#define CPG_CLKMON_IA55 (CPG_BASE + 0x0698) /* Clock monitor register IA55 */ +#define CPG_CLKMON_IM33 (CPG_BASE + 0x069C) /* Clock monitor register IM33 */ +#define CPG_CLKMON_MHU (CPG_BASE + 0x06A0) /* Clock monitor register MHU */ +#define CPG_CLKMON_CST (CPG_BASE + 0x06A4) /* Clock monitor register CST */ +#define CPG_CLKMON_SYC (CPG_BASE + 0x06A8) /* Clock monitor register SYC */ +#define CPG_CLKMON_DAMC_REG (CPG_BASE + 0x06AC) /* Clock monitor register DAMC_REG */ +#define CPG_CLKMON_SYSC (CPG_BASE + 0x06B0) /* Clock monitor register SYSC */ +#define CPG_CLKMON_OSTM (CPG_BASE + 0x06B4) /* Clock monitor register OSTM */ +#define CPG_CLKMON_MTU (CPG_BASE + 0x06B8) /* Clock monitor register MTU */ +#define CPG_CLKMON_POE3 (CPG_BASE + 0x06BC) /* Clock monitor register POE3 */ +#define CPG_CLKMON_WDT (CPG_BASE + 0x06C8) /* Clock monitor register WDT */ +#define CPG_CLKMON_DDR (CPG_BASE + 0x06CC) /* Clock monitor register DDR */ +#define CPG_CLKMON_SPI_MULTI (CPG_BASE + 0x06D0) /* Clock monitor register SPI_MULTI */ +#define CPG_CLKMON_SDHI (CPG_BASE + 0x06D4) /* Clock monitor register SDHI */ +#define CPG_CLKMON_ISU (CPG_BASE + 0x06DC) /* Clock monitor register ISU */ +#define CPG_CLKMON_CRU (CPG_BASE + 0x06E4) /* Clock monitor register CRU */ +#define CPG_CLKMON_MIPI_DSI (CPG_BASE + 0x06E8) /* Clock monitor register MIPI_DSI */ +#define CPG_CLKMON_LCDC (CPG_BASE + 0x06EC) /* Clock monitor register LCDC */ +#define CPG_CLKMON_SSI (CPG_BASE + 0x06F0) /* Clock monitor register SSI */ +#define CPG_CLKMON_SRC (CPG_BASE + 0x06F4) /* Clock monitor register SRC */ +#define CPG_CLKMON_USB (CPG_BASE + 0x06F8) /* Clock monitor register USB */ +#define CPG_CLKMON_ETH (CPG_BASE + 0x06FC) /* Clock monitor register ETH */ +#define CPG_CLKMON_I2C (CPG_BASE + 0x0700) /* Clock monitor register I2C */ +#define CPG_CLKMON_SCIF (CPG_BASE + 0x0704) /* Clock monitor register SCIF */ +#define CPG_CLKMON_SCI (CPG_BASE + 0x0708) /* Clock monitor register SCI */ +#define CPG_CLKMON_IRDA (CPG_BASE + 0x070C) /* Clock monitor register IRDA */ +#define CPG_CLKMON_RSPI (CPG_BASE + 0x0710) /* Clock monitor register RSPI */ +#define CPG_CLKMON_CANFD (CPG_BASE + 0x0714) /* Clock monitor register CANFD */ +#define CPG_CLKMON_GPIO (CPG_BASE + 0x0718) /* Clock monitor register GPIO */ +#define CPG_CLKMON_TSIPG (CPG_BASE + 0x071C) /* Clock monitor register TSIPG */ +#define CPG_CLKMON_JAUTH (CPG_BASE + 0x0720) /* Clock monitor register JAUTH */ +#define CPG_CLKMON_OTP (CPG_BASE + 0x0724) /* Clock monitor register OTP */ +#define CPG_CLKMON_ADC (CPG_BASE + 0x0728) /* Clock monitor register ADC */ +#define CPG_CLKMON_TSU (CPG_BASE + 0x072C) /* Clock monitor register TSU */ +#define CPG_CLKMON_BBGU (CPG_BASE + 0x0730) /* Clock monitor register BBGU */ +#define CPG_CLKMON_AXI_ACPU_BUS (CPG_BASE + 0x0734) /* Clock monitor register AXI_ACPU_BUS */ +#define CPG_CLKMON_AXI_MCPU_BUS (CPG_BASE + 0x0738) /* Clock monitor register AXI_MCPU_BUS */ +#define CPG_CLKMON_AXI_COM_BUS (CPG_BASE + 0x073C) /* Clock monitor register AXI_COM_BUS */ +#define CPG_CLKMON_AXI_VIDEO_BUS (CPG_BASE + 0x0740) /* Clock monitor register AXI_VIDEO_BUS */ +#define CPG_CLKMON_PERI_COM (CPG_BASE + 0x0744) /* Clock monitor register PERI_COM */ +#define CPG_CLKMON_REG1_BUS (CPG_BASE + 0x0748) /* Clock monitor register REG1_BUS */ +#define CPG_CLKMON_REG0_BUS (CPG_BASE + 0x074C) /* Clock monitor register REG0_BUS */ +#define CPG_CLKMON_PERI_CPU (CPG_BASE + 0x0750) /* Clock monitor register PERI_CPU */ +#define CPG_CLKMON_PERI_VIDEO (CPG_BASE + 0x0754) /* Clock monitor register PERI_VIDEO */ +#define CPG_CLKMON_PERI_DDR (CPG_BASE + 0x0758) /* Clock monitor register PERI_DDR */ +#define CPG_CLKMON_AXI_TZCDDR (CPG_BASE + 0x075C) /* Clock monitor register AXI_TZCDDR */ +#define CPG_CLKMON_MTGPGS (CPG_BASE + 0x0760) /* Clock monitor register MTGPGS */ +#define CPG_CLKMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0764) /* Clock monitor register AXI_DEFAULT_SLV */ +#define CPG_CLKMON_OCTA (CPG_BASE + 0x0774) /* Clock monitor register OCTA */ + +#define CPG_RST_CA55 (CPG_BASE + 0x0800) /* Reset ONOFF register CA55 */ +#define CPG_RST_CM33 (CPG_BASE + 0x0804) /* Reset ONOFF register CM33 */ +#define CPG_RST_SRAM_ACPU (CPG_BASE + 0x0808) /* Reset ONOFF register SRAM_ACPU */ +#define CPG_RST_SRAM_MCPU (CPG_BASE + 0x080C) /* Reset ONOFF register SRAM_MCPU */ +#define CPG_RST_ROM (CPG_BASE + 0x0810) /* Reset ONOFF register ROM */ +#define CPG_RST_GIC600 (CPG_BASE + 0x0814) /* Reset ONOFF register GIC600 */ +#define CPG_RST_IA55 (CPG_BASE + 0x0818) /* Reset ONOFF register IA55 */ +#define CPG_RST_IM33 (CPG_BASE + 0x081C) /* Reset ONOFF register IM33 */ +#define CPG_RST_MHU (CPG_BASE + 0x0820) /* Reset ONOFF register MHU */ +#define CPG_RST_CST (CPG_BASE + 0x0824) /* Reset ONOFF register CST */ +#define CPG_RST_SYC (CPG_BASE + 0x0828) /* Reset ONOFF register SYC */ +#define CPG_RST_DMAC (CPG_BASE + 0x082C) /* Reset ONOFF register DMAC */ +#define CPG_RST_SYSC (CPG_BASE + 0x0830) /* Reset ONOFF register SYSC */ +#define CPG_RST_OSTM (CPG_BASE + 0x0834) /* Reset ONOFF register OSTM */ +#define CPG_RST_MTU (CPG_BASE + 0x0838) /* Reset ONOFF register MTU */ +#define CPG_RST_POE3 (CPG_BASE + 0x083C) /* Reset ONOFF register POE3 */ +#define CPG_RST_WDT (CPG_BASE + 0x0848) /* Reset ONOFF register WDT */ +#define CPG_RST_DDR (CPG_BASE + 0x084C) /* Reset ONOFF register DDR */ +#define CPG_RST_SPI (CPG_BASE + 0x0850) /* Reset ONOFF register SPI */ +#define CPG_RST_SDHI (CPG_BASE + 0x0854) /* Reset ONOFF register SDHI */ +#define CPG_RST_ISU (CPG_BASE + 0x085C) /* Reset ONOFF register ISU */ +#define CPG_RST_CRU (CPG_BASE + 0x0864) /* Reset ONOFF register CRU */ +#define CPG_RST_MIPI_DSI (CPG_BASE + 0x0868) /* Reset ONOFF register MIPI_DSI */ +#define CPG_RST_LCDC (CPG_BASE + 0x086C) /* Reset ONOFF register LCDC */ +#define CPG_RST_SSIF (CPG_BASE + 0x0870) /* Reset ONOFF register SSIF */ +#define CPG_RST_SRC (CPG_BASE + 0x0874) /* Reset ONOFF register SRC */ +#define CPG_RST_USB (CPG_BASE + 0x0878) /* Reset ONOFF register USB */ +#define CPG_RST_ETH (CPG_BASE + 0x087C) /* Reset ONOFF register ETH */ +#define CPG_RST_I2C (CPG_BASE + 0x0880) /* Reset ONOFF register I2C */ +#define CPG_RST_SCIF (CPG_BASE + 0x0884) /* Reset ONOFF register SCIF */ +#define CPG_RST_SCI (CPG_BASE + 0x0888) /* Reset ONOFF register SCI */ +#define CPG_RST_IRDA (CPG_BASE + 0x088C) /* Reset ONOFF register IRDA */ +#define CPG_RST_RSPI (CPG_BASE + 0x0890) /* Reset ONOFF register RSPI */ +#define CPG_RST_CANFD (CPG_BASE + 0x0894) /* Reset ONOFF register CANFD */ +#define CPG_RST_GPIO (CPG_BASE + 0x0898) /* Reset ONOFF register GPIO */ +#define CPG_RST_TSIPG (CPG_BASE + 0x089C) /* Reset ONOFF register TSIPG */ +#define CPG_RST_JAUTH (CPG_BASE + 0x08A0) /* Reset ONOFF register JAUTH */ +#define CPG_RST_OTP (CPG_BASE + 0x08A4) /* Reset ONOFF register OTP */ +#define CPG_RST_ADC (CPG_BASE + 0x08A8) /* Reset ONOFF register ADC */ +#define CPG_RST_TSU (CPG_BASE + 0x08AC) /* Reset ONOFF register TSU */ +#define CPG_RST_BBGU (CPG_BASE + 0x08B0) /* Reset ONOFF register BBGU */ +#define CPG_RST_AXI_ACPU_BUS (CPG_BASE + 0x08B4) /* Reset ONOFF register AXI_ACPU_BUS */ +#define CPG_RST_AXI_MCPU_BUS (CPG_BASE + 0x08B8) /* Reset ONOFF register AXI_MCPU_BUS */ +#define CPG_RST_AXI_COM_BUS (CPG_BASE + 0x08BC) /* Reset ONOFF register AXI_COM_BUS */ +#define CPG_RST_AXI_VIDEO_BUS (CPG_BASE + 0x08C0) /* Reset ONOFF register AXI_VIDEO_BUS */ +#define CPG_RST_PERI_COM (CPG_BASE + 0x08C4) /* Reset ONOFF register PERI_COM */ +#define CPG_RST_REG1_BUS (CPG_BASE + 0x08C8) /* Reset ONOFF register REG1_BUS */ +#define CPG_RST_REG0_BUS (CPG_BASE + 0x08CC) /* Reset ONOFF register REG0_BUS */ +#define CPG_RST_PERI_CPU (CPG_BASE + 0x08D0) /* Reset ONOFF register PERI_CPU */ +#define CPG_RST_PERI_VIDEO (CPG_BASE + 0x08D4) /* Reset ONOFF register PERI_VIDEO */ +#define CPG_RST_PERI_DDR (CPG_BASE + 0x08D8) /* Reset ONOFF register PERI_DDR */ +#define CPG_RST_AXI_TZCDDR (CPG_BASE + 0x08DC) /* Reset ONOFF register AXI_TZCDDR */ +#define CPG_RST_MTGPGS (CPG_BASE + 0x08E0) /* Reset ONOFF register MTGPGS */ +#define CPG_RST_AXI_DEFAULT_SLV (CPG_BASE + 0x08E4) /* Reset ONOFF register AXI_DEFAULT_SLV */ +#define CPG_RST_OCTA (CPG_BASE + 0x08F4) /* Reset ONOFF register OCTA */ + +#define CPG_RSTMON_CA55 (CPG_BASE + 0x0980) /* Reset monitor register CA55 */ +#define CPG_RSTMON_CM33 (CPG_BASE + 0x0984) /* Reset monitor register CM33 */ +#define CPG_RSTMON_SRAM_ACPU (CPG_BASE + 0x0988) /* Reset monitor register SRAM_ACPU */ +#define CPG_RSTMON_SRAM_MCPU (CPG_BASE + 0x098C) /* Reset monitor register SRAM_MCPU */ +#define CPG_RSTMON_ROM (CPG_BASE + 0x0990) /* Reset monitor register ROM */ +#define CPG_RSTMON_GIC600 (CPG_BASE + 0x0994) /* Reset monitor register GIC600 */ +#define CPG_RSTMON_IA55 (CPG_BASE + 0x0998) /* Reset monitor register IA55 */ +#define CPG_RSTMON_IM33 (CPG_BASE + 0x099C) /* Reset monitor register IM33 */ +#define CPG_RSTMON_MHU (CPG_BASE + 0x09A0) /* Reset monitor register MHU */ +#define CPG_RSTMON_CST (CPG_BASE + 0x09A4) /* Reset monitor register CST */ +#define CPG_RSTMON_SYC (CPG_BASE + 0x09A8) /* Reset monitor register SYC */ +#define CPG_RSTMON_DMAC (CPG_BASE + 0x09AC) /* Reset monitor register DMAC */ +#define CPG_RSTMON_SYSC (CPG_BASE + 0x09B0) /* Reset monitor register SYSC */ +#define CPG_RSTMON_OSTM (CPG_BASE + 0x09B4) /* Reset monitor register OSTM */ +#define CPG_RSTMON_MTU (CPG_BASE + 0x09B8) /* Reset monitor register MTU */ +#define CPG_RSTMON_POE3 (CPG_BASE + 0x09BC) /* Reset monitor register POE3 */ +#define CPG_RSTMON_WDT (CPG_BASE + 0x09C8) /* Reset monitor register WDT */ +#define CPG_RSTMON_DDR (CPG_BASE + 0x09CC) /* Reset monitor register DDR */ +#define CPG_RSTMON_SPI (CPG_BASE + 0x09D0) /* Reset monitor register SPI */ +#define CPG_RSTMON_SDHI (CPG_BASE + 0x09D4) /* Reset monitor register SDHI */ +#define CPG_RSTMON_ISU (CPG_BASE + 0x09DC) /* Reset monitor register ISU */ +#define CPG_RSTMON_CRU (CPG_BASE + 0x09E4) /* Reset monitor register CRU */ +#define CPG_RSTMON_MIPI_DSI (CPG_BASE + 0x09E8) /* Reset monitor register MIPI_DSI */ +#define CPG_RSTMON_LCDC (CPG_BASE + 0x09EC) /* Reset monitor register LCDC */ +#define CPG_RSTMON_SSIF (CPG_BASE + 0x09F0) /* Reset monitor register SSIF */ +#define CPG_RSTMON_SRC (CPG_BASE + 0x09F4) /* Reset monitor register SRC */ +#define CPG_RSTMON_USB (CPG_BASE + 0x09F8) /* Reset monitor register USB */ +#define CPG_RSTMON_ETH (CPG_BASE + 0x09FC) /* Reset monitor register ETH */ +#define CPG_RSTMON_I2C (CPG_BASE + 0x0A00) /* Reset monitor register I2C */ +#define CPG_RSTMON_SCIF (CPG_BASE + 0x0A04) /* Reset monitor register SCIF */ +#define CPG_RSTMON_SCI (CPG_BASE + 0x0A08) /* Reset monitor register SCI */ +#define CPG_RSTMON_IRDA (CPG_BASE + 0x0A0C) /* Reset monitor register IRDA */ +#define CPG_RSTMON_RSPI (CPG_BASE + 0x0A10) /* Reset monitor register RSPI */ +#define CPG_RSTMON_CANFD (CPG_BASE + 0x0A14) /* Reset monitor register CANFD */ +#define CPG_RSTMON_GPIO (CPG_BASE + 0x0A18) /* Reset monitor register GPIO */ +#define CPG_RSTMON_TSIPG (CPG_BASE + 0x0A1C) /* Reset monitor register TSIPG */ +#define CPG_RSTMON_JAUTH (CPG_BASE + 0x0A20) /* Reset monitor register JAUTH */ +#define CPG_RSTMON_OTP (CPG_BASE + 0x0A24) /* Reset monitor register OTP */ +#define CPG_RSTMON_ADC (CPG_BASE + 0x0A28) /* Reset monitor register ADC */ +#define CPG_RSTMON_TSU (CPG_BASE + 0x0A2C) /* Reset monitor register TSU */ +#define CPG_RSTMON_BBGU (CPG_BASE + 0x0A30) /* Reset monitor register BBGU */ +#define CPG_RSTMON_AXI_ACPU_BUS (CPG_BASE + 0x0A34) /* Reset monitor register AXI_ACPU_BUS */ +#define CPG_RSTMON_AXI_MCPU_BUS (CPG_BASE + 0x0A38) /* Reset monitor register AXI_MCPU_BUS */ +#define CPG_RSTMON_AXI_COM_BUS (CPG_BASE + 0x0A3C) /* Reset monitor register AXI_COM_BUS */ +#define CPG_RSTMON_AXI_VIDEO_BUS (CPG_BASE + 0x0A40) /* Reset monitor register AXI_VIDEO_BUS */ +#define CPG_RSTMON_PERI_COM (CPG_BASE + 0x0A44) /* Reset monitor register PERI_COM */ +#define CPG_RSTMON_REG1_BUS (CPG_BASE + 0x0A48) /* Reset monitor register REG1_BUS */ +#define CPG_RSTMON_REG0_BUS (CPG_BASE + 0x0A4C) /* Reset monitor register REG0_BUS */ +#define CPG_RSTMON_PERI_CPU (CPG_BASE + 0x0A50) /* Reset monitor register PERI_CPU */ +#define CPG_RSTMON_PERI_VIDEO (CPG_BASE + 0x0A54) /* Reset monitor register PERI_VIDEO */ +#define CPG_RSTMON_PERI_DDR (CPG_BASE + 0x0A58) /* Reset monitor register PERI_DDR */ +#define CPG_RSTMON_AXI_TZCDDR (CPG_BASE + 0x0A5C) /* Reset monitor register AXI_TZCDDR */ +#define CPG_RSTMON_MTGPGS (CPG_BASE + 0x0A60) /* Reset monitor register MTGPGS */ +#define CPG_RSTMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0A64) /* Reset monitor register AXI_DEFAULT_SLV */ +#define CPG_RSTMON_OCTA (CPG_BASE + 0x0A74) /* Reset monitor register OCTA */ + +#define CPG_EN_OSTM (CPG_BASE + 0x0B00) /* Enable ONOFF register_OSTM */ +#define CPG_WDTOVF_RST (CPG_BASE + 0x0B10) /* WDT overflow system reset register */ +#define CPG_WDTRST_SEL (CPG_BASE + 0x0B14) /* WDT reset selector register */ +#define CPG_DBGRST (CPG_BASE + 0x0B20) /* Reset ONOFF register DBGRST */ +#define CPG_CLUSTER_PCHMON (CPG_BASE + 0x0B30) /* CA55 Cluster Power Status Monitor Register */ +#define CPG_CLUSTER_PCHCTL (CPG_BASE + 0x0B34) /* CA55 Cluster Power Status Control Register */ +#define CPG_CORE0_PCHMON (CPG_BASE + 0x0B38) /* CA55 Core0 Power Status Monitor Register */ +#define CPG_CORE0_PCHCTL (CPG_BASE + 0x0B3C) /* CA55 Core0 Power Status Control Register */ +#define CPG_CORE1_PCHMON (CPG_BASE + 0x0B40) /* CA55 Core1 Power Status Monitor Register */ +#define CPG_CORE1_PCHCTL (CPG_BASE + 0x0B44) /* CA55 Core1 Power Status Control Register */ +#define CPG_BUS_ACPU_MSTOP (CPG_BASE + 0x0B60) /* MSTOP registerBUS_ACPU */ +#define CPG_BUS_MCPU1_MSTOP (CPG_BASE + 0x0B64) /* MSTOP registerBUS_MCPU1 */ +#define CPG_BUS_MCPU2_MSTOP (CPG_BASE + 0x0B68) /* MSTOP registerBUS_MCPU2 */ +#define CPG_BUS_PERI_COM_MSTOP (CPG_BASE + 0x0B6C) /* MSTOP registerBUS_PERI_COM */ +#define CPG_BUS_PERI_CPU_MSTOP (CPG_BASE + 0x0B70) /* MSTOP registerBUS_PERI_CPU */ +#define CPG_BUS_PERI_DDR_MSTOP (CPG_BASE + 0x0B74) /* MSTOP registerBUS_PERI_DDR */ +#define CPG_BUS_PERI_VIDEO_MSTOP (CPG_BASE + 0x0B78) /* MSTOP registerBUS_PERI_VIDEO */ +#define CPG_BUS_REG0_MSTOP (CPG_BASE + 0x0B7C) /* MSTOP registerBUS_REG0 */ +#define CPG_BUS_REG1_MSTOP (CPG_BASE + 0x0B80) /* MSTOP registerBUS_REG1 */ +#define CPG_BUS_TZCDDR_MSTOP (CPG_BASE + 0x0B84) /* MSTOP registerBUS_TZCDDR */ +#define CPG_MHU_MSTOP (CPG_BASE + 0x0B88) /* MSTOP registerMHU */ +#define CPG_BUS_PERI_STP_MSTOP (CPG_BASE + 0x0B8C) /* MSTOP registerBUS_PERI_STP */ +#define CPG_BUS_MCPU3_MSTOP (CPG_BASE + 0x0B90) /* MSTOP register BUS_MCPU3 */ + +#define CPG_OTHERFUNC1_REG (CPG_BASE + 0x0BE8) /* Other function registers1 */ +#define CPG_OTHERFUNC2_REG (CPG_BASE + 0x0BEC) /* Other function registers2 */ + +#define PLL1_STBY_RESETB (1 << 0) +#define PLL1_STBY_SSC_EN (1 << 2) +#define PLL1_STBY_SSC_MODE0 (1 << 4) +#define PLL1_STBY_SSC_MODE1 (1 << 5) +#define PLL1_STBY_RESETB_WEN (1 << 16) +#define PLL1_STBY_SSC_EN_WEN (1 << 18) +#define PLL1_STBY_SSC_MODE_WEN (1 << 20) +#define PLL1_CLK1_DIV_P_24M (1 << 0) +#define PLL1_CLK1_DIV_P_12M (2 << 0) +#define PLL1_CLK1_DIV_P_8M (3 << 0) +#define PLL1_CLK1_DIV_P_6M (4 << 0) +#define PLL1_CLK2_DIV_S_RATIO1 (0 << 0) +#define PLL1_CLK2_DIV_S_RATIO2 (1 << 0) +#define PLL1_CLK2_DIV_S_RATIO4 (2 << 0) +#define PLL1_CLK2_DIV_S_RATIO8 (3 << 0) +#define PLL1_CLK2_DIV_S_RATIO16 (4 << 0) +#define PLL1_CLK2_DIV_S_RATIO32 (5 << 0) +#define PLL1_CLK2_DIV_S_RATIO64 (6 << 0) +#define PLL1_MON_PLL1_RESETB (1 << 0) +#define PLL1_MON_PLL1_LOCK (1 << 4) +#define PLL4_STBY_RESETB (1 << 0) +#define PLL4_STBY_SSC_EN (1 << 2) +#define PLL4_STBY_SSC_MODE0 (1 << 4) +#define PLL4_STBY_SSC_MODE1 (1 << 5) +#define PLL4_STBY_RESETB_WEN (1 << 16) +#define PLL4_STBY_SSC_EN_WEN (1 << 18) +#define PLL4_STBY_SSC_MODE_WEN (1 << 20) +#define PLL4_CLK1_DIV_P_24M (1 << 0) +#define PLL4_CLK1_DIV_P_12M (2 << 0) +#define PLL4_CLK1_DIV_P_8M (3 << 0) +#define PLL4_CLK1_DIV_P_6M (4 << 0) +#define PLL4_CLK2_DIV_S_RATIO1 (0 << 0) +#define PLL4_CLK2_DIV_S_RATIO2 (1 << 0) +#define PLL4_CLK2_DIV_S_RATIO4 (2 << 0) +#define PLL4_CLK2_DIV_S_RATIO8 (3 << 0) +#define PLL4_CLK2_DIV_S_RATIO16 (4 << 0) +#define PLL4_CLK2_DIV_S_RATIO32 (5 << 0) +#define PLL4_CLK2_DIV_S_RATIO64 (6 << 0) +#define PLL4_MON_PLL4_RESETB (1 << 0) +#define PLL4_MON_PLL4_LOCK (1 << 4) +#define PLL6_STBY_RESETB (1 << 0) +#define PLL6_STBY_SSC_EN (1 << 2) +#define PLL6_STBY_SSC_MODE0 (1 << 4) +#define PLL6_STBY_SSC_MODE1 (1 << 5) +#define PLL6_STBY_RESETB_WEN (1 << 16) +#define PLL6_STBY_SSC_EN_WEN (1 << 18) +#define PLL6_STBY_SSC_MODE_WEN (1 << 20) +#define PLL6_CLK1_DIV_P_24M (1 << 0) +#define PLL6_CLK1_DIV_P_12M (2 << 0) +#define PLL6_CLK1_DIV_P_8M (3 << 0) +#define PLL6_CLK1_DIV_P_6M (4 << 0) +#define PLL6_CLK2_DIV_S_RATIO1 (0 << 0) +#define PLL6_CLK2_DIV_S_RATIO2 (1 << 0) +#define PLL6_CLK2_DIV_S_RATIO4 (2 << 0) +#define PLL6_CLK2_DIV_S_RATIO8 (3 << 0) +#define PLL6_CLK2_DIV_S_RATIO16 (4 << 0) +#define PLL6_CLK2_DIV_S_RATIO32 (5 << 0) +#define PLL6_CLK2_DIV_S_RATIO64 (6 << 0) +#define PLL6_MON_PLL6_RESETB (1 << 0) +#define PLL6_MON_PLL6_LOCK (1 << 4) +#define PLL1_SETTING_SEL_PLL1 (1 << 0) +#define PLL1_SETTING_SEL_PLL1_WEN (1 << 16) +#define PLL_CLK_DIV_M_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 6)))) +#define PLL_CLK_DIV_K_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) +#define PLL_CLK_MRR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) +#define PLL_CLK_MFR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) + +#define PLL2_STBY_RESETB (1 << 0) +#define PLL2_STBY_SSC_EN (1 << 2) +#define PLL2_STBY_DOWNSPREAD (1 << 4) +#define PLL2_STBY_RESETB_WEN (1 << 16) +#define PLL2_STBY_SSC_EN_WEN (1 << 18) +#define PLL2_STBY_DOWNSPREAD_WEN (1 << 20) +#define PLL2_CLK1_POSTDIV1_WEN (1 << 16) +#define PLL2_CLK1_POSTDIV2_WEN (1 << 20) +#define PLL2_CLK1_REFDIV_WEN (1 << 24) +#define PLL2_CLK2_DACPD (1 << 0) +#define PLL2_CLK2_DSMPD (1 << 2) +#define PLL2_CLK2_FOUT4PHASEPD (1 << 4) +#define PLL2_CLK2_FOUTPOSTDIVPD (1 << 6) +#define PLL2_CLK2_FOUTVCOPD (1 << 8) +#define PLL2_CLK2_DACPD_WEN (1 << 16) +#define PLL2_CLK2_DSMPD_WEN (1 << 18) +#define PLL2_CLK2_FOUT4PHASEPD_WEN (1 << 20) +#define PLL2_CLK2_FOUTPOSTDIVPD_WEN (1 << 22) +#define PLL2_CLK2_FOUTVCOPD_WEN (1 << 24) +#define PLL2_CLK6_SEL_EXTWAVE (1 << 0) +#define PLL2_CLK6_SEL_EXTWAVE_WEN (1 << 16) +#define PLL2_MON_PLL2_RESETB (1 << 0) +#define PLL2_MON_PLL2_LOCK (1 << 4) +#define PLL3_STBY_RESETB (1 << 0) +#define PLL3_STBY_SSC_EN (1 << 2) +#define PLL3_STBY_DOWNSPREAD (1 << 4) +#define PLL3_STBY_RESETB_WEN (1 << 16) +#define PLL3_STBY_SSC_EN_WEN (1 << 18) +#define PLL3_STBY_DOWNSPREAD_WEN (1 << 20) +#define PLL3_CLK1_POSTDIV1_WEN (1 << 16) +#define PLL3_CLK1_POSTDIV2_WEN (1 << 20) +#define PLL3_CLK1_REFDIV_WEN (1 << 24) +#define PLL3_CLK2_DACPD (1 << 0) +#define PLL3_CLK2_DSMPD (1 << 2) +#define PLL3_CLK2_FOUT4PHASEPD (1 << 4) +#define PLL3_CLK2_FOUTPOSTDIVPD (1 << 6) +#define PLL3_CLK2_FOUTVCOPD (1 << 8) +#define PLL3_CLK2_DACPD_WEN (1 << 16) +#define PLL3_CLK2_DSMPD_WEN (1 << 18) +#define PLL3_CLK2_FOUT4PHASEPD_WEN (1 << 20) +#define PLL3_CLK2_FOUTPOSTDIVPD_WEN (1 << 22) +#define PLL3_CLK2_FOUTVCOPD_WEN (1 << 24) +#define PLL3_CLK6_SEL_EXTWAVE (1 << 0) +#define PLL3_CLK6_SEL_EXTWAVE_WEN (1 << 16) +#define PLL3_MON_PLL3_RESETB (1 << 0) +#define PLL3_MON_PLL3_LOCK (1 << 4) +#define PLL5_STBY_RESETB (1 << 0) +#define PLL5_STBY_SSC_EN (1 << 2) +#define PLL5_STBY_DOWNSPREAD (1 << 4) +#define PLL5_STBY_RESETB_WEN (1 << 16) +#define PLL5_STBY_SSC_EN_WEN (1 << 18) +#define PLL5_STBY_DOWNSPREAD_WEN (1 << 20) +#define PLL5_CLK1_POSTDIV1_WEN (1 << 16) +#define PLL5_CLK1_POSTDIV2_WEN (1 << 20) +#define PLL5_CLK1_REFDIV_WEN (1 << 24) +#define PLL5_CLK2_DACPD (1 << 0) +#define PLL5_CLK2_DSMPD (1 << 2) +#define PLL5_CLK2_FOUT4PHASEPD (1 << 4) +#define PLL5_CLK2_FOUTPOSTDIVPD (1 << 6) +#define PLL5_CLK2_FOUTVCOPD (1 << 8) +#define PLL5_CLK2_DACPD_WEN (1 << 16) +#define PLL5_CLK2_DSMPD_WEN (1 << 18) +#define PLL5_CLK2_FOUT4PHASEPD_WEN (1 << 20) +#define PLL5_CLK2_FOUTPOSTDIVPD_WEN (1 << 22) +#define PLL5_CLK2_FOUTVCOPD_WEN (1 << 24) +#define PLL5_CLK6_SEL_EXTWAVE (1 << 0) +#define PLL5_CLK6_SEL_EXTWAVE_WEN (1 << 16) +#define PLL5_MON_PLL5_RESETB (1 << 0) +#define PLL5_MON_PLL5_LOCK (1 << 4) + +#define PLL_CLK_POSTDIV1_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) +#define PLL_CLK_POSTDIV2_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 4)))) +#define PLL_CLK_REFDIV_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) +#define PLL_CLK_DIVVAL_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) +#define PLL_CLK_FRACIN_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) +#define PLL_CLK_EXT_MAXADDR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) +#define PLL_CLK_INITIN_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) +#define PLL_CLK_SPREAD_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) + +#define PL1_DDIV_DIVPL1_SET_1_1 (0 << 0) +#define PL1_DDIV_DIVPL1_SET_1_2 (1 << 0) +#define PL1_DDIV_DIVPL1_SET_1_4 (2 << 0) +#define PL1_DDIV_DIVPL1_SET_1_8 (3 << 0) +#define PL1_DDIV_DIVPL1_SET_WEN (1 << 16) +#define PL2_DDIV_DIVPL2A_SET_1_1 (0 << 0) +#define PL2_DDIV_DIVPL2A_SET_1_2 (1 << 0) +#define PL2_DDIV_DIVPL2A_SET_1_4 (2 << 0) +#define PL2_DDIV_DIVPL2A_SET_1_8 (3 << 0) +#define PL2_DDIV_DIVPL2A_SET_1_32 (4 << 0) +#define PL2_DDIV_DIVPL2B_SET_1_1 (0 << 4) +#define PL2_DDIV_DIVPL2B_SET_1_2 (1 << 4) +#define PL2_DDIV_DIVPL2B_SET_1_4 (2 << 4) +#define PL2_DDIV_DIVPL2B_SET_1_8 (3 << 4) +#define PL2_DDIV_DIVPL2B_SET_1_32 (4 << 4) +#define PL2_DDIV_DIVPL2C_SET_1_1 (0 << 8) +#define PL2_DDIV_DIVPL2C_SET_1_2 (1 << 8) +#define PL2_DDIV_DIVPL2C_SET_1_4 (2 << 8) +#define PL2_DDIV_DIVPL2C_SET_1_8 (3 << 8) +#define PL2_DDIV_DIVPL2C_SET_1_32 (4 << 8) +#define PL2_DDIV_DIVDSILPCLK_SET_1_16 (0 << 12) +#define PL2_DDIV_DIVDSILPCLK_SET_1_32 (1 << 12) +#define PL2_DDIV_DIVDSILPCLK_SET_1_64 (2 << 12) +#define PL2_DDIV_DIVDSILPCLK_SET_1_128 (3 << 12) +#define PL2_DDIV_DIVPL2A_WEN (1 << 16) +#define PL2_DDIV_DIVPL2B_WEN (1 << 20) +#define PL2_DDIV_DIVPL2C_WEN (1 << 24) +#define PL2_DDIV_DIVDSILPCLK_WEN (1 << 28) +#define PL3A_DDIV_DIVPL3A_SET_1_1 (0 << 0) +#define PL3A_DDIV_DIVPL3A_SET_1_2 (1 << 0) +#define PL3A_DDIV_DIVPL3A_SET_1_4 (2 << 0) +#define PL3A_DDIV_DIVPL3A_SET_1_8 (3 << 0) +#define PL3A_DDIV_DIVPL3A_SET_1_32 (4 << 0) +#define PL3A_DDIV_DIVPL3B_SET_1_1 (0 << 0) +#define PL3A_DDIV_DIVPL3B_SET_1_2 (1 << 0) +#define PL3A_DDIV_DIVPL3B_SET_1_4 (2 << 0) +#define PL3A_DDIV_DIVPL3B_SET_1_8 (3 << 0) +#define PL3A_DDIV_DIVPL3B_SET_1_32 (4 << 0) +#define PL3A_DDIV_DIVPL3C_SET_1_1 (0 << 0) +#define PL3A_DDIV_DIVPL3C_SET_1_2 (1 << 0) +#define PL3A_DDIV_DIVPL3C_SET_1_4 (2 << 0) +#define PL3A_DDIV_DIVPL3C_SET_1_8 (3 << 0) +#define PL3A_DDIV_DIVPL3C_SET_1_32 (4 << 0) +#define PL3A_DDIV_DIVPL3F_SET_1_1 (0 << 0) +#define PL3A_DDIV_DIVPL3F_SET_1_2 (1 << 0) +#define PL3A_DDIV_DIVPL3F_SET_1_4 (2 << 0) +#define PL3A_DDIV_DIVPL3F_SET_1_8 (3 << 0) +#define PL3A_DDIV_DIVPL3F_SET_1_32 (4 << 0) +#define PL3A_DDIV_DIVPL3A_WEN (1 << 16) +#define PL3A_DDIV_DIVPL3B_WEN (1 << 20) +#define PL3A_DDIV_DIVPL3C_WEN (1 << 24) +#define PL3A_DDIV_DIVPL3F_WEN (1 << 28) +#define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_1 (0 << 0) +#define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_2 (1 << 0) +#define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_4 (2 << 0) +#define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_8 (3 << 0) +#define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_32 (4 << 0) +#define PL3B_DDIV_DIVPL3CLK200FIX_WEN (1 << 16) +#define PL6_DDIV_DIVGPU_SET_1_1 (0 << 0) +#define PL6_DDIV_DIVGPU_SET_1_2 (1 << 0) +#define PL6_DDIV_DIVGPU_SET_1_4 (2 << 0) +#define PL6_DDIV_DIVGPU_SET_1_8 (3 << 0) +#define PL6_DDIV_DIVGPU_WEN (1 << 16) +#define PL2SDHI_DSEL_SEL_SDHI0_SET_CLK533FIX_C (1 << 0) +#define PL2SDHI_DSEL_SEL_SDHI0_SET_DIV_PLL2_DIV8 (2 << 0) +#define PL2SDHI_DSEL_SEL_SDHI0_SET_DIV_PLL2_DIV12 (3 << 0) +#define PL2SDHI_DSEL_SEL_SDHI1_SET_CLK533FIX_C (1 << 4) +#define PL2SDHI_DSEL_SEL_SDHI1_SET_DIV_PLL2_DIV8 (2 << 4) +#define PL2SDHI_DSEL_SEL_SDHI1_SET_DIV_PLL2_DIV12 (3 << 4) +#define PL2SDHI_DSEL_SEL_SDHI0_WEN (1 << 16) +#define PL2SDHI_DSEL_SEL_SDHI1_WEN (1 << 20) +#define PL4_DSEL_SEL_PLL4_SET (1 << 0) +#define PL4_DSEL_SEL_PLL4_WEN (1 << 16) +#define CLKSTATUS_DIVPL1_STS (1 << 0) +#define CLKSTATUS_DIVPL2A_STS (1 << 4) +#define CLKSTATUS_DIVPL2B_STS (1 << 5) +#define CLKSTATUS_DIVPL2C_STS (1 << 6) +#define CLKSTATUS_DIVDSILPCLK_STS (1 << 7) +#define CLKSTATUS_DIVPL3A_STS (1 << 8) +#define CLKSTATUS_DIVPL3B_STS (1 << 9) +#define CLKSTATUS_DIVPL3C_STS (1 << 10) +#define CLKSTATUS_DIVPL3CLK200FIX_STS (1 << 11) +#define CLKSTATUS_DIVPL3F_STS (1 << 12) +#define CLKSTATUS_DIVGPU_STS (1 << 20) +#define CLKSTATUS_SELSDHI0_STS (1 << 28) +#define CLKSTATUS_SELSDHI1_STS (1 << 29) +#define CLKSTATUS_SELPLL4_STS (1 << 31) +#define PL1_CA55_SSEL_SEL_PLL1_SET (1 << 0) +#define PL1_CA55_SSEL_SEL_PLL1_WEN (1 << 16) +#define PL2_SSEL_SEL_PLL2_1_SET (1 << 0) +#define PL2_SSEL_SEL_PLL2_2_SET (1 << 4) +#define PL2_SSEL_SEL_PLL2_1_WEN (1 << 16) +#define PL2_SSEL_SEL_PLL2_2_WEN (1 << 20) +#define PL3_SSEL_SEL_PLL3_1_SET (1 << 0) +#define PL3_SSEL_SEL_PLL3_2_SET (1 << 4) +#define PL3_SSEL_SEL_PLL3_3_SET (1 << 8) +#define PL3_SSEL_SEL_PLL3_5_SET (1 << 12) +#define PL3_SSEL_SEL_PLL3_1_WEN (1 << 16) +#define PL3_SSEL_SEL_PLL3_2_WEN (1 << 20) +#define PL3_SSEL_SEL_PLL3_3_WEN (1 << 24) +#define PL3_SSEL_SEL_PLL3_5_WEN (1 << 28) +#define PL5_SSEL_SEL_PLL5_1_SET (1 << 0) +#define PL5_SSEL_SEL_PLL5_2_SET (1 << 4) +#define PL5_SSEL_SEL_PLL5_1_WEN (1 << 16) +#define PL5_SSEL_SEL_PLL5_2_WEN (1 << 20) +#define PL6_SSEL_SEL_PLL6_1_SET (1 << 0) +#define PL6_SSEL_SEL_GPU1_1_SET (1 << 4) +#define PL6_SSEL_SEL_GPU1_2_SET (1 << 8) +#define PL6_SSEL_SEL_GPU2_SET (1 << 12) +#define PL6_SSEL_SEL_PLL6_1_WEN (1 << 16) +#define PL6_SSEL_SEL_GPU1_1_WEN (1 << 20) +#define PL6_SSEL_SEL_GPU1_2_WEN (1 << 24) +#define PL6_SSEL_SEL_GPU2_WEN (1 << 28) +#define PL6_ETH_SSEL_SEL_PLL6_2_SET (1 << 0) +#define PL6_ETH_SSEL_SEL_ETH_SET (1 << 4) +#define PL6_ETH_SSEL_SEL_PLL6_2_WEN (1 << 16) +#define PL6_ETH_SSEL_SEL_ETH_WEN (1 << 20) +#define PL5_SDIV_DIVDSIA_SET_1_1 (0 << 0) +#define PL5_SDIV_DIVDSIA_SET_1_2 (1 << 0) +#define PL5_SDIV_DIVDSIA_SET_1_4 (2 << 0) +#define PL5_SDIV_DIVDSIA_SET_1_8 (3 << 0) +#define PL5_SDIV_DIVDSIB_SET_1_1 (0 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_2 (1 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_3 (2 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_4 (3 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_5 (4 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_6 (5 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_7 (6 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_8 (7 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_9 (8 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_10 (9 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_11 (10 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_12 (11 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_13 (12 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_14 (13 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_15 (14 << 8) +#define PL5_SDIV_DIVDSIB_SET_1_16 (15 << 8) +#define PL5_SDIV_DIVDSA_WEN (1 << 16) +#define PL5_SDIV_DIVSDIB_WEN (1 << 24) +#define CLKON_CLK0_ON (1 << 0) +#define CLKON_CLK0_ON_WEN (1 << 16) +#define CLKMON_UNIT0_CLK_MON (1 << 0) +#define RST_UNIT0_RSTB (1 << 0) +#define RST_UNIT0_RST_WEN (1 << 16) +#define RSTMON_UNIT0_RST_MON (1 << 0) +#define EN_OSTM_EN0_ON (1 << 0) +#define EN_OSTM_EN1_ON (1 << 1) +#define EN_OSTM_EN2_ON (1 << 2) +#define EN_OSTM_EN0_WEN (1 << 16) +#define EN_OSTM_EN1_WEN (1 << 17) +#define EN_OSTM_EN2_WEN (1 << 18) +#define WDTOVF_RST_WDTOVF0 (1 << 0) +#define WDTOVF_RST_WDTOVF1 (1 << 1) +#define WDTOVF_RST_WDTOVF2 (1 << 2) +#define WDTOVF_RST_WDTOVF3 (1 << 3) +#define WDTOVF_RST_WDTOVF0_WEN (1 << 16) +#define WDTOVF_RST_WDTOVF1_WEN (1 << 17) +#define WDTOVF_RST_WDTOVF2_WEN (1 << 18) +#define WDTOVF_RST_WDTOVF3_WEN (1 << 19) +#define WDTRST_SEL_WDTRSTSEL0 (1 << 0) +#define WDTRST_SEL_WDTRSTSEL1 (1 << 1) +#define WDTRST_SEL_WDTRSTSEL2 (1 << 2) +#define WDTRST_SEL_WDTRSTSEL3 (1 << 3) +#define WDTRST_SEL_WDTRSTSEL4 (1 << 4) +#define WDTRST_SEL_WDTRSTSEL5 (1 << 5) +#define WDTRST_SEL_WDTRSTSEL6 (1 << 6) +#define WDTRST_SEL_WDTRSTSEL7 (1 << 7) +#define WDTRST_SEL_WDTRSTSEL8 (1 << 8) +#define WDTRST_SEL_WDTRSTSEL9 (1 << 9) +#define WDTRST_SEL_WDTRSTSEL10 (1 << 10) +#define WDTRST_SEL_WDTRSTSEL0_WEN (1 << 16) +#define WDTRST_SEL_WDTRSTSEL1_WEN (1 << 17) +#define WDTRST_SEL_WDTRSTSEL2_WEN (1 << 18) +#define WDTRST_SEL_WDTRSTSEL3_WEN (1 << 19) +#define WDTRST_SEL_WDTRSTSEL4_WEN (1 << 20) +#define WDTRST_SEL_WDTRSTSEL5_WEN (1 << 21) +#define WDTRST_SEL_WDTRSTSEL6_WEN (1 << 22) +#define WDTRST_SEL_WDTRSTSEL7_WEN (1 << 23) +#define WDTRST_SEL_WDTRSTSEL8_WEN (1 << 24) +#define WDTRST_SEL_WDTRSTSEL9_WEN (1 << 25) +#define WDTRST_SEL_WDTRSTSEL10_WEN (1 << 26) +#define DBGRST_UNIT0_RSTB (1 << 0) +#define DBGRST_UNIT0_RST_WEN (1 << 16) +#define CLUSTER_PCHMON_PACCEPT_MON (1 << 0) +#define CLUSTER_PCHMON_PDENY_MON (1 << 1) +#define CLUSTER_PCHCTL_PREQ_SET (1 << 0) +#define CLUSTER_PCHCTL_PSTATE0_SET_ON (0x48 << 16) +#define CLUSTER_PCHCTL_PSTATE0_SET_OFF (0x00 << 16) +#define CORE0_PCHMON_PACCEPT0_MON (1 << 0) +#define CORE0_PCHMON_PDENY0_MON (1 << 1) +#define CORE0_PCHCTL_PREQ0_SET (1 << 0) +#define CORE0_PCHCTL_PSTATE0_SET_ON (0x08 << 16) +#define CORE0_PCHCTL_PSTATE0_SET_OFF_EMULATED (0x01 << 16) +#define CORE0_PCHCTL_PSTATE0_SET_OFF (0x00 << 16) +#define CORE1_PCHMON_PACCEPT1_MON (1 << 0) +#define CORE1_PCHMON_PDENY1_MON (1 << 1) +#define CORE1_PCHCTL_PREQ1_SET (1 << 0) +#define CORE1_PCHCTL_PSTATE1_SET_ON (0x08 << 16) +#define CORE1_PCHCTL_PSTATE1_SET_OFF_EMULATED (0x01 << 16) +#define CORE1_PCHCTL_PSTATE1_SET_OFF (0x00 << 16) +#define BUS_MSTOP_MSTOPMODE_SET (1 << 0) +#define BUS_MSTOP_MSTOPMODE_SET_WEN (1 << 16) +#define OTHERFUNC1_REG_RES0_SET (1 << 0) +#define OTHERFUNC1_REG_RES0_ON_WEN (1 << 16) +#define OTHERFUNC2_REG_RES0_SET (1 << 0) +#define OTHERFUNC2_REG_RES0_ON_WEN (1 << 16) + +#define BIT0_ON (1 << 0) +#define BIT1_ON (1 << 1) +#define BIT2_ON (1 << 2) +#define BIT3_ON (1 << 3) +#define BIT4_ON (1 << 4) +#define BIT5_ON (1 << 5) +#define BIT6_ON (1 << 6) +#define BIT7_ON (1 << 7) +#define BIT8_ON (1 << 8) +#define BIT9_ON (1 << 9) +#define BIT10_ON (1 << 10) +#define BIT11_ON (1 << 11) +#define BIT12_ON (1 << 12) +#define BIT13_ON (1 << 13) +#define BIT14_ON (1 << 14) +#define BIT15_ON (1 << 15) +#define BIT16_ON (1 << 16) +#define BIT17_ON (1 << 17) +#define BIT18_ON (1 << 18) +#define BIT19_ON (1 << 19) +#define BIT20_ON (1 << 20) +#define BIT21_ON (1 << 21) +#define BIT22_ON (1 << 22) +#define BIT23_ON (1 << 23) +#define BIT24_ON (1 << 24) +#define BIT25_ON (1 << 25) +#define BIT26_ON (1 << 26) +#define BIT27_ON (1 << 27) +#define BIT28_ON (1 << 28) +#define BIT29_ON (1 << 29) +#define BIT30_ON (1 << 30) +#define BIT31_ON (1 << 31) + +#endif /* __CPG_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/ddr.h b/plat/renesas/rza/common/include/ddr.h new file mode 100644 index 0000000000..c60653a288 --- /dev/null +++ b/plat/renesas/rza/common/include/ddr.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +void ddr_setup(void); + +#endif /* __DDR_H__ */ diff --git a/plat/renesas/rza/common/include/ddr_internal.h b/plat/renesas/rza/common/include/ddr_internal.h new file mode 100644 index 0000000000..7dca21c49a --- /dev/null +++ b/plat/renesas/rza/common/include/ddr_internal.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_INTERNAL_H__ +#define __DDR_INTERNAL_H__ + +#include +#include +#include + +#define MC_PHYSET_NUM (4) +#define SWIZZLE_MC_NUM (9) +#define SIZZLE_PHY_NUM (16) + +static inline uint32_t read_mc_reg(uint32_t offset) +{ + return mmio_read_32(DDR_MC_BASE + offset); +} + +static inline void write_mc_reg(uint32_t offset, uint32_t val) +{ + mmio_write_32(DDR_MC_BASE + offset, val); +} + +static inline void rmw_mc_reg(uint32_t offset, uint32_t mask, uint32_t val) +{ + write_mc_reg(offset, (read_mc_reg(offset) & mask) | val); +} + +static inline uint32_t read_phy_reg(uint32_t offset) +{ + return mmio_read_32(DDR_PHY_BASE + offset); +} + +static inline void write_phy_reg(uint32_t offset, uint32_t val) +{ + mmio_write_32(DDR_PHY_BASE + offset, val); +} + +static inline void rmw_phy_reg(uint32_t offset, uint32_t mask, uint32_t val) +{ + write_phy_reg(offset, (read_phy_reg(offset) & mask) | val); +} + +void ddr_ctrl_reten_en_n(uint8_t val); + + +#endif /* __DDR_INTERNAL_H__ */ diff --git a/plat/renesas/rza/common/include/drivers/auth/auth_common.h b/plat/renesas/rza/common/include/drivers/auth/auth_common.h new file mode 100644 index 0000000000..df240eef35 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/auth/auth_common.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AUTH_COMMON_H +#define AUTH_COMMON_H + +/* + * Authentication framework common types + */ + +/* + * Type of parameters that can be extracted from an image and + * used for authentication + */ +typedef enum auth_param_type_enum { + AUTH_PARAM_NONE, + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ + AUTH_PARAM_NV_CTR, /* A non-volatile counter */ +} auth_param_type_t; + +/* + * Defines an authentication parameter. The cookie will be interpreted by the + * image parser module. + */ +typedef struct auth_param_type_desc_s { + auth_param_type_t type; + void *cookie; +} auth_param_type_desc_t; + +/* + * Store a pointer to the authentication parameter and its length + */ +typedef struct auth_param_data_desc_s { + void *ptr; + unsigned int len; +} auth_param_data_desc_t; + +/* + * Authentication parameter descriptor, including type and value + */ +typedef struct auth_param_desc_s { + auth_param_type_desc_t *type_desc; + auth_param_data_desc_t data; +} auth_param_desc_t; + +/* + * The method type defines how an image is authenticated + */ +typedef enum auth_method_type_enum { + AUTH_METHOD_NONE = 0, + AUTH_METHOD_HASH, /* Authenticate by hash matching */ + AUTH_METHOD_SIG, /* Authenticate by PK operation */ + AUTH_METHOD_NV_CTR, /* Authenticate by Non-Volatile Counter */ + AUTH_METHOD_SBLIB, /* Authenticate by Renesas RZ/G2L SBLib */ + AUTH_METHOD_NUM /* Number of methods */ +} auth_method_type_t; + +/* + * Parameters for authentication by hash matching + */ +typedef struct auth_method_param_hash_s { + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ +} auth_method_param_hash_t; + +/* + * Parameters for authentication by signature + */ +typedef struct auth_method_param_sig_s { + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *data; /* Data signed */ +} auth_method_param_sig_t; + +/* + * Parameters for authentication by NV counter + */ +typedef struct auth_method_param_nv_ctr_s { + auth_param_type_desc_t *cert_nv_ctr; /* NV counter in certificate */ + auth_param_type_desc_t *plat_nv_ctr; /* NV counter in platform */ +} auth_method_param_nv_ctr_t; + +typedef struct auth_method_param_sblib_s { + auth_param_type_desc_t *data; + auth_param_type_desc_t *key_cert; + auth_param_type_desc_t *content_cert; +} auth_method_param_sblib_t; + +/* + * Authentication method descriptor + */ +typedef struct auth_method_desc_s { + auth_method_type_t type; + union { + auth_method_param_hash_t hash; + auth_method_param_sig_t sig; + auth_method_param_nv_ctr_t nv_ctr; + auth_method_param_sblib_t sblib; + } param; +} auth_method_desc_t; + +/* + * Helper macro to define an authentication parameter type descriptor + */ +#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \ + { \ + .type = _type, .cookie = (void *)_cookie \ + } + +/* + * Helper macro to define an authentication parameter data descriptor + */ +#define AUTH_PARAM_DATA_DESC(_ptr, _len) \ + { \ + .ptr = (void *)_ptr, .len = (unsigned int)_len \ + } + +#endif /* AUTH_COMMON_H */ diff --git a/plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h b/plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h new file mode 100644 index 0000000000..592de41470 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CRYPTO_SBLIB_H +#define CRYPTO_SBLIB_H + +void crypto_sblib_init(void); + +int crypto_sblib_auth(void *data_ptr, size_t len, const void *key_cert, + unsigned int key_cert_len, const void *content_cert, + unsigned int content_cert_len); + +#endif /* CRYPTO_SBLIB_H */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h b/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h new file mode 100644 index 0000000000..9d44841b98 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* Dialog AT25QL128A */ +#ifndef _SPI_MULTI_REG_VALUES_H_ +#define _SPI_MULTI_REG_VALUES_H_ +/* + * Selectable definitions + */ +/* In the case of addr width 24bit */ +#define SET_DRENR_ADE_VALUE DRENR_ADE_ADD23_OUT +#define SET_DREAR_EAC_VALUE DREAR_EAC_EXADDR24 + +/* In the case of bit width 1-4-4 and addr width 24bi */ +#define SET_DRCMR_CMD_VALUE DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B +#define SET_DRENR_ADB_VALUE DRENR_ADB_4BIT +#define SET_DRENR_DRDB_VALUE DRENR_DRDB_4BIT +#define SET_DRDMCR_VALUE SPI_MULTI_DUMMY_4CYCLE +#define SET_DRENR_SET_VALUE \ + (DRENR_CDB_1BIT | DRENR_OCDB_1BIT | SET_DRENR_ADB_VALUE | \ + DRENR_OPDB_1BIT | SET_DRENR_DRDB_VALUE | DRENR_CDE | DRENR_DME | \ + SET_DRENR_ADE_VALUE | DRENR_OPDB_4BIT | DRENR_OPDE_OPD3_OUT) + +/* SDR mode serial flash settings */ +#define SPIM_PHYCNT_SET_VALUE \ + (PHYCNT_DEF_DATA | PHYCNT_PHYMEM_SDR_MODE | PHYCNT_WBUF_NOT_USED | \ + PHYCNT_WBUF2_NOT_USED | PHYCNT_CKSEL_SLOW | PHYCNT_HS_OTHER_MODE | \ + PHYCNT_OCT_OTHER_MODE | PHYCNT_EXDS_NOT_USED | \ + PHYCNT_OCTA_HYPER_FLASH | PHYCNT_ALT_ALIGN_NOT_SUPPORTED | \ + PHYCNT_CAL_NOT_PERFOMED) +#define SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE \ + (SPIM_PHYCNT_SET_VALUE | PHYCNT_CKSEL_FAST) +/* Read timing setting */ +#define SPIM_PHYOFFSET1_SET_VALUE \ + (PHYOFFSET1_DEF_DATA | PHYOFFSET1_DDRTMG_SPIDRE_0) +#define SPIM_PHYOFFSET2_SET_VALUE \ + (PHYOFFSET2_DEF_DATA | PHYOFFSET2_OCTTMG_HYPER_FLASH) + +/* Set the QSPIn_SSL setting value */ +#define SPIM_CMNCR_EXTREAD_SET_VALUE \ + (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ + CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ + CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_EXT_READ) + +#define SPIM_CMNCR_MANUAL_SET_VALUE \ + (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ + CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ + CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_MANUAL) + +/* Set SSL delay setting value */ +#define SPIM_SSLDR_SET_VALUE \ + (SSLDR_SCKDL_4_5 | SSLDR_SLNDL_4QSPIn | SSLDR_SPNDL_4QSPIn) + +/* Set the RBE bit and RCF bit and RBURST */ +#define SPIM_DRCR_SET_VALUE (DRCR_RBE | DRCR_RCF | DRCR_RBURST_32_DATALEN) + +/* Set the data read command */ +#define SPIM_DRCMR_SET_VALUE (SET_DRCMR_CMD_VALUE) + +/* Extended external address setting */ +#define SPIM_DREAR_SET_VALUE (SET_DREAR_EAC_VALUE) + +/* Set the bit width of command and address output to 1 bit and */ +/* the address size to 4 byte */ +#define SPIM_DRENR_SET_VALUE (SET_DRENR_SET_VALUE) +/* Dummy cycle setting */ +#define SPIM_DRDMCR_SET_VALUE (SET_DRDMCR_VALUE) + +/* Change to SPI flash mode */ +#define SPIM_DRDRENR_SET_VALUE \ + (DRDRENR_DRDRE_SDR | DRDRENR_OPDRE_SDR | DRDRENR_ADDRE_SDR | \ + DRDRENR_HYPE_SPI) +/* Set the SDR transfer & SPI flash mode */ +#define SPIM_SMDRENR_SET_VALUE (SMDRENR_HYPE_SPI_FLASH) + +/* Set the option data */ +#define SPIM_DROPR_SET_VALUE (0) + +/* Manual Command */ +#define SMCMR_CMD_WRITE_ENABLE (0x06) +#define SMCMR_CMD_WRITE_STATUS_REGISTER_2 (0x31) +#define SMCMR_CMD_READ_STATUS_REGISTER_1 (0x05) +#define SMCMR_CMD_READ_STATUS_REGISTER_2 (0x35) +#define SMCMR_CMD_BIT_SHIFT (16) +#define SMWDR0_1BYTE_DATA_BIT_SHIFT (24) + +/* Manual Command Configure Length */ +#define SPI_MANUAL_COMMAND_SIZE_0 SMENR_SPIDE_NO_SEND +#define SPI_MANUAL_COMMAND_SIZE_8_BIT SMENR_SPIDE_8BIT_SEND +#define SPI_MANUAL_COMMAND_SIZE_16_BIT SMENR_SPIDE_16BIT_SEND +#define SPI_MANUAL_COMMAND_SIZE_32_BIT SMENR_SPIDE_32BIT_SEND +/* Read Status Register-1(05h) */ +#define STATUS_1_BUSY_BIT (1 << 0) +#define STATUS_1_WEL_BIT (1 << 1) +#define STATUS_1_BUSY (1 << 0) +#define STATUS_1_WEL (1 << 1) +/* Read Status Register-1(BUSY flag) read delay time(micro sec) */ +#define STATUS_BUSY_READ_DELAY_TIME (100) +/* Read Status Register-2(35h) */ +/* Write Status Register-2(31h) */ +#define STATUS_2_QE (1 << 1) + +#endif /* _SPI_MULTI_REG_VALUES_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h b/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h new file mode 100644 index 0000000000..3449a76be0 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* MICRON MT25QU512ABB */ +#ifndef _SPI_MULTI_REG_VALUES_H_ +#define _SPI_MULTI_REG_VALUES_H_ +/* + * Selectable definitions + */ + +/* In the case of addr width 24bit */ +#define SET_DRENR_ADE_VALUE DRENR_ADE_ADD23_OUT +#define SET_DREAR_EAC_VALUE DREAR_EAC_EXADDR24 + +/* In the case of bit width 1-4-4 and addr width 24bit */ +#define SET_DRCMR_CMD_VALUE DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B +#define SET_DRENR_ADB_VALUE DRENR_ADB_4BIT +#define SET_DRENR_DRDB_VALUE DRENR_DRDB_4BIT + +/* dummy cycle SPI_MULTI_DUMMY_1CYCLE - SPI_MULTI_DUMMY_20CYCLE */ +#define SET_DRDMCR_VALUE SPI_MULTI_DUMMY_10CYCLE + +/* SDR mode serial flash settings */ +#define SPIM_PHYCNT_SET_VALUE \ + (PHYCNT_DEF_DATA | PHYCNT_PHYMEM_SDR_MODE | PHYCNT_WBUF_NOT_USED | \ + PHYCNT_WBUF2_NOT_USED | PHYCNT_CKSEL_SLOW | PHYCNT_HS_OTHER_MODE | \ + PHYCNT_OCT_OTHER_MODE | PHYCNT_EXDS_NOT_USED | \ + PHYCNT_OCTA_HYPER_FLASH | PHYCNT_ALT_ALIGN_NOT_SUPPORTED | \ + PHYCNT_CAL_NOT_PERFOMED) +#define SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE \ + (SPIM_PHYCNT_SET_VALUE | PHYCNT_CKSEL_FAST) + +/* Read timing setting */ +#define SPIM_PHYOFFSET1_SET_VALUE \ + (PHYOFFSET1_DEF_DATA | PHYOFFSET1_DDRTMG_SPIDRE_0) +#define SPIM_PHYOFFSET2_SET_VALUE \ + (PHYOFFSET2_DEF_DATA | PHYOFFSET2_OCTTMG_HYPER_FLASH) + +/* Set the QSPIn_SSL setting value */ +#define SPIM_CMNCR_EXTREAD_SET_VALUE \ + (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ + CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ + CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_EXT_READ) + +#define SPIM_CMNCR_MANUAL_SET_VALUE \ + (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ + CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ + CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_MANUAL) +/* Set SSL delay setting value */ +#define SPIM_SSLDR_SET_VALUE \ + (SSLDR_SCKDL_4_5 | SSLDR_SLNDL_4QSPIn | SSLDR_SPNDL_4QSPIn) + +/* Set the RBE bit and RCF bit and RBURST */ +#define SPIM_DRCR_SET_VALUE (DRCR_RBE | DRCR_RCF | DRCR_RBURST_32_DATALEN) + +/* Set the data read command */ +#define SPIM_DRCMR_SET_VALUE (SET_DRCMR_CMD_VALUE) + +/* Extended external address setting */ +#define SPIM_DREAR_SET_VALUE (SET_DREAR_EAC_VALUE) + +/* Set the bit width of command and address output to 1 bit and */ +/* the address size to 4 byte */ +#define SPIM_DRENR_SET_VALUE \ + (DRENR_CDB_1BIT | DRENR_OCDB_1BIT | SET_DRENR_ADB_VALUE | \ + DRENR_OPDB_1BIT | SET_DRENR_DRDB_VALUE | DRENR_CDE | DRENR_DME | \ + SET_DRENR_ADE_VALUE | DRENR_OPDE_NO_OUT) +/* Dummy cycle setting */ +#define SPIM_DRDMCR_SET_VALUE (SET_DRDMCR_VALUE) + +/* Change to SPI flash mode */ +#define SPIM_DRDRENR_SET_VALUE \ + (DRDRENR_DRDRE_SDR | DRDRENR_OPDRE_SDR | DRDRENR_ADDRE_SDR | \ + DRDRENR_HYPE_SPI) +/* Set the SDR transfer & SPI flash mode */ +#define SPIM_SMDRENR_SET_VALUE (SMDRENR_HYPE_SPI_FLASH) +/* Manual Command */ +#define SMCMR_CMD_READ_STATUS_REGISTER (0x05) +#define SMCMR_CMD_BIT_SHIFT (16) +#define SMWDR0_1BYTE_DATA_BIT_SHIFT (24) + +/* Manual Command Configure Length */ +#define SPI_MANUAL_COMMAND_SIZE_0 SMENR_SPIDE_NO_SEND +#define SPI_MANUAL_COMMAND_SIZE_8_BIT SMENR_SPIDE_8BIT_SEND +#define SPI_MANUAL_COMMAND_SIZE_16_BIT SMENR_SPIDE_16BIT_SEND +#define SPI_MANUAL_COMMAND_SIZE_32_BIT SMENR_SPIDE_32BIT_SEND + +#endif /* _SPI_MULTI_REG_VALUES_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h new file mode 100644 index 0000000000..03f5101459 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SPI_MULTI_H_ +#define _SPI_MULTI_H_ + +#define SPI_MULTI_ADDR_WIDES_24 (0) +#define SPI_MULTI_ADDR_WIDES_32 (1) + +#define SPI_MULTI_DQ_WIDES_1_1_1 (0) +#define SPI_MULTI_DQ_WIDES_1_1_4 (1) +#define SPI_MULTI_DQ_WIDES_1_4_4 (2) + +#define SPI_MULTI_DUMMY_2CYCLE (1) +#define SPI_MULTI_DUMMY_3CYCLE (2) +#define SPI_MULTI_DUMMY_4CYCLE (3) +#define SPI_MULTI_DUMMY_5CYCLE (4) +#define SPI_MULTI_DUMMY_6CYCLE (5) +#define SPI_MULTI_DUMMY_7CYCLE (6) +#define SPI_MULTI_DUMMY_8CYCLE (7) +#define SPI_MULTI_DUMMY_9CYCLE (8) +#define SPI_MULTI_DUMMY_10CYCLE (9) +#define SPI_MULTI_DUMMY_11CYCLE (10) +#define SPI_MULTI_DUMMY_12CYCLE (11) +#define SPI_MULTI_DUMMY_13CYCLE (12) +#define SPI_MULTI_DUMMY_14CYCLE (13) +#define SPI_MULTI_DUMMY_15CYCLE (14) +#define SPI_MULTI_DUMMY_16CYCLE (15) +#define SPI_MULTI_DUMMY_17CYCLE (16) +#define SPI_MULTI_DUMMY_18CYCLE (17) +#define SPI_MULTI_DUMMY_19CYCLE (18) +#define SPI_MULTI_DUMMY_20CYCLE (19) + +#define SPI_MULTI_SUCCESS (0) +#define SPI_MULTI_ERROR (-1) + +int spi_multi_setup(void); +void spi_multi_setup_device(void); +void spi_multi_timing_set(void); +uint8_t spi_multi_cmd_read(uint8_t command); +void spi_multi_cmd_write(uint8_t command, uint8_t size, uint32_t data); + +#endif /* _SPI_MULTI_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h new file mode 100644 index 0000000000..7e18d3a7a4 --- /dev/null +++ b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SPI_MULTI_REG_H_ +#define _SPI_MULTI_REG_H_ + +#define SPI_MULTI_BASE (0x10060000) +#define SPI_MULTI_BUF (0x10070000) + +#define SPIM_CMNCR (SPI_MULTI_BASE + 0x00000000) /* Common control register */ +#define SPIM_SSLDR (SPI_MULTI_BASE + 0x00000004) /* SSL delay register */ +#define SPIM_DRCR (SPI_MULTI_BASE + 0x0000000C) /* Data read control register */ +#define SPIM_DRCMR (SPI_MULTI_BASE + 0x00000010) /* Data read command setting register */ +#define SPIM_DREAR (SPI_MULTI_BASE + 0x00000014) /* Data read extended address setting register */ +#define SPIM_DROPR (SPI_MULTI_BASE + 0x00000018) /* Data read option setting register */ +#define SPIM_DRENR (SPI_MULTI_BASE + 0x0000001C) /* Data read enable setting register */ +#define SPIM_SMCR (SPI_MULTI_BASE + 0x00000020) /* Manual mode control register */ +#define SPIM_SMCMR (SPI_MULTI_BASE + 0x00000024) /* Manual mode command setting register */ +#define SPIM_SMADR (SPI_MULTI_BASE + 0x00000028) /* Manual mode address setting register */ +#define SPIM_SMOPR (SPI_MULTI_BASE + 0x0000002C) /* Manual mode option setting register */ +#define SPIM_SMENR (SPI_MULTI_BASE + 0x00000030) /* Manual mode enable setting register */ +#define SPIM_SMRDR0 (SPI_MULTI_BASE + 0x00000038) /* Manual mode read data register 0 */ +#define SPIM_SMRDR1 (SPI_MULTI_BASE + 0x0000003C) /* Manual mode read data register 1 */ +#define SPIM_SMWDR0 (SPI_MULTI_BASE + 0x00000040) /* Manual mode write data register 0 */ +#define SPIM_SMWDR1 (SPI_MULTI_BASE + 0x00000044) /* Manual mode write data register 1 */ +#define SPIM_CMNSR (SPI_MULTI_BASE + 0x00000048) /* Common status register */ +#define SPIM_DRDMCR (SPI_MULTI_BASE + 0x00000058) /* Data read dummy cycle setting register */ +#define SPIM_DRDRENR (SPI_MULTI_BASE + 0x0000005C) /* Data read DDR enable register */ +#define SPIM_SMDMCR (SPI_MULTI_BASE + 0x00000060) /* Manual mode dummy cycle setting register */ +#define SPIM_SMDRENR (SPI_MULTI_BASE + 0x00000064) /* Manual mode DDR enable register */ +#define SPIM_PHYCNT (SPI_MULTI_BASE + 0x0000007C) /* PHY control register */ +#define SPIM_PHYOFFSET1 (SPI_MULTI_BASE + 0x00000080) /* PHY offset register 1 */ +#define SPIM_PHYOFFSET2 (SPI_MULTI_BASE + 0x00000084) /* PHY offset register 2 */ +#define SPIM_PHYINT (SPI_MULTI_BASE + 0x00000088) /* PHY interrupt register */ +#define SPIM_PHYADJ1 (SPI_MULTI_BASE + 0x00000070) /* PHY adjustment register 1 */ +#define SPIM_PHYADJ2 (SPI_MULTI_BASE + 0x00000074) /* PHY adjustment register 2 */ + +#define CMNCR_BSZ_FLASH_NUM_1 (0 << 0) +#define CMNCR_BSZ_FLASH_NUM_2 (1 << 0) +#define CMNCR_IO0FV_OUT0 (0 << 8) +#define CMNCR_IO0FV_OUT1 (1 << 8) +#define CMNCR_IO0FV_OUT_PREV (2 << 8) +#define CMNCR_IO0FV_HIZ (3 << 8) +#define CMNCR_IO2FV_OUT0 (0 << 12) +#define CMNCR_IO2FV_OUT1 (1 << 12) +#define CMNCR_IO2FV_OUT_PREV (2 << 12) +#define CMNCR_IO2FV_HIZ (3 << 12) +#define CMNCR_IO3FV_OUT0 (0 << 14) +#define CMNCR_IO3FV_OUT1 (1 << 14) +#define CMNCR_IO3FV_OUT_PREV (2 << 14) +#define CMNCR_IO3FV_HIZ (3 << 14) +#define CMNCR_DEF_DATA (1 << 24) +#define CMNCR_MOIIO0_OUT0 (0 << 16) +#define CMNCR_MOIIO0_OUT1 (1 << 16) +#define CMNCR_MOIIO0_OUT_PREV (2 << 16) +#define CMNCR_MOIIO0_HIZ (3 << 16) +#define CMNCR_MOIIO1_OUT0 (0 << 18) +#define CMNCR_MOIIO1_OUT1 (1 << 18) +#define CMNCR_MOIIO1_OUT_PREV (2 << 18) +#define CMNCR_MOIIO1_HIZ (3 << 18) +#define CMNCR_MOIIO2_OUT0 (0 << 20) +#define CMNCR_MOIIO2_OUT1 (1 << 20) +#define CMNCR_MOIIO2_OUT_PREV (2 << 20) +#define CMNCR_MOIIO2_HIZ (3 << 20) +#define CMNCR_MOIIO3_OUT0 (0 << 22) +#define CMNCR_MOIIO3_OUT1 (1 << 22) +#define CMNCR_MOIIO3_OUT_PREV (2 << 22) +#define CMNCR_MOIIO3_HIZ (3 << 22) +#define CMNCR_MD_MANUAL (U(1) << 31) +#define CMNCR_MD_EXT_READ (0 << 31) +#define SSLDR_SCKDL_1_5 (0 << 0) +#define SSLDR_SCKDL_2_5 (1 << 0) +#define SSLDR_SCKDL_3_5 (2 << 0) +#define SSLDR_SCKDL_4_5 (3 << 0) +#define SSLDR_SCKDL_5_5 (4 << 0) +#define SSLDR_SCKDL_6_5 (5 << 0) +#define SSLDR_SCKDL_7_5 (6 << 0) +#define SSLDR_SCKDL_8_5 (7 << 0) +#define SSLDR_SLNDL_1QSPIn (0 << 8) +#define SSLDR_SLNDL_2QSPIn (1 << 8) +#define SSLDR_SLNDL_3QSPIn (2 << 8) +#define SSLDR_SLNDL_4QSPIn (3 << 8) +#define SSLDR_SLNDL_5QSPIn (4 << 8) +#define SSLDR_SLNDL_6QSPIn (5 << 8) +#define SSLDR_SLNDL_7QSPIn (6 << 8) +#define SSLDR_SLNDL_8QSPIn (7 << 8) +#define SSLDR_SPNDL_1QSPIn (0 << 16) +#define SSLDR_SPNDL_2QSPIn (1 << 16) +#define SSLDR_SPNDL_3QSPIn (2 << 16) +#define SSLDR_SPNDL_4QSPIn (3 << 16) +#define SSLDR_SPNDL_5QSPIn (4 << 16) +#define SSLDR_SPNDL_6QSPIn (5 << 16) +#define SSLDR_SPNDL_7QSPIn (6 << 16) +#define SSLDR_SPNDL_8QSPIn (7 << 16) +#define DRCR_SSLE (1 << 0) +#define DRCR_RBE (1 << 8) +#define DRCR_RCF (1 << 9) +#define DRCR_RBURST_1_DATALEN (0 << 16) +#define DRCR_RBURST_2_DATALEN (1 << 16) +#define DRCR_RBURST_3_DATALEN (2 << 16) +#define DRCR_RBURST_4_DATALEN (3 << 16) +#define DRCR_RBURST_5_DATALEN (4 << 16) +#define DRCR_RBURST_6_DATALEN (5 << 16) +#define DRCR_RBURST_7_DATALEN (6 << 16) +#define DRCR_RBURST_8_DATALEN (7 << 16) +#define DRCR_RBURST_9_DATALEN (8 << 16) +#define DRCR_RBURST_10_DATALEN (9 << 16) +#define DRCR_RBURST_11_DATALEN (10 << 16) +#define DRCR_RBURST_12_DATALEN (11 << 16) +#define DRCR_RBURST_13_DATALEN (12 << 16) +#define DRCR_RBURST_14_DATALEN (13 << 16) +#define DRCR_RBURST_15_DATALEN (14 << 16) +#define DRCR_RBURST_16_DATALEN (15 << 16) +#define DRCR_RBURST_17_DATALEN (16 << 16) +#define DRCR_RBURST_18_DATALEN (17 << 16) +#define DRCR_RBURST_19_DATALEN (18 << 16) +#define DRCR_RBURST_20_DATALEN (19 << 16) +#define DRCR_RBURST_21_DATALEN (20 << 16) +#define DRCR_RBURST_22_DATALEN (21 << 16) +#define DRCR_RBURST_23_DATALEN (22 << 16) +#define DRCR_RBURST_24_DATALEN (23 << 16) +#define DRCR_RBURST_25_DATALEN (24 << 16) +#define DRCR_RBURST_26_DATALEN (25 << 16) +#define DRCR_RBURST_27_DATALEN (26 << 16) +#define DRCR_RBURST_28_DATALEN (27 << 16) +#define DRCR_RBURST_29_DATALEN (28 << 16) +#define DRCR_RBURST_30_DATALEN (29 << 16) +#define DRCR_RBURST_31_DATALEN (30 << 16) +#define DRCR_RBURST_32_DATALEN (31 << 16) +#define DRCR_SSLN (1 << 24) +#define DREAR_EAC_EXADDR24 (0 << 0) +#define DREAR_EAC_EXADDR25 (1 << 0) +#define DREAR_EAC_EXADDR26 (2 << 0) +#define DREAR_EAC_EXADDR27 (3 << 0) +#define DRENR_OPDE_NO_OUT (0 << 4) +#define DRENR_OPDE_OPD3_OUT (8 << 4) +#define DRENR_OPDE_OPD32_OUT (12 << 4) +#define DRENR_OPDE_OPD321_OUT (14 << 4) +#define DRENR_OPDE_OPD3210_OUT (15 << 4) +#define DRENR_ADE_NO_OUT (0 << 8) +#define DRENR_ADE_ADD23_OUT (7 << 8) +#define DRENR_ADE_ADD31_OUT (15 << 8) +#define DRENR_ADE_OCTA_FLASH (12 << 8) +#define DRENR_ADE_HYPER_FLASH (4 << 8) +#define DRENR_OCDE (1 << 12) +#define DRENR_CDE (1 << 14) +#define DRENR_DME (1 << 15) +#define DRENR_DRDB_1BIT (0 << 16) +#define DRENR_DRDB_4BIT (2 << 16) +#define DRENR_OPDB_1BIT (0 << 20) +#define DRENR_OPDB_4BIT (2 << 20) +#define DRENR_ADB_1BIT (0 << 24) +#define DRENR_ADB_4BIT (2 << 24) +#define DRENR_OCDB_1BIT (0 << 28) +#define DRENR_OCDB_4BIT (2 << 28) +#define DRENR_CDB_1BIT (0 << 30) +#define DRENR_CDB_4BIT (0x80000000) +#define SMCR_SPIE (1 << 0) +#define SMCR_SPIWE (1 << 1) +#define SMCR_SPIRE (1 << 2) +#define SMCR_SSLKP (1 << 8) +#define SMENR_SPIDE_NO_SEND (0 << 0) +#define SMENR_SPIDE_8BIT_SEND (8 << 0) +#define SMENR_SPIDE_16BIT_SEND (12 << 0) +#define SMENR_SPIDE_32BIT_SEND (15 << 0) +#define SMENR_OPDE_NO_OUT (0 << 4) +#define SMENR_OPDE_OPD3_OUT (8 << 4) +#define SMENR_OPDE_OPD32_OUT (12 << 4) +#define SMENR_OPDE_OPD321_OUT (14 << 4) +#define SMENR_OPDE_OPD3210_OUT (15 << 4) +#define SMENR_ADE_NO_OUT (0 << 8) +#define SMENR_ADE_ADR23_16_OUT (4 << 8) +#define SMENR_ADE_ADR23_8_OUT (6 << 8) +#define SMENR_ADE_ADR23_0_OUT (7 << 8) +#define SMENR_ADE_ADR31_0_OUT (15 << 8) +#define SMENR_OCDE (1 << 12) +#define SMENR_CDE (1 << 14) +#define SMENR_DME (1 << 15) +#define SMENR_SPIDB_1BIT (0 << 16) +#define SMENR_SPIDB_4BIT (2 << 16) +#define SMENR_OPDB_1BIT (0 << 20) +#define SMENR_OPDB_4BIT (2 << 20) +#define SMENR_ADB_1BIT (0 << 24) +#define SMENR_ADB_4BIT (2 << 24) +#define SMENR_OCDB_1BIT (0 << 28) +#define SMENR_OCDB_4BIT (2 << 28) +#define SMENR_CDB_1BIT (0 << 30) +#define SMENR_CDB_4BIT (U(2) << 30) +#define CMNSR_TEND (1 << 0) +#define CMNSR_SSLF (1 << 1) +#define DRDRENR_DRDRE_DDR (1 << 0) +#define DRDRENR_DRDRE_SDR (0 << 0) +#define DRDRENR_OPDRE_DDR (1 << 4) +#define DRDRENR_OPDRE_SDR (0 << 4) +#define DRDRENR_ADDRE_DDR (1 << 8) +#define DRDRENR_ADDRE_SDR (0 << 8) +#define DRDRENR_HYPE_HYPER (5 << 12) +#define DRDRENR_HYPE_OCTA (4 << 12) +#define DRDRENR_HYPE_SPI (0 << 12) +#define SMDRENR_SPIDRE (1 << 0) +#define SMDRENR_OPDRE (1 << 4) +#define SMDRENR_ADDRE (1 << 8) +#define SMDRENR_HYPE_HYPER_FLASH (5 << 12) +#define SMDRENR_HYPE_OCTA_FLASH (4 << 12) +#define SMDRENR_HYPE_SPI_FLASH (0 << 12) +#define PHYCNT_PHYMEM_SDR_MODE (0 << 0) +#define PHYCNT_PHYMEM_DDR_MODE (1 << 0) +#define PHYCNT_PHYMEM_HYPER_FLASH (3 << 0) +#define PHYCNT_WBUF_USED (1 << 2) +#define PHYCNT_WBUF_NOT_USED (0 << 2) +#define PHYCNT_WBUF2_USED (1 << 4) +#define PHYCNT_WBUF2_NOT_USED (0 << 4) +#define PHYCNT_CKSEL_SLOW (0 << 16) +#define PHYCNT_CKSEL_FAST (3 << 16) +#define PHYCNT_HS_MODE (1 << 18) +#define PHYCNT_HS_OTHER_MODE (0 << 18) +#define PHYCNT_OCT_MODE (1 << 20) +#define PHYCNT_OCT_OTHER_MODE (0 << 20) +#define PHYCNT_EXDS_USED (1 << 21) +#define PHYCNT_EXDS_NOT_USED (0 << 21) +#define PHYCNT_OCTA_HYPER_FLASH (0 << 22) +#define PHYCNT_OCTA_ALTE (1 << 22) +#define PHYCNT_OCTA_ORDER (2 << 22) +#define PHYCNT_ALT_ALIGN_SUPPORTED (1 << 30) +#define PHYCNT_ALT_ALIGN_NOT_SUPPORTED (0 << 30) +#define PHYCNT_CAL_PERFOMED (U(1) << 31) +#define PHYCNT_CAL_NOT_PERFOMED (0 << 31) +#define PHYCNT_DEF_DATA (0x00000260) +#define PHYOFFSET1_DDRTMG_SPIDRE_1 (2 << 28) +#define PHYOFFSET1_DDRTMG_SPIDRE_0 (3 << 28) +#define PHYOFFSET1_DEF_DATA (0x01511144) +#define PHYOFFSET2_OCTTMG_HYPER_FLASH (4 << 8) +#define PHYOFFSET2_OCTTMG_OCTA_FLASH (3 << 8) +#define PHYOFFSET2_DEF_DATA (0x00000031) +#define PHYINT_INT (1 << 0) +#define PHYINT_WPVAL (1 << 1) +#define PHYINT_RSTVAL (1 << 2) +#define PHYINT_INTEN (1 << 24) +#define PHYINT_WPEN (1 << 25) +#define PHYINT_RSTEN (1 << 26) + +#define DREAR_EAV_ADDRE_DATA (2 << 16) + +#define DRCMR_CMD_FAST_READ_3B (0x0B << 16) +#define DRCMR_CMD_QUAD_OUTPUT_FAST_READ_3B (0x6B << 16) +#define DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B (0xEB << 16) +#define DRCMR_CMD_FAST_READ_4B (0x0C << 16) +#define DRCMR_CMD_QUAD_OUTPUT_FAST_READ_4B (0x6C << 16) +#define DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_4B (0xEC << 16) + +#endif /* _SPI_MULTI_REG_H_ */ + diff --git a/plat/renesas/rza/common/include/octa.h b/plat/renesas/rza/common/include/octa.h new file mode 100644 index 0000000000..3230b76b61 --- /dev/null +++ b/plat/renesas/rza/common/include/octa.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _OCTA_API_H_ +#define _OCTA_API_H_ +#include +#include + +#include "xspi_api.h" + +/** xSPI device control structure */ +typedef struct st_octa_ctrl { + bool opened; + uint8_t device_type; + uintptr_t reg_base; + uintptr_t mmap_base; + uint32_t calibration_base; + size_t mmap_size; + uint8_t channel; +} octa_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_octa_ext { + uint32_t device_size; + uint32_t calibration_base; +} octa_ext_t; + +extern const xspi_api_t octa_api; + +#endif /* _OCTA_API_H_ */ diff --git a/plat/renesas/rza/common/include/octa_regs.h b/plat/renesas/rza/common/include/octa_regs.h new file mode 100644 index 0000000000..84de8964bb --- /dev/null +++ b/plat/renesas/rza/common/include/octa_regs.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _OCTA_REG_H_ +#define _OCTA_REG_H_ + +#define OCTA_DCR 0x0000 /* Device command register */ +#define OCTA_DAR 0x0004 /* Device address register */ +#define OCTA_DCSR 0x0008 /* Device command setting register */ +#define OCTA_DSR0 0x000C /* Device size register 0 */ +#define OCTA_DSR1 0x0010 /* Device size register 1 */ +#define OCTA_MDTR 0x0014 /* Memory delay trim register */ +#define OCTA_ACTR 0x0018 /* Auto-calibration timer register */ +#define OCTA_ACAR0 0x001C /* Auto-calibration address register 0 */ +#define OCTA_ACAR1 0x0020 /* Auto-calibration address register 1 */ +#define OCTA_DRCSTR 0x0034 /* Device memory map read chip select timing setting register */ +#define OCTA_DWCSTR 0x0038 /* Device memory map write chip select timing setting register */ +#define OCTA_DCSTR 0x003C /* Device chip select timing setting register */ +#define OCTA_CDSR 0x0040 /* Controller and device setting register */ +#define OCTA_MDLR 0x0044 /* Memory map dummy length register */ +#define OCTA_MRWCR0 0x0048 /* Memory map read/write command register 0 */ +#define OCTA_MRWCR1 0x004C /* Memory map read/write command register 1 */ +#define OCTA_MRWCSR 0x0050 /* Memory map read/write setting register */ +#define OCTA_ESR 0x0054 /* Error status register */ +#define OCTA_CWNDR 0x0058 /* Configure write without data register */ +#define OCTA_CWDR 0x005C /* Configure write data register */ +#define OCTA_CRR 0x0060 /* Configure read register */ +#define OCTA_RSTCNT 0x0080 /* Device reset register */ +#define OCTA_AER 0x0084 /* Address extend register */ + +/* DCR field */ +#define OCTA_DCR_DVCMD1_POS (8UL) +#define OCTA_DCR_DVCMD1 (0xFFUL << OCTA_DCR_DVCMD1_POS) +#define OCTA_DCR_DVCMD0_POS (0UL) +#define OCTA_DCR_DVCMD0 (0xFFUL << OCTA_DCR_DVCMD0_POS) + +/* DAR field */ +#define OCTA_DAR_DVAD3_POS (24UL) +#define OCTA_DAR_DVAD3 (0xFFUL << OCTA_DAR_DVAD3_POS) +#define OCTA_DAR_DVAD2_POS (16UL) +#define OCTA_DAR_DVAD2 (0xFFUL << OCTA_DAR_DVAD2_POS) +#define OCTA_DAR_DVAD1_POS (8UL) +#define OCTA_DAR_DVAD1 (0xFFUL << OCTA_DAR_DVAD1_POS) +#define OCTA_DAR_DVAD0_POS (0UL) +#define OCTA_DAR_DVAD0 (0xFFUL << OCTA_DAR_DVAD0_POS) + +/* DCSR field */ +#define OCTA_DCSR_ACDA_POS (28UL) +#define OCTA_DCSR_ACDA (0x1UL << OCTA_DCSR_ACDA_POS) +#define OCTA_DCSR_DOPI_POS (27UL) +#define OCTA_DCSR_DOPI (0x1UL << OCTA_DCSR_DOPI_POS) +#define OCTA_DCSR_ADLEN_POS (24UL) +#define OCTA_DCSR_ADLEN (0x7UL << OCTA_DCSR_ADLEN_POS) +#define OCTA_DCSR_DAOR_POS (23UL) +#define OCTA_DCSR_DAOR (0x1UL << OCTA_DCSR_DAOR_POS) +#define OCTA_DCSR_CMDLEN_POS (20UL) +#define OCTA_DCSR_CMDLEN (0x7UL << OCTA_DCSR_CMDLEN_POS) +#define OCTA_DCSR_ACDV_POS (19UL) +#define OCTA_DCSR_ACDV (0x1UL << OCTA_DCSR_ACDV_POS) +#define OCTA_DCSR_DMLEN_POS (8UL) +#define OCTA_DCSR_DMLEN (0xFFUL << OCTA_DCSR_DMLEN_POS) +#define OCTA_DCSR_DALEN_POS (0UL) +#define OCTA_DCSR_DALEN (0xFFUL << OCTA_DCSR_DALEN_POS) + +/* DSR0 field */ +#define OCTA_DSR0_DV0TYP_POS (30UL) +#define OCTA_DSR0_DV0TYP (0x3UL << OCTA_DSR0_DV0TYP_POS) +#define OCTA_DSR0_DV0SZ_POS (0UL) +#define OCTA_DSR0_DV0SZ (0x3FFFFFFFUL << OCTA_DSR0_DV0SZ_POS) +#define OCTA_DSR_TYP_FLASH 0u +#define OCTA_DSR_TYP_RAM 1u +#define OCTA_DSR_TYP_NONE 2u + +/* DSR1 field */ +#define OCTA_DSR1_DV1TYP_POS (30UL) +#define OCTA_DSR1_DV1TYP (0x3UL << OCTA_DSR1_DV1TYP_POS) +#define OCTA_DSR1_DV1SZ_POS (0UL) +#define OCTA_DSR1_DV1SZ (0x3FFFFFFFUL << OCTA_DSR1_DV1SZ_POS) + +/* MDTR field */ +#define OCTA_MDTR_DQSEDOPI_POS (24UL) +#define OCTA_MDTR_DQSEDOPI (0xFUL << OCTA_MDTR_DQSEDOPI_POS) +#define OCTA_MDTR_DV1DEL_POS (16UL) +#define OCTA_MDTR_DV1DEL (0xFFUL << OCTA_MDTR_DV1DEL_POS) +#define OCTA_MDTR_DQSESOPI_POS (12UL) +#define OCTA_MDTR_DQSESOPI (0xFUL << OCTA_MDTR_DQSESOPI_POS) +#define OCTA_MDTR_DQSERAM_POS (8UL) +#define OCTA_MDTR_DQSERAM (0xFUL << OCTA_MDTR_DQSERAM_POS) +#define OCTA_MDTR_DV0DEL_POS (0UL) +#define OCTA_MDTR_DV0DEL (0xFFUL << OCTA_MDTR_DV0DEL_POS) + +/* ACTR field */ +#define OCTA_ACTR_CTP_POS (0UL) +#define OCTA_ACTR_CTP (0xFFFFFFFFUL << OCTA_ACTR_CTP_POS) + +/* ACAR0 field */ +#define OCTA_ACAR0_CAD0_POS (0UL) +#define OCTA_ACAR0_CAD0 (0xFFFFFFFFUL << OCTA_ACAR0_CAD0_POS) + +/* ACAR1 field */ +#define OCTA_ACAR1_CAD1_POS (0UL) +#define OCTA_ACAR1_CAD1 (0xFFFFFFFFUL << OCTA_ACAR1_CAD1_POS) + +/* DRCSTR field */ +#define OCTA_DRCSTR_DVRDLO1_POS (30UL) +#define OCTA_DRCSTR_DVRDLO1 (0x3UL << OCTA_DRCSTR_DVRDLO1_POS) +#define OCTA_DRCSTR_DVRDHI1_POS (27UL) +#define OCTA_DRCSTR_DVRDHI1 (0x7UL << OCTA_DRCSTR_DVRDHI1_POS) +#define OCTA_DRCSTR_DVRDCMD1_POS (24UL) +#define OCTA_DRCSTR_DVRDCMD1 (0x7UL << OCTA_DRCSTR_DVRDCMD1_POS) +/* CTR1 and CTRW1 are not available in RZ */ +#define OCTA_DRCSTR_CTR1_POS (23UL) +#define OCTA_DRCSTR_CTR1 (0x1UL << OCTA_DRCSTR_CTR1_POS) +#define OCTA_DRCSTR_CTRW1_POS (16UL) +#define OCTA_DRCSTR_CTRW1 (0x7FUL << OCTA_DRCSTR_CTRW1_POS) +#define OCTA_DRCSTR_DVRDLO0_POS (14UL) +#define OCTA_DRCSTR_DVRDLO0 (0x3UL << OCTA_DRCSTR_DVRDLO0_POS) +#define OCTA_DRCSTR_DVRDHI0_POS (11UL) +#define OCTA_DRCSTR_DVRDHI0 (0x7UL << OCTA_DRCSTR_DVRDHI0_POS) +#define OCTA_DRCSTR_DVRDCMD0_POS (8UL) +#define OCTA_DRCSTR_DVRDCMD0 (0x7UL << OCTA_DRCSTR_DVRDCMD0_POS) +#define OCTA_DRCSTR_CTR0_POS (7UL) +#define OCTA_DRCSTR_CTR0 (0x1UL << OCTA_DRCSTR_CTR0_POS) +#define OCTA_DRCSTR_CTRW0_POS (0UL) +#define OCTA_DRCSTR_CTRW0 (0x7FUL << OCTA_DRCSTR_CTRW0_POS) + +/* DWCSTR field */ +#define OCTA_DWCSTR_DVWLO1_POS (30UL) +#define OCTA_DWCSTR_DVWLO1 (0x3UL << OCTA_DWCSTR_DVWLO1_POS) +#define OCTA_DWCSTR_DVWHI1_POS (27UL) +#define OCTA_DWCSTR_DVWHI1 (0x7UL << OCTA_DWCSTR_DVWHI1_POS) +#define OCTA_DWCSTR_DVWCMD1_POS (24UL) +#define OCTA_DWCSTR_DVWCMD1 (0x7UL << OCTA_DWCSTR_DVWCMD1_POS) +/* CTW1 and CTWW1 are not available in RZ */ +#define OCTA_DWCSTR_CTW1_POS (23UL) +#define OCTA_DWCSTR_CTW1 (0x1UL << OCTA_DWCSTR_CTW1_POS) +#define OCTA_DWCSTR_CTWW1_POS (16UL) +#define OCTA_DWCSTR_CTWW1 (0x7FUL << OCTA_DWCSTR_CTWW1_POS) +#define OCTA_DWCSTR_DVWLO0_POS (14UL) +#define OCTA_DWCSTR_DVWLO0 (0x3UL << OCTA_DWCSTR_DVWLO0_POS) +#define OCTA_DWCSTR_DVWHI0_POS (11UL) +#define OCTA_DWCSTR_DVWHI0 (0x7UL << OCTA_DWCSTR_DVWHI0_POS) +#define OCTA_DWCSTR_DVWCMD0_POS (8UL) +#define OCTA_DWCSTR_DVWCMD0 (0x7UL << OCTA_DWCSTR_DVWCMD0_POS) +/* CTW0 and CTWW0 are not available in RZ */ +#define OCTA_DWCSTR_CTW0_POS (7UL) +#define OCTA_DWCSTR_CTW0 (0x1UL << OCTA_DWCSTR_CTW0_POS) +#define OCTA_DWCSTR_CTWW0_POS (0UL) +#define OCTA_DWCSTR_CTWW0 (0x7FUL << OCTA_DWCSTR_CTWW0_POS) + +/* DCSTR field */ +#define OCTA_DCSTR_DVSELLO_POS (14UL) +#define OCTA_DCSTR_DVSELLO (0x3UL << OCTA_DCSTR_DVSELLO_POS) +#define OCTA_DCSTR_DVSELHI_POS (11UL) +#define OCTA_DCSTR_DVSELHI (0x7UL << OCTA_DCSTR_DVSELHI_POS) +#define OCTA_DCSTR_DVSELCMD_POS (8UL) +#define OCTA_DCSTR_DVSELCMD (0x7UL << OCTA_DCSTR_DVSELCMD_POS) + +/* CDSR field */ +#define OCTA_CDSR_DLFT_POS (31UL) +#define OCTA_CDSR_DLFT (0x1UL << OCTA_CDSR_DLFT_POS) +#define OCTA_CDSR_ACMODE_POS (12UL) +#define OCTA_CDSR_ACMODE (0x3UL << OCTA_CDSR_ACMODE_POS) +#define OCTA_CDSR_ACMODE_DISABLE 0u +#define OCTA_CDSR_ACMODE_ENABLE 1u +#define OCTA_CDSR_ACMEME1_POS (11UL) +#define OCTA_CDSR_ACMEME1 (0x1UL << OCTA_CDSR_ACMEME1_POS) +#define OCTA_CDSR_ACMEME0_POS (10UL) +#define OCTA_CDSR_ACMEME0 (0x1UL << OCTA_CDSR_ACMEME0_POS) +#define OCTA_CDSR_DV1PC_POS (5UL) +#define OCTA_CDSR_DV1PC (0x1UL << OCTA_CDSR_DV1PC_POS) +#define OCTA_CDSR_DV0PC_POS (4UL) +#define OCTA_CDSR_DV0PC (0x1UL << OCTA_CDSR_DV0PC_POS) +#define OCTA_CDSR_DV1TTYP_POS (2UL) +#define OCTA_CDSR_DV1TTYP (0x3UL << OCTA_CDSR_DV1TTYP_POS) +#define OCTA_CDSR_DV0TTYP_POS (0UL) +#define OCTA_CDSR_DV0TTYP (0x3UL << OCTA_CDSR_DV0TTYP_POS) +#define OCTA_CDSR_DVTTYP_SPI 0u +#define OCTA_CDSR_DVTTYP_SOPI 1u +#define OCTA_CDSR_DVTTYP_DOPI 2u + +/* MDLR field */ +#define OCTA_MDLR_DV1WDL_POS (24UL) +#define OCTA_MDLR_DV1WDL (0xFFUL << OCTA_MDLR_DV1WDL_POS) +#define OCTA_MDLR_DV1RDL_POS (16UL) +#define OCTA_MDLR_DV1RDL (0xFFUL << OCTA_MDLR_DV1RDL_POS) +#define OCTA_MDLR_DV0WDL_POS (8UL) +#define OCTA_MDLR_DV0WDL (0xFFUL << OCTA_MDLR_DV0WDL_POS) +#define OCTA_MDLR_DV0RDL_POS (0UL) +#define OCTA_MDLR_DV0RDL (0xFFUL << OCTA_MDLR_DV0RDL_POS) + +/* MRWCR0 field */ +#define OCTA_MRWCR0_D0MWCMD1_POS (24UL) +#define OCTA_MRWCR0_D0MWCMD1 (0xFFUL << OCTA_MRWCR0_D0MWCMD1_POS) +#define OCTA_MRWCR0_D0MWCMD0_POS (16UL) +#define OCTA_MRWCR0_D0MWCMD0 (0xFFUL << OCTA_MRWCR0_D0MWCMD0_POS) +#define OCTA_MRWCR0_D0MRCMD1_POS (8UL) +#define OCTA_MRWCR0_D0MRCMD1 (0xFFUL << OCTA_MRWCR0_D0MRCMD1_POS) +#define OCTA_MRWCR0_D0MRCMD0_POS (0UL) +#define OCTA_MRWCR0_D0MRCMD0 (0xFFUL << OCTA_MRWCR0_D0MRCMD0_POS) + +/* MRWCR1 field */ +#define OCTA_MRWCR1_D1MWCMD1_POS (24UL) +#define OCTA_MRWCR1_D1MWCMD1 (0xFFUL << OCTA_MRWCR1_D1MWCMD1_POS) +#define OCTA_MRWCR1_D1MWCMD0_POS (16UL) +#define OCTA_MRWCR1_D1MWCMD0 (0xFFUL << OCTA_MRWCR1_D1MWCMD0_POS) +#define OCTA_MRWCR1_D1MRCMD1_POS (8UL) +#define OCTA_MRWCR1_D1MRCMD1 (0xFFUL << OCTA_MRWCR1_D1MRCMD1_POS) +#define OCTA_MRWCR1_D1MRCMD0_POS (0UL) +#define OCTA_MRWCR1_D1MRCMD0 (0xFFUL << OCTA_MRWCR1_D1MRCMD0_POS) + +/* MRWCSR field */ +#define OCTA_MRWCSR_MWO1_POS (30UL) +#define OCTA_MRWCSR_MWO1 (0x1UL << OCTA_MRWCSR_MWO1_POS) +#define OCTA_MRWCSR_MWCL1_POS (27UL) +#define OCTA_MRWCSR_MWCL1 (0x7UL << OCTA_MRWCSR_MWCL1_POS) +#define OCTA_MRWCSR_MWAL1_POS (24UL) +#define OCTA_MRWCSR_MWAL1 (0x7UL << OCTA_MRWCSR_MWAL1_POS) +#define OCTA_MRWCSR_MRO1_POS (22UL) +#define OCTA_MRWCSR_MRO1 (0x1UL << OCTA_MRWCSR_MRO1_POS) +#define OCTA_MRWCSR_MRCL1_POS (19UL) +#define OCTA_MRWCSR_MRCL1 (0x7UL << OCTA_MRWCSR_MRCL1_POS) +#define OCTA_MRWCSR_MRAL1_POS (16UL) +#define OCTA_MRWCSR_MRAL1 (0x7UL << OCTA_MRWCSR_MRAL1_POS) +#define OCTA_MRWCSR_MWO0_POS (14UL) +#define OCTA_MRWCSR_MWO0 (0x1UL << OCTA_MRWCSR_MWO0_POS) +#define OCTA_MRWCSR_MWCL0_POS (11UL) +#define OCTA_MRWCSR_MWCL0 (0x7UL << OCTA_MRWCSR_MWCL0_POS) +#define OCTA_MRWCSR_MWAL0_POS (8UL) +#define OCTA_MRWCSR_MWAL0 (0x7UL << OCTA_MRWCSR_MWAL0_POS) +#define OCTA_MRWCSR_MRO0_POS (6UL) +#define OCTA_MRWCSR_MRO0 (0x1UL << OCTA_MRWCSR_MRO0_POS) +#define OCTA_MRWCSR_MRCL0_POS (3UL) +#define OCTA_MRWCSR_MRCL0 (0x7UL << OCTA_MRWCSR_MRCL0_POS) +#define OCTA_MRWCSR_MRAL0_POS (0UL) +#define OCTA_MRWCSR_MRAL0 (0x7UL << OCTA_MRWCSR_MRAL0_POS) + +/* ESR field */ +#define OCTA_ESR_MWESR_POS (8UL) +#define OCTA_ESR_MWESR (0xFFUL << OCTA_ESR_MWESR_POS) +#define OCTA_ESR_MRESR_POS (0UL) +#define OCTA_ESR_MRESR (0xFFUL << OCTA_ESR_MRESR_POS) + +/* CWDR field */ +#define OCTA_CWDR_WD3_POS (24UL) +#define OCTA_CWDR_WD3 (0xFFUL << OCTA_CWDR_WD3_POS) +#define OCTA_CWDR_WD2_POS (16UL) +#define OCTA_CWDR_WD2 (0xFFUL << OCTA_CWDR_WD2_POS) +#define OCTA_CWDR_WD1_POS (8UL) +#define OCTA_CWDR_WD1 (0xFFUL << OCTA_CWDR_WD1_POS) +#define OCTA_CWDR_WD0_POS (0UL) +#define OCTA_CWDR_WD0 (0xFFUL << OCTA_CWDR_WD0_POS) + +/* CRR field */ +#define OCTA_CRR_RD3_POS (24UL) +#define OCTA_CRR_RD3 (0xFFUL << OCTA_CRR_RD3_POS) +#define OCTA_CRR_RD2_POS (16UL) +#define OCTA_CRR_RD2 (0xFFUL << OCTA_CRR_RD2_POS) +#define OCTA_CRR_RD1_POS (8UL) +#define OCTA_CRR_RD1 (0xFFUL << OCTA_CRR_RD1_POS) +#define OCTA_CRR_RD0_POS (0UL) +#define OCTA_CRR_RD0 (0xFFUL << OCTA_CRR_RD0_POS) + +/* RSTCN field */ +#define OCTA_RSTCNT_RSTVAL_POS (0UL) +#define OCTA_RSTCNT_RSTVAL (0x1UL << OCTA_RSTCNT_RSTVAL_POS) + +/* AER field */ +#define OCTA_AER_POS (0UL) +#define OCTA_AER_LE64MB (0x0UL << OCTA_AER_POS) +#define OCTA_AER_128MB (0x1UL << OCTA_AER_POS) +#define OCTA_AER_256MB (0x3UL << OCTA_AER_POS) +#define OCTA_AER_512MB (0x7UL << OCTA_AER_POS) + +#endif /* _OCTA_REG_H_ */ + diff --git a/plat/renesas/rza/common/include/pfc.h b/plat/renesas/rza/common/include/pfc.h new file mode 100644 index 0000000000..429076bfe8 --- /dev/null +++ b/plat/renesas/rza/common/include/pfc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PFC_H__ +#define __PFC_H__ + +void pfc_setup(void); + + +#endif /* __PFC_H__ */ diff --git a/plat/renesas/rza/common/include/pfc_regs.h b/plat/renesas/rza/common/include/pfc_regs.h new file mode 100644 index 0000000000..6fe8b30ebd --- /dev/null +++ b/plat/renesas/rza/common/include/pfc_regs.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PFC_REGS_H__ +#define __PFC_REGS_H__ + +#define PFC_BASE (0x11030000) /* PFC base address */ + +#define PFC_P05 (PFC_BASE + 0x0005) /* Port register */ +#define PFC_P10 (PFC_BASE + 0x0010) /* Port register */ +#define PFC_P11 (PFC_BASE + 0x0011) /* Port register */ +#define PFC_P12 (PFC_BASE + 0x0012) /* Port register */ +#define PFC_P13 (PFC_BASE + 0x0013) /* Port register */ +#define PFC_P14 (PFC_BASE + 0x0014) /* Port register */ +#define PFC_P15 (PFC_BASE + 0x0015) /* Port register */ +#define PFC_P16 (PFC_BASE + 0x0016) /* Port register */ +#define PFC_P17 (PFC_BASE + 0x0017) /* Port register */ +#define PFC_P18 (PFC_BASE + 0x0018) /* Port register */ +#define PFC_P19 (PFC_BASE + 0x0019) /* Port register */ +#define PFC_P1A (PFC_BASE + 0x001A) /* Port register */ +#define PFC_P1B (PFC_BASE + 0x001B) /* Port register */ +#define PFC_P1C (PFC_BASE + 0x001C) /* Port register */ +#define PFC_P1D (PFC_BASE + 0x001D) /* Port register */ +#define PFC_P1E (PFC_BASE + 0x001E) /* Port register */ +#define PFC_P1F (PFC_BASE + 0x001F) /* Port register */ +#define PFC_P20 (PFC_BASE + 0x0020) /* Port register */ +#define PFC_P21 (PFC_BASE + 0x0021) /* Port register */ +#define PFC_P22 (PFC_BASE + 0x0022) /* Port register */ +#define PFC_P23 (PFC_BASE + 0x0023) /* Port register */ +#define PFC_P24 (PFC_BASE + 0x0024) /* Port register */ +#define PFC_P25 (PFC_BASE + 0x0025) /* Port register */ +#define PFC_P26 (PFC_BASE + 0x0026) /* Port register */ +#define PFC_P27 (PFC_BASE + 0x0027) /* Port register */ +#define PFC_P28 (PFC_BASE + 0x0028) /* Port register */ +#define PFC_P29 (PFC_BASE + 0x0029) /* Port register */ +#define PFC_P2A (PFC_BASE + 0x002A) /* Port register */ +#define PFC_P2B (PFC_BASE + 0x002B) /* Port register */ +#define PFC_P2C (PFC_BASE + 0x002C) /* Port register */ +#define PFC_P2D (PFC_BASE + 0x002D) /* Port register */ +#define PFC_P2E (PFC_BASE + 0x002E) /* Port register */ +#define PFC_P2F (PFC_BASE + 0x002F) /* Port register */ +#define PFC_P30 (PFC_BASE + 0x0030) /* Port register */ +#define PFC_P31 (PFC_BASE + 0x0031) /* Port register */ +#define PFC_P32 (PFC_BASE + 0x0032) /* Port register */ +#define PFC_P33 (PFC_BASE + 0x0033) /* Port register */ +#define PFC_P34 (PFC_BASE + 0x0034) /* Port register */ +#define PFC_P35 (PFC_BASE + 0x0035) /* Port register */ +#define PFC_P36 (PFC_BASE + 0x0036) /* Port register */ +#define PFC_P37 (PFC_BASE + 0x0037) /* Port register */ +#define PFC_P38 (PFC_BASE + 0x0038) /* Port register */ +#define PFC_P39 (PFC_BASE + 0x0039) /* Port register */ +#define PFC_P3A (PFC_BASE + 0x003A) /* Port register */ +#define PFC_P3B (PFC_BASE + 0x003B) /* Port register */ +#define PFC_P3C (PFC_BASE + 0x003C) /* Port register */ +#define PFC_P3D (PFC_BASE + 0x003D) /* Port register */ +#define PFC_P3E (PFC_BASE + 0x003E) /* Port register */ +#define PFC_P3F (PFC_BASE + 0x003F) /* Port register */ +#define PFC_P40 (PFC_BASE + 0x0040) /* Port register */ +#define PFC_PM10 (PFC_BASE + 0x0120) /* Port mode register */ +#define PFC_PM11 (PFC_BASE + 0x0122) /* Port mode register */ +#define PFC_PM12 (PFC_BASE + 0x0124) /* Port mode register */ +#define PFC_PM13 (PFC_BASE + 0x0126) /* Port mode register */ +#define PFC_PM14 (PFC_BASE + 0x0128) /* Port mode register */ +#define PFC_PM15 (PFC_BASE + 0x012A) /* Port mode register */ +#define PFC_PM16 (PFC_BASE + 0x012C) /* Port mode register */ +#define PFC_PM17 (PFC_BASE + 0x012E) /* Port mode register */ +#define PFC_PM18 (PFC_BASE + 0x0130) /* Port mode register */ +#define PFC_PM19 (PFC_BASE + 0x0132) /* Port mode register */ +#define PFC_PM1A (PFC_BASE + 0x0134) /* Port mode register */ +#define PFC_PM1B (PFC_BASE + 0x0136) /* Port mode register */ +#define PFC_PM1C (PFC_BASE + 0x0138) /* Port mode register */ +#define PFC_PM1D (PFC_BASE + 0x013A) /* Port mode register */ +#define PFC_PM1E (PFC_BASE + 0x013C) /* Port mode register */ +#define PFC_PM1F (PFC_BASE + 0x013E) /* Port mode register */ +#define PFC_PM20 (PFC_BASE + 0x0140) /* Port mode register */ +#define PFC_PM21 (PFC_BASE + 0x0142) /* Port mode register */ +#define PFC_PM22 (PFC_BASE + 0x0144) /* Port mode register */ +#define PFC_PM23 (PFC_BASE + 0x0146) /* Port mode register */ +#define PFC_PM24 (PFC_BASE + 0x0148) /* Port mode register */ +#define PFC_PM25 (PFC_BASE + 0x014A) /* Port mode register */ +#define PFC_PM26 (PFC_BASE + 0x014C) /* Port mode register */ +#define PFC_PM27 (PFC_BASE + 0x014E) /* Port mode register */ +#define PFC_PM28 (PFC_BASE + 0x0150) /* Port mode register */ +#define PFC_PM29 (PFC_BASE + 0x0152) /* Port mode register */ +#define PFC_PM2A (PFC_BASE + 0x0154) /* Port mode register */ +#define PFC_PM2B (PFC_BASE + 0x0156) /* Port mode register */ +#define PFC_PM2C (PFC_BASE + 0x0158) /* Port mode register */ +#define PFC_PM2D (PFC_BASE + 0x015A) /* Port mode register */ +#define PFC_PM2E (PFC_BASE + 0x015C) /* Port mode register */ +#define PFC_PM2F (PFC_BASE + 0x015E) /* Port mode register */ +#define PFC_PM30 (PFC_BASE + 0x0160) /* Port mode register */ +#define PFC_PM31 (PFC_BASE + 0x0162) /* Port mode register */ +#define PFC_PM32 (PFC_BASE + 0x0164) /* Port mode register */ +#define PFC_PM33 (PFC_BASE + 0x0166) /* Port mode register */ +#define PFC_PM34 (PFC_BASE + 0x0168) /* Port mode register */ +#define PFC_PM35 (PFC_BASE + 0x016A) /* Port mode register */ +#define PFC_PM36 (PFC_BASE + 0x016C) /* Port mode register */ +#define PFC_PM37 (PFC_BASE + 0x016E) /* Port mode register */ +#define PFC_PM38 (PFC_BASE + 0x0170) /* Port mode register */ +#define PFC_PM39 (PFC_BASE + 0x0172) /* Port mode register */ +#define PFC_PM3A (PFC_BASE + 0x0174) /* Port mode register */ +#define PFC_PM3B (PFC_BASE + 0x0176) /* Port mode register */ +#define PFC_PM3C (PFC_BASE + 0x0178) /* Port mode register */ +#define PFC_PM3D (PFC_BASE + 0x017A) /* Port mode register */ +#define PFC_PM3E (PFC_BASE + 0x017C) /* Port mode register */ +#define PFC_PM3F (PFC_BASE + 0x017E) /* Port mode register */ +#define PFC_PM40 (PFC_BASE + 0x0180) /* Port mode register */ +#define PFC_PMC04 (PFC_BASE + 0x0204) /* Port mode control register */ +#define PFC_PMC05 (PFC_BASE + 0x0205) /* Port mode control register */ +#define PFC_PMC10 (PFC_BASE + 0x0210) /* Port mode control register */ +#define PFC_PMC11 (PFC_BASE + 0x0211) /* Port mode control register */ +#define PFC_PMC12 (PFC_BASE + 0x0212) /* Port mode control register */ +#define PFC_PMC13 (PFC_BASE + 0x0213) /* Port mode control register */ +#define PFC_PMC14 (PFC_BASE + 0x0214) /* Port mode control register */ +#define PFC_PMC15 (PFC_BASE + 0x0215) /* Port mode control register */ +#define PFC_PMC16 (PFC_BASE + 0x0216) /* Port mode control register */ +#define PFC_PMC17 (PFC_BASE + 0x0217) /* Port mode control register */ +#define PFC_PMC18 (PFC_BASE + 0x0218) /* Port mode control register */ +#define PFC_PMC19 (PFC_BASE + 0x0219) /* Port mode control register */ +#define PFC_PMC1A (PFC_BASE + 0x021A) /* Port mode control register */ +#define PFC_PMC1B (PFC_BASE + 0x021B) /* Port mode control register */ +#define PFC_PMC1C (PFC_BASE + 0x021C) /* Port mode control register */ +#define PFC_PMC1D (PFC_BASE + 0x021D) /* Port mode control register */ +#define PFC_PMC1E (PFC_BASE + 0x021E) /* Port mode control register */ +#define PFC_PMC1F (PFC_BASE + 0x021F) /* Port mode control register */ +#define PFC_PMC20 (PFC_BASE + 0x0220) /* Port mode control register */ +#define PFC_PMC21 (PFC_BASE + 0x0221) /* Port mode control register */ +#define PFC_PMC22 (PFC_BASE + 0x0222) /* Port mode control register */ +#define PFC_PMC23 (PFC_BASE + 0x0223) /* Port mode control register */ +#define PFC_PMC24 (PFC_BASE + 0x0224) /* Port mode control register */ +#define PFC_PMC25 (PFC_BASE + 0x0225) /* Port mode control register */ +#define PFC_PMC26 (PFC_BASE + 0x0226) /* Port mode control register */ +#define PFC_PMC27 (PFC_BASE + 0x0227) /* Port mode control register */ +#define PFC_PMC28 (PFC_BASE + 0x0228) /* Port mode control register */ +#define PFC_PMC29 (PFC_BASE + 0x0229) /* Port mode control register */ +#define PFC_PMC2A (PFC_BASE + 0x022A) /* Port mode control register */ +#define PFC_PMC2B (PFC_BASE + 0x022B) /* Port mode control register */ +#define PFC_PMC2C (PFC_BASE + 0x022C) /* Port mode control register */ +#define PFC_PMC2D (PFC_BASE + 0x022D) /* Port mode control register */ +#define PFC_PMC2E (PFC_BASE + 0x022E) /* Port mode control register */ +#define PFC_PMC2F (PFC_BASE + 0x022F) /* Port mode control register */ +#define PFC_PMC30 (PFC_BASE + 0x0230) /* Port mode control register */ +#define PFC_PMC31 (PFC_BASE + 0x0231) /* Port mode control register */ +#define PFC_PMC32 (PFC_BASE + 0x0232) /* Port mode control register */ +#define PFC_PMC33 (PFC_BASE + 0x0233) /* Port mode control register */ +#define PFC_PMC34 (PFC_BASE + 0x0234) /* Port mode control register */ +#define PFC_PMC35 (PFC_BASE + 0x0235) /* Port mode control register */ +#define PFC_PMC36 (PFC_BASE + 0x0236) /* Port mode control register */ +#define PFC_PMC37 (PFC_BASE + 0x0237) /* Port mode control register */ +#define PFC_PMC38 (PFC_BASE + 0x0238) /* Port mode control register */ +#define PFC_PMC39 (PFC_BASE + 0x0239) /* Port mode control register */ +#define PFC_PMC3A (PFC_BASE + 0x023A) /* Port mode control register */ +#define PFC_PMC3B (PFC_BASE + 0x023B) /* Port mode control register */ +#define PFC_PMC3C (PFC_BASE + 0x023C) /* Port mode control register */ +#define PFC_PMC3D (PFC_BASE + 0x023D) /* Port mode control register */ +#define PFC_PMC3E (PFC_BASE + 0x023E) /* Port mode control register */ +#define PFC_PMC3F (PFC_BASE + 0x023F) /* Port mode control register */ +#define PFC_PMC40 (PFC_BASE + 0x0240) /* Port mode control register */ +#define PFC_PFC04 (PFC_BASE + 0x0410) /* Port function control register */ +#define PFC_PFC05 (PFC_BASE + 0x0414) /* Port function control register */ +#define PFC_PFC10 (PFC_BASE + 0x0440) /* Port function control register */ +#define PFC_PFC11 (PFC_BASE + 0x0444) /* Port function control register */ +#define PFC_PFC12 (PFC_BASE + 0x0448) /* Port function control register */ +#define PFC_PFC13 (PFC_BASE + 0x044C) /* Port function control register */ +#define PFC_PFC14 (PFC_BASE + 0x0450) /* Port function control register */ +#define PFC_PFC15 (PFC_BASE + 0x0454) /* Port function control register */ +#define PFC_PFC16 (PFC_BASE + 0x0458) /* Port function control register */ +#define PFC_PFC17 (PFC_BASE + 0x045C) /* Port function control register */ +#define PFC_PFC18 (PFC_BASE + 0x0460) /* Port function control register */ +#define PFC_PFC19 (PFC_BASE + 0x0464) /* Port function control register */ +#define PFC_PFC1A (PFC_BASE + 0x0468) /* Port function control register */ +#define PFC_PFC1B (PFC_BASE + 0x046C) /* Port function control register */ +#define PFC_PFC1C (PFC_BASE + 0x0470) /* Port function control register */ +#define PFC_PFC1D (PFC_BASE + 0x0474) /* Port function control register */ +#define PFC_PFC1E (PFC_BASE + 0x0478) /* Port function control register */ +#define PFC_PFC1F (PFC_BASE + 0x047C) /* Port function control register */ +#define PFC_PFC20 (PFC_BASE + 0x0480) /* Port function control register */ +#define PFC_PFC21 (PFC_BASE + 0x0484) /* Port function control register */ +#define PFC_PFC22 (PFC_BASE + 0x0488) /* Port function control register */ +#define PFC_PFC23 (PFC_BASE + 0x048C) /* Port function control register */ +#define PFC_PFC24 (PFC_BASE + 0x0490) /* Port function control register */ +#define PFC_PFC25 (PFC_BASE + 0x0494) /* Port function control register */ +#define PFC_PFC26 (PFC_BASE + 0x0498) /* Port function control register */ +#define PFC_PFC27 (PFC_BASE + 0x049C) /* Port function control register */ +#define PFC_PFC28 (PFC_BASE + 0x04A0) /* Port function control register */ +#define PFC_PFC29 (PFC_BASE + 0x04A4) /* Port function control register */ +#define PFC_PFC2A (PFC_BASE + 0x04A8) /* Port function control register */ +#define PFC_PFC2B (PFC_BASE + 0x04AC) /* Port function control register */ +#define PFC_PFC2C (PFC_BASE + 0x04B0) /* Port function control register */ +#define PFC_PFC2D (PFC_BASE + 0x04B4) /* Port function control register */ +#define PFC_PFC2E (PFC_BASE + 0x04B8) /* Port function control register */ +#define PFC_PFC2F (PFC_BASE + 0x04BC) /* Port function control register */ +#define PFC_PFC30 (PFC_BASE + 0x04C0) /* Port function control register */ +#define PFC_PFC31 (PFC_BASE + 0x04C4) /* Port function control register */ +#define PFC_PFC32 (PFC_BASE + 0x04C8) /* Port function control register */ +#define PFC_PFC33 (PFC_BASE + 0x04CC) /* Port function control register */ +#define PFC_PFC34 (PFC_BASE + 0x04D0) /* Port function control register */ +#define PFC_PFC35 (PFC_BASE + 0x04D4) /* Port function control register */ +#define PFC_PFC36 (PFC_BASE + 0x04D8) /* Port function control register */ +#define PFC_PFC37 (PFC_BASE + 0x04DC) /* Port function control register */ +#define PFC_PFC38 (PFC_BASE + 0x04E0) /* Port function control register */ +#define PFC_PFC39 (PFC_BASE + 0x04E4) /* Port function control register */ +#define PFC_PFC3A (PFC_BASE + 0x04E8) /* Port function control register */ +#define PFC_PFC3B (PFC_BASE + 0x04EC) /* Port function control register */ +#define PFC_PFC3C (PFC_BASE + 0x04F0) /* Port function control register */ +#define PFC_PFC3D (PFC_BASE + 0x04F4) /* Port function control register */ +#define PFC_PFC3E (PFC_BASE + 0x04F8) /* Port function control register */ +#define PFC_PFC3F (PFC_BASE + 0x04FC) /* Port function control register */ +#define PFC_PFC40 (PFC_BASE + 0x0500) /* Port function control register */ +#define PFC_IOLH02 (PFC_BASE + 0x1010) /* IOLH switch register */ +#define PFC_IOLH03 (PFC_BASE + 0x1018) /* IOLH switch register */ +#define PFC_IOLH04 (PFC_BASE + 0x1020) /* IOLH switch register */ +#define PFC_IOLH05 (PFC_BASE + 0x1028) /* IOLH switch register */ +#define PFC_IOLH06 (PFC_BASE + 0x1030) /* IOLH switch register */ +#define PFC_IOLH07 (PFC_BASE + 0x1038) /* IOLH switch register */ +#define PFC_IOLH08 (PFC_BASE + 0x1040) /* IOLH switch register */ +#define PFC_IOLH09 (PFC_BASE + 0x1048) /* IOLH switch register */ +#define PFC_IOLH0A (PFC_BASE + 0x1050) /* IOLH switch register */ +#define PFC_IOLH0B (PFC_BASE + 0x1058) /* IOLH switch register */ +#define PFC_IOLH0C (PFC_BASE + 0x1060) /* IOLH switch register */ +#define PFC_IOLH0D (PFC_BASE + 0x1068) /* IOLH switch register */ +#define PFC_IOLH10 (PFC_BASE + 0x1080) /* IOLH switch register */ +#define PFC_IOLH11 (PFC_BASE + 0x1088) /* IOLH switch register */ +#define PFC_IOLH12 (PFC_BASE + 0x1090) /* IOLH switch register */ +#define PFC_IOLH13 (PFC_BASE + 0x1098) /* IOLH switch register */ +#define PFC_IOLH14 (PFC_BASE + 0x10A0) /* IOLH switch register */ +#define PFC_IOLH15 (PFC_BASE + 0x10A8) /* IOLH switch register */ +#define PFC_IOLH16 (PFC_BASE + 0x10B0) /* IOLH switch register */ +#define PFC_IOLH17 (PFC_BASE + 0x10B8) /* IOLH switch register */ +#define PFC_IOLH18 (PFC_BASE + 0x10C0) /* IOLH switch register */ +#define PFC_IOLH19 (PFC_BASE + 0x10C8) /* IOLH switch register */ +#define PFC_IOLH1A (PFC_BASE + 0x10D0) /* IOLH switch register */ +#define PFC_IOLH1B (PFC_BASE + 0x10D8) /* IOLH switch register */ +#define PFC_IOLH1C (PFC_BASE + 0x10E0) /* IOLH switch register */ +#define PFC_IOLH1D (PFC_BASE + 0x10E8) /* IOLH switch register */ +#define PFC_IOLH1E (PFC_BASE + 0x10F0) /* IOLH switch register */ +#define PFC_IOLH1F (PFC_BASE + 0x10F8) /* IOLH switch register */ +#define PFC_IOLH20 (PFC_BASE + 0x1100) /* IOLH switch register */ +#define PFC_IOLH21 (PFC_BASE + 0x1108) /* IOLH switch register */ +#define PFC_IOLH22 (PFC_BASE + 0x1120) /* IOLH switch register */ +#define PFC_IOLH23 (PFC_BASE + 0x1128) /* IOLH switch register */ +#define PFC_IOLH36 (PFC_BASE + 0x11B0) /* IOLH switch register */ +#define PFC_IOLH37 (PFC_BASE + 0x11B8) /* IOLH switch register */ +#define PFC_IOLH38 (PFC_BASE + 0x11C0) /* IOLH switch register */ +#define PFC_IOLH39 (PFC_BASE + 0x11C8) /* IOLH switch register */ +#define PFC_IOLH3A (PFC_BASE + 0x11D0) /* IOLH switch register */ +#define PFC_IOLH3B (PFC_BASE + 0x11D8) /* IOLH switch register */ +#define PFC_IOLH3C (PFC_BASE + 0x11E0) /* IOLH switch register */ +#define PFC_IOLH3D (PFC_BASE + 0x11E8) /* IOLH switch register */ +#define PFC_IOLH3E (PFC_BASE + 0x11F0) /* IOLH switch register */ +#define PFC_IOLH3F (PFC_BASE + 0x11F8) /* IOLH switch register */ +#define PFC_IOLH40 (PFC_BASE + 0x1200) /* IOLH switch register */ +#define PFC_SR04 (PFC_BASE + 0x1420) /* Slew-Rate switch register */ +#define PFC_SR05 (PFC_BASE + 0x1428) /* Slew-Rate switch register */ +#define PFC_SR06 (PFC_BASE + 0x1430) /* Slew-Rate switch register */ +#define PFC_SR07 (PFC_BASE + 0x1438) /* Slew-Rate switch register */ +#define PFC_SR08 (PFC_BASE + 0x1440) /* Slew-Rate switch register */ +#define PFC_SR09 (PFC_BASE + 0x1448) /* Slew-Rate switch register */ +#define PFC_SR0A (PFC_BASE + 0x1450) /* Slew-Rate switch register */ +#define PFC_SR0B (PFC_BASE + 0x1458) /* Slew-Rate switch register */ +#define PFC_SR0C (PFC_BASE + 0x1460) /* Slew-Rate switch register */ +#define PFC_SR10 (PFC_BASE + 0x1480) /* Slew-Rate switch register */ +#define PFC_SR15 (PFC_BASE + 0x14A8) /* Slew-Rate switch register */ +#define PFC_SR16 (PFC_BASE + 0x14B0) /* Slew-Rate switch register */ +#define PFC_SR1A (PFC_BASE + 0x14D0) /* Slew-Rate switch register */ +#define PFC_SR1B (PFC_BASE + 0x14D8) /* Slew-Rate switch register */ +#define PFC_SR1C (PFC_BASE + 0x14E0) /* Slew-Rate switch register */ +#define PFC_SR1D (PFC_BASE + 0x14E8) /* Slew-Rate switch register */ +#define PFC_SR1E (PFC_BASE + 0x14F0) /* Slew-Rate switch register */ +#define PFC_SR1F (PFC_BASE + 0x14F8) /* Slew-Rate switch register */ +#define PFC_SR20 (PFC_BASE + 0x1500) /* Slew-Rate switch register */ +#define PFC_SR21 (PFC_BASE + 0x1508) /* Slew-Rate switch register */ +#define PFC_SR22 (PFC_BASE + 0x1510) /* Slew-Rate switch register */ +#define PFC_SR23 (PFC_BASE + 0x1518) /* Slew-Rate switch register */ +#define PFC_SR36 (PFC_BASE + 0x15B0) /* Slew-Rate switch register */ +#define PFC_SR37 (PFC_BASE + 0x15B8) /* Slew-Rate switch register */ +#define PFC_IEN06 (PFC_BASE + 0x1830) /* IEN switch register */ +#define PFC_IEN07 (PFC_BASE + 0x1838) /* IEN switch register */ +#define PFC_IEN08 (PFC_BASE + 0x1840) /* IEN switch register */ +#define PFC_IEN09 (PFC_BASE + 0x1848) /* IEN switch register */ +#define PFC_PUPD04 (PFC_BASE + 0x1C20) /* PU/PD switch register */ +#define PFC_PUPD05 (PFC_BASE + 0x1C28) /* PU/PD switch register */ +#define PFC_PUPD06 (PFC_BASE + 0x1C30) /* PU/PD switch register */ +#define PFC_PUPD07 (PFC_BASE + 0x1C38) /* PU/PD switch register */ +#define PFC_PUPD08 (PFC_BASE + 0x1C40) /* PU/PD switch register */ +#define PFC_PUPD09 (PFC_BASE + 0x1C48) /* PU/PD switch register */ +#define PFC_PUPD0A (PFC_BASE + 0x1C50) /* PU/PD switch register */ +#define PFC_PUPD0B (PFC_BASE + 0x1C58) /* PU/PD switch register */ +#define PFC_PUPD0C (PFC_BASE + 0x1C60) /* PU/PD switch register */ +#define PFC_PUPD10 (PFC_BASE + 0x1C80) /* PU/PD switch register */ +#define PFC_PUPD15 (PFC_BASE + 0x1CA8) /* PU/PD switch register */ +#define PFC_PUPD16 (PFC_BASE + 0x1CB0) /* PU/PD switch register */ +#define PFC_PUPD1A (PFC_BASE + 0x1CD0) /* PU/PD switch register */ +#define PFC_PUPD1B (PFC_BASE + 0x1CD8) /* PU/PD switch register */ +#define PFC_PUPD1C (PFC_BASE + 0x1CE0) /* PU/PD switch register */ +#define PFC_PUPD1D (PFC_BASE + 0x1CE8) /* PU/PD switch register */ +#define PFC_PUPD1E (PFC_BASE + 0x1CF0) /* PU/PD switch register */ +#define PFC_PUPD1F (PFC_BASE + 0x1CF8) /* PU/PD switch register */ +#define PFC_PUPD20 (PFC_BASE + 0x1D00) /* PU/PD switch register */ +#define PFC_PUPD21 (PFC_BASE + 0x1D08) /* PU/PD switch register */ +#define PFC_PUPD22 (PFC_BASE + 0x1D10) /* PU/PD switch register */ +#define PFC_PUPD23 (PFC_BASE + 0x1D18) /* PU/PD switch register */ +#define PFC_PUPD36 (PFC_BASE + 0x1DB0) /* PU/PD switch register */ +#define PFC_PUPD37 (PFC_BASE + 0x1DB8) /* PU/PD switch register */ +#define PFC_SD_ch0 (PFC_BASE + 0x3000) /* SD ch0 IO voltage control register */ +#define PFC_SD_ch1 (PFC_BASE + 0x3004) /* SD ch1 IO voltage control register */ +#define PFC_QSPI (PFC_BASE + 0x3008) /* QSPI IO voltage control register */ +#define PFC_ETH_ch0 (PFC_BASE + 0x300C) /* ETH ch0 voltage control register */ +#define PFC_ETH_ch1 (PFC_BASE + 0x3010) /* ETH ch1 voltage control register */ +#define PFC_PWPR (PFC_BASE + 0x3014) /* Write protect */ +#define PFC_FILONOFF01 (PFC_BASE + 0x2008) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF10 (PFC_BASE + 0x2080) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF11 (PFC_BASE + 0x2088) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF12 (PFC_BASE + 0x2090) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF13 (PFC_BASE + 0x2098) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF14 (PFC_BASE + 0x20A0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF15 (PFC_BASE + 0x20A8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF16 (PFC_BASE + 0x20B0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF17 (PFC_BASE + 0x20B8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF18 (PFC_BASE + 0x20C0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF19 (PFC_BASE + 0x20C8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1A (PFC_BASE + 0x20D0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1B (PFC_BASE + 0x20D8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1C (PFC_BASE + 0x20E0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1D (PFC_BASE + 0x20E8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1E (PFC_BASE + 0x20F0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1F (PFC_BASE + 0x20F8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF20 (PFC_BASE + 0x2100) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF21 (PFC_BASE + 0x2108) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF22 (PFC_BASE + 0x2110) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF23 (PFC_BASE + 0x2118) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF24 (PFC_BASE + 0x2120) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF25 (PFC_BASE + 0x2128) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF26 (PFC_BASE + 0x2130) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF27 (PFC_BASE + 0x2138) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF28 (PFC_BASE + 0x2140) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF29 (PFC_BASE + 0x2148) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2A (PFC_BASE + 0x2150) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2B (PFC_BASE + 0x2158) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2C (PFC_BASE + 0x2160) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2D (PFC_BASE + 0x2168) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2E (PFC_BASE + 0x2170) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2F (PFC_BASE + 0x2178) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF30 (PFC_BASE + 0x2180) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF31 (PFC_BASE + 0x2188) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF32 (PFC_BASE + 0x2190) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF33 (PFC_BASE + 0x2198) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF34 (PFC_BASE + 0x21A0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF35 (PFC_BASE + 0x21A8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF36 (PFC_BASE + 0x21B0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF37 (PFC_BASE + 0x21B8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF38 (PFC_BASE + 0x21C0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF39 (PFC_BASE + 0x21C8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3A (PFC_BASE + 0x21D0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3B (PFC_BASE + 0x21D8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3C (PFC_BASE + 0x21E0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3D (PFC_BASE + 0x21E8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3E (PFC_BASE + 0x21F0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3F (PFC_BASE + 0x21F8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF40 (PFC_BASE + 0x2200) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILNUM01 (PFC_BASE + 0x2408) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM10 (PFC_BASE + 0x2480) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM11 (PFC_BASE + 0x2488) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM12 (PFC_BASE + 0x2490) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM13 (PFC_BASE + 0x2498) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM14 (PFC_BASE + 0x24A0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM15 (PFC_BASE + 0x24A8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM16 (PFC_BASE + 0x24B0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM17 (PFC_BASE + 0x24B8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM18 (PFC_BASE + 0x24C0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM19 (PFC_BASE + 0x24C8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1A (PFC_BASE + 0x24D0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1B (PFC_BASE + 0x24D8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1C (PFC_BASE + 0x24E0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1D (PFC_BASE + 0x24E8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1E (PFC_BASE + 0x24F0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1F (PFC_BASE + 0x24F8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM20 (PFC_BASE + 0x2500) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM21 (PFC_BASE + 0x2508) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM22 (PFC_BASE + 0x2510) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM23 (PFC_BASE + 0x2518) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM24 (PFC_BASE + 0x2520) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM25 (PFC_BASE + 0x2528) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM26 (PFC_BASE + 0x2530) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM27 (PFC_BASE + 0x2538) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM28 (PFC_BASE + 0x2540) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM29 (PFC_BASE + 0x2548) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2A (PFC_BASE + 0x2550) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2B (PFC_BASE + 0x2558) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2C (PFC_BASE + 0x2560) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2D (PFC_BASE + 0x2568) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2E (PFC_BASE + 0x2570) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2F (PFC_BASE + 0x2578) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM30 (PFC_BASE + 0x2580) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM31 (PFC_BASE + 0x2588) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM32 (PFC_BASE + 0x2590) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM33 (PFC_BASE + 0x2598) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM34 (PFC_BASE + 0x25A0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM35 (PFC_BASE + 0x25A8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM36 (PFC_BASE + 0x25B0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM37 (PFC_BASE + 0x25B8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM38 (PFC_BASE + 0x25C0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM39 (PFC_BASE + 0x25C8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3A (PFC_BASE + 0x25D0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3B (PFC_BASE + 0x25D8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3C (PFC_BASE + 0x25E0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3D (PFC_BASE + 0x25E8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3E (PFC_BASE + 0x25F0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3F (PFC_BASE + 0x25F8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM40 (PFC_BASE + 0x2600) /* Digital noise filter (FILNUM) register */ +#define PFC_FILCLKSEL01 (PFC_BASE + 0x2808) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL10 (PFC_BASE + 0x2880) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL11 (PFC_BASE + 0x2888) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL12 (PFC_BASE + 0x2890) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL13 (PFC_BASE + 0x2898) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL14 (PFC_BASE + 0x28A0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL15 (PFC_BASE + 0x28A8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL16 (PFC_BASE + 0x28B0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL17 (PFC_BASE + 0x28B8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL18 (PFC_BASE + 0x28C0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL19 (PFC_BASE + 0x28C8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1A (PFC_BASE + 0x28D0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1B (PFC_BASE + 0x28D8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1C (PFC_BASE + 0x28E0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1D (PFC_BASE + 0x28E8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1E (PFC_BASE + 0x28F0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1F (PFC_BASE + 0x28F8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL20 (PFC_BASE + 0x2900) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL21 (PFC_BASE + 0x2908) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL22 (PFC_BASE + 0x2910) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL23 (PFC_BASE + 0x2918) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL24 (PFC_BASE + 0x2920) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL25 (PFC_BASE + 0x2928) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL26 (PFC_BASE + 0x2930) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL27 (PFC_BASE + 0x2938) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL28 (PFC_BASE + 0x2940) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL29 (PFC_BASE + 0x2948) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2A (PFC_BASE + 0x2950) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2B (PFC_BASE + 0x2958) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2C (PFC_BASE + 0x2960) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2D (PFC_BASE + 0x2968) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2E (PFC_BASE + 0x2970) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2F (PFC_BASE + 0x2978) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL30 (PFC_BASE + 0x2980) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL31 (PFC_BASE + 0x2988) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL32 (PFC_BASE + 0x2990) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL33 (PFC_BASE + 0x2998) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL34 (PFC_BASE + 0x29A0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL35 (PFC_BASE + 0x29A8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL36 (PFC_BASE + 0x29B0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL37 (PFC_BASE + 0x29B8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL38 (PFC_BASE + 0x29C0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL39 (PFC_BASE + 0x29C8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3A (PFC_BASE + 0x29D0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3B (PFC_BASE + 0x29D8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3C (PFC_BASE + 0x29E0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3D (PFC_BASE + 0x29E8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3E (PFC_BASE + 0x29F0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3F (PFC_BASE + 0x29F8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL40 (PFC_BASE + 0x2A00) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_ETH_MII (PFC_BASE + 0x3018) /* Register for setting the mode of ETH MII / RGMII */ + +/* Combined terminal setting */ +/* Definition for port register */ +#define P_P0 (1 << 0) +#define P_P1 (1 << 1) +#define P_P2 (1 << 2) +#define P_P3 (1 << 3) +#define P_P4 (1 << 4) +#define P_P5 (1 << 5) +#define P_P6 (1 << 6) +#define P_P7 (1 << 7) +/* Definition for port mode register */ +#define PM0_HIZ (0 << 0) +#define PM0_IN (1 << 0) +#define PM0_OUT_DIS (2 << 0) +#define PM0_OUT_EN (3 << 0) +#define PM1_HIZ (0 << 2) +#define PM1_IN (1 << 2) +#define PM1_OUT_DIS (2 << 2) +#define PM1_OUT_EN (3 << 2) +#define PM2_HIZ (0 << 4) +#define PM2_IN (1 << 4) +#define PM2_OUT_DIS (2 << 4) +#define PM2_OUT_EN (3 << 4) +#define PM3_HIZ (0 << 6) +#define PM3_IN (1 << 6) +#define PM3_OUT_DIS (2 << 6) +#define PM3_OUT_EN (3 << 6) +#define PM4_HIZ (0 << 8) +#define PM4_IN (1 << 8) +#define PM4_OUT_DIS (2 << 8) +#define PM4_OUT_EN (3 << 8) +/* Definition for port mode control register */ +#define PMC_PMC0 (1 << 0) +#define PMC_PMC1 (1 << 1) +#define PMC_PMC2 (1 << 2) +#define PMC_PMC3 (1 << 3) +#define PMC_PMC4 (1 << 4) +#define PMC_PMC5 (1 << 5) +#define PMC_PMC6 (1 << 6) +#define PMC_PMC7 (1 << 7) +/* Definition for port function control register */ +#define PFC0_MODE0 (0 << 0) +#define PFC0_MODE1 (1 << 0) +#define PFC0_MODE2 (2 << 0) +#define PFC0_MODE3 (3 << 0) +#define PFC0_MODE4 (4 << 0) +#define PFC0_MODE5 (5 << 0) +#define PFC1_MODE0 (0 << 4) +#define PFC1_MODE1 (1 << 4) +#define PFC1_MODE2 (2 << 4) +#define PFC1_MODE3 (3 << 4) +#define PFC1_MODE4 (4 << 4) +#define PFC1_MODE5 (5 << 4) +#define PFC2_MODE0 (0 << 8) +#define PFC2_MODE1 (1 << 8) +#define PFC2_MODE2 (2 << 8) +#define PFC2_MODE3 (3 << 8) +#define PFC2_MODE4 (4 << 8) +#define PFC2_MODE5 (5 << 8) +#define PFC3_MODE0 (0 << 12) +#define PFC3_MODE1 (1 << 12) +#define PFC3_MODE2 (2 << 12) +#define PFC3_MODE3 (3 << 12) +#define PFC3_MODE4 (4 << 12) +#define PFC3_MODE5 (5 << 12) +#define PFC4_MODE0 (0 << 16) +#define PFC4_MODE1 (1 << 16) +#define PFC4_MODE2 (2 << 16) +#define PFC4_MODE3 (3 << 16) +#define PFC4_MODE4 (4 << 16) +#define PFC4_MODE5 (5 << 16) +/* Definition for IOLH switch register */ +#define IOLH0_2MA (0 << 0) +#define IOLH0_4MA (1 << 0) +#define IOLH0_8MA (2 << 0) +#define IOLH0_12MA (3 << 0) +#define IOLH1_2MA (0 << 8) +#define IOLH1_4MA (1 << 8) +#define IOLH1_8MA (2 << 8) +#define IOLH1_12MA (3 << 8) +#define IOLH2_2MA (0 << 16) +#define IOLH2_4MA (1 << 16) +#define IOLH2_8MA (2 << 16) +#define IOLH2_12MA (3 << 16) +#define IOLH3_2MA (0 << 24) +#define IOLH3_4MA (1 << 24) +#define IOLH3_8MA (2 << 24) +#define IOLH3_12MA (3 << 24) +#define IOLH4_2MA (0 << 32) +#define IOLH4_4MA (1 << 32) +#define IOLH4_8MA (2 << 32) +#define IOLH4_12MA (3 << 32) +#define IOLH5_2MA (0 << 40) +#define IOLH5_4MA (1 << 40) +#define IOLH5_8MA (2 << 40) +#define IOLH5_12MA (3 << 40) +#define IOLH6_2MA (0 << 48) +#define IOLH6_4MA (1 << 48) +#define IOLH6_8MA (2 << 48) +#define IOLH6_12MA (3 << 48) +#define IOLH7_2MA (0 << 56) +#define IOLH7_4MA (1 << 56) +#define IOLH7_8MA (2 << 56) +#define IOLH7_12MA (3 << 56) +/* Definition for Slew-Rate switch register */ +#define SR0_FAST (1 << 0) +#define SR1_FAST (1 << 8) +#define SR2_FAST (1 << 16) +#define SR3_FAST (1 << 24) +#define SR4_FAST (1 << 32) +#define SR5_FAST (1 << 40) +#define SR6_FAST (1 << 48) +#define SR7_FAST (1 << 56) +/* Definition for IEN switching register */ +#define IEN0_ENABLE (1 << 0) +#define IEN1_ENABLE (1 << 8) +#define IEN2_ENABLE (1 << 16) +#define IEN3_ENABLE (1 << 24) +#define IEN4_ENABLE (1 << 32) +#define IEN5_ENABLE (1 << 40) +#define IEN6_ENABLE (1 << 48) +#define IEN7_ENABLE (1 << 56) +/* Definition for PUPD switching register */ +#define PUPD0_NO (0 << 0) +#define PUPD0_UP (1 << 0) +#define PUPD0_DOWN (2 << 0) +#define PUPD1_NO (0 << 8) +#define PUPD1_UP (1 << 8) +#define PUPD1_DOWN (2 << 8) +#define PUPD2_NO (0 << 16) +#define PUPD2_UP (1 << 16) +#define PUPD2_DOWN (2 << 16) +#define PUPD3_NO (0 << 24) +#define PUPD3_UP (1 << 24) +#define PUPD3_DOWN (2 << 24) +#define PUPD4_NO (0 << 32) +#define PUPD4_UP (1 << 32) +#define PUPD4_DOWN (2 << 32) +#define PUPD5_NO (0 << 40) +#define PUPD5_UP (1 << 40) +#define PUPD5_DOWN (2 << 40) +#define PUPD6_NO (0 << 48) +#define PUPD6_UP (1 << 48) +#define PUPD6_DOWN (2 << 48) +#define PUPD7_NO (0 << 56) +#define PUPD7_UP (1 << 56) +#define PUPD7_DOWN (2 << 56) +/* SD ch0 IO Definition for voltage control register */ +#define SD0_PVDD (1 << 0) +/* SD ch1 IO Definition for voltage control register */ +#define SD1_PVDD (1 << 0) +/* Definition for QSPI IO voltage control register */ +#define QSPI_PVDD (1 << 0) +/* ETH ch0 voltage control register */ +#define ETH_ch0_3_3 (0 << 0) +#define ETH_ch0_1_8 (1 << 0) +#define ETH_ch0_2_5 (2 << 0) +/* ETH ch1 voltage control register */ +#define ETH_ch1_3_3 (0 << 0) +#define ETH_ch1_1_8 (1 << 0) +#define ETH_ch1_2_5 (2 << 0) +/* Write protection definition */ +#define PWPR_B0Wl (1 << 7) +#define PWPR_PFCWE (1 << 6) +/* Digital noise filter (FILONOFF) register */ +#define FILONOFF_FILON0 (1 << 0) +#define FILONOFF_FILON1 (1 << 8) +#define FILONOFF_FILON2 (1 << 16) +#define FILONOFF_FILON3 (1 << 24) +#define FILONOFF_FILON4 (1 << 32) +#define FILONOFF_FILON5 (1 << 40) +#define FILONOFF_FILON6 (1 << 48) +#define FILONOFF_FILON7 (1 << 56) +/* Digital noise filter (FILNUM) register */ +#define FILNUM_FILNUM0_4 (0 << 0) +#define FILNUM_FILNUM0_8 (1 << 0) +#define FILNUM_FILNUM0_12 (2 << 0) +#define FILNUM_FILNUM0_16 (3 << 0) +#define FILNUM_FILNUM1_4 (0 << 8) +#define FILNUM_FILNUM1_8 (1 << 8) +#define FILNUM_FILNUM1_12 (2 << 8) +#define FILNUM_FILNUM1_16 (3 << 8) +#define FILNUM_FILNUM2_4 (0 << 16) +#define FILNUM_FILNUM2_8 (1 << 16) +#define FILNUM_FILNUM2_12 (2 << 16) +#define FILNUM_FILNUM2_16 (3 << 16) +#define FILNUM_FILNUM3_4 (0 << 24) +#define FILNUM_FILNUM3_8 (1 << 24) +#define FILNUM_FILNUM3_12 (2 << 24) +#define FILNUM_FILNUM3_16 (3 << 24) +#define FILNUM_FILNUM4_4 (0 << 32) +#define FILNUM_FILNUM4_8 (1 << 32) +#define FILNUM_FILNUM4_12 (2 << 32) +#define FILNUM_FILNUM4_16 (3 << 32) +#define FILNUM_FILNUM5_4 (0 << 40) +#define FILNUM_FILNUM5_8 (1 << 40) +#define FILNUM_FILNUM5_12 (2 << 40) +#define FILNUM_FILNUM5_16 (3 << 40) +#define FILNUM_FILNUM6_4 (0 << 48) +#define FILNUM_FILNUM6_8 (1 << 48) +#define FILNUM_FILNUM6_12 (2 << 48) +#define FILNUM_FILNUM6_16 (3 << 48) +#define FILNUM_FILNUM7_4 (0 << 56) +#define FILNUM_FILNUM7_8 (1 << 56) +#define FILNUM_FILNUM7_12 (2 << 56) +#define FILNUM_FILNUM7_16 (3 << 56) +/* Digital noise filter (FILCLKSEL) register */ +#define FILCLKSEL_FILCLK0_0 (0 << 0) +#define FILCLKSEL_FILCLK0_1 (1 << 0) +#define FILCLKSEL_FILCLK0_2 (2 << 0) +#define FILCLKSEL_FILCLK0_3 (3 << 0) +#define FILCLKSEL_FILCLK1_0 (0 << 8) +#define FILCLKSEL_FILCLK1_1 (1 << 8) +#define FILCLKSEL_FILCLK1_2 (2 << 8) +#define FILCLKSEL_FILCLK1_3 (3 << 8) +#define FILCLKSEL_FILCLK2_0 (0 << 16) +#define FILCLKSEL_FILCLK2_1 (1 << 16) +#define FILCLKSEL_FILCLK2_2 (2 << 16) +#define FILCLKSEL_FILCLK2_3 (3 << 16) +#define FILCLKSEL_FILCLK3_0 (0 << 24) +#define FILCLKSEL_FILCLK3_1 (1 << 24) +#define FILCLKSEL_FILCLK3_2 (2 << 24) +#define FILCLKSEL_FILCLK3_3 (3 << 24) +#define FILCLKSEL_FILCLK4_0 (0 << 32) +#define FILCLKSEL_FILCLK4_1 (1 << 32) +#define FILCLKSEL_FILCLK4_2 (2 << 32) +#define FILCLKSEL_FILCLK4_3 (3 << 32) +#define FILCLKSEL_FILCLK5_0 (0 << 40) +#define FILCLKSEL_FILCLK5_1 (1 << 40) +#define FILCLKSEL_FILCLK5_2 (2 << 40) +#define FILCLKSEL_FILCLK5_3 (3 << 40) +#define FILCLKSEL_FILCLK6_0 (0 << 48) +#define FILCLKSEL_FILCLK6_1 (1 << 48) +#define FILCLKSEL_FILCLK6_2 (2 << 48) +#define FILCLKSEL_FILCLK6_3 (3 << 48) +#define FILCLKSEL_FILCLK7_0 (0 << 56) +#define FILCLKSEL_FILCLK7_1 (1 << 56) +#define FILCLKSEL_FILCLK7_2 (2 << 56) +#define FILCLKSEL_FILCLK7_3 (3 << 56) +/* Register for setting the mode of ETH MII / RGMII */ +#define ETH_MII_0_MII (1 << 0) +#define ETH_MII_1_MII (1 << 1) + +#define PFC_SET_TBL_NUM (11) +#define PFC_OFF (0) +#define PFC_ON (1) + +#define PFC_MUX_TBL_NUM (4) +#define PFC_QSPI_TBL_NUM (3) +#define PFC_SD_TBL_NUM (4) + +typedef struct { + int flg; + uintptr_t reg; + uint8_t val; +} PFC_REG_UINT8; + +typedef struct { + int flg; + uintptr_t reg; + uint32_t val; +} PFC_REG_UINT32; + +typedef struct { + int flg; + uintptr_t reg; + uint64_t val; +} PFC_REG_UINT64; + + +typedef struct { + PFC_REG_UINT8 pmc; + PFC_REG_UINT32 pfc; + PFC_REG_UINT64 iolh; + PFC_REG_UINT64 pupd; + PFC_REG_UINT64 sr; + PFC_REG_UINT64 ien; +} PFC_REGS; + + +#endif /* __PFC_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/plat_macros.S b/plat/renesas/rza/common/include/plat_macros.S new file mode 100644 index 0000000000..89a0b0c236 --- /dev/null +++ b/plat/renesas/rza/common/include/plat_macros.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + + .macro plat_crash_print_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/renesas/rza/common/include/plat_tzc_def.h b/plat/renesas/rza/common/include/plat_tzc_def.h new file mode 100644 index 0000000000..9c8c396fa3 --- /dev/null +++ b/plat/renesas/rza/common/include/plat_tzc_def.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_TZC_DEF_H +#define PLAT_TZC_DEF_H + +/* Platform specific TrsutZone setup constants */ + +#define PLAT_TZC_REGION_ACCESS_ID_MASK U(0x3) +#define PLAT_TZC_REGION_ACCESS_RDWR(nsaid) \ + (TZC_REGION_ACCESS_RDWR(nsaid & PLAT_TZC_REGION_ACCESS_ID_MASK)) + +#define PLAT_TZC_REGION_ACCESS_S_PRIV \ + (PLAT_TZC_REGION_ACCESS_RDWR(0x1)) +#define PLAT_TZC_REGION_ACCESS_S_UNPRIV \ + (PLAT_TZC_REGION_ACCESS_RDWR(0x0) | PLAT_TZC_REGION_ACCESS_S_PRIV) +#define PLAT_TZC_REGION_ACCESS_NS_PRIV \ + (PLAT_TZC_REGION_ACCESS_RDWR(0x3) | PLAT_TZC_REGION_ACCESS_S_UNPRIV) +#define PLAT_TZC_REGION_ACCESS_NS_UNPRIV \ + (PLAT_TZC_REGION_ACCESS_RDWR(0x2) | PLAT_TZC_REGION_ACCESS_NS_PRIV) + +/* AP shared secure SRAM1 0x00010000 - 0x0001FFFF */ +#define PLAT_AP_TZC_PROT_SRAM1_BASE (0x00010000) +#define PLAT_AP_TZC_PROT_SRAM1_SIZE (0x00010000) +#define PLAT_AP_TZC_PROT_SRAM1_END \ + (PLAT_AP_TZC_PROT_SRAM1_BASE + PLAT_AP_TZC_PROT_SRAM1_SIZE - 1) + +/* AP shared secure SRAM2 0x00020000 - 0x0002FFFF */ +#define PLAT_AP_TZC_PROT_SRAM2_BASE (0x00020000) +#define PLAT_AP_TZC_PROT_SRAM2_SIZE (0x00010000) +#define PLAT_AP_TZC_PROT_SRAM2_END \ + (PLAT_AP_TZC_PROT_SRAM2_BASE + PLAT_AP_TZC_PROT_SRAM2_SIZE - 1) + +/* Trusted Firmware(BL31) secure DRAM 0x43F00000 - 0x440FFFFF */ +#define PLAT_FW_TZC_PROT_DRAM1_BASE (0x43F00000) +#define PLAT_FW_TZC_PROT_DRAM1_SIZE (0x00200000) +#define PLAT_FW_TZC_PROT_DRAM1_END \ + (PLAT_FW_TZC_PROT_DRAM1_BASE + PLAT_FW_TZC_PROT_DRAM1_SIZE - 1) + +/* OP-TEE secure DRAM 0x44100000 - 0x47DFFFFF */ +#define PLAT_TEE_TZC_PROT_DRAM1_BASE (0x44100000) +#define PLAT_TEE_TZC_PROT_DRAM1_SIZE (0x03D00000) +#define PLAT_TEE_TZC_PROT_DRAM1_END \ + (PLAT_TEE_TZC_PROT_DRAM1_BASE + PLAT_TEE_TZC_PROT_DRAM1_SIZE - 1) + +void plat_security_setup(void); + +#endif /* PLAT_TZC_DEF_H */ diff --git a/plat/renesas/rza/common/include/rz_private.h b/plat/renesas/rza/common/include/rz_private.h new file mode 100644 index 0000000000..5866b6bae2 --- /dev/null +++ b/plat/renesas/rza/common/include/rz_private.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __RZ_PRIVATE_H__ +#define __RZ_PRIVATE_H__ + +#include + +/* plat_gic.c */ +void plat_gic_driver_init(void); +void plat_gic_init(void); +void plat_gic_cpuif_enable(void); +void plat_gic_cpuif_disable(void); +void plat_gic_pcpu_init(void); + +/* plat_security.c */ +void plat_tzc400_setup(uintptr_t tzc_base); + +/* plat_storage.c */ +void rz_io_setup(void); + +/* plat_image_load.c */ +#if (APPLOAD == RZ_NOFIP) +void rza_load_fsp(void); +#endif /* (APPLOAD == RZ_NOFIP) */ +void rza_print_descs(void); + +#if RZ_TEST +void rz_run_tests(void); +#define RZ_RUN_TESTS() rz_run_tests() +#else +#define RZ_RUN_TESTS() /* dummy */ +#endif /* RZ_FLASH_TEST */ + +typedef struct bl2_to_bl31_params_mem { + entry_point_info_t bl32_ep_info; + entry_point_info_t bl33_ep_info; +} bl2_to_bl31_params_mem_t; + +#endif /* __RZ_PRIVATE_H__ */ diff --git a/plat/renesas/rza/common/include/rz_sip_svc.h b/plat/renesas/rza/common/include/rz_sip_svc.h new file mode 100644 index 0000000000..42ce446288 --- /dev/null +++ b/plat/renesas/rza/common/include/rz_sip_svc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __RZ_SIP_SVC_H__ +#define __RZ_SIP_SVC_H__ + +/* Function ID to get Device ID */ +#define RZ_SIP_SVC_GET_DEVID U(0x82000010) + +/* Function ID to get Chip ID */ +#define RZ_SIP_SVC_GET_CHIPID U(0x82000011) + +#endif /* __RZ_SIP_SVC_H__ */ diff --git a/plat/renesas/rza/common/include/rza_ipl_version.h b/plat/renesas/rza/common/include/rza_ipl_version.h new file mode 100644 index 0000000000..fd20441c1c --- /dev/null +++ b/plat/renesas/rza/common/include/rza_ipl_version.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RZA_IPL_VERSION_H_ +#define _RZA_IPL_VERSION_H_ + +#define RZA_IPL_VERSION_STRING "v2.1.0" + +#endif /* _RZA_IPL_VERSION_H_ */ diff --git a/plat/renesas/rza/common/include/rza_mmu.h b/plat/renesas/rza/common/include/rza_mmu.h new file mode 100644 index 0000000000..a7528ab4da --- /dev/null +++ b/plat/renesas/rza/common/include/rza_mmu.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RZA_MMU_H_ +#define _RZA_MMU_H_ + +#include "platform_def.h" + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* descripter bits define */ +#define RZA_MMU_DESC_XN (1 << 54) +#define RZA_MMU_DESC_PXN (1 << 53) +#define RZA_MMU_DESC_AF (1 << 10) +#define RZA_MMU_DESC_SH_NS (0 << 8) +#define RZA_MMU_DESC_SH_OS (2 << 8) +#define RZA_MMU_DESC_SH_IS (3 << 8) +#define RZA_MMU_DESC_AP_RW_NONE (0 << 6) +#define RZA_MMU_DESC_AP_RW_RW (1 << 6) +#define RZA_MMU_DESC_AP_RO_NONE (2 << 6) +#define RZA_MMU_DESC_AP_RO_RO (3 << 6) +#define RZA_MMU_DESC_NS (1 << 5) + +/* descripter index for MAIR register */ +#define RZA_MMU_DESC_MAIR_INDEX_0 (0 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_1 (1 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_2 (2 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_3 (3 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_4 (4 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_5 (5 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_6 (6 << 2) +#define RZA_MMU_DESC_MAIR_INDEX_7 (7 << 2) + +/* index number each memory type + * 0: normal memory, cacheable + * 1: device + * 2: normal memory, non-cacheable + */ +#define RZA_MMU_ATTR_NON_CACHEABLE_INDEX (2) +#define RZA_MMU_ATTR_DEVICE_INDEX (1) +#define RZA_MMU_ATTR_IWBWA_OWBWA_NTR_INDEX (0) + +/* Normal Memory, Outer/Inner Non-cacheable */ +#define RZA_MMU_ATTR_NON_CACHEABLE \ + MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) +/* Device */ +#define RZA_MMU_ATTR_DEVICE MAIR_DEV_nGnRE +/* Normal Memory, Outer/Inner Write-Back */ +#define RZA_MMU_ATTR_IWBWA_OWBWA_NTR \ + MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA) + +#define RZA_MMU_ATTR_FIELD_WIDTH (8) +#define RZA_MMU_MAIR_ATTR_SET(attr, index) \ + ((attr) << ((index) * RZA_MMU_ATTR_FIELD_WIDTH)) + +#define RZA_MMU_ATTR_NEXT_TBL (0x03) + +/* descripter entry type */ +#define RZA_MMU_DESC_TABLE_DESC (3 << 0) +#define RZA_MMU_DESC_BLOCK_ENTRY_L12 (1 << 0) +#define RZA_MMU_DESC_BLOCK_ENTRY_L3 (3 << 0) + +/* max address */ +#define RZA_MMU_PHY_ADDR_MAX (PLAT_PHY_ADDR_SPACE_SIZE - 1) +#define RZA_MMU_VIRT_ADDR_MAX (PLAT_VIRT_ADDR_SPACE_SIZE - 1) +#define RZA_MMU_PHY_SIZE_MAX (PLAT_PHY_ADDR_SPACE_SIZE) +#define RZA_MMU_VIRT_SIZE_MAX (PLAT_VIRT_ADDR_SPACE_SIZE) + +/* exception evel */ +#define RZA_MMU_CURRENT_EL0 (0x00) +#define RZA_MMU_CURRENT_EL1 (0x04) +#define RZA_MMU_CURRENT_EL2 (0x08) +#define RZA_MMU_CURRENT_EL3 (0x0C) + +/* Virtual space size per entry each level */ +#define RZA_MMU_L1_ENTRY_SIZE (0x40000000) /* 1GB */ +#define RZA_MMU_L2_ENTRY_SIZE (0x00200000) /* 2MB */ +#define RZA_MMU_L3_ENTRY_SIZE (0x00001000) /* 4KB */ + +/* descripter size (byte) */ +#define RZA_MMU_TABLE_DESC_SIZE (8) + +/* start virtual address each blocks */ +#define RZA_MMU_N1_TABLE_START_VADDR (0x00000000) +#define RZA_MMU_N2_TABLE_START_VADDR (0x40000000) +#define RZA_MMU_N3_TABLE_START_VADDR (0x80000000) +#define RZA_MMU_N4_TABLE_START_VADDR (0xC0000000) + +/* width of virtual space each blocks */ +#define RZA_MMU_TTB_BLOCK_WIDTH (0x40000000) + +#define RZA_MMU_LEVEL2_TABLE_INDEX_MAX (4) +#define RZA_MMU_TABLE_ENTRY (512) + +/* MMU attribute setting (user setting) */ +#define RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE \ + (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ + RZA_MMU_DESC_MAIR_INDEX_0) +#define RZA_MMU_ATTRIBUTE_NORMAL_UNCACHE \ + (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ + RZA_MMU_DESC_MAIR_INDEX_2) +#define RZA_MMU_ATTRIBUTE_DEVICE \ + (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ + RZA_MMU_DESC_MAIR_INDEX_1) +#define RZA_MMU_ATTRIBUTE_ACCESS_FAULT (0x00000000) +#define RZA_MMU_ATTRIBUTE_CONFIG_END (0xFFFFFFFF) + +/* xSPI device extended configuration structure */ +typedef struct mmu_pagetable_config { + uint64_t vaddress; + uint64_t paddress; + uint64_t size; + uint64_t attribute; +} rza_mmu_pgtbl_cfg_t; + +/* external functions */ +int plat_mmu_init(const rza_mmu_pgtbl_cfg_t *config_table); +void plat_mmu_enable(void); + +#endif /* _RZA_MMU_H_ */ diff --git a/plat/renesas/rza/common/include/rza_printf.h b/plat/renesas/rza/common/include/rza_printf.h new file mode 100644 index 0000000000..dd98c74753 --- /dev/null +++ b/plat/renesas/rza/common/include/rza_printf.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RZA_PRINTF_H_ +#define _RZA_PRINTF_H_ + +#include + +/* This header file defines printf that outputs logs with RZ/A3UL. */ + +#define RZ_UNUSED_PARAM(param) (void)(param) +#define STRING(str) #str + +#if (RZA3 == 1) +#if (DEBUG == 1) +#define RZA_PRINTF_VERBOSE(...) printf(__VA_ARGS__) +#else +#define RZA_PRINTF_VERBOSE(...) +#endif /* DEBUG == 1 */ + +#define RZA_PRINTF(...) printf(__VA_ARGS__) +#define RZA_PRINTF_NOTICE(...) RZA_PRINTF_VERBOSE(__VA_ARGS__) +#define RZA_PRINTF_ERROR(...) RZA_PRINTF_VERBOSE(__VA_ARGS__) +#define RZA_PRINTF_WARN(...) RZA_PRINTF_VERBOSE(__VA_ARGS__) +#define RZA_PRINTF_INFO(...) RZA_PRINTF_VERBOSE(__VA_ARGS__) +#else + +#define RZA_PRINTF_VERBOSE(...) +#define RZA_PRINTF(...) +#define RZA_PRINTF_NOTICE(...) NOTICE(__VA_ARGS__) +#define RZA_PRINTF_ERROR(...) ERROR(__VA_ARGS__) +#define RZA_PRINTF_WARN(...) WARN(__VA_ARGS__) +#define RZA_PRINTF_INFO(...) INFO(__VA_ARGS__) + +#endif /* RZA3 == 1 */ + +#endif /* _RZA_PRINTF_H_ */ diff --git a/plat/renesas/rza/common/include/scifa.h b/plat/renesas/rza/common/include/scifa.h new file mode 100644 index 0000000000..80636c6991 --- /dev/null +++ b/plat/renesas/rza/common/include/scifa.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SCIFA_H__ +#define __SCIFA_H__ + +#ifndef __ASSEMBLER__ + +#include +#include + +int console_rza_register(uintptr_t baseaddr, uint32_t clock, + uint32_t baud, console_t *console); + +#endif /* __ASSEMBLER__ */ + +#endif /* __SCIFA_H__ */ diff --git a/plat/renesas/rza/common/include/spim.h b/plat/renesas/rza/common/include/spim.h new file mode 100644 index 0000000000..bcb3d36d77 --- /dev/null +++ b/plat/renesas/rza/common/include/spim.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SPIM_API_H_ +#define _SPIM_API_H_ +#include +#include + +#include "xspi_api.h" + +/** xSPI device control structure */ +typedef struct st_spim_ctrl { + bool opened; + uintptr_t reg_base; + uintptr_t mmap_base; + size_t mmap_size; + uint8_t channel; +} spim_ctrl_t; + +/** xSPI device extended configuration structure */ +typedef struct st_spim_ext { + bool voltage_is_3300mv; +} spim_ext_t; + +extern const xspi_api_t spim_api; + +#endif /* _SPIM_API_H_ */ diff --git a/plat/renesas/rza/common/include/spim_regs.h b/plat/renesas/rza/common/include/spim_regs.h new file mode 100644 index 0000000000..87c6c6d07b --- /dev/null +++ b/plat/renesas/rza/common/include/spim_regs.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SPIM_REG_H_ +#define _SPIM_REG_H_ + +#define SPIM_CMNCR 0x0000 +#define SPIM_SSLDR 0x0004 +#define SPIM_DRCR 0x000c +#define SPIM_DRCMR 0x0010 +#define SPIM_DREAR 0x0014 +#define SPIM_DROPR 0x0018 +#define SPIM_DRENR 0x001c +#define SPIM_SMCR 0x0020 +#define SPIM_SMCMR 0x0024 +#define SPIM_SMADR 0x0028 +#define SPIM_SMOPR 0x002c +#define SPIM_SMENR 0x0030 +#define SPIM_SMRDR0 0x0038 +#define SPIM_SMRDR1 0x003c +#define SPIM_SMWDR0 0x0040 +#define SPIM_SMWDR1 0x0044 +#define SPIM_CMNSR 0x0048 +#define SPIM_DRDMCR 0x0058 +#define SPIM_DRDRENR 0x005c +#define SPIM_SMDMCR 0x0060 +#define SPIM_SMDRENR 0x0064 +#define SPIM_PHYADJ1 0x0070 +#define SPIM_PHYADJ2 0x0074 +#define SPIM_PHYCNT 0x007c +#define SPIM_PHYOFFSET1 0x0080 +#define SPIM_PHYOFFSET2 0x0084 +#define SPIM_PHYINT 0x0088 +#define SPIM_BUFFER 0x10000 + +/* CMNCR field */ +#define SPIM_CMNCR_MD_POS 31 +#define SPIM_CMNCR_MD (1u << SPIM_CMNCR_MD_POS) +#define SPIM_CMNCR_MOIIO3_POS 22 +#define SPIM_CMNCR_MOIIO3 (3u << SPIM_CMNCR_MOIIO3_POS) +#define SPIM_CMNCR_MOIIO2_POS 20 +#define SPIM_CMNCR_MOIIO2 (3u << SPIM_CMNCR_MOIIO2_POS) +#define SPIM_CMNCR_MOIIO1_POS 18 +#define SPIM_CMNCR_MOIIO1 (3u << SPIM_CMNCR_MOIIO1_POS) +#define SPIM_CMNCR_MOIIO0_POS 16 +#define SPIM_CMNCR_MOIIO0 (3u << SPIM_CMNCR_MOIIO0_POS) +#define SPIM_CMNCR_IO3FV_POS 14 +#define SPIM_CMNCR_IO3FV (3u << SPIM_CMNCR_IO3FV_POS) +#define SPIM_CMNCR_IO2FV_POS 12 +#define SPIM_CMNCR_IO2FV (3u << SPIM_CMNCR_IO2FV_POS) +#define SPIM_CMNCR_IO0FV_POS 8 +#define SPIM_CMNCR_IO0FV (3u << SPIM_CMNCR_IO0FV_POS) +#define SPIM_CMNCR_IO_LOW 0u +#define SPIM_CMNCR_IO_HIGH 1u +#define SPIM_CMNCR_IO_KEEP 2u +#define SPIM_CMNCR_IO_HIZ 3u +#define SPIM_CMNCR_BSZ_POS 0 +#define SPIM_CMNCR_BSZ (3u << SPIM_CMNCR_BSZ_POS) +#define SPIM_CMNCR_BSZ_SINGLE 0u +#define SPIM_CMNCR_BSZ_DUAL 1u +#define SPIM_CMNCR_BSZ_OCTA 1u +#define SPIM_CMNCR_BSZ_HYPER 1u + +/* SSLDR field */ +#define SPIM_SSLDR_SPNDL_POS 16 +#define SPIM_SSLDR_SPNDL (7u << SPIM_SSLDR_SPNDL_POS) +#define SPIM_SSLDR_SLNDL_POS 8 +#define SPIM_SSLDR_SLNDL (7u << SPIM_SSLDR_SLNDL_POS) +#define SPIM_SSLDR_SCKDL_POS 0 +#define SPIM_SSLDR_SCKDL (7u << SPIM_SSLDR_SCKDL_POS) + +/* DRCR field */ +#define SPIM_DRCR_SSLN_POS 24 +#define SPIM_DRCR_SSLN (1u << SPIM_DRCR_SSLN_POS) +#define SPIM_DRCR_RBURST_POS 16 +#define SPIM_DRCR_RBURST (31u << SPIM_DRCR_RBURST_POS) +#define SPIM_DRCR_RCF_POS 9 +#define SPIM_DRCR_RCF (1u << SPIM_DRCR_RCF_POS) +#define SPIM_DRCR_RBE_POS 8 +#define SPIM_DRCR_RBE (1u << SPIM_DRCR_RBE_POS) +#define SPIM_DRCR_SSLE_POS 0 +#define SPIM_DRCR_SSLE (1u << SPIM_DRCR_SSLE_POS) + +/* DREAR field */ +#define SPIM_DREAR_EAV_POS 16 +#define SPIM_DREAR_EAV (255u << SPIM_DREAR_EAV_POS) +#define SPIM_DREAR_EAC_POS 0 +#define SPIM_DREAR_EAC (7u << SPIM_DREAR_EAC_POS) + +/* DRCMR field */ +#define SPIM_DRCMR_CMD_POS 16 +#define SPIM_DRCMR_CMD (255u << SPIM_DRCMR_CMD_POS) +#define SPIM_DRCMR_OCMD_POS 0 +#define SPIM_DRCMR_OCMD (255u << SPIM_DRCMR_OCMD_POS) + +/* DROPR field */ +#define SPIM_DROPR_OPD3_POS 24 +#define SPIM_DROPR_OPD3 (255u << SPIM_DROPR_OPD3_POS) +#define SPIM_DROPR_OPD2_POS 16 +#define SPIM_DROPR_OPD2 (255u << SPIM_DROPR_OPD2_POS) +#define SPIM_DROPR_OPD1_POS 8 +#define SPIM_DROPR_OPD1 (255u << SPIM_DROPR_OPD1_POS) +#define SPIM_DROPR_OPD0_POS 0 +#define SPIM_DROPR_OPD0 (255u << SPIM_DROPR_OPD0_POS) + +/* CMNSR field */ +#define SPIM_CMNSR_SSLF_POS 1 +#define SPIM_CMNSR_SSLF (1u << SPIM_CMNSR_SSLF_POS) +#define SPIM_CMNSR_TEND_POS 0 +#define SPIM_CMNSR_TEND (1u << SPIM_CMNSR_TEND_POS) + +/* DRDMCR field */ +#define SPIM_DRDMCR_DMCYC_POS 0 +#define SPIM_DRDMCR_DMCYC (31u << SPIM_DRDMCR_DMCYC_POS) + +/* DRENR field */ +#define SPIM_DRENR_CDB_POS 30 +#define SPIM_DRENR_CDB (3u << SPIM_DRENR_CDB_POS) +#define SPIM_DRENR_OCDB_POS 28 +#define SPIM_DRENR_OCDB (3u << SPIM_DRENR_OCDB_POS) +#define SPIM_DRENR_ADB_POS 24 +#define SPIM_DRENR_ADB (3u << SPIM_DRENR_ADB_POS) +#define SPIM_DRENR_OPDB_POS 20 +#define SPIM_DRENR_OPDB (3u << SPIM_DRENR_OPDB_POS) +#define SPIM_DRENR_DRDB_POS 16 +#define SPIM_DRENR_DRDB (3u << SPIM_DRENR_DRDB_POS) +#define SPIM_DRENR_DB_4BIT 2u +#define SPIM_DRENR_DB_1BIT 0u +#define SPIM_DRENR_DME_POS 15 +#define SPIM_DRENR_DME (1u << SPIM_DRENR_DME_POS) +#define SPIM_DRENR_CDE_POS 14 +#define SPIM_DRENR_CDE (1u << SPIM_DRENR_CDE_POS) +#define SPIM_DRENR_OCDE_POS 12 +#define SPIM_DRENR_OCDE (1u << SPIM_DRENR_OCDE_POS) +#define SPIM_DRENR_ADE_POS 8 +#define SPIM_DRENR_ADE (15u << SPIM_DRENR_ADE_POS) +#define SPIM_DRENR_ADE_3BYTE 7u +#define SPIM_DRENR_ADE_4BYTE 15u +#define SPIM_DRENR_ADE_OPI 12u +#define SPIM_DRENR_ADE_HYPER 4u +#define SPIM_DRENR_ADE_NONE 0u +#define SPIM_DRENR_OPDE_POS 4 +#define SPIM_DRENR_OPDE (15u << SPIM_DRENR_OPDE_POS) +#define SPIM_DRENR_OPDE_NONE 0u +#define SPIM_DRENR_OPDE_1BYTE 8u +#define SPIM_DRENR_OPDE_2BYTE 12u +#define SPIM_DRENR_OPDE_3BYTE 14u +#define SPIM_DRENR_OPDE_4BYTE 15u + +/* SMCR field */ +#define SPIM_SMCR_SSLKP_POS 8 +#define SPIM_SMCR_SSLKP (1u << SPIM_SMCR_SSLKP_POS) +#define SPIM_SMCR_SPIRE_POS 2 +#define SPIM_SMCR_SPIRE (1u << SPIM_SMCR_SPIRE_POS) +#define SPIM_SMCR_SPIWE_POS 1 +#define SPIM_SMCR_SPIWE (1u << SPIM_SMCR_SPIWE_POS) +#define SPIM_SMCR_SPIE_POS 0 +#define SPIM_SMCR_SPIE (1u << SPIM_SMCR_SPIE_POS) + +/* SMCMR field */ +#define SPIM_SMCMR_CMD_POS 16 +#define SPIM_SMCMR_CMD (255u << SPIM_SMCMR_CMD_POS) +#define SPIM_SMCMR_OCMD_POS 0 +#define SPIM_SMCMR_OCMD (255u << SPIM_SMCMR_OCMD_POS) + +/* SMOPR field */ +#define SPIM_SMOPR_OPD3_POS 24 +#define SPIM_SMOPR_OPD3 (255u << SPIM_SMOPR_OPD3_POS) +#define SPIM_SMOPR_OPD2_POS 16 +#define SPIM_SMOPR_OPD2 (255u << SPIM_SMOPR_OPD2_POS) +#define SPIM_SMOPR_OPD1_POS 8 +#define SPIM_SMOPR_OPD1 (255u << SPIM_SMOPR_OPD1_POS) +#define SPIM_SMOPR_OPD0_POS 0 +#define SPIM_SMOPR_OPD0 (255u << SPIM_SMOPR_OPD0_POS) + +/* SMENR field */ +#define SPIM_SMENR_CDB_POS 30 +#define SPIM_SMENR_CDB (3u << SPIM_SMENR_CDB_POS) +#define SPIM_SMENR_OCDB_POS 28 +#define SPIM_SMENR_OCDB (3u << SPIM_SMENR_OCDB_POS) +#define SPIM_SMENR_ADB_POS 24 +#define SPIM_SMENR_ADB (3u << SPIM_SMENR_ADB_POS) +#define SPIM_SMENR_OPDB_POS 20 +#define SPIM_SMENR_OPDB (3u << SPIM_SMENR_OPDB_POS) +#define SPIM_SMENR_SPIDB_POS 16 +#define SPIM_SMENR_SPIDB (3u << SPIM_SMENR_SPIDB_POS) +#define SPIM_SMENR_DB_4BIT 2u +#define SPIM_SMENR_DB_1BIT 0u +#define SPIM_SMENR_DME_POS 15 +#define SPIM_SMENR_DME (1u << SPIM_SMENR_DME_POS) +#define SPIM_SMENR_CDE_POS 14 +#define SPIM_SMENR_CDE (1u << SPIM_SMENR_CDE_POS) +#define SPIM_SMENR_OCDE_POS 12 +#define SPIM_SMENR_OCDE (1u << SPIM_SMENR_OCDE_POS) +#define SPIM_SMENR_ADE_POS 8 +#define SPIM_SMENR_ADE (15u << SPIM_SMENR_ADE_POS) +#define SPIM_SMENR_ADE_3BYTE 7u +#define SPIM_SMENR_ADE_4BYTE 15u +#define SPIM_SMENR_ADE_OPI 12u +#define SPIM_SMENR_ADE_HYPER 4u +#define SPIM_SMENR_ADE_NONE 0u +#define SPIM_SMENR_OPDE_POS 4 +#define SPIM_SMENR_OPDE (15u << SPIM_SMENR_OPDE_POS) +#define SPIM_SMENR_OPDE_NONE 0u +#define SPIM_SMENR_OPDE_1BYTE 8u +#define SPIM_SMENR_OPDE_2BYTE 12u +#define SPIM_SMENR_OPDE_3BYTE 14u +#define SPIM_SMENR_OPDE_4BYTE 15u +#define SPIM_SMENR_SPIDE_POS 0 +#define SPIM_SMENR_SPIDE (15u << SPIM_SMENR_SPIDE_POS) +#define SPIM_SMENR_SPIDE_NONE 0u +#define SPIM_SMENR_SPIDE_BYTE 8u +#define SPIM_SMENR_SPIDE_WORD 12u +#define SPIM_SMENR_SPIDE_LONG 15u + +/* DRDRENR field */ +#define SPIM_DRDRENR_HYPE_POS 12 +#define SPIM_DRDRENR_HYPE (7u << SPIM_DRDRENR_HYPE_POS) +#define SPIM_DRDRENR_SPI 0u +#define SPIM_DRDRENR_DDR 5u +#define SPIM_DRDRENR_OCTADDR 4u +#define SPIM_DRDRENR_ADDRE_POS 8 +#define SPIM_DRDRENR_ADDRE (1u << SPIM_DRDRENR_ADDRE_POS) +#define SPIM_DRDRENR_OPDRE_POS 4 +#define SPIM_DRDRENR_OPDRE (1u << SPIM_DRDRENR_OPDRE_POS) +#define SPIM_DRDRENR_DRDRE_POS 0 +#define SPIM_DRDRENR_DRDRE (1u << SPIM_DRDRENR_DRDRE_POS) + +/* SMDMCR field */ +#define SPIM_SMDMCR_DMCYC_POS 0 +#define SPIM_SMDMCR_DMCYC (31u << SPIM_SMDMCR_DMCYC_POS) + +/* SMDRENR field */ +#define SPIM_SMDRENR_HYPE_POS 12 +#define SPIM_SMDRENR_HYPE (7u << SPIM_SMDRENR_HYPE_POS) +#define SPIM_SMDRENR_SPI 0u +#define SPIM_SMDRENR_DDR 5u +#define SPIM_SMDRENR_OCTADDR 4u +#define SPIM_SMDRENR_ADDRE_POS 8 +#define SPIM_SMDRENR_ADDRE (1u << SPIM_SMDRENR_ADDRE_POS) +#define SPIM_SMDRENR_OPDRE_POS 4 +#define SPIM_SMDRENR_OPDRE (1u << SPIM_SMDRENR_OPDRE_POS) +#define SPIM_SMDRENR_DRDRE_POS 0 +#define SPIM_SMDRENR_DRDRE (1u << SPIM_SMDRENR_DRDRE_POS) + +/* PHYCNT field */ +#define SPIM_PHYCNT_CAL_POS 31 +#define SPIM_PHYCNT_CAL (1u << SPIM_PHYCNT_CAL_POS) +#define SPIM_PHYCNT_ALT_ALIGN_POS 30 +#define SPIM_PHYCNT_ALT_ALIGN (1u << SPIM_PHYCNT_ALT_ALIGN_POS) +#define SPIM_PHYCNT_OCTA_POS 22 +#define SPIM_PHYCNT_OCTA (3u << SPIM_PHYCNT_OCTA_POS) +#define SPIM_PHYCNT_OCTA_DDR_ALT 1u +#define SPIM_PHYCNT_OCTA_DDR_SEQ 2u +#define SPIM_PHYCNT_EXDS_POS 21 +#define SPIM_PHYCNT_EXDS (1u << SPIM_PHYCNT_EXDS_POS) +#define SPIM_PHYCNT_OCT_POS 20 +#define SPIM_PHYCNT_OCT (1u << SPIM_PHYCNT_OCT_POS) +#define SPIM_PHYCNT_HS_POS 18 +#define SPIM_PHYCNT_HS (1u << SPIM_PHYCNT_HS_POS) +#define SPIM_PHYCNT_CKSEL_POS 16 +#define SPIM_PHYCNT_CKSEL (3u << SPIM_PHYCNT_CKSEL_POS) +#define SPIM_PHYCNT_WBUF2_POS 4 +#define SPIM_PHYCNT_WBUF2 (1u << SPIM_PHYCNT_WBUF2_POS) +#define SPIM_PHYCNT_WBUF_POS 2 +#define SPIM_PHYCNT_WBUF (1u << SPIM_PHYCNT_WBUF_POS) +#define SPIM_PHYCNT_PHYMEM_POS 0 +#define SPIM_PHYCNT_PHYMEM (3u << SPIM_PHYCNT_PHYMEM_POS) +#define SPIM_PHYCNT_SDR 0u +#define SPIM_PHYCNT_DDR 1u +#define SPIM_PHYCNT_HYPER 3u + +/* PHYOFFSET1 field */ +#define SPIM_PHYOFFSET1_DDRTMG_POS 28 +#define SPIM_PHYOFFSET1_DDRTMG (7u << SPIM_PHYOFFSET1_DDRTMG_POS) +#define SPIM_PHYOFFSET1_DDR 2u +#define SPIM_PHYOFFSET1_SDR 3u + +/* PHYOFFSET2 field */ +#define SPIM_PHYOFFSET2_OCTTMG_POS 8 +#define SPIM_PHYOFFSET2_OCTTMG (7u << SPIM_PHYOFFSET2_OCTTMG_POS) +#define SPIM_PHYOFFSET2_SPI 4u +#define SPIM_PHYOFFSET2_HYPER 4u +#define SPIM_PHYOFFSET2_SPI_WBUF 0u +#define SPIM_PHYOFFSET2_OPI 3u + + + + +#endif /* _SPIM_REG_H_ */ + + diff --git a/plat/renesas/rza/common/include/syc.h b/plat/renesas/rza/common/include/syc.h new file mode 100644 index 0000000000..c5bccf6081 --- /dev/null +++ b/plat/renesas/rza/common/include/syc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SYC_H__ +#define __SYC_H__ + +void syc_init(unsigned int freq); +unsigned int syc_get_freq(void); + +#endif /* __SYC_H__ */ diff --git a/plat/renesas/rza/common/include/sys.h b/plat/renesas/rza/common/include/sys.h new file mode 100644 index 0000000000..1259105222 --- /dev/null +++ b/plat/renesas/rza/common/include/sys.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SYS_H__ +#define __SYS_H__ + +#define MASK_BOOTM_DEVICE (0x0F) +#define MASK_BOOTM_SECURE (0x10) + +#define BOOT_MODE_ESD (0) +#define BOOT_MODE_EMMC_1_8 (1) +#define BOOT_MODE_EMMC_3_3 (2) +#define BOOT_MODE_SPI_1_8 (3) +#define BOOT_MODE_SPI_3_3 (4) +#define BOOT_MODE_SCIF (5) +#define BOOT_MODE_NAND_SPI_1_8 (6) +#define BOOT_MODE_NAND_SPI_3_3 (7) + +#endif /* __SYS_H__ */ diff --git a/plat/renesas/rza/common/include/sys_regs.h b/plat/renesas/rza/common/include/sys_regs.h new file mode 100644 index 0000000000..5512375c3e --- /dev/null +++ b/plat/renesas/rza/common/include/sys_regs.h @@ -0,0 +1,859 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SYS_REGS_H__ +#define __SYS_REGS_H__ + +#define SYS_BASE (0x11020000) + +#define SYS_MSTACCCTL0 (SYS_BASE + 0x00000000) +#define SYS_MSTACCCTL1 (SYS_BASE + 0x00000004) +#define SYS_MSTACCCTL2 (SYS_BASE + 0x00000008) +#define SYS_MSTACCCTL3 (SYS_BASE + 0x0000000C) +#define SYS_MSTACCCTL4 (SYS_BASE + 0x00000010) +#define SYS_MSTACCCTL5 (SYS_BASE + 0x00000014) +#define SYS_SLVACCCTL0 (SYS_BASE + 0x00000100) +#define SYS_SLVACCCTL1 (SYS_BASE + 0x00000104) +#define SYS_SLVACCCTL2 (SYS_BASE + 0x00000108) +#define SYS_SLVACCCTL3 (SYS_BASE + 0x0000010C) +#define SYS_SLVACCCTL4 (SYS_BASE + 0x00000110) +#define SYS_SLVACCCTL5 (SYS_BASE + 0x00000114) +#define SYS_SLVACCCTL6 (SYS_BASE + 0x00000118) +#define SYS_SLVACCCTL7 (SYS_BASE + 0x0000011C) +#define SYS_SLVACCCTL8 (SYS_BASE + 0x00000120) +#define SYS_SLVACCCTL9 (SYS_BASE + 0x00000124) +#define SYS_SLVACCCTL10 (SYS_BASE + 0x00000128) +#define SYS_SLVACCCTL11 (SYS_BASE + 0x0000012C) +#define SYS_SLVACCCTL12 (SYS_BASE + 0x00000130) +#define SYS_SLVACCCTL13 (SYS_BASE + 0x00000134) +#define SYS_SLVACCCTL14 (SYS_BASE + 0x00000138) +#define SYS_SLVACCCTL15 (SYS_BASE + 0x0000013C) +#define SYS_RAM0_ECC (SYS_BASE + 0x00000200) +#define SYS_RAM0_EN (SYS_BASE + 0x00000204) +#define SYS_RAM0_TEST (SYS_BASE + 0x00000208) +#define SYS_RAM0_MON (SYS_BASE + 0x0000020C) +#define SYS_RAM1_ECC (SYS_BASE + 0x00000210) +#define SYS_RAM1_EN (SYS_BASE + 0x00000214) +#define SYS_RAM1_TEST (SYS_BASE + 0x00000218) +#define SYS_RAM1_MON (SYS_BASE + 0x0000021C) +#define SYS_WDT0_CTRL (SYS_BASE + 0x00000220) +#define SYS_WDT1_CTRL (SYS_BASE + 0x00000230) +#define SYS_WDT2_CTRL (SYS_BASE + 0x00000240) +#define SYS_WDT3_CTRL (SYS_BASE + 0x00000250) +#define SYS_GPU_COHE (SYS_BASE + 0x00000300) +#define SYS_GPU_STRP (SYS_BASE + 0x00000304) +#define SYS_GPU_TEXT (SYS_BASE + 0x00000308) +#define SYS_H264_CFG0 (SYS_BASE + 0x00000310) +#define SYS_H264_CFG1 (SYS_BASE + 0x00000314) +#define SYS_H264_CFG2 (SYS_BASE + 0x00000318) +#define SYS_H264_MON (SYS_BASE + 0x0000031C) +#define SYS_H264_BSTOP (SYS_BASE + 0x00000320) +#define SYS_GETH0_CFG (SYS_BASE + 0x00000330) +#define SYS_GETH1_CFG (SYS_BASE + 0x00000340) +#define SYS_I2C0_CFG (SYS_BASE + 0x00000400) +#define SYS_I2C1_CFG (SYS_BASE + 0x00000410) +#define SYS_I2C2_CFG (SYS_BASE + 0x00000420) +#define SYS_I2C3_CFG (SYS_BASE + 0x00000430) +#define SYS_CANFD_CFG (SYS_BASE + 0x00000440) +#define SYS_SCIF0_CFG (SYS_BASE + 0x00000450) +#define SYS_SCIF1_CFG (SYS_BASE + 0x00000460) +#define SYS_SCIF2_CFG (SYS_BASE + 0x00000470) +#define SYS_SCIF3_CFG (SYS_BASE + 0x00000480) +#define SYS_SCIF4_CFG (SYS_BASE + 0x00000490) +#define SYS_SCI0_CFG (SYS_BASE + 0x000004A0) +#define SYS_SCI1_CFG (SYS_BASE + 0x000004B0) +#define SYS_CM33_STAT (SYS_BASE + 0x00000800) +#define SYS_CM33_CFG0 (SYS_BASE + 0x00000804) +#define SYS_CM33_CFG1 (SYS_BASE + 0x00000808) +#define SYS_CM33_CFG2 (SYS_BASE + 0x0000080C) +#define SYS_CM33_CFG3 (SYS_BASE + 0x00000810) +#define SYS_CM33_LOCK (SYS_BASE + 0x00000814) +#define SYS_CM33_CTL (SYS_BASE + 0x00000818) +#define SYS_CA55_CFG_AArch0 (SYS_BASE + 0x00000840) +#define SYS_CA55_CFG_AArch1 (SYS_BASE + 0x00000844) +#define SYS_CA55_CFG_Endian0 (SYS_BASE + 0x00000848) +#define SYS_CA55_CFG_Endian1 (SYS_BASE + 0x0000084C) +#define SYS_CA55_CFG_Thumb0 (SYS_BASE + 0x00000850) +#define SYS_CA55_CFG_Thumb1 (SYS_BASE + 0x00000854) +#define SYS_CA55_CFG_RVAL0 (SYS_BASE + 0x00000858) +#define SYS_CA55_CFG_RVAH0 (SYS_BASE + 0x0000085C) +#define SYS_CA55_CFG_RVAL1 (SYS_BASE + 0x00000860) +#define SYS_CA55_CFG_RVAH1 (SYS_BASE + 0x00000864) +#define SYS_CA55_CFG_VA0 (SYS_BASE + 0x00000868) +#define SYS_CA55_CFG_VA1 (SYS_BASE + 0x0000086C) +#define SYS_BBG_CTRL_ENABLE (SYS_BASE + 0x00000900) +#define SYS_BBG_CTRL (SYS_BASE + 0x00000904) +#define SYS_BBG_CTRL_MON (SYS_BASE + 0x00000908) +#define SYS_BBG_OFFSET0 (SYS_BASE + 0x0000090C) +#define SYS_BBG_OFFSET1 (SYS_BASE + 0x00000910) +#define SYS_BBG_OFFSET2 (SYS_BASE + 0x00000914) +#define SYS_BBG_OFFSET3 (SYS_BASE + 0x00000918) +#define SYS_BBG_OFFSET4 (SYS_BASE + 0x0000091C) +#define SYS_BBG_OFFSET5 (SYS_BASE + 0x00000920) +#define SYS_BBG_OFFSET6 (SYS_BASE + 0x00000924) +#define SYS_BBG_OFFSET7 (SYS_BASE + 0x00000928) +#define SYS_BBG_OFFSET_CTRL (SYS_BASE + 0x00000930) +#define SYS_BBG_PFREQ_MON (SYS_BASE + 0x00000934) +#define SYS_BBG_NFREQ_MON (SYS_BASE + 0x00000938) +#define SYS_BBG_TEMP_MON (SYS_BASE + 0x0000093C) +#define SYS_BBG_VOLT_MON (SYS_BASE + 0x00000940) +#define SYS_LSI_MODE (SYS_BASE + 0x00000A00) +#define SYS_LSI_DEVID (SYS_BASE + 0x00000A04) +#define SYS_LSI_PRR (SYS_BASE + 0x00000A08) +#define SYS_LSI_OTPSECEN (SYS_BASE + 0x00000A0C) +#define SYS_LSI_OTPSECMODE (SYS_BASE + 0x00000A10) +#define SYS_LSI_OTPJAM (SYS_BASE + 0x00000A14) +#define SYS_LSI_OTPCORE (SYS_BASE + 0x00000A18) +#define SYS_LSI_OTPPOC (SYS_BASE + 0x00000A20) +#define SYS_JAUTH_JUDGE (SYS_BASE + 0x00000B00) +#define SYS_AOF0 (SYS_BASE + 0x00000C00) +#define SYS_AOF1 (SYS_BASE + 0x00000C04) +#define SYS_AOF2 (SYS_BASE + 0x00000C08) +#define SYS_AOF3 (SYS_BASE + 0x00000C0C) +#define SYS_AOF4 (SYS_BASE + 0x00000C10) +#define SYS_AOF5 (SYS_BASE + 0x00000C14) +#define SYS_AOF6 (SYS_BASE + 0x00000C18) +#define SYS_AOF7 (SYS_BASE + 0x00000C1C) +#define SYS_AOF8 (SYS_BASE + 0x00000C20) +#define SYS_LP_CTL0 (SYS_BASE + 0x00000D00) +#define SYS_LP_CTL1 (SYS_BASE + 0x00000D04) +#define SYS_LP_CTL2 (SYS_BASE + 0x00000D08) +#define SYS_LP_CTL3 (SYS_BASE + 0x00000D0C) +#define SYS_LP_CTL4 (SYS_BASE + 0x00000D10) +#define SYS_LP_CTL5 (SYS_BASE + 0x00000D14) +#define SYS_LP_CTL6 (SYS_BASE + 0x00000D18) +#define SYS_LP_CTL7 (SYS_BASE + 0x00000D1C) +#define SYS_LP_CTL8 (SYS_BASE + 0x00000D20) +#define SYS_LP_CM33CTL0 (SYS_BASE + 0x00000D24) +#define SYS_LP_CM33CTL1 (SYS_BASE + 0x00000D28) +#define SYS_LP_CM33CTL2 (SYS_BASE + 0x00000D2C) +#define SYS_LP_CM33CPG (SYS_BASE + 0x00000D30) +#define SYS_LP_CA55_CTL0 (SYS_BASE + 0x00000D34) +#define SYS_LP_CA55CK_CTL1 (SYS_BASE + 0x00000D38) +#define SYS_LP_CA55CK_CTL2 (SYS_BASE + 0x00000D3C) +#define SYS_LP_CA55CK_CTL3 (SYS_BASE + 0x00000D40) +#define SYS_LP_CA55CPGC0 (SYS_BASE + 0x00000D44) +#define SYS_LP_CA55CPGC1 (SYS_BASE + 0x00000D48) +#define SYS_LP_GPU_CTL (SYS_BASE + 0x00000D50) +#define SYS_GPREG_0 (SYS_BASE + 0x00000E00) +#define SYS_GPREG_1 (SYS_BASE + 0x00000E04) +#define SYS_GPREG_2 (SYS_BASE + 0x00000E08) +#define SYS_GPREG_3 (SYS_BASE + 0x00000E0C) +#define SYS_RESREG_0 (SYS_BASE + 0x00000E10) +#define SYS_RESREG_1 (SYS_BASE + 0x00000E14) +#define SYS_RESREG_2 (SYS_BASE + 0x00000E18) +#define SYS_RESREG_3 (SYS_BASE + 0x00000E1C) +#define SYS_IPCONT (SYS_BASE + 0x00000E20) + +#define MSTACCCTL0_DMAC0_AWPU (1 << 0) +#define MSTACCCTL0_DMAC0_AWNS (1 << 1) +#define MSTACCCTL0_DMAC0_AWSEL (1 << 3) +#define MSTACCCTL0_DMAC0_ARRU (1 << 4) +#define MSTACCCTL0_DMAC0_ARNS (1 << 5) +#define MSTACCCTL0_DMAC0_ARSEL (1 << 7) +#define MSTACCCTL0_DMAC1_AWPU (1 << 8) +#define MSTACCCTL0_DMAC1_AWNS (1 << 9) +#define MSTACCCTL0_DMAC1_AWSEL (1 << 11) +#define MSTACCCTL0_DMAC1_ARRU (1 << 12) +#define MSTACCCTL0_DMAC1_ARNS (1 << 13) +#define MSTACCCTL0_DMAC1_ARSEL (1 << 15) +#define MSTACCCTL0_GPU_AWPU (1 << 16) +#define MSTACCCTL0_GPU_AWNS (1 << 17) +#define MSTACCCTL0_GPU_AWSEL (1 << 19) +#define MSTACCCTL0_GPU_ARRU (1 << 20) +#define MSTACCCTL0_GPU_ARNS (1 << 21) +#define MSTACCCTL0_GPU_ARSEL (1 << 23) +#define MSTACCCTL1_SDHI0_AWPU (1 << 0) +#define MSTACCCTL1_SDHI0_AWNS (1 << 1) +#define MSTACCCTL1_SDHI0_AWSEL (1 << 3) +#define MSTACCCTL1_SDHI0_ARRU (1 << 4) +#define MSTACCCTL1_SDHI0_ARNS (1 << 5) +#define MSTACCCTL1_SDHI0_ARSEL (1 << 7) +#define MSTACCCTL1_SDHI1_AWPU (1 << 8) +#define MSTACCCTL1_SDHI1_AWNS (1 << 9) +#define MSTACCCTL1_SDHI1_AWSEL (1 << 11) +#define MSTACCCTL1_SDHI1_ARRU (1 << 12) +#define MSTACCCTL1_SDHI1_ARNS (1 << 13) +#define MSTACCCTL1_SDHI1_ARSEL (1 << 15) +#define MSTACCCTL1_GEther0_AWPU (1 << 16) +#define MSTACCCTL1_GEther0_AWNS (1 << 17) +#define MSTACCCTL1_GEther0_AWSEL (1 << 19) +#define MSTACCCTL1_GEther0_ARRU (1 << 20) +#define MSTACCCTL1_GEther0_ARNS (1 << 21) +#define MSTACCCTL1_GEther0_ARSEL (1 << 23) +#define MSTACCCTL1_GEther1_AWPU (1 << 24) +#define MSTACCCTL1_GEther1_AWNS (1 << 25) +#define MSTACCCTL1_GEther1_AWSEL (1 << 27) +#define MSTACCCTL1_GEther1_ARRU (1 << 28) +#define MSTACCCTL1_GEther1_ARNS (1 << 29) +#define MSTACCCTL1_GEther1_ARSEL (1 << 31) +#define MSTACCCTL2_USB2_0H_AWPU (1 << 0) +#define MSTACCCTL2_USB2_0H_AWNS (1 << 1) +#define MSTACCCTL2_USB2_0H_AWSEL (1 << 3) +#define MSTACCCTL2_USB2_0H_ARRU (1 << 4) +#define MSTACCCTL2_USB2_0H_ARNS (1 << 5) +#define MSTACCCTL2_USB2_0H_ARSEL (1 << 7) +#define MSTACCCTL2_USB2_1H_AWPU (1 << 8) +#define MSTACCCTL2_USB2_1H_AWNS (1 << 9) +#define MSTACCCTL2_USB2_1H_AWSEL (1 << 11) +#define MSTACCCTL2_USB2_1H_ARRU (1 << 12) +#define MSTACCCTL2_USB2_1H_ARNS (1 << 13) +#define MSTACCCTL2_USB2_1H_ARSEL (1 << 15) +#define MSTACCCTL2_USB2_0D_AWPU (1 << 16) +#define MSTACCCTL2_USB2_0D_AWNS (1 << 17) +#define MSTACCCTL2_USB2_0D_AWSEL (1 << 19) +#define MSTACCCTL2_USB2_0D_ARRU (1 << 20) +#define MSTACCCTL2_USB2_0D_ARNS (1 << 21) +#define MSTACCCTL2_USB2_0D_ARSEL (1 << 23) +#define MSTACCCTL3_H264_AWPU (1 << 0) +#define MSTACCCTL3_H264_AWNS (1 << 1) +#define MSTACCCTL3_H264_AWSEL (1 << 3) +#define MSTACCCTL3_H264_ARRU (1 << 4) +#define MSTACCCTL3_H264_ARNS (1 << 5) +#define MSTACCCTL3_H264_ARSEL (1 << 7) +#define MSTACCCTL3_LCDC_AWPU (1 << 8) +#define MSTACCCTL3_LCDC_AWNS (1 << 9) +#define MSTACCCTL3_LCDC_AWSEL (1 << 11) +#define MSTACCCTL3_LCDC_ARRU (1 << 12) +#define MSTACCCTL3_LCDC_ARNS (1 << 13) +#define MSTACCCTL3_LCDC_ARSEL (1 << 15) +#define MSTACCCTL3_DSI_AWPU (1 << 16) +#define MSTACCCTL3_DSI_AWNS (1 << 17) +#define MSTACCCTL3_DSI_AWSEL (1 << 19) +#define MSTACCCTL3_DSI_ARRU (1 << 20) +#define MSTACCCTL3_DSI_ARNS (1 << 21) +#define MSTACCCTL3_DSI_ARSEL (1 << 23) +#define MSTACCCTL4_ISU_AWPU (1 << 0) +#define MSTACCCTL4_ISU_AWNS (1 << 1) +#define MSTACCCTL4_ISU_AWSEL (1 << 3) +#define MSTACCCTL4_ISU_ARRU (1 << 4) +#define MSTACCCTL4_ISU_ARNS (1 << 5) +#define MSTACCCTL4_ISU_ARSEL (1 << 7) +#define MSTACCCTL4_CRU_VD_AWPU (1 << 16) +#define MSTACCCTL4_CRU_VD_AWNS (1 << 17) +#define MSTACCCTL4_CRU_VD_AWSEL (1 << 19) +#define MSTACCCTL4_CRU_VD_ARRU (1 << 20) +#define MSTACCCTL4_CRU_VD_ARNS (1 << 21) +#define MSTACCCTL4_CRU_VD_ARSEL (1 << 23) +#define MSTACCCTL4_CRU_ST_AWPU (1 << 24) +#define MSTACCCTL4_CRU_ST_AWNS (1 << 25) +#define MSTACCCTL4_CRU_ST_AWSEL (1 << 27) +#define MSTACCCTL4_CRU_ST_ARRU (1 << 28) +#define MSTACCCTL4_CRU_ST_ARNS (1 << 29) +#define MSTACCCTL4_CRU_ST_ARSEL (1 << 31) +#define MSTACCCTL5_DRP0_AWPU (1 << 0) +#define MSTACCCTL5_DRP0_AWNS (1 << 1) +#define MSTACCCTL5_DRP0_AWSEL (1 << 3) +#define MSTACCCTL5_DRP0_ARRU (1 << 4) +#define MSTACCCTL5_DRP0_ARNS (1 << 5) +#define MSTACCCTL5_DRP0_ARSEL (1 << 7) +#define MSTACCCTL5_DRP1_AWPU (1 << 8) +#define MSTACCCTL5_DRP1_AWNS (1 << 9) +#define MSTACCCTL5_DRP1_AWSEL (1 << 11) +#define MSTACCCTL5_DRP1_ARRU (1 << 12) +#define MSTACCCTL5_DRP1_ARNS (1 << 13) +#define MSTACCCTL5_DRP1_ARSEL (1 << 15) +#define MSTACCCTL5_DRP2_AWPU (1 << 16) +#define MSTACCCTL5_DRP2_AWNS (1 << 17) +#define MSTACCCTL5_DRP2_AWSEL (1 << 19) +#define MSTACCCTL5_DRP2_ARRU (1 << 20) +#define MSTACCCTL5_DRP2_ARNS (1 << 21) +#define MSTACCCTL5_DRP2_ARSEL (1 << 23) +#define MSTACCCTL5_DRP3_AWPU (1 << 24) +#define MSTACCCTL5_DRP3_AWNS (1 << 25) +#define MSTACCCTL5_DRP3_AWSEL (1 << 27) +#define MSTACCCTL5_DRP3_ARRU (1 << 28) +#define MSTACCCTL5_DRP3_ARNS (1 << 29) +#define MSTACCCTL5_DRP3_ARSEL (1 << 31) +#define SLVACCCTL0_SRAM0_SL_00 (0 << 0) +#define SLVACCCTL0_SRAM0_SL_01 (1 << 0) +#define SLVACCCTL0_SRAM0_SL_10 (2 << 0) +#define SLVACCCTL0_SRAM0_SL_11 (3 << 0) +#define SLVACCCTL0_SRAM1_SL_00 (0 << 2) +#define SLVACCCTL0_SRAM1_SL_01 (1 << 2) +#define SLVACCCTL0_SRAM1_SL_10 (2 << 2) +#define SLVACCCTL0_SRAM1_SL_11 (3 << 2) +#define SLVACCCTL0_GPV_ACPU_SL_10 (2 << 4) +#define SLVACCCTL0_GPV_ACPU_SL_11 (3 << 4) +#define SLVACCCTL0_GPV_MCPU_SL_10 (2 << 6) +#define SLVACCCTL0_GPV_MCPU_SL_11 (3 << 6) +#define SLVACCCTL0_GPV_REG0_SL_10 (2 << 8) +#define SLVACCCTL0_GPV_REG0_SL_11 (3 << 8) +#define SLVACCCTL0_GPV_REG1_SL_10 (2 << 10) +#define SLVACCCTL0_GPV_REG1_SL_11 (3 << 10) +#define SLVACCCTL0_GPV_PERIVIDEO_SL_10 (2 << 12) +#define SLVACCCTL0_GPV_PERIVIDEO_SL_11 (3 << 12) +#define SLVACCCTL0_GPV_PERICPU_SL_10 (2 << 14) +#define SLVACCCTL0_GPV_PERICPU_SL_11 (3 << 14) +#define SLVACCCTL0_GPV_PERIDDR_SL_10 (2 << 16) +#define SLVACCCTL0_GPV_PERIDDR_SL_11 (3 << 16) +#define SLVACCCTL0_GPV_PERICOM_SL_10 (2 << 18) +#define SLVACCCTL0_GPV_PERICOM_SL_11 (3 << 18) +#define SLVACCCTL0_GPV_MXCOM_SL_10 (2 << 20) +#define SLVACCCTL0_GPV_MXCOM_SL_11 (3 << 20) +#define SLVACCCTL0_GPV_MXVIDEO_SL_10 (2 << 22) +#define SLVACCCTL0_GPV_MXVIDEO_SL_11 (3 << 22) +#define SLVACCCTL0_GPV_MXDRP_SL_10 (2 << 24) +#define SLVACCCTL0_GPV_MXDRP_SL_11 (3 << 24) +#define SLVACCCTL0_GPV_PERISTP_SL_10 (2 << 26) +#define SLVACCCTL0_GPV_PERISTP_SL_11 (3 << 26) +#define SLVACCCTL1_TZC0_SL_10 (2 << 0) +#define SLVACCCTL1_TZC0_SL_11 (3 << 0) +#define SLVACCCTL1_TZC1_SL_10 (2 << 2) +#define SLVACCCTL1_TZC1_SL_11 (3 << 2) +#define SLVACCCTL1_TZC2_SL_10 (2 << 4) +#define SLVACCCTL1_TZC2_SL_11 (3 << 4) +#define SLVACCCTL1_TZC3_SL_10 (2 << 6) +#define SLVACCCTL1_TZC3_SL_11 (3 << 6) +#define SLVACCCTL1_CST_SL_00 (0 << 10) +#define SLVACCCTL1_CST_SL_01 (1 << 10) +#define SLVACCCTL1_CST_SL_10 (2 << 10) +#define SLVACCCTL1_CST_SL_11 (3 << 10) +#define SLVACCCTL1_CPG_SL_00 (0 << 12) +#define SLVACCCTL1_CPG_SL_01 (1 << 12) +#define SLVACCCTL1_CPG_SL_10 (2 << 12) +#define SLVACCCTL1_CPG_SL_11 (3 << 12) +#define SLVACCCTL1_SYSC_SL_00 (0 << 14) +#define SLVACCCTL1_SYSC_SL_01 (1 << 14) +#define SLVACCCTL1_SYSC_SL_10 (2 << 14) +#define SLVACCCTL1_SYSC_SL_11 (3 << 14) +#define SLVACCCTL1_SYC_SL_00 (0 << 16) +#define SLVACCCTL1_SYC_SL_01 (1 << 16) +#define SLVACCCTL1_SYC_SL_10 (2 << 16) +#define SLVACCCTL1_SYC_SL_11 (3 << 16) +#define SLVACCCTL1_GIC_SL_00 (0 << 18) +#define SLVACCCTL1_GIC_SL_01 (1 << 18) +#define SLVACCCTL1_GIC_SL_10 (2 << 18) +#define SLVACCCTL1_GIC_SL_11 (3 << 18) +#define SLVACCCTL1_IA55_IM33_SL_00 (0 << 20) +#define SLVACCCTL1_IA55_IM33_SL_01 (1 << 20) +#define SLVACCCTL1_IA55_IM33_SL_10 (2 << 20) +#define SLVACCCTL1_IA55_IM33_SL_11 (3 << 20) +#define SLVACCCTL1_GPIO_SL_00 (0 << 22) +#define SLVACCCTL1_GPIO_SL_01 (1 << 22) +#define SLVACCCTL1_GPIO_SL_10 (2 << 22) +#define SLVACCCTL1_GPIO_SL_11 (3 << 22) +#define SLVACCCTL1_MHU_SL_00 (0 << 24) +#define SLVACCCTL1_MHU_SL_01 (1 << 24) +#define SLVACCCTL1_MHU_SL_10 (2 << 24) +#define SLVACCCTL1_MHU_SL_11 (3 << 24) +#define SLVACCCTL1_DMAC0_SL_00 (0 << 26) +#define SLVACCCTL1_DMAC0_SL_01 (1 << 26) +#define SLVACCCTL1_DMAC0_SL_10 (2 << 26) +#define SLVACCCTL1_DMAC0_SL_11 (3 << 26) +#define SLVACCCTL1_DMAC1_SL_00 (0 << 28) +#define SLVACCCTL1_DMAC1_SL_01 (1 << 28) +#define SLVACCCTL1_DMAC1_SL_10 (2 << 28) +#define SLVACCCTL1_DMAC1_SL_11 (3 << 28) +#define SLVACCCTL2_OSTM0_SL_00 (0 << 0) +#define SLVACCCTL2_OSTM0_SL_01 (1 << 0) +#define SLVACCCTL2_OSTM0_SL_10 (2 << 0) +#define SLVACCCTL2_OSTM0_SL_11 (3 << 0) +#define SLVACCCTL2_OSTM1_SL_00 (0 << 2) +#define SLVACCCTL2_OSTM1_SL_01 (1 << 2) +#define SLVACCCTL2_OSTM1_SL_10 (2 << 2) +#define SLVACCCTL2_OSTM1_SL_11 (3 << 2) +#define SLVACCCTL2_OSTM2_SL_00 (0 << 4) +#define SLVACCCTL2_OSTM2_SL_01 (1 << 4) +#define SLVACCCTL2_OSTM2_SL_10 (2 << 4) +#define SLVACCCTL2_OSTM2_SL_11 (3 << 4) +#define SLVACCCTL2_WDT0_SL_00 (0 << 6) +#define SLVACCCTL2_WDT0_SL_01 (1 << 6) +#define SLVACCCTL2_WDT0_SL_10 (2 << 6) +#define SLVACCCTL2_WDT0_SL_11 (3 << 6) +#define SLVACCCTL2_WDT1_SL_00 (0 << 8) +#define SLVACCCTL2_WDT1_SL_01 (1 << 8) +#define SLVACCCTL2_WDT1_SL_10 (2 << 8) +#define SLVACCCTL2_WDT1_SL_11 (3 << 8) +#define SLVACCCTL2_WDT2_SL_00 (0 << 10) +#define SLVACCCTL2_WDT2_SL_01 (1 << 10) +#define SLVACCCTL2_WDT2_SL_10 (2 << 10) +#define SLVACCCTL2_WDT2_SL_11 (3 << 10) +#define SLVACCCTL2_WDT3_SL_00 (0 << 12) +#define SLVACCCTL2_WDT3_SL_01 (1 << 12) +#define SLVACCCTL2_WDT3_SL_10 (2 << 12) +#define SLVACCCTL2_WDT3_SL_11 (3 << 12) +#define SLVACCCTL2_MTU3A_SL_00 (0 << 14) +#define SLVACCCTL2_MTU3A_SL_01 (1 << 14) +#define SLVACCCTL2_MTU3A_SL_10 (2 << 14) +#define SLVACCCTL2_MTU3A_SL_11 (3 << 14) +#define SLVACCCTL2_POE3_SL_00 (0 << 16) +#define SLVACCCTL2_POE3_SL_01 (1 << 16) +#define SLVACCCTL2_POE3_SL_10 (2 << 16) +#define SLVACCCTL2_POE3_SL_11 (3 << 16) +#define SLVACCCTL2_GPT_SL_00 (0 << 18) +#define SLVACCCTL2_GPT_SL_01 (1 << 18) +#define SLVACCCTL2_GPT_SL_10 (2 << 18) +#define SLVACCCTL2_GPT_SL_11 (3 << 18) +#define SLVACCCTL2_POEG_SL_00 (0 << 20) +#define SLVACCCTL2_POEG_SL_01 (1 << 20) +#define SLVACCCTL2_POEG_SL_10 (2 << 20) +#define SLVACCCTL2_POEG_SL_11 (3 << 20) +#define SLVACCCTL2_DDR_SL_00 (0 << 22) +#define SLVACCCTL2_DDR_SL_01 (1 << 22) +#define SLVACCCTL2_DDR_SL_10 (2 << 22) +#define SLVACCCTL2_DDR_SL_11 (3 << 22) +#define SLVACCCTL3_GPU_SL_00 (0 << 0) +#define SLVACCCTL3_GPU_SL_01 (1 << 0) +#define SLVACCCTL3_GPU_SL_10 (2 << 0) +#define SLVACCCTL3_GPU_SL_11 (3 << 0) +#define SLVACCCTL3_H264_SL_00 (0 << 2) +#define SLVACCCTL3_H264_SL_01 (1 << 2) +#define SLVACCCTL3_H264_SL_10 (2 << 2) +#define SLVACCCTL3_H264_SL_11 (3 << 2) +#define SLVACCCTL3_CRU_SL_00 (0 << 4) +#define SLVACCCTL3_CRU_SL_01 (1 << 4) +#define SLVACCCTL3_CRU_SL_10 (2 << 4) +#define SLVACCCTL3_CRU_SL_11 (3 << 4) +#define SLVACCCTL3_ISU_SL_00 (0 << 6) +#define SLVACCCTL3_ISU_SL_01 (1 << 6) +#define SLVACCCTL3_ISU_SL_10 (2 << 6) +#define SLVACCCTL3_ISU_SL_11 (3 << 6) +#define SLVACCCTL3_DSIPHY_SL_00 (0 << 8) +#define SLVACCCTL3_DSIPHY_SL_01 (1 << 8) +#define SLVACCCTL3_DSIPHY_SL_10 (2 << 8) +#define SLVACCCTL3_DSIPHY_SL_11 (3 << 8) +#define SLVACCCTL3_DSILINK_SL_00 (0 << 10) +#define SLVACCCTL3_DSILINK_SL_01 (1 << 10) +#define SLVACCCTL3_DSILINK_SL_10 (2 << 10) +#define SLVACCCTL3_DSILINK_SL_11 (3 << 10) +#define SLVACCCTL3_LCDC_SL_00 (0 << 12) +#define SLVACCCTL3_LCDC_SL_01 (1 << 12) +#define SLVACCCTL3_LCDC_SL_10 (2 << 12) +#define SLVACCCTL3_LCDC_SL_11 (3 << 12) +#define SLVACCCTL3_DRP_SL_00 (0 << 14) +#define SLVACCCTL3_DRP_SL_01 (1 << 14) +#define SLVACCCTL3_DRP_SL_10 (2 << 14) +#define SLVACCCTL3_DRP_SL_11 (3 << 14) +#define SLVACCCTL3_USBT_SL_00 (0 << 16) +#define SLVACCCTL3_USBT_SL_01 (1 << 16) +#define SLVACCCTL3_USBT_SL_10 (2 << 16) +#define SLVACCCTL3_USBT_SL_11 (3 << 16) +#define SLVACCCTL3_USB20_SL_00 (0 << 18) +#define SLVACCCTL3_USB20_SL_01 (1 << 18) +#define SLVACCCTL3_USB20_SL_10 (2 << 18) +#define SLVACCCTL3_USB20_SL_11 (3 << 18) +#define SLVACCCTL3_USB21_SL_00 (0 << 20) +#define SLVACCCTL3_USB21_SL_01 (1 << 20) +#define SLVACCCTL3_USB21_SL_10 (2 << 20) +#define SLVACCCTL3_USB21_SL_11 (3 << 20) +#define SLVACCCTL3_SDHI0_SL_00 (0 << 22) +#define SLVACCCTL3_SDHI0_SL_01 (1 << 22) +#define SLVACCCTL3_SDHI0_SL_10 (2 << 22) +#define SLVACCCTL3_SDHI0_SL_11 (3 << 22) +#define SLVACCCTL3_SDHI1_SL_00 (0 << 24) +#define SLVACCCTL3_SDHI1_SL_01 (1 << 24) +#define SLVACCCTL3_SDHI1_SL_10 (2 << 24) +#define SLVACCCTL3_SDHI1_SL_11 (3 << 24) +#define SLVACCCTL3_ETH0_SL_00 (0 << 26) +#define SLVACCCTL3_ETH0_SL_01 (1 << 26) +#define SLVACCCTL3_ETH0_SL_10 (2 << 26) +#define SLVACCCTL3_ETH0_SL_11 (3 << 26) +#define SLVACCCTL3_ETH1_SL_00 (0 << 28) +#define SLVACCCTL3_ETH1_SL_01 (1 << 28) +#define SLVACCCTL3_ETH1_SL_10 (2 << 28) +#define SLVACCCTL3_ETH1_SL_11 (3 << 28) +#define SLVACCCTL4_I2C0_SL_00 (0 << 0) +#define SLVACCCTL4_I2C0_SL_01 (1 << 0) +#define SLVACCCTL4_I2C0_SL_10 (2 << 0) +#define SLVACCCTL4_I2C0_SL_11 (3 << 0) +#define SLVACCCTL4_I2C1_SL_00 (0 << 2) +#define SLVACCCTL4_I2C1_SL_01 (1 << 2) +#define SLVACCCTL4_I2C1_SL_10 (2 << 2) +#define SLVACCCTL4_I2C1_SL_11 (3 << 2) +#define SLVACCCTL4_I2C2_SL_00 (0 << 4) +#define SLVACCCTL4_I2C2_SL_01 (1 << 4) +#define SLVACCCTL4_I2C2_SL_10 (2 << 4) +#define SLVACCCTL4_I2C2_SL_11 (3 << 4) +#define SLVACCCTL4_I2C3_SL_00 (0 << 6) +#define SLVACCCTL4_I2C3_SL_01 (1 << 6) +#define SLVACCCTL4_I2C3_SL_10 (2 << 6) +#define SLVACCCTL4_I2C3_SL_11 (3 << 6) +#define SLVACCCTL4_CANFD_SL_00 (0 << 8) +#define SLVACCCTL4_CANFD_SL_01 (1 << 8) +#define SLVACCCTL4_CANFD_SL_10 (2 << 8) +#define SLVACCCTL4_CANFD_SL_11 (3 << 8) +#define SLVACCCTL4_RSPI_SL_00 (0 << 10) +#define SLVACCCTL4_RSPI_SL_01 (1 << 10) +#define SLVACCCTL4_RSPI_SL_10 (2 << 10) +#define SLVACCCTL4_RSPI_SL_11 (3 << 10) +#define SLVACCCTL4_SCIF0_SL_00 (0 << 16) +#define SLVACCCTL4_SCIF0_SL_01 (1 << 16) +#define SLVACCCTL4_SCIF0_SL_10 (2 << 16) +#define SLVACCCTL4_SCIF0_SL_11 (3 << 16) +#define SLVACCCTL4_SCIF1_SL_00 (0 << 18) +#define SLVACCCTL4_SCIF1_SL_01 (1 << 18) +#define SLVACCCTL4_SCIF1_SL_10 (2 << 18) +#define SLVACCCTL4_SCIF1_SL_11 (3 << 18) +#define SLVACCCTL4_SCIF2_SL_00 (0 << 20) +#define SLVACCCTL4_SCIF2_SL_01 (1 << 20) +#define SLVACCCTL4_SCIF2_SL_10 (2 << 20) +#define SLVACCCTL4_SCIF2_SL_11 (3 << 20) +#define SLVACCCTL4_SCIF3_SL_00 (0 << 22) +#define SLVACCCTL4_SCIF3_SL_01 (1 << 22) +#define SLVACCCTL4_SCIF3_SL_10 (2 << 22) +#define SLVACCCTL4_SCIF3_SL_11 (3 << 22) +#define SLVACCCTL4_SCIF4_SL_00 (0 << 24) +#define SLVACCCTL4_SCIF4_SL_01 (1 << 24) +#define SLVACCCTL4_SCIF4_SL_10 (2 << 24) +#define SLVACCCTL4_SCIF4_SL_11 (3 << 24) +#define SLVACCCTL4_SCI0_SL_00 (0 << 26) +#define SLVACCCTL4_SCI0_SL_01 (1 << 26) +#define SLVACCCTL4_SCI0_SL_10 (2 << 26) +#define SLVACCCTL4_SCI0_SL_11 (3 << 26) +#define SLVACCCTL4_SCI1_SL_00 (0 << 28) +#define SLVACCCTL4_SCI1_SL_01 (1 << 28) +#define SLVACCCTL4_SCI1_SL_10 (2 << 28) +#define SLVACCCTL4_SCI1_SL_11 (3 << 28) +#define SLVACCCTL4_IRDA_SL_00 (0 << 30) +#define SLVACCCTL4_IRDA_SL_01 (1 << 30) +#define SLVACCCTL4_IRDA_SL_10 (2 << 30) +#define SLVACCCTL4_IRDA_SL_11 (3 << 30) +#define SLVACCCTL5_SSIF_SL_00 (0 << 0) +#define SLVACCCTL5_SSIF_SL_01 (1 << 0) +#define SLVACCCTL5_SSIF_SL_10 (2 << 0) +#define SLVACCCTL5_SSIF_SL_11 (3 << 0) +#define SLVACCCTL5_SRC_SL_00 (0 << 4) +#define SLVACCCTL5_SRC_SL_01 (1 << 4) +#define SLVACCCTL5_SRC_SL_10 (2 << 4) +#define SLVACCCTL5_SRC_SL_11 (3 << 4) +#define SLVACCCTL6_ADC_SL_00 (0 << 0) +#define SLVACCCTL6_ADC_SL_01 (1 << 0) +#define SLVACCCTL6_ADC_SL_10 (2 << 0) +#define SLVACCCTL6_ADC_SL_11 (3 << 0) +#define SLVACCCTL6_TSU_SL_00 (0 << 2) +#define SLVACCCTL6_TSU_SL_01 (1 << 2) +#define SLVACCCTL6_TSU_SL_10 (2 << 2) +#define SLVACCCTL6_TSU_SL_11 (3 << 2) +#define SLVACCCTL7_TSIP_SL_00 (0 << 0) +#define SLVACCCTL7_TSIP_SL_01 (1 << 0) +#define SLVACCCTL7_TSIP_SL_10 (2 << 0) +#define SLVACCCTL7_TSIP_SL_11 (3 << 0) +#define SLVACCCTL7_OTP_SL_00 (0 << 2) +#define SLVACCCTL7_OTP_SL_01 (1 << 2) +#define SLVACCCTL7_OTP_SL_10 (2 << 2) +#define SLVACCCTL7_OTP_SL_11 (3 << 2) +#define SLVACCCTL8_CM33_SL_00 (0 << 0) +#define SLVACCCTL8_CM33_SL_01 (1 << 0) +#define SLVACCCTL8_CM33_SL_10 (2 << 0) +#define SLVACCCTL8_CM33_SL_11 (3 << 0) +#define SLVACCCTL8_CA55_SL_00 (0 << 2) +#define SLVACCCTL8_CA55_SL_01 (1 << 2) +#define SLVACCCTL8_CA55_SL_10 (2 << 2) +#define SLVACCCTL8_CA55_SL_11 (3 << 2) +#define SLVACCCTL9_BBG_SL_00 (0 << 0) +#define SLVACCCTL9_BBG_SL_01 (1 << 0) +#define SLVACCCTL9_BBG_SL_10 (2 << 0) +#define SLVACCCTL9_BBG_SL_11 (3 << 0) +#define SLVACCCTL10_LSI_S_00 (0 << 0) +#define SLVACCCTL10_LSI_S_01 (1 << 0) +#define SLVACCCTL10_LSI_S_10 (2 << 0) +#define SLVACCCTL10_LSI_S_11 (3 << 0) +#define SLVACCCTL11_JAUTH_SL_00 (0 << 0) +#define SLVACCCTL11_JAUTH_SL_01 (1 << 0) +#define SLVACCCTL11_JAUTH_SL_10 (2 << 0) +#define SLVACCCTL11_JAUTH_SL_11 (3 << 0) +#define SLVACCCTL12_AOF_SL_00 (0 << 0) +#define SLVACCCTL12_AOF_SL_01 (1 << 0) +#define SLVACCCTL12_AOF_SL_10 (2 << 0) +#define SLVACCCTL12_AOF_SL_11 (3 << 0) +#define SLVACCCTL13LP_SL_00 (0 << 0) +#define SLVACCCTL13LP_SL_01 (1 << 0) +#define SLVACCCTL13LP_SL_10 (2 << 0) +#define SLVACCCTL13LP_SL_11 (3 << 0) +#define SLVACCCTL14_GPREG_SL_00 (0 << 0) +#define SLVACCCTL14_GPREG_SL_01 (1 << 0) +#define SLVACCCTL14_GPREG_SL_10 (2 << 0) +#define SLVACCCTL14_GPREG_SL_11 (3 << 0) +#define SLVACCCTL15_RESREG_SL_00 (0 << 0) +#define SLVACCCTL15_RESREG_SL_01 (1 << 0) +#define SLVACCCTL15_RESREG_SL_10 (2 << 0) +#define SLVACCCTL15_RESREG_SL_11 (3 << 0) +#define RAM0_ECC_VECCEN (1 << 0) +#define RAM0_ECC_EC7TERVE (1 << 1) +#define RAM0_EN_VCEN (1 << 0) +#define RAM0_EN_VLWEN (1 << 1) +#define RAM0_TEST_READTEST (1 << 0) +#define RAM0_MON_RAMON_O (1 << 0) +#define RAM1_ECC_VECCEN (1 << 0) +#define RAM1_ECC_EC7TERVE (1 << 1) +#define RAM1_EN_VCEN (1 << 0) +#define RAM1_EN_VLWEN (1 << 1) +#define RAM1_TEST_READTEST (1 << 0) +#define RAM1_MON_RAMON_O (1 << 0) +#define WDT0_CTRL_WDTSTOP (1 << 0) +#define WDT0_CTRL_WDTSTOPMASK (1 << 16) +#define WDT1_CTRL_WDTSTOP (1 << 0) +#define WDT1_CTRL_WDTSTOPMASK (1 << 16) +#define WDT2_CTRL_WDTSTOP (1 << 0) +#define WDT2_CTRL_WDTSTOPMASK (1 << 16) +#define WDT3_CTRL_WDTSTOP (1 << 0) +#define WDT3_CTRL_WDTSTOPMASK (1 << 16) +#define GPU_COHE_COHERENCY (1 << 0) +#define GPU_TEXT_TEXFMTENABLE (1 << 0) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_00 (0 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_01 (1 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_10 (2 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_11 (3 << 24) +#define H264_CFG1_VPI_CAXI2_ENABLE_N (1 << 0) +#define H264_CFG2_VPI_CAXI_DPIC_STALL (1 << 0) +#define H264_MON_VPO_CAXI_DPIC_VALID (1 << 0) +#define H264_MON_VPO_CAXI_DPIC_MBL_START (1 << 8) +#define H264_MON_VPO_CAXI_DPIC_2D_START (1 << 16) +#define H264_BSTOP_FCI_CL_ISREQ_P (1 << 0) +#define H264_BSTOP_FCO_CL_ISACK_P (1 << 16) +#define GETH0_CFG_AVB_MIIMG_PIMODE (1 << 0) +#define GETH0_CFG_FEC_MIIMG_PIMODE (1 << 16) +#define GETH0_CFG_FEC_GIGA_ENABLE (1 << 24) +#define GETH1_CFG_AVB_MIIMG_PIMODE (1 << 0) +#define GETH1_CFG_FEC_MIIMG_PIMODE (1 << 16) +#define GETH1_CFG_FEC_GIGA_ENABLE (1 << 24) +#define I2C0_CFG_af_bypass (1 << 0) +#define I2C0_CFG_c2dloop (1 << 8) +#define I2C0_CFG_d2cloop (1 << 9) +#define I2C1_CFG_af_bypass (1 << 0) +#define I2C1_CFG_c2dloop (1 << 8) +#define I2C1_CFG_d2cloop (1 << 9) +#define I2C2_CFG_af_bypass (1 << 0) +#define I2C2_CFG_c2dloop (1 << 8) +#define I2C2_CFG_d2cloop (1 << 9) +#define I2C3_CFG_af_bypass (1 << 0) +#define I2C3_CFG_c2dloop (1 << 8) +#define I2C3_CFG_d2cloop (1 << 9) +#define CANFD_CFG_RS_CANFD_MODE (1 << 0) +#define CANFD_CFG_RS_CANFD_NON_ISO_SEL (1 << 1) +#define CANFD_CFG_RS_CANFD_NON_ISO_EN (1 << 2) +#define SCIF0_CFG_e1_iotestmd (1 << 0) +#define SCIF1_CFG_e1_iotestmd (1 << 0) +#define SCIF2_CFG_e1_iotestmd (1 << 0) +#define SCIF3_CFG_e1_iotestmd (1 << 0) +#define SCIF4_CFG_e1_iotestmd (1 << 0) +#define SCI0_CFG_SY_TM32 (1 << 0) +#define SCI1_CFG__SY_TM32 (1 << 0) +#define CM33_STAT_CORECLKEN (1 << 0) +#define CM33_LOCK_LOCKSVTAIRCR (1 << 0) +#define CM33_LOCK_LOCKNSVTOR (1 << 1) +#define CM33_LOCK_LOCKSMPU (1 << 2) +#define CM33_LOCK_LOCKNSMPU (1 << 3) +#define CM33_LOCK_LOCKSAU (1 << 4) +#define CM33_CTL_CPUWAIT (1 << 0) +#define CA55_CFG_AArch0_AA64nAA32_0 (1 << 0) +#define CA55_CFG_AArch1_AA64nAA32_1 (1 << 1) +#define CA55_CFG_Endian0_CFGEND0 (1 << 0) +#define CA55_CFG_Endian1_CFGEND1 (1 << 1) +#define CA55_CFG_Thumb0_CFGTE0 (1 << 0) +#define CA55_CFG_Thumb1_CFGTE1 (1 << 1) +#define CA55_CFG_VA0_VINITHI0 (1 << 0) +#define CA55_CFG_VA1_VINITHI1 (1 << 1) +#define BBG_CTRL_ENABLE_REG_EN (1 << 0) +#define BBG_CTRL_REG_EN_CP (1 << 15) +#define BBG_CTRL_REG_EN_VBBP (1 << 13) +#define BBG_CTRL_REG_EN_VBBN (1 << 14) +#define BBG_CTRL_MON_EN_CP_STATE (1 << 15) +#define BBG_CTRL_MON_EN_VBBP_STATE (1 << 13) +#define BBG_CTRL_MON_EN_VBBN_STATE (1 << 14) +#define BBG_OFFSET_CTRL_EN_OFFSET (1 << 15) +#define BBG_OFFSET_INDEX_SEL_00 (0 << 0) +#define BBG_OFFSET_INDEX_SEL_01 (1 << 0) +#define BBG_OFFSET_INDEX_SEL_10 (2 << 0) +#define BBG_OFFSET_INDEX_SEL_11 (3 << 0) +#define BBG_OFFSET_P_TYPE_SEL_00 (0 << 2) +#define BBG_OFFSET_P_TYPE_SEL_01 (1 << 2) +#define BBG_OFFSET_P_TYPE_SEL_10 (2 << 2) +#define BBG_OFFSET_P_TYPE_SEL_11 (3 << 2) +#define BBG_OFFSET_N_TYPE_SEL_00 (0 << 4) +#define BBG_OFFSET_N_TYPE_SEL_01 (1 << 4) +#define BBG_OFFSET_N_TYPE_SEL_10 (2 << 4) +#define BBG_OFFSET_N_TYPE_SEL_11 (3 << 4) +#define BBG_OFFSET_R0_VALID_INV (1 << 6) +#define BBG_OFFSET_R1_VALID_INV (1 << 7) +#define BBG_OFFSET_R2_VALID_INV (1 << 8) +#define BBG_OFFSET_R0_VALID_NAND (1 << 9) +#define BBG_OFFSET_R1_VALID_NAND (1 << 10) +#define BBG_OFFSET_R2_VALID_NAND (1 << 11) +#define BBG_OFFSET_R0_VALID_NOR (1 << 12) +#define BBG_OFFSET_R1_VALID_NOR (1 << 13) +#define BBG_OFFSET_R2_VALID_NOR (1 << 14) +#define BBG_PFREQ_MON_P_FREQ_VALID (1 << 15) +#define BBG_NFREQ_MON_N_FREQ_VALID (1 << 15) +#define BBG_TEMP_MON_TEMP_VALID (1 << 15) +#define BBG_VOLT_MON_VOLT_VALID (1 << 15) +#define LSI_MODE_STAT_CPUHOLD (1 << 8) +#define LSI_MODE_STAT_DEBUGEN (1 << 9) +#define LSI_MODE_STAT_MD_CLKS (1 << 12) +#define LSI_MODE_STAT_MD_OSCDRV_00 (0 << 14) +#define LSI_MODE_STAT_MD_OSCDRV_01 (1 << 14) +#define LSI_MODE_STAT_MD_OSCDRV_10 (2 << 14) +#define LSI_MODE_STAT_MD_OSCDRV_11 (3 << 14) +#define LSI_MODE_STAT_STAT_SEC_EN (1 << 16) +#define LSI_PRR_CA55_1CPU (1 << 0) +#define LSI_PRR_CM33_DIS (1 << 4) +#define LSI_PRR_GPU_DIS (1 << 8) +#define LSI_OTPSECEN_SECEN (1 << 0) +#define LSI_OTPSECMODE_SECBT_SD (1 << 0) +#define LSI_OTPSECMODE_SECBT_EMMC18 (1 << 1) +#define LSI_OTPSECMODE_SECBT_EMMC33 (1 << 2) +#define LSI_OTPSECMODE_SECBT_SPI18 (1 << 3) +#define LSI_OTPSECMODE_SECBT_SPI33 (1 << 4) +#define LSI_OTPJAM_JAM_00 (0 << 0) +#define LSI_OTPJAM_JAM_01 (1 << 0) +#define LSI_OTPJAM_JAM_10 (2 << 0) +#define LSI_OTPJAM_JAM_11 (3 << 0) +#define LSI_OTPCORE_CA55_FREQ_00 (0 << 0) +#define LSI_OTPCORE_CA55_FREQ_01 (1 << 0) +#define LSI_OTPCORE_CA55_FREQ_10 (2 << 0) +#define LSI_OTPCORE_CA55_FREQ_11 (3 << 0) +#define LSI_OTPPOC_SD_E_00 (0 << 0) +#define LSI_OTPPOC_SD_E_01 (1 << 0) +#define LSI_OTPPOC_SD_E_10 (2 << 0) +#define LSI_OTPPOC_SD_E_11 (3 << 0) +#define LSI_OTPPOC_EMMC18_E_00 (0 << 2) +#define LSI_OTPPOC_EMMC18_E_01 (1 << 2) +#define LSI_OTPPOC_EMMC18_E_10 (2 << 2) +#define LSI_OTPPOC_EMMC18_E_11 (3 << 2) +#define LSI_OTPPOC_EMMC33_E_00 (0 << 4) +#define LSI_OTPPOC_EMMC33_E_01 (1 << 4) +#define LSI_OTPPOC_EMMC33_E_10 (2 << 4) +#define LSI_OTPPOC_EMMC33_E_11 (3 << 4) +#define LSI_OTPPOC_SPI18_E_00 (0 << 6) +#define LSI_OTPPOC_SPI18_E_01 (1 << 6) +#define LSI_OTPPOC_SPI18_E_10 (2 << 6) +#define LSI_OTPPOC_SPI18_E_11 (3 << 6) +#define LSI_OTPPOC_SPI33_E_00 (0 << 8) +#define LSI_OTPPOC_SPI33_E_01 (1 << 8) +#define LSI_OTPPOC_SPI33_E_10 (2 << 8) +#define LSI_OTPPOC_SPI33_E_11 (3 << 8) +#define LSI_OTPPOC_SCIF_E_00 (0 << 10) +#define LSI_OTPPOC_SCIF_E_01 (1 << 10) +#define LSI_OTPPOC_SCIF_E_10 (2 << 10) +#define LSI_OTPPOC_SCIF_E_11 (3 << 10) +#define LP_CTL0_MAIN_CPU (1 << 0) +#define LP_CTL1_STBY (1 << 0) +#define LP_CTL1_CA55SLEEP_REQ_00 (0 << 8) +#define LP_CTL1_CA55SLEEP_REQ_01 (1 << 8) +#define LP_CTL1_CA55SLEEP_REQ_10 (2 << 8) +#define LP_CTL1_CA55SLEEP_REQ_11 (3 << 8) +#define LP_CTL1_CM33SLEEP_REQ (1 << 12) +#define LP_CTL1_STBY_CA55ST (1 << 16) +#define LP_CTL1_STBY_CM33ST (1 << 17) +#define LP_CTL1_CA55SLEEP_ACK_00 (0 << 24) +#define LP_CTL1_CA55SLEEP_ACK_01 (1 << 24) +#define LP_CTL1_CA55SLEEP_ACK_10 (2 << 24) +#define LP_CTL1_CA55SLEEP_ACK_11 (3 << 24) +#define LP_CTL1_CM33SLEEP_ACK (1 << 28) +#define LP_CTL2_CA55_STBYCTL (1 << 0) +#define LP_CTL3_U0DP_F (1 << 0) +#define LP_CTL3_U0DM_F (1 << 1) +#define LP_CTL3_U0VBUSIN_F (1 << 2) +#define LP_CTL3_U0OVRCLR_F (1 << 3) +#define LP_CTL3_U1DP_F (1 << 8) +#define LP_CTL3_U1DM_F (1 << 9) +#define LP_CTL3_U1OVRCLR_F (1 << 11) +#define LP_CTL3_NMI_F (1 << 24) +#define LP_CTL4_U0DP_E (1 << 0) +#define LP_CTL4_U0DM_E (1 << 1) +#define LP_CTL4_U0VBUSIN_E (1 << 2) +#define LP_CTL4_U0OVRCLR_E (1 << 3) +#define LP_CTL4_U1DP_E (1 << 8) +#define LP_CTL4_U1DM_E (1 << 9) +#define LP_CTL4_U1OVRCLR_E (1 << 11) +#define LP_CTL4_IRQ_E0 (1 << 16) +#define LP_CTL4_IRQ_E1 (1 << 17) +#define LP_CTL4_IRQ_E2 (1 << 18) +#define LP_CTL4_IRQ_E3 (1 << 19) +#define LP_CTL4_IRQ_E4 (1 << 20) +#define LP_CTL4_IRQ_E5 (1 << 21) +#define LP_CTL4_IRQ_E6 (1 << 22) +#define LP_CTL4_IRQ_E7 (1 << 23) +#define LP_CTL4_NMI_E (1 << 24) +#define LP_CTL5_Q4_DENY_F (1 << 0) +#define LP_CTL5_Q9_DENY_F (1 << 1) +#define LP_CTL5_Q10_DENY_F (1 << 2) +#define LP_CTL5_STBY_F (1 << 4) +#define LP_CTL5_CA55SLEEP0_F (1 << 8) +#define LP_CTL5_CA55SLEEP1_F (1 << 9) +#define LP_CTL5_CM33SLEEP_F (1 << 10) +#define LP_CTL5_CA55STBYDONE_F (1 << 16) +#define LP_CTL5_CM33STBYR_F (1 << 20) +#define LP_CTL6_Q4_DENY_E (1 << 0) +#define LP_CTL6_Q9_DENY_E (1 << 1) +#define LP_CTL6_Q10_DENY_E (1 << 2) +#define LP_CTL6_STBY_E (1 << 4) +#define LP_CTL6_CA55STBYDONE_E (1 << 5) +#define LP_CTL6_CM33STBYR_E (1 << 6) +#define LP_CTL6_CA55SLEEP0_E (1 << 8) +#define LP_CTL6_CA55SLEEP1_E (1 << 9) +#define LP_CTL6_CM33SLEEP_E (1 << 10) +#define LP_CTL7_IM33_MASK (1 << 0) +#define LP_CTL8_SUBCPU_RTRIG (1 << 0) +#define LP_CM33CTL0_SLEEPING (1 << 0) +#define LP_CM33CTL0_SLEEPDEEP (1 << 4) +#define LP_CM33CTL0_WAKEUP (1 << 8) +#define LP_CM33CTL0_SYSRESETREQ (1 << 9) +#define LP_CM33CTL0_SLEEPHOLDREQn (1 << 16) +#define LP_CM33CTL0_SLEEPHOLDACKn (1 << 17) +#define LP_CM33CTL0_WICENREQ (1 << 24) +#define LP_CM33CTL0_WICENACK (1 << 25) +#define LP_CM33CTL1_COREQACTIVE (1 << 0) +#define LP_CM33CTL1_DBGQACTIVE (1 << 4) +#define LP_CM33CTL1_COREQREQn (1 << 8) +#define LP_CM33CTL1_DBGQREQn (1 << 12) +#define LP_CM33CTL1_COREQACCEPTn (1 << 16) +#define LP_CM33CTL1_QDBGACCEPTn (1 << 20) +#define LP_CM33CTL1_COREQDENY (1 << 24) +#define LP_CM33CTL1_DBGQDENY (1 << 28) +#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL1_PCLKQACTIVE (1 << 8) +#define LP_CA55CK_CTL1_ATCLKQACTIVE (1 << 9) +#define LP_CA55CK_CTL1_GICCLKQACTIVE (1 << 10) +#define LP_CA55CK_CTL1_PDBGCLKQACTIVE (1 << 11) +#define LP_CA55CK_CTL2_QREQn_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL2_QREQn_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL2_PCLKQREQn (1 << 8) +#define LP_CA55CK_CTL2_ATCLKQREQn (1 << 9) +#define LP_CA55CK_CTL2_GICCLKQREQn (1 << 10) +#define LP_CA55CK_CTL2_PDBGCLKQREQn (1 << 11) +#define LP_CA55CK_CTL3_SCLKQACCEPTn (1 << 0) +#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL3_PCLKQACCEPTn (1 << 8) +#define LP_CA55CK_CTL3_ATCLKQACCEPTn (1 << 9) +#define LP_CA55CK_CTL3_GICCLKQACCEPTn (1 << 10) +#define LP_CA55CK_CTL3_PDBGCLKQACCEPTn (1 << 11) +#define LP_CA55CK_CTL3_SCLKQDENY (1 << 16) +#define LP_CA55CK_CTL3_QDENY_Q_CLK_SLV (1 << 17) +#define LP_CA55CK_CTL3_QDENY_Q_CLK_MST (1 << 18) +#define LP_CA55CK_CTL3_PCLKQDENY (1 << 24) +#define LP_CA55CK_CTL3_ATCLKQDENY (1 << 25) +#define LP_CA55CK_CTL3_GICCLKQDENY (1 << 26) +#define LP_CA55CK_CTL3_PDBGCLKQDENY (1 << 27) +#define LP_GPU_CTL_QACTIVE_GPU (1 << 0) +#define LP_GPU_CTL_QACTIVE_AXI_SLV (1 << 1) +#define LP_GPU_CTL_QACTIVE_AXI_MST (1 << 2) +#define LP_GPU_CTL_QACTIVE_ACE_SLV (1 << 3) +#define LP_GPU_CTL_QACTIVE_ACE_MST (1 << 4) +#define LP_GPU_CTL_QREQn_GPU (1 << 8) +#define LP_GPU_CTL_QREQn_AXI_SLV (1 << 9) +#define LP_GPU_CTL_QREQn_AXI_MST (1 << 10) +#define LP_GPU_CTL_QREQn_ACE_SLV (1 << 11) +#define LP_GPU_CTL_QREQn_ACE_MST (1 << 12) +#define LP_GPU_CTL_QACCEPTn_GPU (1 << 16) +#define LP_GPU_CTL_QACCEPTn_AXI_SLV (1 << 17) +#define LP_GPU_CTL_QACCEPTn_AXI_MST (1 << 18) +#define LP_GPU_CTL_QACCEPTn_ACE_SLV (1 << 19) +#define LP_GPU_CTL_QACCEPTn_ACE_MST (1 << 20) +#define LP_GPU_CTL_QDENY_GPU (1 << 24) +#define LP_GPU_CTL_QDENY_AXI_SLV (1 << 25) +#define LP_GPU_CTL_QDENY_AXI_MST (1 << 26) +#define LP_GPU_CTL_QDENY_ACE_SLV (1 << 27) +#define LP_GPU_CTL_QDENY_ACE_MST (1 << 28) +#define IPCONT_SEL_SPI_OCTA_POS 0 +#define IPCONT_SEL_SPI_OCTA (1u << IPCONT_SEL_SPI_OCTA_POS) +#define IPCONT_SEL_SPI_OCTA_SPI 0u +#define IPCONT_SEL_SPI_OCTA_OCTA 1u + +#endif /* __SYS_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/xspi_api.h b/plat/renesas/rza/common/include/xspi_api.h new file mode 100644 index 0000000000..c050a9f9bc --- /dev/null +++ b/plat/renesas/rza/common/include/xspi_api.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _XSPI_API_H_ +#define _XSPI_API_H_ + +#include +#include +#include + +/** xSPI feature flags */ +#define XSPI_FEATURE_FORM112 (1U << 0) /* Form 1-1-2 supported */ +#define XSPI_FEATURE_FORM122 (1U << 1) /* Form 1-2-2 supported */ +#define XSPI_FEATURE_FORM222 (1U << 2) /* Form 2-2-2 supported */ +#define XSPI_FEATURE_DUAL \ + (XSPI_FEATURE_FORM112 | XSPI_FEATURE_FORM122 | XSPI_FEATURE_FORM222) +#define XSPI_FEATURE_FORM114 (1U << 3) /* Form 1-1-4 supported */ +#define XSPI_FEATURE_FORM144 (1U << 4) /* Form 1-4-4 supported */ +#define XSPI_FEATURE_FORM444 (1U << 5) /* Form 4-4-4 supported */ +#define XSPI_FEATURE_QUAD \ + (XSPI_FEATURE_FORM114 | XSPI_FEATURE_FORM144 | XSPI_FEATURE_FORM444) +#define XSPI_FEATURE_FORM118 (1U << 6) /* Form 1-1-8 supported */ +#define XSPI_FEATURE_FORM188 (1U << 7) /* Form 1-8-8 supported */ +#define XSPI_FEATURE_FORM888 (1U << 8) /* Form 8-8-8 supported */ +#define XSPI_FEATURE_OCTAL \ + (XSPI_FEATURE_FORM118 | XSPI_FEATURE_FORM188 | XSPI_FEATURE_FORM888) +#define XSPI_FEATURE_XIP_READ (1U << 12) /* XIP Read operation support */ +#define XSPI_FEATURE_XIP_WRITE (1U << 13) /* XIP Write operation support */ +#define XSPI_FEATURE_DDROP (1U << 14) /* DDR support for OP */ +#define XSPI_FEATURE_DDR (1U << 15) /* DDR support for Address/Data */ +#define XSPI_FEATURE_OCTARAM (1U << 16) /* OctaRAM addressing (RAS/CAS) supported */ + +/** xSPI transfer additional flags */ +#define XSPI_FLAGS_SEQUENTIAL_DDR \ + (1U << 0) /* Enable inverted order for DDR transfer */ +#define XSPI_FLAGS_FORCE_STROBE \ + (1U << 1) /* Force to use of data strobe signal for timing reference */ +#define XSPI_FLAGS_DATA_ACCESS \ + (1U << 2) /* Force to use data access method for exec_op */ + +/** xSPI Transfer form */ +typedef enum e_xspi_transfer_form { + SPI_FORM_1_1_1, /* Command executes at 1-1-1 form */ + SPI_FORM_1_1_2, /* Command executes at 1-1-2 form */ + SPI_FORM_1_2_2, /* Command executes at 1-2-2 form */ + SPI_FORM_2_2_2, /* Command executes at 2-2-2 form */ + SPI_FORM_1_1_4, /* Command executes at 1-1-4 form */ + SPI_FORM_1_4_4, /* Command executes at 1-4-4 form */ + SPI_FORM_4_4_4, /* Command executes at 4-4-4 form */ + SPI_FORM_1_1_8, /* Command executes at 1-1-8 form */ + SPI_FORM_1_8_8, /* Command executes at 1-8-8 form */ + SPI_FORM_8_8_8, /* Command executes at 8-8-8 form */ +} xspi_transfer_form_t; + +/** xSPI interface configuration */ +typedef struct st_xspi_cfg { + uint8_t channel; /* Channel number to be used */ + uintptr_t base; /* Regisgter base address */ + void const *extend; /* Implementation specific extended configuration */ +} xspi_cfg_t; + +/** xSPI control block. Allocate an implementation specific control block to pass into the xSPI API calls. */ +typedef void xspi_ctrl_t; + +/** xSPI operation table + */ +typedef struct st_xspi_op { + xspi_transfer_form_t form; ///< Transfer form + uint16_t op; ///< Operation code (for 2 byte op, highside used as 1st byte) + uint8_t op_size; ///< Operation code size (0 to 2) + bool op_is_ddr; ///< Operation code phase is DDR + uint32_t address; ///< Address (ignored for configuring in-place access) + uint8_t address_size; ///< Address size (0 to 4) + bool address_is_ddr; ///< Address phase is DDR + uint8_t additional_size; ///< Additional data size + uint32_t additional_value; ///< Additional data value + uint8_t dummy_cycles; ///< Dummy cycle count (as clocks) + size_t transfer_size; ///< Transfer size by bytes (ignored for configuring in-place access) + void *transfer_buffer; ///< Transfer buffer pointer (ignored for configuring in-place access) + bool transfer_is_ddr; ///< Transfer phase is DDR + uint8_t transfer_flag; ///< Additional transfer flags + uint8_t force_idle_level_mask; ///< Whether or not to force each IO level during the idle state + uint8_t force_idle_level_value; ///< IO level during the idle state + uint8_t slch_value; + uint8_t clsh_value; + uint8_t shsl_value; +} xspi_op_t; + +/** Shared Interface definition for xSPI */ +typedef struct st_xspi_api { + /** Prepare a channel for xSPI operation. + * + * @param[in, out] ctrl Pointer to user-provided storage for the control block. + * @param[in] cfg Pointer to xSPI configuration structure. + */ + int (*open)(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg); + + /** Clean up the xSPI control block. + * + * @param[in] ctrl Pointer to the opened control block. + */ + int (*close)(xspi_ctrl_t *const ctrl); + + /** Post initialization routine + * + * @param[in] ctrl Pointer to the opened control block. + */ + int (*post_init)(xspi_ctrl_t *const ctrl); + + /** Execute operation. + * + * @param[in, out] ctrl Pointer to the control block. + * @param[in] op Operation structure + * @param[in] is_write Transaction phase direction is write + */ + int (*exec_op)(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, + bool is_write); + + /** Configure for in-place access. + * For enabling in-place access, start_xip must be called. + * + * @param[in, out] ctrl Pointer to the control block. + * @param[in] rop Operation structure for read operation. + * @param[in] wop Operation structure for write operation. + * @note + * For the flash, wop must be nullptr. + * @note + * For the OctaRAM, wop must be specified. + */ + int (*configure_xip)(xspi_ctrl_t *const ctrl, + xspi_op_t const *const rop, + xspi_op_t const *const wop); + + /** Starting in-place access. + * For configuring in-place access, configure_xip must be called. + * + * @param[in, out] ctrl Pointer to the control block. + */ + int (*start_xip)(xspi_ctrl_t *const ctrl); + + /** Stopping in-place access. + * + * @param[in, out] ctrl Pointer to the control block. + */ + int (*stop_xip)(xspi_ctrl_t *const ctrl); + + /** Do manual calibration. + * + * @param[in, out] ctrl Pointer to the control block. + */ + int (*run_manual_calibration)(xspi_ctrl_t *const ctrl); + + /** Enabling auto calibration. + * + * @param[in, out] ctrl Pointer to the control block. + */ + int (*enable_auto_calibration)(xspi_ctrl_t *const ctrl); + + /** Disabling auto calibration. + * + * @param[in, out] ctrl Pointer to the control block. + */ + int (*disable_auto_calibration)(xspi_ctrl_t *const ctrl); + + /** Setting SPI frequency. + * + * @param[in, out] ctrl Pointer to the control block. + * @param[in] frequency_hz Pointer to the control block. + */ + int (*set_frequency)(xspi_ctrl_t *const ctrl, int frequency_hz); + + /** Invalidate cache for entire MMAP + * + * @param[in] ctrl Pointer to the control block. + */ + int (*inv_mmap)(xspi_ctrl_t *const ctrl); + + /** Clean cache for entire MMAP + * + * @param[in] ctrl Pointer to the control block. + */ + int (*clean_mmap)(xspi_ctrl_t *const ctrl); + + /** Get MMAP base + * + * @param[in] ctrl Pointer to the control block. + */ + uintptr_t (*get_mmap_base)(xspi_ctrl_t *const ctrl); + + /** Get MMAP size + * + * @param[in] ctrl Pointer to the control block. + */ + size_t (*get_mmap_size)(xspi_ctrl_t *const ctrl); + + /** Get features flag + * + * @param[in] ctrl Pointer to the control block. + */ + uint32_t (*get_features)(xspi_ctrl_t *const ctrl); +} xspi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_xspi_instance { + xspi_ctrl_t *ctrl; ///< Pointer to the control structure for this instance + xspi_cfg_t const *cfg; ///< Pointer to the configuration structure for this instance + xspi_api_t const *api; ///< Pointer to the API structure for this instance +} xspi_instance_t; + +/* external functions */ +extern void xspi_setup(void); + +int rz_xspi_read(void *buf, uint64_t from, size_t length); +#endif /* _XSPI_API_H_ */ diff --git a/plat/renesas/rza/common/include/xspidevice_api.h b/plat/renesas/rza/common/include/xspidevice_api.h new file mode 100644 index 0000000000..8ed371dd9a --- /dev/null +++ b/plat/renesas/rza/common/include/xspidevice_api.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _XSPIDEVICE_API_H_ +#define _XSPIDEVICE_API_H_ +#include +#include + +#include "xspi_api.h" + +/** xSPI device information */ +typedef struct st_xspidevice_info { + uint32_t capacity; /* Amount of memory */ + uint32_t minimum_erase_size; /* Minimum erase size (bytes) */ + char device_vendor[32]; /* Device vendor name */ + char device_product[32]; /* Device product name */ +} xspidevice_info_t; + +/** xSPI device configuration */ +typedef struct st_xspidevice_cfg { + const xspi_instance_t *xspi; /* Associated xSPI instance */ + void const *extend; /* Implementation configuration */ +} xspidevice_cfg_t; + +/** xSPI device control block. Allocate an implementation specific control block to pass into the xSPI API calls. */ +typedef void xspidevice_ctrl_t; + +/** xSPI device write status. */ +typedef enum xspidevice_write_status { + WRITE_STATUS_OK, + WRITE_STATUS_IN_PROGRESS, + WRITE_STATUS_PROTECTED, + WRITE_STATUS_FAIL, + WRITE_STATUS_SUSPENDED, + WRITE_STATUS_DISABLED, +} xspidevice_write_status_t; + +/** Shared Interface definition for xSPI */ +typedef struct st_xspidevice_api { + /** Prepare for communicate with SPI device + * + * @param[in, out] ctrl Control block allocated by user. + * @param[in] cfg Instance configuration parameter. + */ + int (*open)(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg); + + /** Clean up the xSPI control block. + * + * @param[in] ctrl Opened control block. + */ + int (*close)(xspidevice_ctrl_t *ctrl); + + /** Execute operation. + * + * @param[in, out] ctrl Opened control block. + * @param[in] op Operation structure + * @param[in] is_write Transaction phase direction is write + */ + int (*exec_op)(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, + bool is_write); + + /** Entering in-place access mode. + * + * @param[in, out] ctrl Opened control block. + */ + int (*enter_xip)(xspidevice_ctrl_t *ctrl); + + /** Exiting in-place access mode. + * + * @param[in, out] ctrl Opened control block. + */ + int (*exit_xip)(xspidevice_ctrl_t *ctrl); + + /** Get device information. + * + * @param[in, out] ctrl Opened control block. + * @param[out] info Pointer to user-provided storage for the device information + */ + int (*get_info)(xspidevice_ctrl_t *ctrl, xspidevice_info_t *info); + + /** Read memory + * + * @param[in, out] ctrl Opened control block. + * @param[out] buffer Pointer to user-provided storage for the read data + * @param[in] address Start address to read + * @param[in] length Bytes to read + */ + int (*read)(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, + size_t length); + + /** Write memory + * + * @param[in, out] ctrl Opened control block. + * @param[in] buffer Pointer to user-provided storage for the write data + * @param[in] address Start address to write + * @param[in] length Bytes to write + */ + int (*write)(xspidevice_ctrl_t *ctrl, void const *buffer, + size_t address, size_t length); + + /** Erase memory + * + * @param[in, out] ctrl Opened control block. + * @param[in] address Start address to write + * @param[in] length Bytes to write + */ + int (*erase)(xspidevice_ctrl_t *ctrl, size_t address, size_t length); + + /** Get write status + * + * @param[in, out] ctrl Opened control block. + */ + enum xspidevice_write_status (*get_write_status)( + xspidevice_ctrl_t *ctrl); + +} xspidevice_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_xspidevice_instance { + xspidevice_ctrl_t *ctrl; /* control structure */ + xspidevice_cfg_t const *cfg; /* configuration structure */ + xspidevice_api_t const *api; /* API structure */ +} xspidevice_instance_t; + +extern const int xspidevices_count; +extern const xspidevice_instance_t *xspidevices[]; + +#endif /* _XSPIDEVICE_API_H_ */ diff --git a/plat/renesas/rza/common/plat_early_setup.S b/plat/renesas/rza/common/plat_early_setup.S new file mode 100644 index 0000000000..b4ea588df7 --- /dev/null +++ b/plat/renesas/rza/common/plat_early_setup.S @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#define SYS_REG_BASE (0x1102) +#define SYS_REG_LSI_MODE (0xA00) +#define SYS_BITPOS_LSI_MODE_STAT_DEBUGEN (9) + +#define WAIT_CNT_HIGH16 (0x100) +#define WAIT_CNT_LOW16 (0) + + .globl plat_setup_early_console + + +func plat_setup_early_console + /* clear icache (SCTLR_EL3 init) */ + mov_imm x4, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT | SCTLR_SA_BIT | \ + SCTLR_A_BIT | SCTLR_DSSBS_BIT)) + msr sctlr_el3, x4 + isb + + /* check DEBUGEN */ + mov x4, #SYS_REG_LSI_MODE + movk x4, #SYS_REG_BASE, LSL #16 + ldr w5, [x4] + /* skip wait if DEBUGEN = 0 */ + tbz x5, #SYS_BITPOS_LSI_MODE_STAT_DEBUGEN, skip_wait + + /* wait */ + mov x4, #WAIT_CNT_LOW16 + movk x4, #WAIT_CNT_HIGH16, LSL #16 +wait_loop: + cbz x4, skip_wait + sub x4, x4, #1 + b wait_loop +skip_wait: + ret +endfunc plat_setup_early_console diff --git a/plat/renesas/rza/common/plat_gic.c b/plat/renesas/rza/common/plat_gic.c new file mode 100644 index 0000000000..0f8c743bb5 --- /dev/null +++ b/plat/renesas/rza/common/plat_gic.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include +#include +#include + +uintptr_t plat_rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr) +{ + mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +const gicv3_driver_data_t rza_gic_data = { + .gicd_base = PLAT_GICD_BASE, + .gicr_base = PLAT_GICR_BASE, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = plat_rdistif_base_addrs, + .mpidr_to_core_pos = plat_mpidr_to_core_pos, +}; + +void plat_gic_driver_init(void) +{ + gicv3_driver_init(&rza_gic_data); +} + +void plat_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void plat_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +void plat_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +void plat_gic_pcpu_init(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); +} diff --git a/plat/renesas/rza/common/plat_image_load.c b/plat/renesas/rza/common/plat_image_load.c new file mode 100644 index 0000000000..e10416226d --- /dev/null +++ b/plat/renesas/rza/common/plat_image_load.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#if (APPLOAD == RZ_NOFIP) +#define FSP_FROM_XSPI_BASE (FSP_BASE - RZA3_XSPI_MEMORY_BASE) +typedef struct fsp_app_header { + uint64_t entry_addr; + uint64_t entry_addr_inv; + uint64_t dest_addr; + uint64_t dest_addr_inv; + uint64_t payload_size; + uint64_t payload_size_inv; + uint8_t padding[432]; + uint8_t signature[32]; + uint8_t app_payload_start; +} fsp_app_header_t; +#endif /* (APPLOAD == RZ_NOFIP) */ + +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} + +void plat_flush_next_bl_params(void) +{ +} + +#if (APPLOAD == RZ_NOFIP) +int rz_check_fsp_header(fsp_app_header_t *header) +{ + int ret = 0; + + RZA_PRINTF_VERBOSE("Check Application Header...\n"); + if (~(header->entry_addr) != header->entry_addr_inv) { + ret = -1; + ERROR("The value of the entry point address does not match its inverted value\n"); + } + + if (0 == ret) { + if (~(header->dest_addr) != header->dest_addr_inv) { + ret = -1; + ERROR("The address to copy application image does not match its inverted value\n"); + } + } + + if (0 == ret) { + if (~(header->payload_size) != header->payload_size_inv) { + ret = -1; + ERROR("The size of application image does not match its inverted value\n"); + } + } + + if ((FSP_BASE + RZ_APP_PAYLOAD_OFFSET) != header->dest_addr) { + if (0 == ret) { + if ((header->dest_addr < PLAT_SRAM_BASE) || + ((header->dest_addr + header->payload_size) > + (PLAT_SRAM_BASE + PLAT_SRAM_SIZE))) { + if ((header->dest_addr < PLAT_SPIROM_BASE) || + ((header->dest_addr + header->payload_size) > + (PLAT_SPIROM_BASE + PLAT_SPIROM_SIZE))) { + if ((header->dest_addr < + PLAT_DDR1_BASE) || + ((header->dest_addr + + header->payload_size) > + (PLAT_DDR1_BASE + PLAT_DDR1_SIZE + + PLAT_DDR2_SIZE))) { + ret = -1; + ERROR("The application image to copy does not fit in memory\n"); + } + } + } + } + } + + if (0 == ret) { + RZA_PRINTF_VERBOSE("Success!\n"); + } + + return ret; +} + +void rz_update_descs(fsp_app_header_t *header) +{ + bl_params_t *bl2_params; + + bl2_params = plat_get_next_bl_params(); + + bl2_params->head->image_info->image_base = (uintptr_t)header->dest_addr; + bl2_params->head->image_info->image_max_size = header->payload_size; + bl2_params->head->image_info->h.attr |= IMAGE_ATTRIB_SKIP_LOADING; + bl2_params->head->ep_info->pc = (uintptr_t)header->entry_addr; + flush_bl_params_desc(); +} + +static fsp_app_header_t header_impl; +void rza_load_fsp(void) +{ + int ret = 0; + fsp_app_header_t *header; + + header = &header_impl; + + rz_xspi_read(header, FSP_FROM_XSPI_BASE, sizeof(*header)); + + ret = rz_check_fsp_header(header); + + if (0 == ret) { + if ((FSP_BASE + RZ_APP_PAYLOAD_OFFSET) != header->dest_addr) { + rz_xspi_read((void *)header->dest_addr, + RZ_APP_PAYLOAD_OFFSET + FSP_FROM_XSPI_BASE, + (size_t)header->payload_size); + flush_dcache_range((uintptr_t)(header->dest_addr), + header->payload_size); + } + rz_update_descs(header); + } else { + panic(); + } +} +#endif /* (APPLOAD == RZ_NOFIP) */ + +void rza_print_descs(void) +{ + bl_params_t *bl2_params; + + bl2_params = plat_get_next_bl_params(); + + /* In the case of release build, bl2_params isn't used */ + RZ_UNUSED_PARAM(bl2_params); + RZA_PRINTF_VERBOSE("Address to copy the application: 0x%08llx\n", + (uint64_t)bl2_params->head->image_info->image_base); + RZA_PRINTF_VERBOSE("Entry Point Address: 0x%08llx\n", + (uint64_t)bl2_params->head->ep_info->pc); + RZA_PRINTF_VERBOSE("Copy Data Size: %dbyte\n", + bl2_params->head->image_info->image_max_size); + RZA_PRINTF_VERBOSE("SPSR_EL3 settings:\n"); + if (MODE_RW_64 == GET_RW(bl2_params->head->ep_info->spsr)) { + RZA_PRINTF_VERBOSE("AArch64 execution state\n"); + } else { + RZA_PRINTF_VERBOSE("AArch32 execution state\n"); + } + + if (0 != ((bl2_params->head->ep_info->spsr >> SPSR_DAIF_SHIFT) & + DAIF_DBG_BIT)) { + RZA_PRINTF_VERBOSE("Debug exception enable\n"); + } + + if (0 != ((bl2_params->head->ep_info->spsr >> SPSR_DAIF_SHIFT) & + DAIF_ABT_BIT)) { + RZA_PRINTF_VERBOSE("SError interrupt enable\n"); + } + + if (0 != ((bl2_params->head->ep_info->spsr >> SPSR_DAIF_SHIFT) & + DAIF_IRQ_BIT)) { + RZA_PRINTF_VERBOSE("IRQ interrupt enable\n"); + } + + if (0 != ((bl2_params->head->ep_info->spsr >> SPSR_DAIF_SHIFT) & + DAIF_FIQ_BIT)) { + RZA_PRINTF_VERBOSE("FIQ interrupt enable\n"); + } + + RZA_PRINTF_VERBOSE("EL and stack pointer: "); + RZA_PRINTF_VERBOSE("EL%d", GET_EL(bl2_params->head->ep_info->spsr)); + if (MODE_SP_EL0 == GET_SP(bl2_params->head->ep_info->spsr)) { + RZA_PRINTF_VERBOSE("t\n"); + } else { + RZA_PRINTF_VERBOSE("h\n"); + } + + RZA_PRINTF("Jump to Application\n"); +} diff --git a/plat/renesas/rza/common/plat_pm.c b/plat/renesas/rza/common/plat_pm.c new file mode 100644 index 0000000000..fe94299b11 --- /dev/null +++ b/plat/renesas/rza/common/plat_pm.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include +#include + +uintptr_t gp_warm_ep; + +static int rza_pwr_domain_on(u_register_t mpidr) +{ + const uint32_t rval[2][2] = { + { SYS_CA55_CFG_RVAL0, SYS_CA55_CFG_RVAH0 }, + { SYS_CA55_CFG_RVAL1, SYS_CA55_CFG_RVAH1 } + }; + const uint32_t pch[2][2] = { { CPG_CORE0_PCHCTL, CPG_CORE0_PCHMON }, + { CPG_CORE1_PCHCTL, CPG_CORE1_PCHMON } }; + uint8_t coreid = MPIDR_AFFLVL1_VAL(mpidr); + + if (coreid > 1) + return PSCI_E_INVALID_PARAMS; + + mmio_write_32(rval[coreid][0], (uint32_t)(gp_warm_ep & 0xFFFFFFFC)); + mmio_write_32(rval[coreid][1], (uint32_t)((gp_warm_ep >> 32) & 0xFF)); + + /* Assert PORESET */ + mmio_write_32(CPG_RST_CA55, (0x00010000 << coreid)); + while ((mmio_read_32(CPG_RSTMON_CA55) & (0x1 << coreid)) == 0x0) + ; + + /* Deassert PORESET */ + mmio_write_32(CPG_RST_CA55, (0x00050005 << coreid)); + while ((mmio_read_32(CPG_RSTMON_CA55) & (0x1 << coreid)) != 0x0) + ; + + mmio_write_32(pch[coreid][0], 0x00080001); + while ((mmio_read_32(pch[coreid][1]) & 0x1) != 0x1) + ; + mmio_write_32(pch[coreid][0], 0x00080000); + while ((mmio_read_32(pch[coreid][1]) & 0x1) != 0x0) + ; + + return PSCI_E_SUCCESS; +} + +static void rza_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ +#if !DEBUG_PLAT_FPGA + plat_gic_pcpu_init(); + plat_gic_cpuif_enable(); +#endif +} + +const plat_psci_ops_t rza_plat_psci_ops = { + .pwr_domain_on = rza_pwr_domain_on, + .pwr_domain_on_finish = rza_pwr_domain_on_finish, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + gp_warm_ep = sec_entrypoint; + *psci_ops = &rza_plat_psci_ops; + + return 0; +} diff --git a/plat/renesas/rza/common/plat_rz_common.c b/plat/renesas/rza/common/plat_rz_common.c new file mode 100644 index 0000000000..110655d96f --- /dev/null +++ b/plat/renesas/rza/common/plat_rz_common.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +unsigned int plat_get_syscnt_freq2(void) +{ + return syc_get_freq(); +} diff --git a/plat/renesas/rza/common/plat_security.c b/plat/renesas/rza/common/plat_security.c new file mode 100644 index 0000000000..fa138877f7 --- /dev/null +++ b/plat/renesas/rza/common/plat_security.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +#include "plat_tzc_def.h" +#include "platform_def.h" +#include "rza_printf.h" +#include "sys_regs.h" + +typedef struct arm_tzc_regions_info { + unsigned long long base; + unsigned long long end; + unsigned int sec_attr; + unsigned int nsaid_permissions; +} arm_tzc_regions_info_t; + +static const struct { + uint32_t reg; + uint32_t msk; + uint32_t val; +} sys_acctl[] = { + /* Master Access Control Register */ + { SYS_MSTACCCTL0, 0x00BB00BBU, 0x00AAAA88U }, + { SYS_MSTACCCTL1, 0xBBBBBBBBU, 0xAAAAAAAAU }, + { SYS_MSTACCCTL2, 0x00BBBBBBU, 0x00AAAAAAU }, + { SYS_MSTACCCTL3, 0x00BBBBBBU, 0x00AAAAAAU }, + { SYS_MSTACCCTL4, 0x0B0B00BBU, 0x0A0A00AAU }, + { SYS_MSTACCCTL5, 0x00000000U, 0x00000000U }, + /* Slave Access Control Register */ + { SYS_SLVACCCTL0, 0x0000000FU, 0x00000008U }, + { SYS_SLVACCCTL1, 0x3FFF3CFFU, 0x0800C0AAU }, + { SYS_SLVACCCTL2, 0x00FFCFFFU, 0x00000002U }, + { SYS_SLVACCCTL3, 0x3FFF3FFFU, 0x00000000U }, + { SYS_SLVACCCTL4, 0xFFFF0FFFU, 0x00000000U }, + { SYS_SLVACCCTL5, 0x00000033U, 0x00000000U }, + { SYS_SLVACCCTL6, 0x0000000FU, 0x00000000U }, + { SYS_SLVACCCTL7, 0x0000000CU, 0x00000008U }, + { SYS_SLVACCCTL8, 0x0000000FU, 0x00000000U }, + { SYS_SLVACCCTL9, 0x00000000U, 0x00000000U }, + { SYS_SLVACCCTL10, 0x00000003U, 0x00000000U }, + { SYS_SLVACCCTL11, 0x00000000U, 0x00000000U }, + { SYS_SLVACCCTL12, 0x00000003U, 0x00000000U }, + { SYS_SLVACCCTL13, 0x00000003U, 0x00000000U }, + { SYS_SLVACCCTL14, 0x00000003U, 0x00000000U }, + { SYS_SLVACCCTL15, 0x00000000U, 0x00000000U }, +}; + +void plat_access_control_setup(void) +{ + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(sys_acctl); i++) { + uint32_t val = mmio_read_32(sys_acctl[i].reg) & + (~sys_acctl[i].msk); + val |= (sys_acctl[i].val & sys_acctl[i].msk); + mmio_write_32(sys_acctl[i].reg, val); + } +} + +uint8_t tzc400_get_num_filters(uintptr_t tzc_base) +{ + uint32_t tzc400_build; + + tzc400_build = mmio_read_32(tzc_base + BUILD_CONFIG_OFF); + + return (uint8_t)((tzc400_build >> BUILD_CONFIG_NF_SHIFT) & + BUILD_CONFIG_NF_MASK) + + 1U; +} + +void plat_tzc400_setup(uintptr_t tzc_base, + const arm_tzc_regions_info_t *tzc_regions) +{ + uint8_t num_filters; + unsigned int region_index = 1U; + const arm_tzc_regions_info_t *p; + const arm_tzc_regions_info_t init_tzc_regions[] = { { 0 } }; + + INFO("Configuring TrustZone Controller\n"); + + tzc400_init(tzc_base); + + tzc400_disable_filters(); + + tzc400_configure_region0(TZC_REGION_S_RDWR, + PLAT_TZC_REGION_ACCESS_NS_UNPRIV); + + if (tzc_regions == NULL) + p = init_tzc_regions; + else + p = tzc_regions; + + num_filters = tzc400_get_num_filters(tzc_base); + + for (; p->base != 0UL; p++) { + tzc400_configure_region((1 << num_filters) - 1, region_index, + p->base, p->end, p->sec_attr, + p->nsaid_permissions); + region_index++; + } + + INFO("Total %u regions set.\n", region_index); + + tzc400_set_action(TZC_ACTION_ERR); + + tzc400_enable_filters(); +} + +#if IMAGE_BL2 +static void bl2_security_setup(void) +{ + const arm_tzc_regions_info_t ddr_tzc_regions[] = { +#ifndef RZA3 +#if TRUSTED_BOARD_BOOT + /* security for BL31 and OP-TEE */ + { PLAT_FW_TZC_PROT_DRAM1_BASE, PLAT_FW_TZC_PROT_DRAM1_END, + TZC_REGION_S_RDWR, PLAT_TZC_REGION_ACCESS_S_UNPRIV }, + { PLAT_TEE_TZC_PROT_DRAM1_BASE, PLAT_TEE_TZC_PROT_DRAM1_END, + TZC_REGION_S_RDWR, PLAT_TZC_REGION_ACCESS_S_UNPRIV }, +#endif /* TRUSTED_BOARD_BOOT */ + {} +#else + { 0 } +#endif + }; + + /* initialize TZC-400 */ + plat_tzc400_setup(PLAT_TZC_DDR_BASE, &ddr_tzc_regions[0]); + plat_tzc400_setup(PLAT_TZC_SPI_BASE, NULL); + + /* setup Master/Slave Access Control */ + plat_access_control_setup(); +} +#endif + +#if IMAGE_BL31 +static void bl31_security_setup(void) +{ + const arm_tzc_regions_info_t msram_tzc_regions[] = { +#if TRUSTED_BOARD_BOOT + { PLAT_AP_TZC_PROT_SRAM1_BASE, PLAT_AP_TZC_PROT_SRAM1_END, + TZC_REGION_S_RDWR, PLAT_TZC_REGION_ACCESS_S_UNPRIV }, +#endif /* TRUSTED_BOARD_BOOT */ + {} + }; + + const arm_tzc_regions_info_t asram_tzc_regions[] = { +#if TRUSTED_BOARD_BOOT + { PLAT_AP_TZC_PROT_SRAM2_BASE, PLAT_AP_TZC_PROT_SRAM2_END, + TZC_REGION_S_RDWR, PLAT_TZC_REGION_ACCESS_S_UNPRIV }, +#endif /* TRUSTED_BOARD_BOOT */ + {} + }; + + /* Additional settings for TZC-400 SRAM */ + plat_tzc400_setup(PLAT_TZC_MSRAM_BASE, &msram_tzc_regions[0]); + plat_tzc400_setup(PLAT_TZC_ASRAM_BASE, &asram_tzc_regions[0]); +} +#endif + +void plat_security_setup(void) +{ +#if IMAGE_BL2 + bl2_security_setup(); +#endif + +#if IMAGE_BL31 + bl31_security_setup(); +#endif +} diff --git a/plat/renesas/rza/common/plat_storage.c b/plat/renesas/rza/common/plat_storage.c new file mode 100644 index 0000000000..2889b8d0e0 --- /dev/null +++ b/plat/renesas/rza/common/plat_storage.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static uintptr_t memdrv_dev_handle; +static uintptr_t fip_dev_handle; +static uintptr_t emmcdrv_dev_handle; + +static uintptr_t boot_io_drv_id; + +static const io_block_spec_t spirom_block_spec = { + .offset = PLAT_SPIROM_FIP_BASE, + .length = PLAT_SPIROM_FIP_SIZE, +}; + +static const io_drv_spec_t emmc_block_spec = { + .offset = PLAT_EMMC_FIP_BASE, + .length = PLAT_EMMC_FIP_SIZE, +}; + +static const io_uuid_spec_t bl31_file_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_file_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl33_file_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t soc_fw_key_cert_file_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_content_cert_file_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_file_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_content_cert_file_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_file_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_content_cert_file_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif + +static int32_t open_emmcdrv(const uintptr_t spec); +static int32_t open_memmap(const uintptr_t spec); +static int32_t open_fipdrv(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int32_t (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy *policies; + +static const struct plat_io_policy spirom_policies[] = { + [FIP_IMAGE_ID] = { &memdrv_dev_handle, (uintptr_t)&spirom_block_spec, + &open_memmap }, + [BL31_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl31_file_spec, + &open_fipdrv }, + [BL32_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl32_file_spec, + &open_fipdrv }, + [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_file_spec, + &open_fipdrv }, +#if TRUSTED_BOARD_BOOT + [SOC_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_file_spec, + &open_fipdrv }, + [SOC_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&soc_fw_content_cert_file_spec, + &open_fipdrv }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_file_spec, + &open_fipdrv }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&tos_fw_content_cert_file_spec, + &open_fipdrv }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_file_spec, + &open_fipdrv }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&nt_fw_content_cert_file_spec, + &open_fipdrv }, +#endif + { 0, 0, 0 } +}; + +static const struct plat_io_policy emmc_policies[] = { + [FIP_IMAGE_ID] = { &emmcdrv_dev_handle, (uintptr_t)&emmc_block_spec, + &open_emmcdrv }, + [BL31_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl31_file_spec, + &open_fipdrv }, + [BL32_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl32_file_spec, + &open_fipdrv }, + [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_file_spec, + &open_fipdrv }, +#if TRUSTED_BOARD_BOOT + [SOC_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_file_spec, + &open_fipdrv }, + [SOC_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&soc_fw_content_cert_file_spec, + &open_fipdrv }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_file_spec, + &open_fipdrv }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&tos_fw_content_cert_file_spec, + &open_fipdrv }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_file_spec, + &open_fipdrv }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { &fip_dev_handle, + (uintptr_t)&nt_fw_content_cert_file_spec, + &open_fipdrv }, +#endif + { 0, 0, 0 } +}; + +static int32_t open_fipdrv(const uintptr_t spec) +{ + int32_t result; + + result = io_dev_init(fip_dev_handle, boot_io_drv_id); + if (result != 0) + return result; + + return result; +} + +static int32_t open_memmap(const uintptr_t spec) +{ + uintptr_t handle; + int32_t result; + + result = io_dev_init(memdrv_dev_handle, 0); + if (result != 0) + return result; + + result = io_open(memdrv_dev_handle, spec, &handle); + if (result == 0) + io_close(handle); + + return result; +} + +static int32_t open_emmcdrv(const uintptr_t spec) +{ + return io_dev_init(emmcdrv_dev_handle, 0); +} + +void rz_io_setup(void) +{ + const io_dev_connector_t *memmap; + const io_dev_connector_t *emmc; + const io_dev_connector_t *rza; + uint16_t boot_dev; + + boot_dev = *((uint16_t *)PLAT_BOOTINFO_BASE) & MASK_BOOTM_DEVICE; + + boot_io_drv_id = FIP_IMAGE_ID; + + xspi_setup(); + + register_io_dev_fip(&rza); + + io_dev_open(rza, 0, &fip_dev_handle); + + if ((boot_dev == BOOT_MODE_SPI_1_8) || + (boot_dev == BOOT_MODE_SPI_3_3) || + (boot_dev == BOOT_MODE_NAND_SPI_1_8) || + (boot_dev == BOOT_MODE_NAND_SPI_3_3)) { + register_io_dev_memmap(&memmap); + io_dev_open(memmap, 0, &memdrv_dev_handle); + + policies = &spirom_policies[0]; + } else if (USE_EMMC && (boot_dev == BOOT_MODE_EMMC_1_8 || + boot_dev == BOOT_MODE_EMMC_3_3)) { + if (emmc_init() != EMMC_SUCCESS) { + NOTICE("BL2: Failed to eMMC driver initialize.\n"); + panic(); + } + emmc_memcard_power(EMMC_POWER_ON); + if (emmc_mount() != EMMC_SUCCESS) { + NOTICE("BL2: Failed to eMMC mount operation.\n"); + panic(); + } + + register_io_dev_emmcdrv(&emmc); + io_dev_open(emmc, 0, &emmcdrv_dev_handle); + + policies = &emmc_policies[0]; + } else { + panic(); + } +} + +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + const struct plat_io_policy *policy; + int result; + + policy = &policies[image_id]; + + result = policy->check(policy->image_spec); + if (result != 0) + return result; + + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + + return 0; +} diff --git a/plat/renesas/rza/common/plat_topology.c b/plat/renesas/rza/common/plat_topology.c new file mode 100644 index 0000000000..64996680a6 --- /dev/null +++ b/plat/renesas/rza/common/plat_topology.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +static const unsigned char rza_power_domain_tree_desc[] = { + PLATFORM_SYSTEM_COUNT, PLATFORM_CLUSTER_COUNT, PLATFORM_CORE_COUNT +}; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rza_power_domain_tree_desc; +} + +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + cluster_id = MPIDR_AFFLVL2_VAL(mpidr); + cpu_id = MPIDR_AFFLVL1_VAL(mpidr); + + if ((cluster_id >= PLATFORM_CLUSTER_COUNT) || + (cpu_id >= PLATFORM_CORE_COUNT)) + return -1; + + return cpu_id; +} diff --git a/plat/renesas/rza/common/rz_bl2_xspi_config.sh b/plat/renesas/rza/common/rz_bl2_xspi_config.sh new file mode 100644 index 0000000000..c9758f7beb --- /dev/null +++ b/plat/renesas/rza/common/rz_bl2_xspi_config.sh @@ -0,0 +1,159 @@ +#!/bin/sh +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +envfile=$1 +outfile=$2 +_devices= +_index=0 + +usage() +{ + echo "" + echo "Please specify environment definition file and output file" + exit 1 +} + +error() +{ + local message=$1 + shift + echo "" + echo "Error: $message" + exit 1 +} + +add_device() +{ + local basename=$1 + shift + + # indirect dereference + eval _if_name=\$RZ_${basename}_IF + eval _if_config=\$RZ_${basename}_IF_CONFIG + eval _device=\$${basename}_DEVICE + eval _option=\$${basename}_OPTION + eval _if_option=\$${basename}_IF_OPTION + + # add if defined + if [ -n "$_device" ]; then + # IF + cat << EOT >> "${outfile}" +${_if_name}_ctrl_t xspi${_index}_ctrl; + +EOT + if [ -n "$_if_option" ]; then + cat << EOT >> "${outfile}" +const ${_if_name}_ext_t xspi${_index}_ext = { + ${_if_option} +}; + +const xspi_cfg_t xspi${_index}_cfg = { + ${_if_config}, + .extend=&xspi${_index}_ext +}; +EOT + else + cat << EOT >> "${outfile}" +const xspi_cfg_t xspi${_index}_cfg = { + ${_if_config}, + .extend=NULL +}; +EOT + fi + cat << EOT >> "${outfile}" + +const xspi_instance_t xspi${_index} = { + .ctrl=&xspi${_index}_ctrl, + .cfg=&xspi${_index}_cfg, + .api=&${_if_name}_api +}; + +EOT + + # DEVICE + cat << EOT >> "${outfile}" +${_device}_ctrl_t xspidevice${_index}_ctrl; + +EOT + if [ -n "$_option" ]; then + cat << EOT >> "${outfile}" +const ${_device}_ext_t xspidevice${_index}_ext = { + ${_option} +}; + +const xspidevice_cfg_t xspidevice${_index}_cfg = { + .xspi=&xspi${_index}, + .extend=&xspidevice${_index}_ext +}; +EOT + else + cat << EOT >> "${outfile}" +const xspidevice_cfg_t xspidevice${_index}_cfg = { + .xspi=&xspi${_index}, + .extend=NULL +}; +EOT + fi + cat << EOT >> "${outfile}" + +const xspidevice_instance_t xspidevice${_index} = { + .ctrl=&xspidevice${_index}_ctrl, + .cfg=&xspidevice${_index}_cfg, + .api=&${_device}_api +}; + +EOT + + # append device + _devices="${_devices} xspidevice${_index}" + + _index=`expr ${_index} + 1` + fi +} + +# Script begin +if [ -z "$envfile" ]; then + usage +fi + +if [ -z "$outfile" ]; then + usage +fi + +# Create outfile and test if failed +echo "/* Generated by ${0} */" > "$outfile" +if ! [ $? ]; then + error "Aborted." +fi + +# Import environment +if [ -f "$envfile" ]; then + . "$envfile" +fi + +# Append includes +for header in $RZ_XSPI_HEADERS +do + echo "#include \"$header\"" >> "${outfile}" +done +echo "" >> "${outfile}" + +# Append definitions +for device in $RZ_XSPI_CONFIGS +do + add_device $device +done + +# List device instances +if [ -n "$_devices" ]; then + echo "const int xspidevices_count = ${_index};" >> "${outfile}" + echo "const xspidevice_instance_t * xspidevices[${_index}] = {" >> "${outfile}" + for instance in $_devices + do + echo " &${instance}," >> "${outfile}" + done + echo "};" >> "${outfile}" +fi + diff --git a/plat/renesas/rza/common/rz_common.mk b/plat/renesas/rza/common/rz_common.mk new file mode 100644 index 0000000000..3031ae9829 --- /dev/null +++ b/plat/renesas/rza/common/rz_common.mk @@ -0,0 +1,112 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +RESET_TO_BL2 := 1 +COLD_BOOT_SINGLE_CPU := 1 +PROGRAMMABLE_RESET_ADDRESS := 1 +WARMBOOT_ENABLE_DCACHE_EARLY := 1 +GICV3_SUPPORT_GIC600 := 1 +HW_ASSISTED_COHERENCY := 1 +USE_COHERENT_MEM := 0 +TRUSTED_BOARD_BOOT := 0 +PROTECTED_CHIPID := 1 +DEBUG_PLAT_FPGA := 0 +EARLY_CONSOLE := 1 +$(eval $(call add_define,PROTECTED_CHIPID)) +$(eval $(call add_define,DEBUG_PLAT_FPGA)) + +WA_PLAT_GIC64BIT := 1 +$(eval $(call add_define,WA_PLAT_GIC64BIT)) + +ifeq (${DEBUG_PLAT_FPGA}, 0) + USE_SDRAM ?= 1 +else + USE_SDRAM ?= 0 +endif +$(eval $(call add_define,USE_SDRAM)) + +USE_EMMC ?= 0 +$(eval $(call add_define,USE_EMMC)) + +# Enable workarounds for selected Cortex-A55 erratas. +ERRATA_A55_1530923 := 1 + +ifeq (${APPLOAD},RZ_NOFIP) +FSP_BASE ?= 0x20020000 +$(eval $(call add_define,FSP_BASE)) +endif + +PLAT_INCLUDES := -Iplat/renesas/rza/common/include \ + -Iplat/renesas/rza/common/drivers/emmc \ + -Iplat/renesas/rza/common/drivers/io \ + -Idrivers/renesas/common/io + +RZ_TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ + drivers/delay_timer/delay_timer.c + +ifneq (${USE_SDRAM}, 0) +DDR_SOURCES := plat/renesas/rza/common/drivers/ddr/ddr.c +endif + +ifneq (${ARCH_TYPE}, 0) +MMU_SOURCE := plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c +endif + +BL2_SOURCES += lib/cpus/aarch64/cortex_a55.S \ + ${RZ_TIMER_SOURCES} \ + ${DYN_CFG_SOURCES} \ + common/desc_image_load.c \ + drivers/io/io_storage.c \ + drivers/io/io_memmap.c \ + drivers/io/io_fip.c \ + drivers/arm/tzc/tzc400.c \ + plat/renesas/rza/common/drivers/io/io_emmcdrv.c \ + plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c \ + plat/renesas/rza/common/drivers/emmc/emmc_utility.c \ + plat/renesas/rza/common/drivers/emmc/emmc_mount.c \ + plat/renesas/rza/common/drivers/emmc/emmc_init.c \ + plat/renesas/rza/common/drivers/emmc/emmc_read.c \ + plat/renesas/rza/common/drivers/emmc/emmc_cmd.c \ + plat/renesas/rza/common/bl2_plat_setup.c \ + plat/renesas/rza/common/bl2_plat_mem_params_desc.c \ + plat/renesas/rza/common/plat_image_load.c \ + plat/renesas/rza/common/plat_early_setup.S \ + plat/renesas/rza/common/plat_storage.c \ + plat/renesas/rza/common/plat_security.c \ + plat/renesas/rza/common/aarch64/plat_helpers.S \ + plat/renesas/rza/common/drivers/syc.c \ + plat/renesas/rza/common/drivers/pfc.c \ + plat/renesas/rza/common/drivers/cpg.c \ + ${DDR_SOURCES} \ + ${XSPI_SOURCES} \ + ${MMU_SOURCE} + +# Include GICv3 driver files +GICV3_IMPL := GIC600 +include drivers/arm/gic/v3/gicv3.mk + +include lib/xlat_tables_v2/xlat_tables.mk +PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \ + plat/renesas/rza/common/plat_rz_common.c \ + plat/renesas/rza/common/drivers/scifa.S + +ifneq (${TRUSTED_BOARD_BOOT},0) +# Include common TBB sources +AUTH_SOURCES := drivers/auth/img_parser_mod.c + +# Include the selected chain of trust sources. +ifeq (${COT},tbbr) +AUTH_SOURCES += plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c +else +$(error Unknown chain of trust ${COT}) +endif + +# Include RZ TBB sources +AUTH_SOURCES += plat/renesas/rza/common/drivers/auth/auth_mod.c \ + plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c \ + plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c +BL2_SOURCES += ${AUTH_SOURCES} +endif diff --git a/plat/renesas/rza/common/rz_image.pl b/plat/renesas/rza/common/rz_image.pl new file mode 100644 index 0000000000..8299b9c416 --- /dev/null +++ b/plat/renesas/rza/common/rz_image.pl @@ -0,0 +1,74 @@ +#!/usr/bin/perl -w +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +use strict; +use bigint; +my $size_limit = 0x1D000; + +die("Not enough parameter\n") if ($#ARGV < 0); + +# Open input file +my $name = shift(@ARGV); +my $outname; +if ($#ARGV < 0) { + $outname = "rz_" . $name; +} +else { + $outname = shift(@ARGV); +} +open(my $origin, '<', $name) or die("Can not open input file"); +binmode $origin; + +# Obtaining size ($st[7]) +my @st = stat($origin); + +# Check appended size +my $size = ($st[7] + 3) & "0xfffffffffffffffc"; +my $msg; +if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";} +die("$msg too big ($size > $size_limit)") if ($size > $size_limit); + +# Create temporary file +open(my $out, '>', $outname) or die("Can not open output file"); +binmode $out; + +# Write header +$out->print(pack('L', $size)); +for(my $i = 1; $i < 112; $i++) { + $out->print(pack('L', 0xffffffff)); +} +$out->print(pack('L', 0xffff0000)); +$out->print(pack('L', 0x000800ff)); +$out->print(pack('L', 0x00fff700)); +$out->print(pack('L', 0xf700f708)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xaa55ffff)); + +# Append original data to temporary file +my $buf; +read($origin, $buf, $st[7]); +$out->print($buf); +if($st[7] < $size) { + warn "Not aligned. Append " . ($size-$st[7]) . " zero(s)"; + # Append zero + for(;$st[7] < $size; $size--) { + $out->print(pack('C', 0)); + } +} +$out->flush; + +# close +close $out; +close $origin; diff --git a/plat/renesas/rza/common/rz_plat_sip_handler.c b/plat/renesas/rza/common/rz_plat_sip_handler.c new file mode 100644 index 0000000000..3df7bd40bf --- /dev/null +++ b/plat/renesas/rza/common/rz_plat_sip_handler.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#define RZ_OTP_BASE_DEVID (PLAT_OTP_BASE + 0x1178) +#define RZ_OTP_BASE_CHIPID (PLAT_OTP_BASE + 0x1140) + +static uintptr_t rz_otp_handler_devid(void *handle, u_register_t x1) +{ + uint32_t devid = mmio_read_32(RZ_OTP_BASE_DEVID); + SMC_RET1(handle, devid); +} + +static uintptr_t rz_otp_handler_chipid(void *handle, u_register_t x1, + u_register_t flags) +{ + uint32_t chipid[4]; + +#if (PROTECTED_CHIPID == 1) + uint32_t ns = is_caller_non_secure(flags); + if (ns) { + WARN("%s: Unauthorized service call from non-secure\n", + __func__); + SMC_RET1(handle, SMC_UNK); + } +#endif + + chipid[0] = mmio_read_32(RZ_OTP_BASE_CHIPID + 0x0); + chipid[1] = mmio_read_32(RZ_OTP_BASE_CHIPID + 0x4); + chipid[2] = mmio_read_32(RZ_OTP_BASE_CHIPID + 0x8); + chipid[3] = mmio_read_32(RZ_OTP_BASE_CHIPID + 0xC); + + SMC_RET4(handle, chipid[0], chipid[1], chipid[2], chipid[3]); +} + +uintptr_t rz_plat_sip_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, u_register_t x4, + void *cookie, void *handle, u_register_t flags) +{ + switch (smc_fid) { + case RZ_SIP_SVC_GET_DEVID: + return rz_otp_handler_devid(handle, x1); + case RZ_SIP_SVC_GET_CHIPID: + return rz_otp_handler_chipid(handle, x1, flags); + default: + WARN("%s: Unimplemented RZ SiP Service Call: 0x%x\n", __func__, + smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/plat/renesas/rza/common/rz_sip_svc.c b/plat/renesas/rza/common/rz_sip_svc.c new file mode 100644 index 0000000000..77ca5071c8 --- /dev/null +++ b/plat/renesas/rza/common/rz_sip_svc.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include +#include +#include + +#pragma weak rz_plat_sip_handler + +uintptr_t rz_plat_sip_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, u_register_t x4, + void *cookie, void *handle, u_register_t flags) +{ + WARN("%s: Unimplemented RZ SiP Service Call: 0x%x\n", __func__, + smc_fid); + SMC_RET1(handle, SMC_UNK); +} + +/* + * This function handles RZ defined SiP Calls + */ +static uintptr_t rz_sip_handler(unsigned int smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, void *handle, + u_register_t flags) +{ + return rz_plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC(rz_sip_svc, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, NULL, + rz_sip_handler); diff --git a/plat/renesas/rza/common/rz_xspi_common.mk b/plat/renesas/rza/common/rz_xspi_common.mk new file mode 100644 index 0000000000..db1831428d --- /dev/null +++ b/plat/renesas/rza/common/rz_xspi_common.mk @@ -0,0 +1,67 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +RZ_BUILD_PLAT_TMP := $(BUILD_PLAT) +RZ_XSPI_DEF := $(RZ_BUILD_PLAT_TMP)/rz_bl2_xspi_def.c +RZ_XSPI_ENV := $(RZ_BUILD_PLAT_TMP)/rz_bl2_xspi.env +RZ_XSPI_HEADERS := xspi_api.h xspidevice_api.h $(RZ_XSPI_HEADERS) +RZ_USE_XSPI := 0 + +RZ_XSPIFLASH_DISABLE_WRITE := 1 +RZ_XSPI_FORCE_VOLTAGE_SETTING := 0 +$(eval $(call add_define,RZ_XSPIFLASH_DISABLE_WRITE)) +$(eval $(call add_define,RZ_XSPI_FORCE_VOLTAGE_SETTING)) + +rz_uniq = $(if $1,$(firstword $1) $(call rz_uniq,$(filter-out $(firstword $1),$1))) + +define RZ_XSPI_ADD_IFDRIVER + $(eval RZ_XSPI_SOURCES:=$(RZ_XSPI_SOURCES) $(RZ_XSPI_DRIVER_PATH)/$(1).c) + $(eval RZ_XSPI_HEADERS:=$(RZ_XSPI_HEADERS) $(1).h) +endef + +define RZ_XSPI_INCLUDE_MAKEFILE + $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(call RZ_XSPI_ADD_IFDRIVER,$(RZ_$(1)_IF))) + $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(eval include plat/renesas/rza/common/drivers/xspidevice/$($(1)_DEVICE)/rz_xspidevice.mk)) + $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(eval RZ_USE_XSPI:=1)) +endef + +# export environment to shell +define RZ_ADD_ENV + @echo $(1)=\"$(strip $($(1)))\" >> $@ + +endef + +define RZ_XSPI_ADD_ENV + $(call RZ_ADD_ENV,RZ_$(1)_IF) + $(call RZ_ADD_ENV,RZ_$(1)_IF_CONFIG) + $(call RZ_ADD_ENV,$(1)_DEVICE) + $(call RZ_ADD_ENV,$(1)_OPTION) + $(call RZ_ADD_ENV,$(1)_IF_OPTION) +endef + +# include makefile for xspidevice driver +$(foreach element,$(RZ_XSPI_CONFIGS),$(call RZ_XSPI_INCLUDE_MAKEFILE,$(element))) + +# eliminate duplicated entries in sources and headers +RZ_XSPI_SOURCES:=$(call rz_uniq,$(RZ_XSPI_SOURCES)) +RZ_XSPI_HEADERS:=$(call rz_uniq,$(RZ_XSPI_HEADERS)) + +# add sources +ifneq ($(RZ_USE_XSPI),0) + XSPI_SOURCES+=$(RZ_XSPI_SOURCES) + XSPI_SOURCES+=$(RZ_XSPI_DEF) +# Outs env file +$(RZ_XSPI_ENV): $(RZ_BUILD_PLAT_TMP) + @echo -n "" > $@ + $(foreach element,$(RZ_XSPI_CONFIGS),$(call RZ_XSPI_ADD_ENV,$(element))) + $(call RZ_ADD_ENV,RZ_XSPI_CONFIGS) + $(call RZ_ADD_ENV,RZ_XSPI_HEADERS) + $(call RZ_ADD_ENV,PLAT) + $(call RZ_ADD_ENV,BOARD) + +$(RZ_XSPI_DEF): $(RZ_XSPI_ENV) + $(Q)$(SHELL) plat/renesas/rza/common/rz_bl2_xspi_config.sh "$(RZ_XSPI_ENV)" "$(RZ_XSPI_DEF)" +endif diff --git a/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c b/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c new file mode 100644 index 0000000000..1489876d24 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +void ddr_ctrl_reten_en_n(uint8_t val) +{ + val &= 1; + write_phy_reg(DDRPHY_R79, (val << 1)); +} diff --git a/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c b/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c new file mode 100644 index 0000000000..ab1826b22a --- /dev/null +++ b/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +const char ddr_an_version[] = "v0.0.41"; + +const uint32_t mc_init_tbl[][2] = { + { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000008 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x00027100 }, { DENALI_CTL_13, 0x00061A80 }, + { DENALI_CTL_14, 0x08160200 }, { DENALI_CTL_15, 0x00000000 }, + { DENALI_CTL_16, 0x06000404 }, { DENALI_CTL_17, 0x00002700 }, + { DENALI_CTL_18, 0x06060020 }, { DENALI_CTL_19, 0x0600200B }, + { DENALI_CTL_20, 0x000C0406 }, { DENALI_CTL_21, 0x0400DB60 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000C0B }, + { DENALI_CTL_24, 0x0B031701 }, { DENALI_CTL_25, 0x0100000B }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x00000058 }, { DENALI_CTL_31, 0x00000610 }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00140005 }, + { DENALI_CTL_34, 0x00600200 }, { DENALI_CTL_35, 0x00000060 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00018400 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00018400 }, + { DENALI_CTL_44, 0x00018400 }, { DENALI_CTL_45, 0x00018400 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00212100 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000C70 }, + { DENALI_CTL_70, 0x00000004 }, { DENALI_CTL_71, 0x00000018 }, + { DENALI_CTL_72, 0x00000C70 }, { DENALI_CTL_73, 0x00000004 }, + { DENALI_CTL_74, 0x00000018 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, + { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, + { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x00BEBD03 }, + { DENALI_CTL_118, 0x0000C350 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, + { DENALI_CTL_122, 0x04010100 }, { DENALI_CTL_123, 0x00010104 }, + { DENALI_CTL_124, 0x01FF0000 }, { DENALI_CTL_125, 0x00003F00 }, + { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060700 }, + { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01030101 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x030A0205 }, { DENALI_CTL_399, 0x00200307 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017104E2 }, + { DENALI_CTL_414, 0x4F5E64A8 }, { DENALI_CTL_415, 0x00003C30 }, + { DENALI_CTL_416, 0x00003C28 }, { DENALI_CTL_417, 0x00000000 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c b/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c new file mode 100644 index 0000000000..3567f7cf29 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +const char ddr_an_version[] = "v0.0.32"; + +const uint32_t mc_init_tbl[][2] = { + { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, + { DENALI_CTL_14, 0x07140200 }, { DENALI_CTL_15, 0x00000000 }, + { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002100 }, + { DENALI_CTL_18, 0x0505001B }, { DENALI_CTL_19, 0x05001B0A }, + { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A0A }, + { DENALI_CTL_24, 0x0A031401 }, { DENALI_CTL_25, 0x0100000A }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x0000004A }, { DENALI_CTL_31, 0x0000050C }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, + { DENALI_CTL_34, 0x00500200 }, { DENALI_CTL_35, 0x00000050 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00014300 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00014300 }, + { DENALI_CTL_44, 0x00014300 }, { DENALI_CTL_45, 0x00014300 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A60 }, + { DENALI_CTL_70, 0x00000004 }, { DENALI_CTL_71, 0x00000010 }, + { DENALI_CTL_72, 0x00000A60 }, { DENALI_CTL_73, 0x00000004 }, + { DENALI_CTL_74, 0x00000010 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, + { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, + { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, + { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, + { DENALI_CTL_122, 0x04010100 }, { DENALI_CTL_123, 0x00010104 }, + { DENALI_CTL_124, 0x01FF0000 }, { DENALI_CTL_125, 0x00003F00 }, + { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, + { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01030101 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x01090205 }, { DENALI_CTL_399, 0x00200106 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, + { DENALI_CTL_414, 0x4F5E64A8 }, { DENALI_CTL_415, 0x00003C30 }, + { DENALI_CTL_416, 0x00003C28 }, { DENALI_CTL_417, 0x00000000 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3m/drivers/xspi.c b/plat/renesas/rza/soc/a3m/drivers/xspi.c new file mode 100644 index 0000000000..2ee8da56be --- /dev/null +++ b/plat/renesas/rza/soc/a3m/drivers/xspi.c @@ -0,0 +1,71 @@ +#include + +#include +#include +#include +#include + +static int sub_init_xip(const xspidevice_instance_t *inst) +{ + int result; + result = inst->api->open(inst->ctrl, inst->cfg); + if (!result) { + result = inst->api->enter_xip(inst->ctrl); + inst->api->close(inst->ctrl); + } + return result; +} + +static int sub_post_init_xip(const xspi_instance_t *xspi) +{ + int result; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (!result) { + xspi->api->enable_auto_calibration(xspi->ctrl); + result = xspi->api->post_init(xspi->ctrl); + xspi->api->close(xspi->ctrl); + } + return result; +} + +void xspi_setup(void) +{ + int i; + int result = 0; + +#ifdef XSPI_DEVICE_TYPE + RZA_PRINTF("Configure %s Flash Memory\n", XSPI_DEVICE_TYPE); +#endif + for (i = 0; result >= 0 && i < xspidevices_count; i++) { + result = sub_init_xip(xspidevices[i]); + if (result < 0) { + ERROR("xspi.c: abort on sub_init_xip (#%d)\n", i); + panic(); + } + } + for (i = 0; result >= 0 && i < xspidevices_count; i++) { + result = sub_post_init_xip(xspidevices[i]->cfg->xspi); + if (result < 0) { + ERROR("xspi.c: abort on sub_post_init_xip (#%d)\n", i); + panic(); + } + } +} + +/** + * memcpy for xspi + */ +int rz_xspi_read(void *to, uint64_t offset, size_t length) +{ + int result; + const xspidevice_instance_t *inst = xspidevices[0]; + if (!inst) + return -1; + + result = inst->api->open(inst->ctrl, inst->cfg); + if (!result) { + inst->api->read(inst->ctrl, to, (size_t)offset, length); + inst->api->close(inst->ctrl); + } + return result; +} diff --git a/plat/renesas/rza/soc/a3m/include/cpg_opt.h b/plat/renesas/rza/soc/a3m/include/cpg_opt.h new file mode 100644 index 0000000000..4d04dd455f --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/cpg_opt.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CPG_OPT_H__ +#define __CPG_OPT_H__ + +#define CPG_RST_DDR_OPT_VALUE (0x00000000) + +#endif // __CPG_OPT_H__ diff --git a/plat/renesas/rza/soc/a3m/include/ddr_mc_if.h b/plat/renesas/rza/soc/a3m/include/ddr_mc_if.h new file mode 100644 index 0000000000..095d78e3c3 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/ddr_mc_if.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_MC_IF_H__ +#define __DDR_MC_IF_H__ + +#include + +#define MC_INIT_NUM (436) + +#define LP_CMD_OFFSET (0) + +#define DDRMC_R000 DENALI_CTL_00 +#define DDRMC_R001 DENALI_CTL_11 +#define DDRMC_R002 DENALI_CTL_14 +#define DDRMC_R003 DENALI_CTL_15 +#define DDRMC_R004 DENALI_CTL_56 +#define DDRMC_R005 DENALI_CTL_59 +#define DDRMC_R006 DENALI_CTL_60 +#define DDRMC_R007 DENALI_CTL_64 +#define DDRMC_R008 DENALI_CTL_67 +#define DDRMC_R009 DENALI_CTL_70 +#define DDRMC_R010 DENALI_CTL_71 +#define DDRMC_R011 DENALI_CTL_73 +#define DDRMC_R012 DENALI_CTL_74 +#define DDRMC_R013 DENALI_CTL_75 +#define DDRMC_R014 DENALI_CTL_76 +#define DDRMC_R015 DENALI_CTL_81 +#define DDRMC_R016 DENALI_CTL_82 +#define DDRMC_R017 DENALI_CTL_83 +#define DDRMC_R018 DENALI_CTL_84 +#define DDRMC_R019 DENALI_CTL_133 +#define DDRMC_R020 DENALI_CTL_134 +#define DDRMC_R021 DENALI_CTL_146 +#define DDRMC_R022 DENALI_CTL_147 +#define DDRMC_R023 DENALI_CTL_154 +#define DDRMC_R024 DENALI_CTL_155 +#define DDRMC_R025 DENALI_CTL_176 +#define DDRMC_R026 DENALI_CTL_177 +#define DDRMC_R027 DENALI_CTL_391 +#define DDRMC_R028 DENALI_CTL_398 +#define DDRMC_R029 DENALI_CTL_401 +#define DDRMC_R030 DENALI_CTL_403 +#define DDRMC_R031 DENALI_CTL_404 +#define DDRMC_R032 DENALI_CTL_405 +#define DDRMC_R033 DENALI_CTL_406 +#define DDRMC_R034 DENALI_CTL_407 +#define DDRMC_R035 DENALI_CTL_408 +#define DDRMC_R036 DENALI_CTL_409 +#define DDRMC_R037 DENALI_CTL_410 +#define DDRMC_R038 DENALI_CTL_411 +#define DDRMC_R039 DENALI_CTL_413 +#define DDRMC_R040 DENALI_CTL_414 +#define DDRMC_R041 DENALI_CTL_415 +#define DDRMC_R042 DENALI_CTL_416 +#define DDRMC_R043 DENALI_CTL_417 +#define DDRMC_R044 DENALI_CTL_418 + +#endif // __DDR_MC_IF_H__ diff --git a/plat/renesas/rza/soc/a3m/include/ddr_mc_regs.h b/plat/renesas/rza/soc/a3m/include/ddr_mc_regs.h new file mode 100644 index 0000000000..0295207b69 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/ddr_mc_regs.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_MC_REGS_H__ +#define __DDR_MC_REGS_H__ + +#include + +#define DDR_MC_BASE PLAT_DDR_MEMC_BASE +#define MC_INIT_NUM (436) + +#define BASE_MC DDR_MC_BASE +#define USER_DEF_REG_0_ADDR (BASE_MC + 0x064C) +#define USER_DEF_REG_1_ADDR (BASE_MC + 0x0650) +#define USER_DEF_REG_2_ADDR (BASE_MC + 0x0654) +#define USER_DEF_REG_3_ADDR (BASE_MC + 0x0658) +#define USER_DEF_REG_4_ADDR (BASE_MC + 0x065C) +#define USER_DEF_REG_5_ADDR (BASE_MC + 0x0660) +#define USER_DEF_REG_6_ADDR (BASE_MC + 0x0664) +#define USER_DEF_REG_7_ADDR (BASE_MC + 0x0668) +#define USER_DEF_REG_8_ADDR (BASE_MC + 0x066C) +#define USER_DEF_REG_9_ADDR (BASE_MC + 0x0670) +#define USER_DEF_REG_10_ADDR (BASE_MC + 0x0674) +#define USER_DEF_REG_11_ADDR (BASE_MC + 0x0678) +#define USER_DEF_REG_12_ADDR (BASE_MC + 0x067C) +#define USER_DEF_REG_13_ADDR (BASE_MC + 0x0680) +#define USER_DEF_REG_14_ADDR (BASE_MC + 0x0684) +#define USER_DEF_REG_15_ADDR (BASE_MC + 0x0688) + +#define DENALI_CTL_00 (0x0000) +#define DENALI_CTL_01 (0x0004) +#define DENALI_CTL_02 (0x0008) +#define DENALI_CTL_03 (0x000C) +#define DENALI_CTL_04 (0x0010) +#define DENALI_CTL_05 (0x0014) +#define DENALI_CTL_06 (0x0018) +#define DENALI_CTL_07 (0x001C) +#define DENALI_CTL_08 (0x0020) +#define DENALI_CTL_09 (0x0024) +#define DENALI_CTL_10 (0x0028) +#define DENALI_CTL_11 (0x002C) +#define DENALI_CTL_12 (0x0030) +#define DENALI_CTL_13 (0x0034) +#define DENALI_CTL_14 (0x0038) +#define DENALI_CTL_15 (0x003C) +#define DENALI_CTL_16 (0x0040) +#define DENALI_CTL_17 (0x0044) +#define DENALI_CTL_18 (0x0048) +#define DENALI_CTL_19 (0x004C) +#define DENALI_CTL_20 (0x0050) +#define DENALI_CTL_21 (0x0054) +#define DENALI_CTL_22 (0x0058) +#define DENALI_CTL_23 (0x005C) +#define DENALI_CTL_24 (0x0060) +#define DENALI_CTL_25 (0x0064) +#define DENALI_CTL_26 (0x0068) +#define DENALI_CTL_27 (0x006C) +#define DENALI_CTL_28 (0x0070) +#define DENALI_CTL_29 (0x0074) +#define DENALI_CTL_30 (0x0078) +#define DENALI_CTL_31 (0x007C) +#define DENALI_CTL_32 (0x0080) +#define DENALI_CTL_33 (0x0084) +#define DENALI_CTL_34 (0x0088) +#define DENALI_CTL_35 (0x008C) +#define DENALI_CTL_36 (0x0090) +#define DENALI_CTL_37 (0x0094) +#define DENALI_CTL_38 (0x0098) +#define DENALI_CTL_39 (0x009C) +#define DENALI_CTL_40 (0x00A0) +#define DENALI_CTL_41 (0x00A4) +#define DENALI_CTL_42 (0x00A8) +#define DENALI_CTL_43 (0x00AC) +#define DENALI_CTL_44 (0x00B0) +#define DENALI_CTL_45 (0x00B4) +#define DENALI_CTL_46 (0x00B8) +#define DENALI_CTL_47 (0x00BC) +#define DENALI_CTL_48 (0x00C0) +#define DENALI_CTL_49 (0x00C4) +#define DENALI_CTL_50 (0x00C8) +#define DENALI_CTL_51 (0x00CC) +#define DENALI_CTL_52 (0x00D0) +#define DENALI_CTL_53 (0x00D4) +#define DENALI_CTL_54 (0x00D8) +#define DENALI_CTL_55 (0x00DC) +#define DENALI_CTL_56 (0x00E0) +#define DENALI_CTL_57 (0x00E4) +#define DENALI_CTL_58 (0x00E8) +#define DENALI_CTL_59 (0x00EC) +#define DENALI_CTL_60 (0x00F0) +#define DENALI_CTL_61 (0x00F4) +#define DENALI_CTL_62 (0x00F8) +#define DENALI_CTL_63 (0x00FC) +#define DENALI_CTL_64 (0x0100) +#define DENALI_CTL_65 (0x0104) +#define DENALI_CTL_66 (0x0108) +#define DENALI_CTL_67 (0x010C) +#define DENALI_CTL_68 (0x0110) +#define DENALI_CTL_69 (0x0114) +#define DENALI_CTL_70 (0x0118) +#define DENALI_CTL_71 (0x011C) +#define DENALI_CTL_72 (0x0120) +#define DENALI_CTL_73 (0x0124) +#define DENALI_CTL_74 (0x0128) +#define DENALI_CTL_75 (0x012C) +#define DENALI_CTL_76 (0x0130) +#define DENALI_CTL_77 (0x0134) +#define DENALI_CTL_78 (0x0138) +#define DENALI_CTL_79 (0x013C) +#define DENALI_CTL_80 (0x0140) +#define DENALI_CTL_81 (0x0144) +#define DENALI_CTL_82 (0x0148) +#define DENALI_CTL_83 (0x014C) +#define DENALI_CTL_84 (0x0150) +#define DENALI_CTL_85 (0x0154) +#define DENALI_CTL_86 (0x0158) +#define DENALI_CTL_87 (0x015C) +#define DENALI_CTL_88 (0x0160) +#define DENALI_CTL_89 (0x0164) +#define DENALI_CTL_90 (0x0168) +#define DENALI_CTL_91 (0x016C) +#define DENALI_CTL_92 (0x0170) +#define DENALI_CTL_93 (0x0174) +#define DENALI_CTL_94 (0x0178) +#define DENALI_CTL_95 (0x017C) +#define DENALI_CTL_96 (0x0180) +#define DENALI_CTL_97 (0x0184) +#define DENALI_CTL_98 (0x0188) +#define DENALI_CTL_99 (0x018C) +#define DENALI_CTL_100 (0x0190) +#define DENALI_CTL_101 (0x0194) +#define DENALI_CTL_102 (0x0198) +#define DENALI_CTL_103 (0x019C) +#define DENALI_CTL_104 (0x01A0) +#define DENALI_CTL_105 (0x01A4) +#define DENALI_CTL_106 (0x01A8) +#define DENALI_CTL_107 (0x01AC) +#define DENALI_CTL_108 (0x01B0) +#define DENALI_CTL_109 (0x01B4) +#define DENALI_CTL_110 (0x01B8) +#define DENALI_CTL_111 (0x01BC) +#define DENALI_CTL_112 (0x01C0) +#define DENALI_CTL_113 (0x01C4) +#define DENALI_CTL_114 (0x01C8) +#define DENALI_CTL_115 (0x01CC) +#define DENALI_CTL_116 (0x01D0) +#define DENALI_CTL_117 (0x01D4) +#define DENALI_CTL_118 (0x01D8) +#define DENALI_CTL_119 (0x01DC) +#define DENALI_CTL_120 (0x01E0) +#define DENALI_CTL_121 (0x01E4) +#define DENALI_CTL_122 (0x01E8) +#define DENALI_CTL_123 (0x01EC) +#define DENALI_CTL_124 (0x01F0) +#define DENALI_CTL_125 (0x01F4) +#define DENALI_CTL_126 (0x01F8) +#define DENALI_CTL_127 (0x01FC) +#define DENALI_CTL_128 (0x0200) +#define DENALI_CTL_129 (0x0204) +#define DENALI_CTL_130 (0x0208) +#define DENALI_CTL_131 (0x020C) +#define DENALI_CTL_132 (0x0210) +#define DENALI_CTL_133 (0x0214) +#define DENALI_CTL_134 (0x0218) +#define DENALI_CTL_135 (0x021C) +#define DENALI_CTL_136 (0x0220) +#define DENALI_CTL_137 (0x0224) +#define DENALI_CTL_138 (0x0228) +#define DENALI_CTL_139 (0x022C) +#define DENALI_CTL_140 (0x0230) +#define DENALI_CTL_141 (0x0234) +#define DENALI_CTL_142 (0x0238) +#define DENALI_CTL_143 (0x023C) +#define DENALI_CTL_144 (0x0240) +#define DENALI_CTL_145 (0x0244) +#define DENALI_CTL_146 (0x0248) +#define DENALI_CTL_147 (0x024C) +#define DENALI_CTL_148 (0x0250) +#define DENALI_CTL_149 (0x0254) +#define DENALI_CTL_150 (0x0258) +#define DENALI_CTL_151 (0x025C) +#define DENALI_CTL_152 (0x0260) +#define DENALI_CTL_153 (0x0264) +#define DENALI_CTL_154 (0x0268) +#define DENALI_CTL_155 (0x026C) +#define DENALI_CTL_156 (0x0270) +#define DENALI_CTL_157 (0x0274) +#define DENALI_CTL_158 (0x0278) +#define DENALI_CTL_159 (0x027C) +#define DENALI_CTL_160 (0x0280) +#define DENALI_CTL_161 (0x0284) +#define DENALI_CTL_162 (0x0288) +#define DENALI_CTL_163 (0x028C) +#define DENALI_CTL_164 (0x0290) +#define DENALI_CTL_165 (0x0294) +#define DENALI_CTL_166 (0x0298) +#define DENALI_CTL_167 (0x029C) +#define DENALI_CTL_168 (0x02A0) +#define DENALI_CTL_169 (0x02A4) +#define DENALI_CTL_170 (0x02A8) +#define DENALI_CTL_171 (0x02AC) +#define DENALI_CTL_172 (0x02B0) +#define DENALI_CTL_173 (0x02B4) +#define DENALI_CTL_174 (0x02B8) +#define DENALI_CTL_175 (0x02BC) +#define DENALI_CTL_176 (0x02C0) +#define DENALI_CTL_177 (0x02C4) +#define DENALI_CTL_178 (0x02C8) +#define DENALI_CTL_179 (0x02CC) +#define DENALI_CTL_180 (0x02D0) +#define DENALI_CTL_181 (0x02D4) +#define DENALI_CTL_182 (0x02D8) +#define DENALI_CTL_183 (0x02DC) +#define DENALI_CTL_184 (0x02E0) +#define DENALI_CTL_185 (0x02E4) +#define DENALI_CTL_186 (0x02E8) +#define DENALI_CTL_187 (0x02EC) +#define DENALI_CTL_188 (0x02F0) +#define DENALI_CTL_189 (0x02F4) +#define DENALI_CTL_190 (0x02F8) +#define DENALI_CTL_191 (0x02FC) +#define DENALI_CTL_192 (0x0300) +#define DENALI_CTL_193 (0x0304) +#define DENALI_CTL_194 (0x0308) +#define DENALI_CTL_195 (0x030C) +#define DENALI_CTL_196 (0x0310) +#define DENALI_CTL_197 (0x0314) +#define DENALI_CTL_198 (0x0318) +#define DENALI_CTL_199 (0x031C) +#define DENALI_CTL_200 (0x0320) +#define DENALI_CTL_201 (0x0324) +#define DENALI_CTL_202 (0x0328) +#define DENALI_CTL_203 (0x032C) +#define DENALI_CTL_204 (0x0330) +#define DENALI_CTL_205 (0x0334) +#define DENALI_CTL_206 (0x0338) +#define DENALI_CTL_207 (0x033C) +#define DENALI_CTL_208 (0x0340) +#define DENALI_CTL_209 (0x0344) +#define DENALI_CTL_210 (0x0348) +#define DENALI_CTL_211 (0x034C) +#define DENALI_CTL_212 (0x0350) +#define DENALI_CTL_213 (0x0354) +#define DENALI_CTL_214 (0x0358) +#define DENALI_CTL_215 (0x035C) +#define DENALI_CTL_216 (0x0360) +#define DENALI_CTL_217 (0x0364) +#define DENALI_CTL_218 (0x0368) +#define DENALI_CTL_219 (0x036C) +#define DENALI_CTL_220 (0x0370) +#define DENALI_CTL_221 (0x0374) +#define DENALI_CTL_222 (0x0378) +#define DENALI_CTL_223 (0x037C) +#define DENALI_CTL_224 (0x0380) +#define DENALI_CTL_225 (0x0384) +#define DENALI_CTL_226 (0x0388) +#define DENALI_CTL_227 (0x038C) +#define DENALI_CTL_228 (0x0390) +#define DENALI_CTL_229 (0x0394) +#define DENALI_CTL_230 (0x0398) +#define DENALI_CTL_231 (0x039C) +#define DENALI_CTL_232 (0x03A0) +#define DENALI_CTL_233 (0x03A4) +#define DENALI_CTL_234 (0x03A8) +#define DENALI_CTL_235 (0x03AC) +#define DENALI_CTL_236 (0x03B0) +#define DENALI_CTL_237 (0x03B4) +#define DENALI_CTL_238 (0x03B8) +#define DENALI_CTL_239 (0x03BC) +#define DENALI_CTL_240 (0x03C0) +#define DENALI_CTL_241 (0x03C4) +#define DENALI_CTL_242 (0x03C8) +#define DENALI_CTL_243 (0x03CC) +#define DENALI_CTL_244 (0x03D0) +#define DENALI_CTL_245 (0x03D4) +#define DENALI_CTL_246 (0x03D8) +#define DENALI_CTL_247 (0x03DC) +#define DENALI_CTL_248 (0x03E0) +#define DENALI_CTL_249 (0x03E4) +#define DENALI_CTL_250 (0x03E8) +#define DENALI_CTL_251 (0x03EC) +#define DENALI_CTL_252 (0x03F0) +#define DENALI_CTL_253 (0x03F4) +#define DENALI_CTL_254 (0x03F8) +#define DENALI_CTL_255 (0x03FC) +#define DENALI_CTL_256 (0x0400) +#define DENALI_CTL_257 (0x0404) +#define DENALI_CTL_258 (0x0408) +#define DENALI_CTL_259 (0x040C) +#define DENALI_CTL_260 (0x0410) +#define DENALI_CTL_261 (0x0414) +#define DENALI_CTL_262 (0x0418) +#define DENALI_CTL_263 (0x041C) +#define DENALI_CTL_264 (0x0420) +#define DENALI_CTL_265 (0x0424) +#define DENALI_CTL_266 (0x0428) +#define DENALI_CTL_267 (0x042C) +#define DENALI_CTL_268 (0x0430) +#define DENALI_CTL_269 (0x0434) +#define DENALI_CTL_270 (0x0438) +#define DENALI_CTL_271 (0x043C) +#define DENALI_CTL_272 (0x0440) +#define DENALI_CTL_273 (0x0444) +#define DENALI_CTL_274 (0x0448) +#define DENALI_CTL_275 (0x044C) +#define DENALI_CTL_276 (0x0450) +#define DENALI_CTL_277 (0x0454) +#define DENALI_CTL_278 (0x0458) +#define DENALI_CTL_279 (0x045C) +#define DENALI_CTL_280 (0x0460) +#define DENALI_CTL_281 (0x0464) +#define DENALI_CTL_282 (0x0468) +#define DENALI_CTL_283 (0x046C) +#define DENALI_CTL_284 (0x0470) +#define DENALI_CTL_285 (0x0474) +#define DENALI_CTL_286 (0x0478) +#define DENALI_CTL_287 (0x047C) +#define DENALI_CTL_288 (0x0480) +#define DENALI_CTL_289 (0x0484) +#define DENALI_CTL_290 (0x0488) +#define DENALI_CTL_291 (0x048C) +#define DENALI_CTL_292 (0x0490) +#define DENALI_CTL_293 (0x0494) +#define DENALI_CTL_294 (0x0498) +#define DENALI_CTL_295 (0x049C) +#define DENALI_CTL_296 (0x04A0) +#define DENALI_CTL_297 (0x04A4) +#define DENALI_CTL_298 (0x04A8) +#define DENALI_CTL_299 (0x04AC) +#define DENALI_CTL_300 (0x04B0) +#define DENALI_CTL_301 (0x04B4) +#define DENALI_CTL_302 (0x04B8) +#define DENALI_CTL_303 (0x04BC) +#define DENALI_CTL_304 (0x04C0) +#define DENALI_CTL_305 (0x04C4) +#define DENALI_CTL_306 (0x04C8) +#define DENALI_CTL_307 (0x04CC) +#define DENALI_CTL_308 (0x04D0) +#define DENALI_CTL_309 (0x04D4) +#define DENALI_CTL_310 (0x04D8) +#define DENALI_CTL_311 (0x04DC) +#define DENALI_CTL_312 (0x04E0) +#define DENALI_CTL_313 (0x04E4) +#define DENALI_CTL_314 (0x04E8) +#define DENALI_CTL_315 (0x04EC) +#define DENALI_CTL_316 (0x04F0) +#define DENALI_CTL_317 (0x04F4) +#define DENALI_CTL_318 (0x04F8) +#define DENALI_CTL_319 (0x04FC) +#define DENALI_CTL_320 (0x0500) +#define DENALI_CTL_321 (0x0504) +#define DENALI_CTL_322 (0x0508) +#define DENALI_CTL_323 (0x050C) +#define DENALI_CTL_324 (0x0510) +#define DENALI_CTL_325 (0x0514) +#define DENALI_CTL_326 (0x0518) +#define DENALI_CTL_327 (0x051C) +#define DENALI_CTL_328 (0x0520) +#define DENALI_CTL_329 (0x0524) +#define DENALI_CTL_330 (0x0528) +#define DENALI_CTL_331 (0x052C) +#define DENALI_CTL_332 (0x0530) +#define DENALI_CTL_333 (0x0534) +#define DENALI_CTL_334 (0x0538) +#define DENALI_CTL_335 (0x053C) +#define DENALI_CTL_336 (0x0540) +#define DENALI_CTL_337 (0x0544) +#define DENALI_CTL_338 (0x0548) +#define DENALI_CTL_339 (0x054C) +#define DENALI_CTL_340 (0x0550) +#define DENALI_CTL_341 (0x0554) +#define DENALI_CTL_342 (0x0558) +#define DENALI_CTL_343 (0x055C) +#define DENALI_CTL_344 (0x0560) +#define DENALI_CTL_345 (0x0564) +#define DENALI_CTL_346 (0x0568) +#define DENALI_CTL_347 (0x056C) +#define DENALI_CTL_348 (0x0570) +#define DENALI_CTL_349 (0x0574) +#define DENALI_CTL_350 (0x0578) +#define DENALI_CTL_351 (0x057C) +#define DENALI_CTL_352 (0x0580) +#define DENALI_CTL_353 (0x0584) +#define DENALI_CTL_354 (0x0588) +#define DENALI_CTL_355 (0x058C) +#define DENALI_CTL_356 (0x0590) +#define DENALI_CTL_357 (0x0594) +#define DENALI_CTL_358 (0x0598) +#define DENALI_CTL_359 (0x059C) +#define DENALI_CTL_360 (0x05A0) +#define DENALI_CTL_361 (0x05A4) +#define DENALI_CTL_362 (0x05A8) +#define DENALI_CTL_363 (0x05AC) +#define DENALI_CTL_364 (0x05B0) +#define DENALI_CTL_365 (0x05B4) +#define DENALI_CTL_366 (0x05B8) +#define DENALI_CTL_367 (0x05BC) +#define DENALI_CTL_368 (0x05C0) +#define DENALI_CTL_369 (0x05C4) +#define DENALI_CTL_370 (0x05C8) +#define DENALI_CTL_371 (0x05CC) +#define DENALI_CTL_372 (0x05D0) +#define DENALI_CTL_373 (0x05D4) +#define DENALI_CTL_374 (0x05D8) +#define DENALI_CTL_375 (0x05DC) +#define DENALI_CTL_376 (0x05E0) +#define DENALI_CTL_377 (0x05E4) +#define DENALI_CTL_378 (0x05E8) +#define DENALI_CTL_379 (0x05EC) +#define DENALI_CTL_380 (0x05F0) +#define DENALI_CTL_381 (0x05F4) +#define DENALI_CTL_382 (0x05F8) +#define DENALI_CTL_383 (0x05FC) +#define DENALI_CTL_384 (0x0600) +#define DENALI_CTL_385 (0x0604) +#define DENALI_CTL_386 (0x0608) +#define DENALI_CTL_387 (0x060C) +#define DENALI_CTL_388 (0x0610) +#define DENALI_CTL_389 (0x0614) +#define DENALI_CTL_390 (0x0618) +#define DENALI_CTL_391 (0x061C) +#define DENALI_CTL_392 (0x0620) +#define DENALI_CTL_393 (0x0624) +#define DENALI_CTL_394 (0x0628) +#define DENALI_CTL_395 (0x062C) +#define DENALI_CTL_396 (0x0630) +#define DENALI_CTL_397 (0x0634) +#define DENALI_CTL_398 (0x0638) +#define DENALI_CTL_399 (0x063C) +#define DENALI_CTL_400 (0x0640) +#define DENALI_CTL_401 (0x0644) +#define DENALI_CTL_402 (0x0648) +#define DENALI_CTL_403 (0x064C) +#define DENALI_CTL_404 (0x0650) +#define DENALI_CTL_405 (0x0654) +#define DENALI_CTL_406 (0x0658) +#define DENALI_CTL_407 (0x065C) +#define DENALI_CTL_408 (0x0660) +#define DENALI_CTL_409 (0x0664) +#define DENALI_CTL_410 (0x0668) +#define DENALI_CTL_411 (0x066C) +#define DENALI_CTL_412 (0x0670) +#define DENALI_CTL_413 (0x0674) +#define DENALI_CTL_414 (0x0678) +#define DENALI_CTL_415 (0x067C) +#define DENALI_CTL_416 (0x0680) +#define DENALI_CTL_417 (0x0684) +#define DENALI_CTL_418 (0x0688) +#define DENALI_CTL_419 (0x068C) +#define DENALI_CTL_420 (0x0690) +#define DENALI_CTL_421 (0x0694) +#define DENALI_CTL_422 (0x0698) +#define DENALI_CTL_423 (0x069C) +#define DENALI_CTL_424 (0x06A0) +#define DENALI_CTL_425 (0x06A4) +#define DENALI_CTL_426 (0x06A8) +#define DENALI_CTL_427 (0x06AC) +#define DENALI_CTL_428 (0x06B0) +#define DENALI_CTL_429 (0x06B4) +#define DENALI_CTL_430 (0x06B8) +#define DENALI_CTL_431 (0x06BC) +#define DENALI_CTL_432 (0x06C0) +#define DENALI_CTL_433 (0x06C4) +#define DENALI_CTL_434 (0x06C8) +#define DENALI_CTL_435 (0x06CC) + +#endif // __DDR_MC_REGS_H__ diff --git a/plat/renesas/rza/soc/a3m/include/ddr_phy_regs.h b/plat/renesas/rza/soc/a3m/include/ddr_phy_regs.h new file mode 100644 index 0000000000..2389179ed5 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/ddr_phy_regs.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_PHY_REGS_H__ +#define __DDR_PHY_REGS_H__ + +#include + +#define DDR_PHY_BASE PLAT_DDR_PHY_BASE + +#define DDRPHY_R00 (0x040) +#define DDRPHY_R01 (0x044) +#define DDRPHY_R02 (0x048) +#define DDRPHY_R03 (0x04C) +#define DDRPHY_R04 (0x050) +#define DDRPHY_R05 (0x058) +#define DDRPHY_R06 (0x05C) +#define DDRPHY_R07 (0x060) +#define DDRPHY_R08 (0x064) +#define DDRPHY_R09 (0x068) +#define DDRPHY_R10 (0x09C) +#define DDRPHY_R11 (0x0A8) +#define DDRPHY_R12 (0x0C0) +#define DDRPHY_R13 (0x0C4) +#define DDRPHY_R14 (0x0C8) +#define DDRPHY_R15 (0x0CC) +#define DDRPHY_R16 (0x0D0) +#define DDRPHY_R17 (0x0E8) +#define DDRPHY_R18 (0x100) +#define DDRPHY_R19 (0x104) +#define DDRPHY_R20 (0x108) +#define DDRPHY_R21 (0x10C) +#define DDRPHY_R22 (0x110) +#define DDRPHY_R23 (0x114) +#define DDRPHY_R24 (0x118) +#define DDRPHY_R25 (0x11C) +#define DDRPHY_R26 (0x120) +#define DDRPHY_R27 (0x124) +#define DDRPHY_R28 (0x128) +#define DDRPHY_R29 (0x12C) +#define DDRPHY_R30 (0x130) +#define DDRPHY_R31 (0x134) +#define DDRPHY_R32 (0x138) +#define DDRPHY_R33 (0x13C) +#define DDRPHY_R34 (0x140) +#define DDRPHY_R35 (0x144) +#define DDRPHY_R36 (0x148) +#define DDRPHY_R37 (0x14C) +#define DDRPHY_R38 (0x150) +#define DDRPHY_R39 (0x154) +#define DDRPHY_R40 (0x158) +#define DDRPHY_R41 (0x15C) +#define DDRPHY_R42 (0x160) +#define DDRPHY_R43 (0x164) +#define DDRPHY_R44 (0x168) +#define DDRPHY_R45 (0x16C) +#define DDRPHY_R46 (0x170) +#define DDRPHY_R47 (0x174) +#define DDRPHY_R48 (0x178) +#define DDRPHY_R49 (0x17C) +#define DDRPHY_R50 (0x180) +#define DDRPHY_R51 (0x188) +#define DDRPHY_R52 (0x18C) +#define DDRPHY_R53 (0x190) +#define DDRPHY_R54 (0x194) +#define DDRPHY_R55 (0x19C) +#define DDRPHY_R56 (0x1A0) +#define DDRPHY_R57 (0x1A4) +#define DDRPHY_R58 (0x1A8) +#define DDRPHY_R59 (0x1AC) +#define DDRPHY_R60 (0x1B0) +#define DDRPHY_R61 (0x1B4) +#define DDRPHY_R62 (0x1B8) +#define DDRPHY_R63 (0x1BC) +#define DDRPHY_R64 (0x1C0) +#define DDRPHY_R65 (0x1C4) +#define DDRPHY_R66 (0x1C8) +#define DDRPHY_R67 (0x1CC) +#define DDRPHY_R68 (0x1D0) +#define DDRPHY_R69 (0x1D4) +#define DDRPHY_R70 (0x1D8) +#define DDRPHY_R71 (0x1DC) +#define DDRPHY_R72 (0x1E0) +#define DDRPHY_R73 (0x1E4) +#define DDRPHY_R74 (0x1E8) +#define DDRPHY_R75 (0x1EC) +#define DDRPHY_R76 (0x1F0) +#define DDRPHY_R77 (0x200) +#define DDRPHY_R78 (0x204) +#define DDRPHY_R79 (0x240) + +#endif // __DDR_PHY_REGS_H__ diff --git a/plat/renesas/rza/soc/a3m/include/platform_def.h b/plat/renesas/rza/soc/a3m/include/platform_def.h new file mode 100644 index 0000000000..9918dbe90e --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/platform_def.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#ifndef __ASSEMBLER__ +#include +#endif + +#include +#include + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE U(0x1000) + +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(2) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_SYSTEM_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_PWR_LVL_STATES U(2) + +#define MAX_IO_DEVICES U(2) +#define MAX_IO_HANDLES U(2) +#define MAX_IO_BLOCK_DEVICES U(1) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#if !TRUSTED_BOARD_BOOT +#define BL2_BASE (0x00012000) +#define BL2_LIMIT (0x0002F000) +#else +#define BL2_BASE (0x00013000) +#define BL2_LIMIT (0x0002F000) +#endif + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_BASE (0x44000000) +#define BL31_LIMIT (0x44040000) + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef SPD_none +#define BL32_BASE (0x44100000) +#define BL32_LIMIT (BL32_BASE + 0x100000) +#endif + +/******************************************************************************* + * BL33 + ******************************************************************************/ +#define BL33_BASE (0x50000000) +#define BL33_LIMIT (BL33_BASE + 0x08000000) + +/******************************************************************************* + * BSP + ******************************************************************************/ +#define BSP_BASE (0x50000000) +#define BSP_LIMIT (BSP_BASE + 0x08000000) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#if IMAGE_BL2 +#define MAX_XLAT_TABLES U(4) +#define MAX_MMAP_REGIONS U(9) +#elif IMAGE_BL31 +#define MAX_XLAT_TABLES U(6) +#define MAX_MMAP_REGIONS U(9) +#endif + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) + +/******************************************************************************* + * Determining the use of FIP format + ******************************************************************************/ +#define RZ_NOFIP (0) +#define RZ_FIP (1) + +#define ARMv8A (1) + +#define RZ_APP_PAYLOAD_OFFSET (0x200) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/renesas/rza/soc/a3m/include/rza3m_def.h b/plat/renesas/rza/soc/a3m/include/rza3m_def.h new file mode 100644 index 0000000000..1f841a0938 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/include/rza3m_def.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __RZA3M_DEF_H__ +#define __RZA3M_DEF_H__ + +#define PLAT_BOOT_ROM_BASE (0x00000000) +#define PLAT_MSRAM_BASE (0x00010000) +#define PLAT_ASRAM_BASE (0x00020000) +#define PLAT_DEVICE_BASE (0x10000000) +#define PLAT_SCIF0_BASE (0x1004B800) +#define PLAT_SPIMULT_BASE (0x10060000) +#define PLAT_SPIMULT_WBUF_BASE (0x10070000) +#define PLAT_SYC_BASE (0x11000000) +#define PLAT_CPG_BASE (0x11010000) +#define PLAT_SYSC_BASE (0x11020000) +#define PLAT_GPIO_BASE (0x11030000) +#define PLAT_TZC_ASRAM_BASE (0x11040000) +#define PLAT_TZC_MSRAM_BASE (0x11050000) +#define PLAT_TZC_SPI_BASE (0x11060000) +#define PLAT_TZC_DDR_BASE (0x11070000) +#define PLAT_DDR_PHY_BASE (0x11400000) +#define PLAT_DDR_MEMC_BASE (0x11410000) +#define PLAT_OTP_BASE (0x11860000) +#define PLAT_GIC_BASE (0x11900000) +#define PLAT_SD0_BASE (0x11C00000) +#define PLAT_SPIROM_BASE (0x20000000) +#define PLAT_DDR1_BASE (0x40000000) +#define PLAT_DDR2_BASE (0x80000000) +#define PLAT_DDR3_BASE (0x100000000) + +#define PLAT_GICD_BASE (PLAT_GIC_BASE) +#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) + +#define PLAT_SRAM_BASE (PLAT_MSRAM_BASE) + +#define PLAT_BOOT_ROM_SIZE (0x00010000 - PLAT_BOOT_ROM_BASE) +#define PLAT_MSRAM_SIZE (0x00020000 - PLAT_MSRAM_BASE) +#define PLAT_ASRAM_SIZE (0x00030000 - PLAT_ASRAM_BASE) +#define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) +#define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) +#define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) +#define PLAT_DDR1_SIZE (PLAT_DDR2_BASE - PLAT_DDR1_BASE) +#define PLAT_DDR2_SIZE (PLAT_DDR3_BASE - PLAT_DDR2_BASE) + +#define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) +#define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) + +#define PLAT_OTP_DEVICE_INFO (PLAT_OTP_BASE + 0x1178) + +#define PLAT_EMMC_FIP_BASE (0x00020000) +#define PLAT_EMMC_FIP_SIZE (0x001DFFFF) + +#define PLAT_SYC_INCK_HZ (24000000) +#define PLAT_UART_INCK_HZ (100000000) +#define PLAT_UART_BARDRATE (115200) + +/* Boot Info base address */ +#define PLAT_BOOTINFO_BASE (PLAT_SRAM_BASE) + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE (PLAT_SRAM_BASE + 0x0001F000) +#define PARAMS_SIZE (0x1000) + +#endif /* __RZA3M_DEF_H__ */ diff --git a/plat/renesas/rza/soc/a3m/rz_image.pl b/plat/renesas/rza/soc/a3m/rz_image.pl new file mode 100644 index 0000000000..9019b865a3 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/rz_image.pl @@ -0,0 +1,124 @@ +#!/usr/bin/perl -w +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +use strict; +use bigint; +use Digest::SHA; + +sub padding256 { + my ($f, $size, $fourth) = @_; + + for(my $i=1;$i<4;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C', $fourth)); + for(my $i=5;$i<57;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0b111 << 29)) >> 29)); + for(my $i=58;$i<61;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0x1F << 0)) << 3)); + $f->print(pack('C',($size & (0xFF << 5)) >> 5)); + $f->print(pack('C',($size & (0xFF << 13)) >> 13)); + $f->print(pack('C',($size & (0xFF << 21)) >> 21)); + for(my $i=65;$i<257;$i++) { + $f->print(pack('C', 0)); + } +} + +my $size_limit = 0x1D000; + +die("Not enough parameter\n") if ($#ARGV < 0); + +# Open input file +my $name = shift(@ARGV); +my $outname; +if ($#ARGV < 0) { + $outname = "rz_" . $name; +} +else { + $outname = shift(@ARGV); +} +my $tmpname = $outname.".tmp"; +open(my $origin, '<', $name) or die("Can not open input file"); +binmode $origin; + +# Obtaining size ($st[7]) +my @st = stat($origin); + +# Check appended size +my $size = ($st[7] + 255) & "0xffffffffffffff00"; +my $msg; +if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";} +die("$msg too big ($size > $size_limit)") if ($size > $size_limit); + +open(my $tmp, '>', $tmpname) or die("Can not open temporary file"); +binmode $tmp; + +# WritePadding +my $buf; +read($origin, $buf, $st[7]); +$tmp->print($buf); +#print "size:$size st:$st[7]\n"; +if ($size != $st[7]) { + $tmp->print(pack('C', 0x80)); + for(my $i=($st[7] + 1);$i<$size;$i++) { + $tmp->print(pack('C', 0)); + } + padding256($tmp, $st[7], 0); +} else { + padding256($tmp, $st[7], 0x80); +} +close($tmp); +open($tmp, '<', $tmpname) or die("Can not open temporary file"); +# Sha256 +my $sha = Digest::SHA->new(256); +$sha->addfile($tmpname); +my $digest = $sha->digest(); + +seek($origin, 0,0); +$size += 256; + +# Create bin file +open(my $out, '>', $outname) or die("Can not open output file"); +binmode $out; +# Write header +$out->print(pack('L', $size)); +for(my $i = 1; $i < 4; $i++) { + $out->print(pack('L', 0xffffffff)); +} +$out->print($digest); +for(my $i = 12; $i < 112; $i++) { + $out->print(pack('L', 0xffffffff)); +} +$out->print(pack('L', 0xffff0000)); +$out->print(pack('L', 0x000800ff)); +$out->print(pack('L', 0x00fff700)); +$out->print(pack('L', 0xf700f708)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xaa55ffff)); + +# Append original data to temporary file +read($tmp, $buf, $size); +$out->print($buf); +$out->flush; + +close($tmp); +#unlink($tmpname); +# close +close $out; +close $origin; diff --git a/plat/renesas/rza/soc/a3m/rz_image_nand.pl b/plat/renesas/rza/soc/a3m/rz_image_nand.pl new file mode 100644 index 0000000000..deb4262566 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/rz_image_nand.pl @@ -0,0 +1,143 @@ +#!/usr/bin/perl -w +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +use strict; +use bigint; +use Digest::SHA; + +sub padding256 { + my ($f, $size, $fourth) = @_; + + for(my $i=1;$i<4;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C', $fourth)); + for(my $i=5;$i<57;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0b111 << 29)) >> 29)); + for(my $i=58;$i<61;$i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0x1F << 0)) << 3)); + $f->print(pack('C',($size & (0xFF << 5)) >> 5)); + $f->print(pack('C',($size & (0xFF << 13)) >> 13)); + $f->print(pack('C',($size & (0xFF << 21)) >> 21)); + for(my $i=65;$i<257;$i++) { + $f->print(pack('C', 0)); + } +} + +my $size_limit = 0x1D000; + +die("Not enough parameter\n") if ($#ARGV < 0); + +# Open input file +my $name = shift(@ARGV); +my $outname; +if ($#ARGV < 0) { + $outname = "rz_" . $name; +} +else { + $outname = shift(@ARGV); +} +my $tmpname = $outname.".tmp"; +my $headername = $outname.".header"; +open(my $origin, '<', $name) or die("Can not open input file"); +binmode $origin; + +# Obtaining size ($st[7]) +my @st = stat($origin); + +# Check appended size +my $size = ($st[7] + 255) & "0xffffffffffffff00"; +my $msg; +if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";} +die("$msg too big ($size > $size_limit)") if ($size > $size_limit); + +open(my $tmp, '>', $tmpname) or die("Can not open temporary file"); +binmode $tmp; + +# WritePadding +my $buf; +read($origin, $buf, $st[7]); +$tmp->print($buf); +#print "size:$size st:$st[7]\n"; +if ($size != $st[7]) { + $tmp->print(pack('C', 0x80)); + for(my $i=($st[7] + 1);$i<$size;$i++) { + $tmp->print(pack('C', 0)); + } + padding256($tmp, $st[7], 0); +} else { + padding256($tmp, $st[7], 0x80); +} +close($tmp); +open($tmp, '<', $tmpname) or die("Can not open temporary file"); +# Sha256 +my $sha = Digest::SHA->new(256); +$sha->addfile($tmpname); +my $digest = $sha->digest(); + +seek($origin, 0,0); +$size += 256; + +# Create bin file +open(my $out, '>', $outname) or die("Can not open output file"); +open(my $header, '>', $headername) or die("Can not open output file"); + +binmode $out; +binmode $header; +# Write header +$header->print(pack('L', $size)); +for(my $i = 1; $i < 4; $i++) { + $header->print(pack('L', 0xffffffff)); +} +$header->print($digest); +for(my $i = 12; $i < 112; $i++) { + $header->print(pack('L', 0xffffffff)); +} +$header->print(pack('L', 0xffff0000)); +$header->print(pack('L', 0x000800ff)); +$header->print(pack('L', 0x00fff700)); +$header->print(pack('L', 0xf700f708)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xffffffff)); +$header->print(pack('L', 0xaa55ffff)); +close($header); +open($header, '<', $headername) or die("Can not open output file"); +binmode $header; + +read($header, my $hbuf, 0x200); +my @head = unpack('C512', $hbuf); + +for(my $h = 0;$h<2;$h++) { + for my $i (0..$#head){ + $out->print(pack('C', $head[$i])); + } + for my $i (0..$#head){ + $out->print(pack('C', 255 - $head[$i])); + } +} + +# Append original data to temporary file +read($tmp, $buf, $size); +$out->print($buf); +$out->flush; + +close($tmp); +#unlink($tmpname); +# close +close $out; +close $origin; diff --git a/plat/renesas/rza/soc/a3m/rz_xspi.mk b/plat/renesas/rza/soc/a3m/rz_xspi.mk new file mode 100644 index 0000000000..3b508d6dd7 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/rz_xspi.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +RZ_XSPI_DRIVER_PATH := plat/renesas/rza/common/drivers/xspi + +RZ_XSPI_CONFIGS := XSPI0 XSPI1 XSPI2 +RZ_XSPI_SOURCES := plat/renesas/rza/soc/a3m/drivers/xspi.c +RZ_XSPI_HEADERS := +RZ_XSPI0_IF := spim +RZ_XSPI0_IF_CONFIG := .channel=0, .base=0x10060000 +RZ_XSPI1_IF := octa +RZ_XSPI1_IF_CONFIG := .channel=0, .base=0x10080000 +RZ_XSPI2_IF := octa +RZ_XSPI2_IF_CONFIG := .channel=1, .base=0x10080000 +RZ_XSPI_EXCLUSIVE_SELECTOR := 1 +RZ_SPIM_SDR_FREQ_LIMIT := 66625000 +RZ_OCTA_FREQ_LIMIT := 100000000 + +ifneq ($(strip $(XSPI0_DEVICE)),) + ifneq ($(strip $(XSPI1_DEVICE)),) + $(error XSPI0_DEVICE and XSPI1_DEVICE can not be specified at the same time.) + endif + ifneq ($(strip $(XSPI2_DEVICE)),) + $(error XSPI0_DEVICE and XSPI2_DEVICE can not be specified at the same time.) + endif +endif + +include plat/renesas/rza/common/rz_xspi_common.mk + +$(eval $(call add_define,RZ_XSPI_EXCLUSIVE_SELECTOR)) +$(eval $(call add_define,RZ_SPIM_SDR_FREQ_LIMIT)) +$(eval $(call add_define,RZ_OCTA_FREQ_LIMIT)) diff --git a/plat/renesas/rza/soc/a3m/soc.mk b/plat/renesas/rza/soc/a3m/soc.mk new file mode 100644 index 0000000000..b05effe092 --- /dev/null +++ b/plat/renesas/rza/soc/a3m/soc.mk @@ -0,0 +1,64 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_INCLUDES += -Iplat/renesas/rza/soc/a3m/include + +DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c + +RZA3 := 1 +RZA3M := 1 +DEVICE_TYPE := 1 +ARCH_TYPE := ARMv8A +LOG_LEVEL := 10 +ifeq (${SOC_TYPE},2) +DEVICE_TYPE := 2 +endif +RZA3_XSPI_MEMORY_BASE := 0x20000000 + +$(eval $(call add_define,RZA3)) +$(eval $(call add_define,RZA3M)) +$(eval $(call add_define,DEVICE_TYPE)) +$(eval $(call add_define,ARCH_TYPE)) +$(eval $(call add_define,RZA3_XSPI_MEMORY_BASE)) + +# set file name +RZ_ELF := $(BUILD_PLAT)/rz$(BOARD)_ipl.elf +BL2_ELF := $(BUILD_PLAT)/bl2/bl2.elf +RZ_BIN := $(BUILD_PLAT)/rz$(BOARD)_ipl.bin +BL2_BIN := $(BUILD_PLAT)/bl2.bin +RZ_MAP := $(BUILD_PLAT)/rz$(BOARD)_ipl.map +BL2_MAP := $(BUILD_PLAT)/bl2/bl2.map +RZ_DUMP := $(BUILD_PLAT)/rz$(BOARD)_ipl.dump +BL2_DUMP := $(BUILD_PLAT)/bl2/bl2.dump +RZ_SREC := $(BUILD_PLAT)/rz$(BOARD)_ipl.srec + +bl2: $(RZ_ELF) $(RZ_BIN) $(RZ_LINKER) $(RZ_MAP) $(RZ_DUMP) $(RZ_SREC) + +$(RZ_ELF): $(BL2_ELF) + $(call SHELL_COPY,$<,$@) + +$(RZ_BIN): $(BL2_BIN) + @echo " IMG $@" +ifeq ($(NAND),1) + $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3m/rz_image_nand.pl "$<" "$@" +else + $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3m/rz_image.pl "$<" "$@" +endif + +$(BL2_MAP): $(BL2_ELF) +$(RZ_MAP): $(BL2_MAP) + $(call SHELL_COPY,$<,$@) + +$(RZ_DUMP): $(BL2_DUMP) + $(call SHELL_COPY,$<,$@) + +$(RZ_SREC): $(RZ_BIN) + @echo " SREC $@" + $(q)$($(ARCH)-oc) -I binary -O srec --adjust-vma=0x20000000 --srec-forceS3 "$<" "$@" + +ifeq (${RZ_TEST},1) +-include plat/renesas/rza/common/drivers/tests/rz_test.mk +endif diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c new file mode 100644 index 0000000000..1489876d24 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +void ddr_ctrl_reten_en_n(uint8_t val) +{ + val &= 1; + write_phy_reg(DDRPHY_R79, (val << 1)); +} diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c new file mode 100644 index 0000000000..86cb986f83 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +const char ddr_an_version[] = "v0.0.0"; + +const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { + { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, + { DENALI_CTL_14, 0x07120200 }, { DENALI_CTL_15, 0x00000000 }, + { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002100 }, + { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E09 }, + { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A09 }, + { DENALI_CTL_24, 0x09031301 }, { DENALI_CTL_25, 0x01000009 }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x000000AE }, { DENALI_CTL_31, 0x00001448 }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, + { DENALI_CTL_34, 0x00B40200 }, { DENALI_CTL_35, 0x000000B4 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, + { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A50 }, + { DENALI_CTL_70, 0x00000206 }, { DENALI_CTL_71, 0x00000210 }, + { DENALI_CTL_72, 0x00000A50 }, { DENALI_CTL_73, 0x00000206 }, + { DENALI_CTL_74, 0x00000210 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, + { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, + { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, + { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, + { DENALI_CTL_122, 0x02010100 }, { DENALI_CTL_123, 0x00010102 }, + { DENALI_CTL_124, 0x07FF0000 }, { DENALI_CTL_125, 0x0000FF00 }, + { DENALI_CTL_126, 0x0FFF0800 }, { DENALI_CTL_127, 0x0100FF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C030000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, + { DENALI_CTL_176, 0x02020001 }, { DENALI_CTL_177, 0x01020101 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x01080205 }, { DENALI_CTL_399, 0x00200106 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000200 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, + { DENALI_CTL_414, 0x4F6C01E8 }, { DENALI_CTL_415, 0x00007822 }, + { DENALI_CTL_416, 0x1E1E3C22 }, { DENALI_CTL_417, 0x00000000 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c new file mode 100644 index 0000000000..43dac1ea19 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const char ddr_an_version[] = "v3.0.0"; + +const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { + { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, + { DENALI_CTL_14, 0x07140200 }, { DENALI_CTL_15, 0x00000000 }, + { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002200 }, + { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E0A }, + { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A0A }, + { DENALI_CTL_24, 0x0A031401 }, { DENALI_CTL_25, 0x0100000A }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x000000EA }, { DENALI_CTL_31, 0x00001448 }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, + { DENALI_CTL_34, 0x00F00200 }, { DENALI_CTL_35, 0x000000F0 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, + { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A60 }, + { DENALI_CTL_70, 0x00000006 }, { DENALI_CTL_71, 0x00000010 }, + { DENALI_CTL_72, 0x00000A60 }, { DENALI_CTL_73, 0x00000006 }, + { DENALI_CTL_74, 0x00000010 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, + { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, + { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, + { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, + { DENALI_CTL_122, 0x01010100 }, { DENALI_CTL_123, 0x00010101 }, + { DENALI_CTL_124, 0x0FFF0000 }, { DENALI_CTL_125, 0x0001FF00 }, + { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, + { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01030101 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x01090205 }, { DENALI_CTL_399, 0x00200106 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, + { DENALI_CTL_414, 0x4F6306E8 }, { DENALI_CTL_415, 0x00002822 }, + { DENALI_CTL_416, 0x00003C22 }, { DENALI_CTL_417, 0x00000000 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c new file mode 100644 index 0000000000..5f6ea0f612 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const char ddr_an_version[] = "v3.0.0"; + +const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { + { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, + { DENALI_CTL_14, 0x07120200 }, { DENALI_CTL_15, 0x00000000 }, + { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002100 }, + { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E09 }, + { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A09 }, + { DENALI_CTL_24, 0x09031301 }, { DENALI_CTL_25, 0x01000009 }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x000000AE }, { DENALI_CTL_31, 0x00001448 }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, + { DENALI_CTL_34, 0x00B40200 }, { DENALI_CTL_35, 0x000000B4 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, + { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A50 }, + { DENALI_CTL_70, 0x00000006 }, { DENALI_CTL_71, 0x00000010 }, + { DENALI_CTL_72, 0x00000A50 }, { DENALI_CTL_73, 0x00000006 }, + { DENALI_CTL_74, 0x00000010 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, + { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, + { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, + { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, + { DENALI_CTL_122, 0x02010100 }, { DENALI_CTL_123, 0x00010102 }, + { DENALI_CTL_124, 0x07FF0000 }, { DENALI_CTL_125, 0x0000FF00 }, + { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, + { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01020101 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x01080205 }, { DENALI_CTL_399, 0x00200106 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, + { DENALI_CTL_414, 0x4F6306E8 }, { DENALI_CTL_415, 0x00002822 }, + { DENALI_CTL_416, 0x00003C22 }, { DENALI_CTL_417, 0x00000000 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c new file mode 100644 index 0000000000..0f40dd90a6 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 + */ + +#include + +#include + +const char ddr_an_version[] = "v3.0.0"; + +const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { + { DENALI_CTL_00, 0x00000A00 }, { DENALI_CTL_01, 0x00000000 }, + { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, + { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, + { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, + { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, + { DENALI_CTL_10, 0x01000008 }, { DENALI_CTL_11, 0x00100100 }, + { DENALI_CTL_12, 0x00027100 }, { DENALI_CTL_13, 0x00061A80 }, + { DENALI_CTL_14, 0x09180255 }, { DENALI_CTL_15, 0x18180000 }, + { DENALI_CTL_16, 0x05050404 }, { DENALI_CTL_17, 0x00002806 }, + { DENALI_CTL_18, 0x0602001C }, { DENALI_CTL_19, 0x06001C0C }, + { DENALI_CTL_20, 0x00180806 }, { DENALI_CTL_21, 0x0400DB60 }, + { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000C0C }, + { DENALI_CTL_24, 0x0C031801 }, { DENALI_CTL_25, 0x0100000C }, + { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, + { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, + { DENALI_CTL_30, 0x00000118 }, { DENALI_CTL_31, 0x00001860 }, + { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00140005 }, + { DENALI_CTL_34, 0x01200255 }, { DENALI_CTL_35, 0x00000120 }, + { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, + { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, + { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00061800 }, + { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00061800 }, + { DENALI_CTL_44, 0x00061800 }, { DENALI_CTL_45, 0x00061800 }, + { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, + { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, + { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, + { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, + { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00212100 }, + { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, + { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, + { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, + { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, + { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, + { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, + { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000214 }, + { DENALI_CTL_70, 0x00000101 }, { DENALI_CTL_71, 0x00000000 }, + { DENALI_CTL_72, 0x00000214 }, { DENALI_CTL_73, 0x00000101 }, + { DENALI_CTL_74, 0x00000000 }, { DENALI_CTL_75, 0x00000000 }, + { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, + { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, + { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000080 }, + { DENALI_CTL_82, 0x00000080 }, { DENALI_CTL_83, 0x0000040F }, + { DENALI_CTL_84, 0x0000040F }, { DENALI_CTL_85, 0x01010000 }, + { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, + { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, + { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, + { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, + { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, + { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, + { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, + { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, + { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, + { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, + { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, + { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, + { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, + { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, + { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, + { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x00BEBD03 }, + { DENALI_CTL_118, 0x0000C350 }, { DENALI_CTL_119, 0x00000000 }, + { DENALI_CTL_120, 0x02000400 }, { DENALI_CTL_121, 0x00000080 }, + { DENALI_CTL_122, 0x01010100 }, { DENALI_CTL_123, 0x00010101 }, + { DENALI_CTL_124, 0x0FFF0000 }, { DENALI_CTL_125, 0x0001FF00 }, + { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, + { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, + { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, + { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, + { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, + { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000001 }, + { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, + { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, + { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, + { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, + { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, + { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, + { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, + { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, + { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, + { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, + { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, + { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, + { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, + { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, + { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, + { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, + { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, + { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, + { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060800 }, + { DENALI_CTL_176, 0x01000001 }, { DENALI_CTL_177, 0x01030000 }, + { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, + { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, + { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, + { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, + { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, + { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, + { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, + { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, + { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, + { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, + { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, + { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, + { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, + { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, + { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, + { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, + { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, + { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, + { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, + { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, + { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, + { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, + { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, + { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, + { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, + { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, + { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, + { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, + { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, + { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, + { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, + { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, + { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, + { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, + { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, + { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, + { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, + { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, + { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, + { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, + { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, + { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, + { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, + { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, + { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, + { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, + { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, + { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, + { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, + { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, + { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, + { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, + { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, + { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, + { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, + { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, + { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, + { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, + { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, + { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, + { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, + { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, + { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, + { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, + { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, + { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, + { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, + { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, + { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, + { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, + { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, + { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, + { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, + { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, + { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, + { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, + { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, + { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, + { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, + { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, + { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, + { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, + { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, + { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, + { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, + { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, + { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, + { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, + { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, + { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, + { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, + { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, + { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, + { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, + { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, + { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, + { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, + { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, + { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, + { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, + { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, + { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, + { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, + { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, + { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, + { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, + { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, + { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, + { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, + { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, + { DENALI_CTL_398, 0x030B0205 }, { DENALI_CTL_399, 0x00200308 }, + { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, + { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, + { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, + { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, + { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, + { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, + { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x037204E2 }, + { DENALI_CTL_414, 0x57630BB8 }, { DENALI_CTL_415, 0x00002828 }, + { DENALI_CTL_416, 0x00003C22 }, { DENALI_CTL_417, 0x00102611 }, + { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, + { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, + { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, + { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, + { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, + { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, + { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, + { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, + { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } +}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/xspi.c b/plat/renesas/rza/soc/a3ul/drivers/xspi.c new file mode 100644 index 0000000000..2ee8da56be --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/drivers/xspi.c @@ -0,0 +1,71 @@ +#include + +#include +#include +#include +#include + +static int sub_init_xip(const xspidevice_instance_t *inst) +{ + int result; + result = inst->api->open(inst->ctrl, inst->cfg); + if (!result) { + result = inst->api->enter_xip(inst->ctrl); + inst->api->close(inst->ctrl); + } + return result; +} + +static int sub_post_init_xip(const xspi_instance_t *xspi) +{ + int result; + result = xspi->api->open(xspi->ctrl, xspi->cfg); + if (!result) { + xspi->api->enable_auto_calibration(xspi->ctrl); + result = xspi->api->post_init(xspi->ctrl); + xspi->api->close(xspi->ctrl); + } + return result; +} + +void xspi_setup(void) +{ + int i; + int result = 0; + +#ifdef XSPI_DEVICE_TYPE + RZA_PRINTF("Configure %s Flash Memory\n", XSPI_DEVICE_TYPE); +#endif + for (i = 0; result >= 0 && i < xspidevices_count; i++) { + result = sub_init_xip(xspidevices[i]); + if (result < 0) { + ERROR("xspi.c: abort on sub_init_xip (#%d)\n", i); + panic(); + } + } + for (i = 0; result >= 0 && i < xspidevices_count; i++) { + result = sub_post_init_xip(xspidevices[i]->cfg->xspi); + if (result < 0) { + ERROR("xspi.c: abort on sub_post_init_xip (#%d)\n", i); + panic(); + } + } +} + +/** + * memcpy for xspi + */ +int rz_xspi_read(void *to, uint64_t offset, size_t length) +{ + int result; + const xspidevice_instance_t *inst = xspidevices[0]; + if (!inst) + return -1; + + result = inst->api->open(inst->ctrl, inst->cfg); + if (!result) { + inst->api->read(inst->ctrl, to, (size_t)offset, length); + inst->api->close(inst->ctrl); + } + return result; +} diff --git a/plat/renesas/rza/soc/a3ul/include/cpg_opt.h b/plat/renesas/rza/soc/a3ul/include/cpg_opt.h new file mode 100644 index 0000000000..4d04dd455f --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/cpg_opt.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CPG_OPT_H__ +#define __CPG_OPT_H__ + +#define CPG_RST_DDR_OPT_VALUE (0x00000000) + +#endif // __CPG_OPT_H__ diff --git a/plat/renesas/rza/soc/a3ul/include/ddr_mc_if.h b/plat/renesas/rza/soc/a3ul/include/ddr_mc_if.h new file mode 100644 index 0000000000..095d78e3c3 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/ddr_mc_if.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_MC_IF_H__ +#define __DDR_MC_IF_H__ + +#include + +#define MC_INIT_NUM (436) + +#define LP_CMD_OFFSET (0) + +#define DDRMC_R000 DENALI_CTL_00 +#define DDRMC_R001 DENALI_CTL_11 +#define DDRMC_R002 DENALI_CTL_14 +#define DDRMC_R003 DENALI_CTL_15 +#define DDRMC_R004 DENALI_CTL_56 +#define DDRMC_R005 DENALI_CTL_59 +#define DDRMC_R006 DENALI_CTL_60 +#define DDRMC_R007 DENALI_CTL_64 +#define DDRMC_R008 DENALI_CTL_67 +#define DDRMC_R009 DENALI_CTL_70 +#define DDRMC_R010 DENALI_CTL_71 +#define DDRMC_R011 DENALI_CTL_73 +#define DDRMC_R012 DENALI_CTL_74 +#define DDRMC_R013 DENALI_CTL_75 +#define DDRMC_R014 DENALI_CTL_76 +#define DDRMC_R015 DENALI_CTL_81 +#define DDRMC_R016 DENALI_CTL_82 +#define DDRMC_R017 DENALI_CTL_83 +#define DDRMC_R018 DENALI_CTL_84 +#define DDRMC_R019 DENALI_CTL_133 +#define DDRMC_R020 DENALI_CTL_134 +#define DDRMC_R021 DENALI_CTL_146 +#define DDRMC_R022 DENALI_CTL_147 +#define DDRMC_R023 DENALI_CTL_154 +#define DDRMC_R024 DENALI_CTL_155 +#define DDRMC_R025 DENALI_CTL_176 +#define DDRMC_R026 DENALI_CTL_177 +#define DDRMC_R027 DENALI_CTL_391 +#define DDRMC_R028 DENALI_CTL_398 +#define DDRMC_R029 DENALI_CTL_401 +#define DDRMC_R030 DENALI_CTL_403 +#define DDRMC_R031 DENALI_CTL_404 +#define DDRMC_R032 DENALI_CTL_405 +#define DDRMC_R033 DENALI_CTL_406 +#define DDRMC_R034 DENALI_CTL_407 +#define DDRMC_R035 DENALI_CTL_408 +#define DDRMC_R036 DENALI_CTL_409 +#define DDRMC_R037 DENALI_CTL_410 +#define DDRMC_R038 DENALI_CTL_411 +#define DDRMC_R039 DENALI_CTL_413 +#define DDRMC_R040 DENALI_CTL_414 +#define DDRMC_R041 DENALI_CTL_415 +#define DDRMC_R042 DENALI_CTL_416 +#define DDRMC_R043 DENALI_CTL_417 +#define DDRMC_R044 DENALI_CTL_418 + +#endif // __DDR_MC_IF_H__ diff --git a/plat/renesas/rza/soc/a3ul/include/ddr_mc_regs.h b/plat/renesas/rza/soc/a3ul/include/ddr_mc_regs.h new file mode 100644 index 0000000000..1757eb67c6 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/ddr_mc_regs.h @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_MC_REGS_H__ +#define __DDR_MC_REGS_H__ + +#include + +#define DDR_MC_BASE PLAT_DDR_MEMC_BASE +#define MC_INIT_NUM (436) + +#define DENALI_CTL_00 (0x0000) +#define DENALI_CTL_01 (0x0004) +#define DENALI_CTL_02 (0x0008) +#define DENALI_CTL_03 (0x000C) +#define DENALI_CTL_04 (0x0010) +#define DENALI_CTL_05 (0x0014) +#define DENALI_CTL_06 (0x0018) +#define DENALI_CTL_07 (0x001C) +#define DENALI_CTL_08 (0x0020) +#define DENALI_CTL_09 (0x0024) +#define DENALI_CTL_10 (0x0028) +#define DENALI_CTL_11 (0x002C) +#define DENALI_CTL_12 (0x0030) +#define DENALI_CTL_13 (0x0034) +#define DENALI_CTL_14 (0x0038) +#define DENALI_CTL_15 (0x003C) +#define DENALI_CTL_16 (0x0040) +#define DENALI_CTL_17 (0x0044) +#define DENALI_CTL_18 (0x0048) +#define DENALI_CTL_19 (0x004C) +#define DENALI_CTL_20 (0x0050) +#define DENALI_CTL_21 (0x0054) +#define DENALI_CTL_22 (0x0058) +#define DENALI_CTL_23 (0x005C) +#define DENALI_CTL_24 (0x0060) +#define DENALI_CTL_25 (0x0064) +#define DENALI_CTL_26 (0x0068) +#define DENALI_CTL_27 (0x006C) +#define DENALI_CTL_28 (0x0070) +#define DENALI_CTL_29 (0x0074) +#define DENALI_CTL_30 (0x0078) +#define DENALI_CTL_31 (0x007C) +#define DENALI_CTL_32 (0x0080) +#define DENALI_CTL_33 (0x0084) +#define DENALI_CTL_34 (0x0088) +#define DENALI_CTL_35 (0x008C) +#define DENALI_CTL_36 (0x0090) +#define DENALI_CTL_37 (0x0094) +#define DENALI_CTL_38 (0x0098) +#define DENALI_CTL_39 (0x009C) +#define DENALI_CTL_40 (0x00A0) +#define DENALI_CTL_41 (0x00A4) +#define DENALI_CTL_42 (0x00A8) +#define DENALI_CTL_43 (0x00AC) +#define DENALI_CTL_44 (0x00B0) +#define DENALI_CTL_45 (0x00B4) +#define DENALI_CTL_46 (0x00B8) +#define DENALI_CTL_47 (0x00BC) +#define DENALI_CTL_48 (0x00C0) +#define DENALI_CTL_49 (0x00C4) +#define DENALI_CTL_50 (0x00C8) +#define DENALI_CTL_51 (0x00CC) +#define DENALI_CTL_52 (0x00D0) +#define DENALI_CTL_53 (0x00D4) +#define DENALI_CTL_54 (0x00D8) +#define DENALI_CTL_55 (0x00DC) +#define DENALI_CTL_56 (0x00E0) +#define DENALI_CTL_57 (0x00E4) +#define DENALI_CTL_58 (0x00E8) +#define DENALI_CTL_59 (0x00EC) +#define DENALI_CTL_60 (0x00F0) +#define DENALI_CTL_61 (0x00F4) +#define DENALI_CTL_62 (0x00F8) +#define DENALI_CTL_63 (0x00FC) +#define DENALI_CTL_64 (0x0100) +#define DENALI_CTL_65 (0x0104) +#define DENALI_CTL_66 (0x0108) +#define DENALI_CTL_67 (0x010C) +#define DENALI_CTL_68 (0x0110) +#define DENALI_CTL_69 (0x0114) +#define DENALI_CTL_70 (0x0118) +#define DENALI_CTL_71 (0x011C) +#define DENALI_CTL_72 (0x0120) +#define DENALI_CTL_73 (0x0124) +#define DENALI_CTL_74 (0x0128) +#define DENALI_CTL_75 (0x012C) +#define DENALI_CTL_76 (0x0130) +#define DENALI_CTL_77 (0x0134) +#define DENALI_CTL_78 (0x0138) +#define DENALI_CTL_79 (0x013C) +#define DENALI_CTL_80 (0x0140) +#define DENALI_CTL_81 (0x0144) +#define DENALI_CTL_82 (0x0148) +#define DENALI_CTL_83 (0x014C) +#define DENALI_CTL_84 (0x0150) +#define DENALI_CTL_85 (0x0154) +#define DENALI_CTL_86 (0x0158) +#define DENALI_CTL_87 (0x015C) +#define DENALI_CTL_88 (0x0160) +#define DENALI_CTL_89 (0x0164) +#define DENALI_CTL_90 (0x0168) +#define DENALI_CTL_91 (0x016C) +#define DENALI_CTL_92 (0x0170) +#define DENALI_CTL_93 (0x0174) +#define DENALI_CTL_94 (0x0178) +#define DENALI_CTL_95 (0x017C) +#define DENALI_CTL_96 (0x0180) +#define DENALI_CTL_97 (0x0184) +#define DENALI_CTL_98 (0x0188) +#define DENALI_CTL_99 (0x018C) +#define DENALI_CTL_100 (0x0190) +#define DENALI_CTL_101 (0x0194) +#define DENALI_CTL_102 (0x0198) +#define DENALI_CTL_103 (0x019C) +#define DENALI_CTL_104 (0x01A0) +#define DENALI_CTL_105 (0x01A4) +#define DENALI_CTL_106 (0x01A8) +#define DENALI_CTL_107 (0x01AC) +#define DENALI_CTL_108 (0x01B0) +#define DENALI_CTL_109 (0x01B4) +#define DENALI_CTL_110 (0x01B8) +#define DENALI_CTL_111 (0x01BC) +#define DENALI_CTL_112 (0x01C0) +#define DENALI_CTL_113 (0x01C4) +#define DENALI_CTL_114 (0x01C8) +#define DENALI_CTL_115 (0x01CC) +#define DENALI_CTL_116 (0x01D0) +#define DENALI_CTL_117 (0x01D4) +#define DENALI_CTL_118 (0x01D8) +#define DENALI_CTL_119 (0x01DC) +#define DENALI_CTL_120 (0x01E0) +#define DENALI_CTL_121 (0x01E4) +#define DENALI_CTL_122 (0x01E8) +#define DENALI_CTL_123 (0x01EC) +#define DENALI_CTL_124 (0x01F0) +#define DENALI_CTL_125 (0x01F4) +#define DENALI_CTL_126 (0x01F8) +#define DENALI_CTL_127 (0x01FC) +#define DENALI_CTL_128 (0x0200) +#define DENALI_CTL_129 (0x0204) +#define DENALI_CTL_130 (0x0208) +#define DENALI_CTL_131 (0x020C) +#define DENALI_CTL_132 (0x0210) +#define DENALI_CTL_133 (0x0214) +#define DENALI_CTL_134 (0x0218) +#define DENALI_CTL_135 (0x021C) +#define DENALI_CTL_136 (0x0220) +#define DENALI_CTL_137 (0x0224) +#define DENALI_CTL_138 (0x0228) +#define DENALI_CTL_139 (0x022C) +#define DENALI_CTL_140 (0x0230) +#define DENALI_CTL_141 (0x0234) +#define DENALI_CTL_142 (0x0238) +#define DENALI_CTL_143 (0x023C) +#define DENALI_CTL_144 (0x0240) +#define DENALI_CTL_145 (0x0244) +#define DENALI_CTL_146 (0x0248) +#define DENALI_CTL_147 (0x024C) +#define DENALI_CTL_148 (0x0250) +#define DENALI_CTL_149 (0x0254) +#define DENALI_CTL_150 (0x0258) +#define DENALI_CTL_151 (0x025C) +#define DENALI_CTL_152 (0x0260) +#define DENALI_CTL_153 (0x0264) +#define DENALI_CTL_154 (0x0268) +#define DENALI_CTL_155 (0x026C) +#define DENALI_CTL_156 (0x0270) +#define DENALI_CTL_157 (0x0274) +#define DENALI_CTL_158 (0x0278) +#define DENALI_CTL_159 (0x027C) +#define DENALI_CTL_160 (0x0280) +#define DENALI_CTL_161 (0x0284) +#define DENALI_CTL_162 (0x0288) +#define DENALI_CTL_163 (0x028C) +#define DENALI_CTL_164 (0x0290) +#define DENALI_CTL_165 (0x0294) +#define DENALI_CTL_166 (0x0298) +#define DENALI_CTL_167 (0x029C) +#define DENALI_CTL_168 (0x02A0) +#define DENALI_CTL_169 (0x02A4) +#define DENALI_CTL_170 (0x02A8) +#define DENALI_CTL_171 (0x02AC) +#define DENALI_CTL_172 (0x02B0) +#define DENALI_CTL_173 (0x02B4) +#define DENALI_CTL_174 (0x02B8) +#define DENALI_CTL_175 (0x02BC) +#define DENALI_CTL_176 (0x02C0) +#define DENALI_CTL_177 (0x02C4) +#define DENALI_CTL_178 (0x02C8) +#define DENALI_CTL_179 (0x02CC) +#define DENALI_CTL_180 (0x02D0) +#define DENALI_CTL_181 (0x02D4) +#define DENALI_CTL_182 (0x02D8) +#define DENALI_CTL_183 (0x02DC) +#define DENALI_CTL_184 (0x02E0) +#define DENALI_CTL_185 (0x02E4) +#define DENALI_CTL_186 (0x02E8) +#define DENALI_CTL_187 (0x02EC) +#define DENALI_CTL_188 (0x02F0) +#define DENALI_CTL_189 (0x02F4) +#define DENALI_CTL_190 (0x02F8) +#define DENALI_CTL_191 (0x02FC) +#define DENALI_CTL_192 (0x0300) +#define DENALI_CTL_193 (0x0304) +#define DENALI_CTL_194 (0x0308) +#define DENALI_CTL_195 (0x030C) +#define DENALI_CTL_196 (0x0310) +#define DENALI_CTL_197 (0x0314) +#define DENALI_CTL_198 (0x0318) +#define DENALI_CTL_199 (0x031C) +#define DENALI_CTL_200 (0x0320) +#define DENALI_CTL_201 (0x0324) +#define DENALI_CTL_202 (0x0328) +#define DENALI_CTL_203 (0x032C) +#define DENALI_CTL_204 (0x0330) +#define DENALI_CTL_205 (0x0334) +#define DENALI_CTL_206 (0x0338) +#define DENALI_CTL_207 (0x033C) +#define DENALI_CTL_208 (0x0340) +#define DENALI_CTL_209 (0x0344) +#define DENALI_CTL_210 (0x0348) +#define DENALI_CTL_211 (0x034C) +#define DENALI_CTL_212 (0x0350) +#define DENALI_CTL_213 (0x0354) +#define DENALI_CTL_214 (0x0358) +#define DENALI_CTL_215 (0x035C) +#define DENALI_CTL_216 (0x0360) +#define DENALI_CTL_217 (0x0364) +#define DENALI_CTL_218 (0x0368) +#define DENALI_CTL_219 (0x036C) +#define DENALI_CTL_220 (0x0370) +#define DENALI_CTL_221 (0x0374) +#define DENALI_CTL_222 (0x0378) +#define DENALI_CTL_223 (0x037C) +#define DENALI_CTL_224 (0x0380) +#define DENALI_CTL_225 (0x0384) +#define DENALI_CTL_226 (0x0388) +#define DENALI_CTL_227 (0x038C) +#define DENALI_CTL_228 (0x0390) +#define DENALI_CTL_229 (0x0394) +#define DENALI_CTL_230 (0x0398) +#define DENALI_CTL_231 (0x039C) +#define DENALI_CTL_232 (0x03A0) +#define DENALI_CTL_233 (0x03A4) +#define DENALI_CTL_234 (0x03A8) +#define DENALI_CTL_235 (0x03AC) +#define DENALI_CTL_236 (0x03B0) +#define DENALI_CTL_237 (0x03B4) +#define DENALI_CTL_238 (0x03B8) +#define DENALI_CTL_239 (0x03BC) +#define DENALI_CTL_240 (0x03C0) +#define DENALI_CTL_241 (0x03C4) +#define DENALI_CTL_242 (0x03C8) +#define DENALI_CTL_243 (0x03CC) +#define DENALI_CTL_244 (0x03D0) +#define DENALI_CTL_245 (0x03D4) +#define DENALI_CTL_246 (0x03D8) +#define DENALI_CTL_247 (0x03DC) +#define DENALI_CTL_248 (0x03E0) +#define DENALI_CTL_249 (0x03E4) +#define DENALI_CTL_250 (0x03E8) +#define DENALI_CTL_251 (0x03EC) +#define DENALI_CTL_252 (0x03F0) +#define DENALI_CTL_253 (0x03F4) +#define DENALI_CTL_254 (0x03F8) +#define DENALI_CTL_255 (0x03FC) +#define DENALI_CTL_256 (0x0400) +#define DENALI_CTL_257 (0x0404) +#define DENALI_CTL_258 (0x0408) +#define DENALI_CTL_259 (0x040C) +#define DENALI_CTL_260 (0x0410) +#define DENALI_CTL_261 (0x0414) +#define DENALI_CTL_262 (0x0418) +#define DENALI_CTL_263 (0x041C) +#define DENALI_CTL_264 (0x0420) +#define DENALI_CTL_265 (0x0424) +#define DENALI_CTL_266 (0x0428) +#define DENALI_CTL_267 (0x042C) +#define DENALI_CTL_268 (0x0430) +#define DENALI_CTL_269 (0x0434) +#define DENALI_CTL_270 (0x0438) +#define DENALI_CTL_271 (0x043C) +#define DENALI_CTL_272 (0x0440) +#define DENALI_CTL_273 (0x0444) +#define DENALI_CTL_274 (0x0448) +#define DENALI_CTL_275 (0x044C) +#define DENALI_CTL_276 (0x0450) +#define DENALI_CTL_277 (0x0454) +#define DENALI_CTL_278 (0x0458) +#define DENALI_CTL_279 (0x045C) +#define DENALI_CTL_280 (0x0460) +#define DENALI_CTL_281 (0x0464) +#define DENALI_CTL_282 (0x0468) +#define DENALI_CTL_283 (0x046C) +#define DENALI_CTL_284 (0x0470) +#define DENALI_CTL_285 (0x0474) +#define DENALI_CTL_286 (0x0478) +#define DENALI_CTL_287 (0x047C) +#define DENALI_CTL_288 (0x0480) +#define DENALI_CTL_289 (0x0484) +#define DENALI_CTL_290 (0x0488) +#define DENALI_CTL_291 (0x048C) +#define DENALI_CTL_292 (0x0490) +#define DENALI_CTL_293 (0x0494) +#define DENALI_CTL_294 (0x0498) +#define DENALI_CTL_295 (0x049C) +#define DENALI_CTL_296 (0x04A0) +#define DENALI_CTL_297 (0x04A4) +#define DENALI_CTL_298 (0x04A8) +#define DENALI_CTL_299 (0x04AC) +#define DENALI_CTL_300 (0x04B0) +#define DENALI_CTL_301 (0x04B4) +#define DENALI_CTL_302 (0x04B8) +#define DENALI_CTL_303 (0x04BC) +#define DENALI_CTL_304 (0x04C0) +#define DENALI_CTL_305 (0x04C4) +#define DENALI_CTL_306 (0x04C8) +#define DENALI_CTL_307 (0x04CC) +#define DENALI_CTL_308 (0x04D0) +#define DENALI_CTL_309 (0x04D4) +#define DENALI_CTL_310 (0x04D8) +#define DENALI_CTL_311 (0x04DC) +#define DENALI_CTL_312 (0x04E0) +#define DENALI_CTL_313 (0x04E4) +#define DENALI_CTL_314 (0x04E8) +#define DENALI_CTL_315 (0x04EC) +#define DENALI_CTL_316 (0x04F0) +#define DENALI_CTL_317 (0x04F4) +#define DENALI_CTL_318 (0x04F8) +#define DENALI_CTL_319 (0x04FC) +#define DENALI_CTL_320 (0x0500) +#define DENALI_CTL_321 (0x0504) +#define DENALI_CTL_322 (0x0508) +#define DENALI_CTL_323 (0x050C) +#define DENALI_CTL_324 (0x0510) +#define DENALI_CTL_325 (0x0514) +#define DENALI_CTL_326 (0x0518) +#define DENALI_CTL_327 (0x051C) +#define DENALI_CTL_328 (0x0520) +#define DENALI_CTL_329 (0x0524) +#define DENALI_CTL_330 (0x0528) +#define DENALI_CTL_331 (0x052C) +#define DENALI_CTL_332 (0x0530) +#define DENALI_CTL_333 (0x0534) +#define DENALI_CTL_334 (0x0538) +#define DENALI_CTL_335 (0x053C) +#define DENALI_CTL_336 (0x0540) +#define DENALI_CTL_337 (0x0544) +#define DENALI_CTL_338 (0x0548) +#define DENALI_CTL_339 (0x054C) +#define DENALI_CTL_340 (0x0550) +#define DENALI_CTL_341 (0x0554) +#define DENALI_CTL_342 (0x0558) +#define DENALI_CTL_343 (0x055C) +#define DENALI_CTL_344 (0x0560) +#define DENALI_CTL_345 (0x0564) +#define DENALI_CTL_346 (0x0568) +#define DENALI_CTL_347 (0x056C) +#define DENALI_CTL_348 (0x0570) +#define DENALI_CTL_349 (0x0574) +#define DENALI_CTL_350 (0x0578) +#define DENALI_CTL_351 (0x057C) +#define DENALI_CTL_352 (0x0580) +#define DENALI_CTL_353 (0x0584) +#define DENALI_CTL_354 (0x0588) +#define DENALI_CTL_355 (0x058C) +#define DENALI_CTL_356 (0x0590) +#define DENALI_CTL_357 (0x0594) +#define DENALI_CTL_358 (0x0598) +#define DENALI_CTL_359 (0x059C) +#define DENALI_CTL_360 (0x05A0) +#define DENALI_CTL_361 (0x05A4) +#define DENALI_CTL_362 (0x05A8) +#define DENALI_CTL_363 (0x05AC) +#define DENALI_CTL_364 (0x05B0) +#define DENALI_CTL_365 (0x05B4) +#define DENALI_CTL_366 (0x05B8) +#define DENALI_CTL_367 (0x05BC) +#define DENALI_CTL_368 (0x05C0) +#define DENALI_CTL_369 (0x05C4) +#define DENALI_CTL_370 (0x05C8) +#define DENALI_CTL_371 (0x05CC) +#define DENALI_CTL_372 (0x05D0) +#define DENALI_CTL_373 (0x05D4) +#define DENALI_CTL_374 (0x05D8) +#define DENALI_CTL_375 (0x05DC) +#define DENALI_CTL_376 (0x05E0) +#define DENALI_CTL_377 (0x05E4) +#define DENALI_CTL_378 (0x05E8) +#define DENALI_CTL_379 (0x05EC) +#define DENALI_CTL_380 (0x05F0) +#define DENALI_CTL_381 (0x05F4) +#define DENALI_CTL_382 (0x05F8) +#define DENALI_CTL_383 (0x05FC) +#define DENALI_CTL_384 (0x0600) +#define DENALI_CTL_385 (0x0604) +#define DENALI_CTL_386 (0x0608) +#define DENALI_CTL_387 (0x060C) +#define DENALI_CTL_388 (0x0610) +#define DENALI_CTL_389 (0x0614) +#define DENALI_CTL_390 (0x0618) +#define DENALI_CTL_391 (0x061C) +#define DENALI_CTL_392 (0x0620) +#define DENALI_CTL_393 (0x0624) +#define DENALI_CTL_394 (0x0628) +#define DENALI_CTL_395 (0x062C) +#define DENALI_CTL_396 (0x0630) +#define DENALI_CTL_397 (0x0634) +#define DENALI_CTL_398 (0x0638) +#define DENALI_CTL_399 (0x063C) +#define DENALI_CTL_400 (0x0640) +#define DENALI_CTL_401 (0x0644) +#define DENALI_CTL_402 (0x0648) +#define DENALI_CTL_403 (0x064C) +#define DENALI_CTL_404 (0x0650) +#define DENALI_CTL_405 (0x0654) +#define DENALI_CTL_406 (0x0658) +#define DENALI_CTL_407 (0x065C) +#define DENALI_CTL_408 (0x0660) +#define DENALI_CTL_409 (0x0664) +#define DENALI_CTL_410 (0x0668) +#define DENALI_CTL_411 (0x066C) +#define DENALI_CTL_412 (0x0670) +#define DENALI_CTL_413 (0x0674) +#define DENALI_CTL_414 (0x0678) +#define DENALI_CTL_415 (0x067C) +#define DENALI_CTL_416 (0x0680) +#define DENALI_CTL_417 (0x0684) +#define DENALI_CTL_418 (0x0688) +#define DENALI_CTL_419 (0x068C) +#define DENALI_CTL_420 (0x0690) +#define DENALI_CTL_421 (0x0694) +#define DENALI_CTL_422 (0x0698) +#define DENALI_CTL_423 (0x069C) +#define DENALI_CTL_424 (0x06A0) +#define DENALI_CTL_425 (0x06A4) +#define DENALI_CTL_426 (0x06A8) +#define DENALI_CTL_427 (0x06AC) +#define DENALI_CTL_428 (0x06B0) +#define DENALI_CTL_429 (0x06B4) +#define DENALI_CTL_430 (0x06B8) +#define DENALI_CTL_431 (0x06BC) +#define DENALI_CTL_432 (0x06C0) +#define DENALI_CTL_433 (0x06C4) +#define DENALI_CTL_434 (0x06C8) +#define DENALI_CTL_435 (0x06CC) + +#endif // __DDR_MC_REGS_H__ diff --git a/plat/renesas/rza/soc/a3ul/include/ddr_phy_regs.h b/plat/renesas/rza/soc/a3ul/include/ddr_phy_regs.h new file mode 100644 index 0000000000..2389179ed5 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/ddr_phy_regs.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DDR_PHY_REGS_H__ +#define __DDR_PHY_REGS_H__ + +#include + +#define DDR_PHY_BASE PLAT_DDR_PHY_BASE + +#define DDRPHY_R00 (0x040) +#define DDRPHY_R01 (0x044) +#define DDRPHY_R02 (0x048) +#define DDRPHY_R03 (0x04C) +#define DDRPHY_R04 (0x050) +#define DDRPHY_R05 (0x058) +#define DDRPHY_R06 (0x05C) +#define DDRPHY_R07 (0x060) +#define DDRPHY_R08 (0x064) +#define DDRPHY_R09 (0x068) +#define DDRPHY_R10 (0x09C) +#define DDRPHY_R11 (0x0A8) +#define DDRPHY_R12 (0x0C0) +#define DDRPHY_R13 (0x0C4) +#define DDRPHY_R14 (0x0C8) +#define DDRPHY_R15 (0x0CC) +#define DDRPHY_R16 (0x0D0) +#define DDRPHY_R17 (0x0E8) +#define DDRPHY_R18 (0x100) +#define DDRPHY_R19 (0x104) +#define DDRPHY_R20 (0x108) +#define DDRPHY_R21 (0x10C) +#define DDRPHY_R22 (0x110) +#define DDRPHY_R23 (0x114) +#define DDRPHY_R24 (0x118) +#define DDRPHY_R25 (0x11C) +#define DDRPHY_R26 (0x120) +#define DDRPHY_R27 (0x124) +#define DDRPHY_R28 (0x128) +#define DDRPHY_R29 (0x12C) +#define DDRPHY_R30 (0x130) +#define DDRPHY_R31 (0x134) +#define DDRPHY_R32 (0x138) +#define DDRPHY_R33 (0x13C) +#define DDRPHY_R34 (0x140) +#define DDRPHY_R35 (0x144) +#define DDRPHY_R36 (0x148) +#define DDRPHY_R37 (0x14C) +#define DDRPHY_R38 (0x150) +#define DDRPHY_R39 (0x154) +#define DDRPHY_R40 (0x158) +#define DDRPHY_R41 (0x15C) +#define DDRPHY_R42 (0x160) +#define DDRPHY_R43 (0x164) +#define DDRPHY_R44 (0x168) +#define DDRPHY_R45 (0x16C) +#define DDRPHY_R46 (0x170) +#define DDRPHY_R47 (0x174) +#define DDRPHY_R48 (0x178) +#define DDRPHY_R49 (0x17C) +#define DDRPHY_R50 (0x180) +#define DDRPHY_R51 (0x188) +#define DDRPHY_R52 (0x18C) +#define DDRPHY_R53 (0x190) +#define DDRPHY_R54 (0x194) +#define DDRPHY_R55 (0x19C) +#define DDRPHY_R56 (0x1A0) +#define DDRPHY_R57 (0x1A4) +#define DDRPHY_R58 (0x1A8) +#define DDRPHY_R59 (0x1AC) +#define DDRPHY_R60 (0x1B0) +#define DDRPHY_R61 (0x1B4) +#define DDRPHY_R62 (0x1B8) +#define DDRPHY_R63 (0x1BC) +#define DDRPHY_R64 (0x1C0) +#define DDRPHY_R65 (0x1C4) +#define DDRPHY_R66 (0x1C8) +#define DDRPHY_R67 (0x1CC) +#define DDRPHY_R68 (0x1D0) +#define DDRPHY_R69 (0x1D4) +#define DDRPHY_R70 (0x1D8) +#define DDRPHY_R71 (0x1DC) +#define DDRPHY_R72 (0x1E0) +#define DDRPHY_R73 (0x1E4) +#define DDRPHY_R74 (0x1E8) +#define DDRPHY_R75 (0x1EC) +#define DDRPHY_R76 (0x1F0) +#define DDRPHY_R77 (0x200) +#define DDRPHY_R78 (0x204) +#define DDRPHY_R79 (0x240) + +#endif // __DDR_PHY_REGS_H__ diff --git a/plat/renesas/rza/soc/a3ul/include/platform_def.h b/plat/renesas/rza/soc/a3ul/include/platform_def.h new file mode 100644 index 0000000000..4f9e0d3d16 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/platform_def.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#ifndef __ASSEMBLER__ +#include +#endif + +#include +#include + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ +#define PLATFORM_STACK_SIZE U(0x1000) + +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_COUNT U(2) + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_SYSTEM_COUNT) + +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) +#define PLAT_MAX_PWR_LVL_STATES U(2) + +#define MAX_IO_DEVICES U(2) +#define MAX_IO_HANDLES U(2) +#define MAX_IO_BLOCK_DEVICES U(1) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#if !TRUSTED_BOARD_BOOT +#define BL2_BASE (0x00012000) +#define BL2_LIMIT (0x0002F000) +#else +#define BL2_BASE (0x00013000) +#define BL2_LIMIT (0x0002F000) +#endif + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_BASE (0x44000000) +#define BL31_LIMIT (0x44040000) + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef SPD_none +#define BL32_BASE (0x44100000) +#define BL32_LIMIT (BL32_BASE + 0x100000) +#endif + +/******************************************************************************* + * BL33 + ******************************************************************************/ +#define BL33_BASE (0x50000000) +#define BL33_LIMIT (BL33_BASE + 0x08000000) + +/******************************************************************************* + * BSP + ******************************************************************************/ +#define BSP_BASE (0x50000000) +#define BSP_LIMIT (BSP_BASE + 0x08000000) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#if IMAGE_BL2 +#define MAX_XLAT_TABLES U(4) +#define MAX_MMAP_REGIONS U(9) +#elif IMAGE_BL31 +#define MAX_XLAT_TABLES U(6) +#define MAX_MMAP_REGIONS U(9) +#endif + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) + +/******************************************************************************* + * Determining the use of FIP format + ******************************************************************************/ +#define RZ_NOFIP (0) +#define RZ_FIP (1) + +#define ARMv8A (1) + +#define RZ_APP_PAYLOAD_OFFSET (0x200) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +#endif /* PLATFORM_DEF_H */ diff --git a/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h b/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h new file mode 100644 index 0000000000..06b7752f88 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __RZA3UL_DEF_H__ +#define __RZA3UL_DEF_H__ + +#define PLAT_BOOT_ROM_BASE (0x00000000) +#define PLAT_MSRAM_BASE (0x00010000) +#define PLAT_ASRAM_BASE (0x00020000) +#define PLAT_DEVICE_BASE (0x10000000) +#define PLAT_SCIF0_BASE (0x1004B800) +#define PLAT_SPIMULT_BASE (0x10060000) +#define PLAT_SPIMULT_WBUF_BASE (0x10070000) +#define PLAT_SYC_BASE (0x11000000) +#define PLAT_CPG_BASE (0x11010000) +#define PLAT_SYSC_BASE (0x11020000) +#define PLAT_GPIO_BASE (0x11030000) +#define PLAT_TZC_ASRAM_BASE (0x11040000) +#define PLAT_TZC_MSRAM_BASE (0x11050000) +#define PLAT_TZC_SPI_BASE (0x11060000) +#define PLAT_TZC_DDR_BASE (0x11070000) +#define PLAT_DDR_PHY_BASE (0x11400000) +#define PLAT_DDR_MEMC_BASE (0x11410000) +#define PLAT_OTP_BASE (0x11860000) +#define PLAT_GIC_BASE (0x11900000) +#define PLAT_SD0_BASE (0x11C00000) +#define PLAT_SPIROM_BASE (0x20000000) +#define PLAT_DDR1_BASE (0x40000000) +#define PLAT_DDR2_BASE (0x80000000) +#define PLAT_DDR3_BASE (0x100000000) + +#define PLAT_GICD_BASE (PLAT_GIC_BASE) +#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) + +#define PLAT_SRAM_BASE (PLAT_MSRAM_BASE) + +#define PLAT_BOOT_ROM_SIZE (0x00010000 - PLAT_BOOT_ROM_BASE) +#define PLAT_MSRAM_SIZE (0x00020000 - PLAT_MSRAM_BASE) +#define PLAT_ASRAM_SIZE (0x00030000 - PLAT_ASRAM_BASE) +#define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) +#define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) +#define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) +#define PLAT_DDR1_SIZE (PLAT_DDR2_BASE - PLAT_DDR1_BASE) +#define PLAT_DDR2_SIZE (PLAT_DDR3_BASE - PLAT_DDR2_BASE) + +#define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) +#define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) + +#define PLAT_OTP_DEVICE_INFO (PLAT_OTP_BASE + 0x1178) + +#define PLAT_EMMC_FIP_BASE (0x00020000) +#define PLAT_EMMC_FIP_SIZE (0x001DFFFF) + +#define PLAT_SYC_INCK_HZ (24000000) +#define PLAT_UART_INCK_HZ (100000000) +#define PLAT_UART_BARDRATE (115200) + +/* Boot Info base address */ +#define PLAT_BOOTINFO_BASE (PLAT_SRAM_BASE) + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE (PLAT_SRAM_BASE + 0x0001F000) +#define PARAMS_SIZE (0x1000) + +#endif /* __RZA3UL_DEF_H__ */ diff --git a/plat/renesas/rza/soc/a3ul/rz_image.pl b/plat/renesas/rza/soc/a3ul/rz_image.pl new file mode 100644 index 0000000000..8299b9c416 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/rz_image.pl @@ -0,0 +1,74 @@ +#!/usr/bin/perl -w +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause + +use strict; +use bigint; +my $size_limit = 0x1D000; + +die("Not enough parameter\n") if ($#ARGV < 0); + +# Open input file +my $name = shift(@ARGV); +my $outname; +if ($#ARGV < 0) { + $outname = "rz_" . $name; +} +else { + $outname = shift(@ARGV); +} +open(my $origin, '<', $name) or die("Can not open input file"); +binmode $origin; + +# Obtaining size ($st[7]) +my @st = stat($origin); + +# Check appended size +my $size = ($st[7] + 3) & "0xfffffffffffffffc"; +my $msg; +if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";} +die("$msg too big ($size > $size_limit)") if ($size > $size_limit); + +# Create temporary file +open(my $out, '>', $outname) or die("Can not open output file"); +binmode $out; + +# Write header +$out->print(pack('L', $size)); +for(my $i = 1; $i < 112; $i++) { + $out->print(pack('L', 0xffffffff)); +} +$out->print(pack('L', 0xffff0000)); +$out->print(pack('L', 0x000800ff)); +$out->print(pack('L', 0x00fff700)); +$out->print(pack('L', 0xf700f708)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xffffffff)); +$out->print(pack('L', 0xaa55ffff)); + +# Append original data to temporary file +my $buf; +read($origin, $buf, $st[7]); +$out->print($buf); +if($st[7] < $size) { + warn "Not aligned. Append " . ($size-$st[7]) . " zero(s)"; + # Append zero + for(;$st[7] < $size; $size--) { + $out->print(pack('C', 0)); + } +} +$out->flush; + +# close +close $out; +close $origin; diff --git a/plat/renesas/rza/soc/a3ul/rz_xspi.mk b/plat/renesas/rza/soc/a3ul/rz_xspi.mk new file mode 100644 index 0000000000..3e8a7d2ae1 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/rz_xspi.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +RZ_XSPI_DRIVER_PATH := plat/renesas/rza/common/drivers/xspi + +RZ_XSPI_CONFIGS := XSPI0 XSPI1 XSPI2 +RZ_XSPI_SOURCES := plat/renesas/rza/soc/a3ul/drivers/xspi.c +RZ_XSPI_HEADERS := +RZ_XSPI0_IF := spim +RZ_XSPI0_IF_CONFIG := .channel=0, .base=0x10060000 +RZ_XSPI1_IF := octa +RZ_XSPI1_IF_CONFIG := .channel=0, .base=0x10080000 +RZ_XSPI2_IF := octa +RZ_XSPI2_IF_CONFIG := .channel=1, .base=0x10080000 +RZ_XSPI_EXCLUSIVE_SELECTOR := 1 +RZ_SPIM_SDR_FREQ_LIMIT := 66625000 +RZ_OCTA_FREQ_LIMIT := 100000000 + +ifneq ($(strip $(XSPI0_DEVICE)),) + ifneq ($(strip $(XSPI1_DEVICE)),) + $(error XSPI0_DEVICE and XSPI1_DEVICE can not be specified at the same time.) + endif + ifneq ($(strip $(XSPI2_DEVICE)),) + $(error XSPI0_DEVICE and XSPI2_DEVICE can not be specified at the same time.) + endif +endif + +include plat/renesas/rza/common/rz_xspi_common.mk + +$(eval $(call add_define,RZ_XSPI_EXCLUSIVE_SELECTOR)) +$(eval $(call add_define,RZ_SPIM_SDR_FREQ_LIMIT)) +$(eval $(call add_define,RZ_OCTA_FREQ_LIMIT)) diff --git a/plat/renesas/rza/soc/a3ul/soc.mk b/plat/renesas/rza/soc/a3ul/soc.mk new file mode 100644 index 0000000000..0df067df14 --- /dev/null +++ b/plat/renesas/rza/soc/a3ul/soc.mk @@ -0,0 +1,60 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_INCLUDES += -Iplat/renesas/rza/soc/a3ul/include + +DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c + +RZA3 := 1 +RZA3UL := 1 +DEVICE_TYPE := 1 +ARCH_TYPE := ARMv8A +LOG_LEVEL := 10 +ifeq (${SOC_TYPE},2) +DEVICE_TYPE := 2 +endif +RZA3_XSPI_MEMORY_BASE := 0x20000000 + +$(eval $(call add_define,RZA3)) +$(eval $(call add_define,RZA3UL)) +$(eval $(call add_define,DEVICE_TYPE)) +$(eval $(call add_define,ARCH_TYPE)) +$(eval $(call add_define,RZA3_XSPI_MEMORY_BASE)) + +# set file name +RZ_ELF := $(BUILD_PLAT)/rz$(BOARD)_ipl.elf +BL2_ELF := $(BUILD_PLAT)/bl2/bl2.elf +RZ_BIN := $(BUILD_PLAT)/rz$(BOARD)_ipl.bin +BL2_BIN := $(BUILD_PLAT)/bl2.bin +RZ_MAP := $(BUILD_PLAT)/rz$(BOARD)_ipl.map +BL2_MAP := $(BUILD_PLAT)/bl2/bl2.map +RZ_DUMP := $(BUILD_PLAT)/rz$(BOARD)_ipl.dump +BL2_DUMP := $(BUILD_PLAT)/bl2/bl2.dump +RZ_SREC := $(BUILD_PLAT)/rz$(BOARD)_ipl.srec + +bl2: $(RZ_ELF) $(RZ_BIN) $(RZ_LINKER) $(RZ_MAP) $(RZ_DUMP) $(RZ_SREC) + +$(RZ_ELF): $(BL2_ELF) + $(call SHELL_COPY,$<,$@) + +$(RZ_BIN): $(BL2_BIN) + @echo " IMG $@" + $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3ul/rz_image.pl "$<" "$@" + +$(BL2_MAP): $(BL2_ELF) +$(RZ_MAP): $(BL2_MAP) + $(call SHELL_COPY,$<,$@) + +$(RZ_DUMP): $(BL2_DUMP) + $(call SHELL_COPY,$<,$@) + +$(RZ_SREC): $(RZ_BIN) + @echo " SREC $@" + $(q)$($(ARCH)-oc) -I binary -O srec --adjust-vma=0x20000000 --srec-forceS3 "$<" "$@" + +ifeq (${RZ_TEST},1) +-include plat/renesas/rza/common/drivers/tests/rz_test.mk +endif From 71fcce068e7721689e957206c972baa086f018b3 Mon Sep 17 00:00:00 2001 From: Nhut Nguyen Date: Wed, 15 Oct 2025 14:51:17 +0700 Subject: [PATCH 2/2] plat: renesas: Improve RZ/A platform Improve RZ/A platform Signed-off-by: Nhut Nguyen --- .../renesas/common/scifa}/scifa.S | 92 ++- .../renesas/common/syc}/syc.c | 0 .../renesas/rza}/auth/auth_mod.c | 40 +- .../renesas/rza}/auth/sblib/crypto_sblib.c | 7 +- .../rza}/auth/sblib/sblib_api_private.h | 6 +- .../renesas/rza}/auth/sblib/sblib_parser.c | 4 +- .../renesas/rza}/auth/tbbr/tbbr_cot.c | 0 .../drivers => drivers/renesas/rza/cpg}/cpg.c | 69 +- .../drivers => drivers/renesas/rza}/ddr/ddr.c | 87 +- .../renesas/rza}/ddr/param_swizzle_T1.c | 0 .../renesas/rza}/ddr/param_swizzle_T3bcud2.c | 2 +- .../drivers => drivers/renesas/rza/pfc}/pfc.c | 6 +- .../renesas/rza}/xspi/octa.c | 76 +- .../renesas/rza}/xspi/spim.c | 53 +- .../renesas/rza/xspi}/xspi.c | 9 + .../octaflash_mx66uw/octaflash_mx66uw.c | 21 +- .../octaflash_mx66uw/octaflash_mx66uw_api.h | 1 - .../octaflash_mx66uw/rz_xspidevice.mk | 11 + .../xspidevice/octaram_apsxx/octaram_apsxx.c | 4 +- .../octaram_apsxx/octaram_apsxx_api.h | 1 - .../xspidevice/octaram_apsxx/rz_xspidevice.mk | 11 + .../qspiflash_at25/qspiflash_at25.c | 16 +- .../qspiflash_at25/qspiflash_at25_api.h | 1 - .../qspiflash_at25/rz_xspidevice.mk | 11 + .../qspiflash_mx25l25645g.c | 37 +- .../qspiflash_mx25l25645g_api.h | 1 - .../qspiflash_mx25l25645g/rz_xspidevice.mk | 11 + .../drivers/renesas/rza}/auth/auth_common.h | 52 +- .../renesas/rza}/auth/sblib/crypto_sblib.h | 5 +- .../drivers/renesas/rza/console}/scifa.h | 4 +- .../drivers/renesas/rza/cpg}/cpg.h | 6 +- .../drivers/renesas/rza/cpg}/cpg_regs.h | 408 +++++----- .../drivers/renesas/rza/ddr}/ddr.h | 0 .../drivers/renesas/rza/ddr}/ddr_internal.h | 6 +- .../drivers/renesas/rza/octal}/octa.h | 0 .../drivers/renesas/rza/octal}/octa_regs.h | 0 .../drivers/renesas/rza/pfc}/pfc.h | 1 - include/drivers/renesas/rza/pfc/pfc_regs.h | 746 ++++++++++++++++++ .../drivers/renesas/rza/spim}/spim.h | 0 .../drivers/renesas/rza/spim}/spim_regs.h | 0 .../drivers/renesas/rza/syc}/syc.h | 0 .../drivers/renesas/rza/sys}/sys.h | 0 .../drivers/renesas/rza/sys}/sys_regs.h | 568 ++++++------- .../drivers/renesas/rza/xspi}/xspi_api.h | 10 +- .../renesas/rza/xspi}/xspidevice_api.h | 5 +- plat/renesas/rza/board/a3m_ek_nor/platform.mk | 4 +- .../rza/board/a3ul_smarc_octal/platform.mk | 2 +- .../rza/board/a3ul_smarc_qspi/platform.mk | 2 +- plat/renesas/rza/common/bl2_plat_setup.c | 70 +- .../common/drivers/ddr/param_swizzle_T1b.c | 46 -- .../common/drivers/ddr/param_swizzle_T1bc.c | 46 -- .../common/drivers/ddr/param_swizzle_T1c.c | 46 -- .../common/drivers/ddr/param_swizzle_T1vbc.c | 46 -- .../common/drivers/ddr/param_swizzle_T1vc.c | 46 -- .../common/drivers/ddr/param_swizzle_T2c.c | 46 -- .../common/drivers/ddr/param_swizzle_T2vc.c | 46 -- .../common/drivers/ddr/param_swizzle_T3bc.c | 46 -- .../common/drivers/ddr/param_swizzle_T3bcud.c | 46 -- .../common/drivers/ddr/param_swizzle_T3bcul.c | 46 -- .../common/drivers/ddr/param_swizzle_T3cl.c | 46 -- .../rza/common/drivers/emmc/emmc_cmd.c | 495 ------------ .../rza/common/drivers/emmc/emmc_config.h | 20 - .../rza/common/drivers/emmc/emmc_def.h | 78 -- .../rza/common/drivers/emmc/emmc_hal.h | 535 ------------- .../rza/common/drivers/emmc/emmc_init.c | 143 ---- .../rza/common/drivers/emmc/emmc_interrupt.c | 192 ----- .../rza/common/drivers/emmc/emmc_mount.c | 664 ---------------- .../rza/common/drivers/emmc/emmc_read.c | 127 --- .../rza/common/drivers/emmc/emmc_registers.h | 194 ----- .../rza/common/drivers/emmc/emmc_std.h | 475 ----------- .../rza/common/drivers/emmc/emmc_utility.c | 200 ----- .../rza/common/drivers/io/io_emmcdrv.c | 203 ----- .../rza/common/drivers/io/io_emmcdrv.h | 13 - .../common/drivers/rza_mmu/ARMv8A/rza_mmu.c | 236 ------ .../spi_multi/AT25QL128A/spi_multi_device.c | 55 -- .../spi_multi/MT25QU512ABB/spi_multi_device.c | 10 - .../rza/common/drivers/spi_multi/spi_multi.c | 158 ---- .../octaflash_mx66uw/rz_xspidevice.mk | 11 - .../xspidevice/octaram_apsxx/rz_xspidevice.mk | 11 - .../qspiflash_at25/rz_xspidevice.mk | 11 - .../qspiflash_mx25l25645g/rz_xspidevice.mk | 11 - .../AT25QL128A/spi_multi_reg_values.h | 105 --- .../MT25QU512ABB/spi_multi_reg_values.h | 90 --- .../include/drivers/spi_multi/spi_multi.h | 46 -- .../drivers/spi_multi/spi_multi_regs.h | 255 ------ plat/renesas/rza/common/include/pfc_regs.h | 746 ------------------ plat/renesas/rza/common/include/rz_private.h | 9 +- plat/renesas/rza/common/include/rza_mmu.h | 131 --- plat/renesas/rza/common/plat_gic.c | 57 -- plat/renesas/rza/common/plat_image_load.c | 31 +- plat/renesas/rza/common/plat_pm.c | 74 -- plat/renesas/rza/common/plat_rz_common.c | 2 +- plat/renesas/rza/common/plat_security.c | 2 +- plat/renesas/rza/common/plat_storage.c | 156 +--- plat/renesas/rza/common/rz_common.mk | 49 +- plat/renesas/rza/common/rz_plat_sip_handler.c | 2 + plat/renesas/rza/common/rz_xspi_common.mk | 4 +- .../renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c | 2 +- plat/renesas/rza/soc/a3m/include/cpg_opt.h | 12 - .../rza/soc/a3m/include/platform_def.h | 6 +- plat/renesas/rza/soc/a3m/include/rza3m_def.h | 7 +- plat/renesas/rza/soc/a3m/rz_xspi.mk | 9 +- plat/renesas/rza/soc/a3m/soc.mk | 4 +- .../rza/soc/a3ul/drivers/ddr/ddr_a3ul.c | 2 +- .../a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c | 232 ------ .../a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c | 232 ------ .../a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c | 232 ------ plat/renesas/rza/soc/a3ul/drivers/xspi.c | 71 -- plat/renesas/rza/soc/a3ul/include/cpg_opt.h | 12 - .../rza/soc/a3ul/include/platform_def.h | 6 +- .../renesas/rza/soc/a3ul/include/rza3ul_def.h | 89 +-- plat/renesas/rza/soc/a3ul/rz_image.pl | 74 -- plat/renesas/rza/soc/a3ul/rz_xspi.mk | 9 +- plat/renesas/rza/soc/a3ul/soc.mk | 2 +- .../soc => tools/renesas/rza}/a3m/rz_image.pl | 0 .../renesas/rza}/a3m/rz_image_nand.pl | 64 +- .../renesas/rza/a3ul}/rz_image.pl | 0 .../renesas/rza}/rz_bl2_xspi_config.sh | 0 118 files changed, 1840 insertions(+), 7798 deletions(-) rename {plat/renesas/rza/common/drivers => drivers/renesas/common/scifa}/scifa.S (75%) rename {plat/renesas/rza/common/drivers => drivers/renesas/common/syc}/syc.c (100%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/auth/auth_mod.c (92%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/auth/sblib/crypto_sblib.c (78%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/auth/sblib/sblib_api_private.h (98%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/auth/sblib/sblib_parser.c (97%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/auth/tbbr/tbbr_cot.c (100%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza/cpg}/cpg.c (93%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/ddr/ddr.c (93%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/ddr/param_swizzle_T1.c (100%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/ddr/param_swizzle_T3bcud2.c (96%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza/pfc}/pfc.c (97%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspi/octa.c (98%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspi/spim.c (99%) rename {plat/renesas/rza/soc/a3m/drivers => drivers/renesas/rza/xspi}/xspi.c (91%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c (98%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h (97%) create mode 100644 drivers/renesas/rza/xspidevice/octaflash_mx66uw/rz_xspidevice.mk rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/octaram_apsxx/octaram_apsxx.c (99%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/octaram_apsxx/octaram_apsxx_api.h (96%) create mode 100644 drivers/renesas/rza/xspidevice/octaram_apsxx/rz_xspidevice.mk rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/qspiflash_at25/qspiflash_at25.c (99%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/qspiflash_at25/qspiflash_at25_api.h (96%) create mode 100644 drivers/renesas/rza/xspidevice/qspiflash_at25/rz_xspidevice.mk rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c (98%) rename {plat/renesas/rza/common/drivers => drivers/renesas/rza}/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h (98%) create mode 100644 drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk rename {plat/renesas/rza/common/include/drivers => include/drivers/renesas/rza}/auth/auth_common.h (62%) rename {plat/renesas/rza/common/include/drivers => include/drivers/renesas/rza}/auth/sblib/crypto_sblib.h (58%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/console}/scifa.h (74%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/cpg}/cpg.h (97%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/cpg}/cpg_regs.h (60%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/ddr}/ddr.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/ddr}/ddr_internal.h (91%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/octal}/octa.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/octal}/octa_regs.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/pfc}/pfc.h (99%) create mode 100644 include/drivers/renesas/rza/pfc/pfc_regs.h rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/spim}/spim.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/spim}/spim_regs.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/syc}/syc.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/sys}/sys.h (100%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/sys}/sys_regs.h (65%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/xspi}/xspi_api.h (96%) rename {plat/renesas/rza/common/include => include/drivers/renesas/rza/xspi}/xspidevice_api.h (96%) delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c delete mode 100644 plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_cmd.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_config.h delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_def.h delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_hal.h delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_init.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_mount.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_read.c delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_registers.h delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_std.h delete mode 100644 plat/renesas/rza/common/drivers/emmc/emmc_utility.c delete mode 100644 plat/renesas/rza/common/drivers/io/io_emmcdrv.c delete mode 100644 plat/renesas/rza/common/drivers/io/io_emmcdrv.h delete mode 100644 plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c delete mode 100644 plat/renesas/rza/common/drivers/spi_multi/AT25QL128A/spi_multi_device.c delete mode 100644 plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c delete mode 100644 plat/renesas/rza/common/drivers/spi_multi/spi_multi.c delete mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk delete mode 100644 plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk delete mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk delete mode 100644 plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk delete mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h delete mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h delete mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h delete mode 100644 plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h delete mode 100644 plat/renesas/rza/common/include/pfc_regs.h delete mode 100644 plat/renesas/rza/common/include/rza_mmu.h delete mode 100644 plat/renesas/rza/common/plat_gic.c delete mode 100644 plat/renesas/rza/common/plat_pm.c delete mode 100644 plat/renesas/rza/soc/a3m/include/cpg_opt.h delete mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c delete mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c delete mode 100644 plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c delete mode 100644 plat/renesas/rza/soc/a3ul/drivers/xspi.c delete mode 100644 plat/renesas/rza/soc/a3ul/include/cpg_opt.h delete mode 100644 plat/renesas/rza/soc/a3ul/rz_image.pl rename {plat/renesas/rza/soc => tools/renesas/rza}/a3m/rz_image.pl (100%) rename {plat/renesas/rza/soc => tools/renesas/rza}/a3m/rz_image_nand.pl (73%) rename {plat/renesas/rza/common => tools/renesas/rza/a3ul}/rz_image.pl (100%) rename {plat/renesas/rza/common => tools/renesas/rza}/rz_bl2_xspi_config.sh (100%) diff --git a/plat/renesas/rza/common/drivers/scifa.S b/drivers/renesas/common/scifa/scifa.S similarity index 75% rename from plat/renesas/rza/common/drivers/scifa.S rename to drivers/renesas/common/scifa/scifa.S index e430c43e34..d258243ed6 100644 --- a/plat/renesas/rza/common/drivers/scifa.S +++ b/drivers/renesas/common/scifa/scifa.S @@ -8,40 +8,39 @@ #include #include -#define SMR (0x00) -#define BRR (0x02) +#define SMR (0x00) +#define BRR (0x02) #define MDDR (0x02) -#define SCR (0x04) +#define SCR (0x04) #define FTDR (0x06) -#define FSR (0x08) +#define FSR (0x08) #define FRDR (0x0A) -#define FCR (0x0C) -#define FDR (0x0E) +#define FCR (0x0C) +#define FDR (0x0E) #define SPTR (0x10) -#define LSR (0x12) +#define LSR (0x12) #define SEMR (0x14) #define FTCR (0x16) -#define SCR_CKE_MASK (0x03) -#define SCR_CKE_INTERN (0x00) +#define SCR_CKE_MASK (0x03) +#define SCR_CKE_INTERN (0x00) #define SCR_RE_ON (0x10) #define SCR_TE_ON (0x20) #define SCR_INIT (0x00) #define SCR_READY (SCR_INIT | SCR_RE_ON | SCR_TE_ON) -#define FCR_RFRST_RST (0x02) -#define FCR_TFRST_RST (0x04) +#define FCR_RFRST_RST (0x02) +#define FCR_TFRST_RST (0x04) #define FCR_BASE (0x00) #define FCR_RST (FCR_BASE | FCR_RFRST_RST | FCR_TFRST_RST) #define FCR_RUN (FCR_BASE) #define SMR_INIT (0x00) -#define SEMR_NFEN_ON (0x04) -#define SEMR_MDDRS_BRR (0x00) -#define SEMR_MDDRS_MDDR (0x10) -#define SEMR_BRME_ON (0x20) -//#define SEMR_BASE (SEMR_NFEN_ON) +#define SEMR_NFEN_ON (0x04) +#define SEMR_MDDRS_BRR (0x00) +#define SEMR_MDDRS_MDDR (0x10) +#define SEMR_BRME_ON (0x20) #define SEMR_BASE (0x00) #define SEMR_BRR (SEMR_BASE | SEMR_MDDRS_BRR) #define SEMR_MDDR (SEMR_BASE | SEMR_MDDRS_MDDR | SEMR_BRME_ON) @@ -49,20 +48,29 @@ #define FTCR_TTRGS (0x0080) #define FTCR_RTRGS (0x8000) -#define FSR_TDFE_SHIFT (5) -#define FSR_TEND_SHIFT (6) +#define FSR_TDFE_SHIFT (5) +#define FSR_TEND_SHIFT (6) #define FSR_TEND (1<parent; - rc = auth_get_param(param->key_cert, content_cert_desc, + rc = auth_get_param(param->content_cert, content_cert_desc, &content_cert_ptr, &content_cert_len); - return_if_error(rc); + if (rc != 0) { + return rc; + } /* Get the key certificate that is the parent of the content certificate */ key_cert_desc = content_cert_desc->parent; - rc = auth_get_param(param->content_cert, key_cert_desc, &key_cert_ptr, + rc = auth_get_param(param->key_cert, key_cert_desc, &key_cert_ptr, &key_cert_len); - return_if_error(rc); + if (rc != 0) { + return rc; + } /* Get the data to authenticate from the current image */ rc = img_parser_get_auth_param(img_desc->img_type, param->data, img, img_len, &data_ptr, &data_len); - return_if_error(rc); + if (rc != 0) { + return rc; + } /* Ask Renesas SB-Lib to authenticate this image */ - rc = crypto_sblib_auth(data_ptr, data_len, key_cert_ptr, key_cert_len, - content_cert_ptr, content_cert_len); + rc = crypto_sblib_auth(key_cert_ptr, key_cert_len, content_cert_ptr, + content_cert_len); return rc; } @@ -196,7 +195,9 @@ int auth_mod_verify_img(unsigned int img_id, void *img_ptr, /* Ask the parser to check the image integrity */ rc = img_parser_check_integrity(img_desc->img_type, img_ptr, img_len); - return_if_error(rc); + if (rc != 0) { + return rc; + } /* Authenticate the image using the methods indicated in the image descriptor. */ if (img_desc->img_auth_methods == NULL) @@ -216,7 +217,10 @@ int auth_mod_verify_img(unsigned int img_id, void *img_ptr, rc = 1; break; } - return_if_error(rc); + + if (rc != 0) { + return rc; + } } /* Extract the parameters indicated in the image descriptor to @@ -233,7 +237,9 @@ int auth_mod_verify_img(unsigned int img_id, void *img_ptr, img_desc->img_type, img_desc->authenticated_data[i].type_desc, img_ptr, img_len, ¶m_ptr, ¶m_len); - return_if_error(rc); + if (rc != 0) { + return rc; + } /* Check parameter size */ if (param_len > diff --git a/plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c b/drivers/renesas/rza/auth/sblib/crypto_sblib.c similarity index 78% rename from plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c rename to drivers/renesas/rza/auth/sblib/crypto_sblib.c index 7dc3d9c0d5..7ede7b717e 100644 --- a/plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c +++ b/drivers/renesas/rza/auth/sblib/crypto_sblib.c @@ -17,9 +17,8 @@ static sb_secure_boot_api_t secure_boot_api; -int crypto_sblib_auth(void *data_ptr, size_t len, const void *key_cert, - unsigned int key_cert_len, const void *content_cert, - unsigned int content_cert_len) +int crypto_sblib_auth(const void *key_cert, unsigned int key_cert_len, + const void *content_cert, unsigned int content_cert_len) { sb_ret_t rc; @@ -27,7 +26,7 @@ int crypto_sblib_auth(void *data_ptr, size_t len, const void *key_cert, rc = secure_boot_api(key_cert, key_cert_len, content_cert, content_cert_len, NULL); - if (SB_RET_SUCCESS != rc) + if (rc != SB_RET_SUCCESS) return CRYPTO_ERR_UNKNOWN; return CRYPTO_SUCCESS; diff --git a/plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h b/drivers/renesas/rza/auth/sblib/sblib_api_private.h similarity index 98% rename from plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h rename to drivers/renesas/rza/auth/sblib/sblib_api_private.h index 4e8a28759c..d79b373c06 100644 --- a/plat/renesas/rza/common/drivers/auth/sblib/sblib_api_private.h +++ b/drivers/renesas/rza/auth/sblib/sblib_api_private.h @@ -28,7 +28,7 @@ */ #define SB_RET_SAME_IMAGE_VERSION ((sb_ret_t)0x55005501UL) -/** A internal failure */ +/** An internal failure */ #define SB_RET_ERR_INTERNAL_FAIL ((sb_ret_t)0xAAAA0000UL) /** An invalid argument was entered */ @@ -73,7 +73,7 @@ /** Unsupported algorithm */ #define SB_RET_ERR_CRYPTO_UNSUPPORTED_ALGORITHM ((sb_ret_t)0xAAAA0202UL) -/** Other resorece is using CryptoIP. */ +/** Other resource is using CryptoIP. */ #define SB_RET_ERR_CRYPTO_RESOURCE_CONFLICT ((sb_ret_t)0xAAAA0203UL) /** Parameter error */ @@ -82,7 +82,7 @@ /** CRC mismatch */ #define SB_RET_ERR_CRC_MISMATCH ((sb_ret_t)0xAAAA0300UL) -/** Unsupported polynominal */ +/** Unsupported polynomial */ #define SB_RET_ERR_CRC_UNSUPPORTED_POLYNOMIAL ((sb_ret_t)0xAAAA0301UL) /** Image version lower than the current image version is installed */ diff --git a/plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c b/drivers/renesas/rza/auth/sblib/sblib_parser.c similarity index 97% rename from plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c rename to drivers/renesas/rza/auth/sblib/sblib_parser.c index ec39b1515b..c676a9aec1 100644 --- a/plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c +++ b/drivers/renesas/rza/auth/sblib/sblib_parser.c @@ -30,7 +30,7 @@ static void clear_temp_vars(void) do { \ zeromem(&x, sizeof(x)); \ clean_dcache_range((uintptr_t) &x, sizeof(x)); \ - } while (0); + } while (0) #undef ZERO_AND_CLEAN } @@ -61,7 +61,7 @@ static int check_integrity(void *img, unsigned int img_len) int rc; uint32_t magic; - if (SB_MANIFEST_LEN_MIN > img_len) + if (img_len < SB_MANIFEST_LEN_MIN) return IMG_PARSER_ERR_FORMAT; magic = *(uint32_t *)img; diff --git a/plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c b/drivers/renesas/rza/auth/tbbr/tbbr_cot.c similarity index 100% rename from plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c rename to drivers/renesas/rza/auth/tbbr/tbbr_cot.c diff --git a/plat/renesas/rza/common/drivers/cpg.c b/drivers/renesas/rza/cpg/cpg.c similarity index 93% rename from plat/renesas/rza/common/drivers/cpg.c rename to drivers/renesas/rza/cpg/cpg.c index eb3c0286c9..0bf2e98f59 100644 --- a/plat/renesas/rza/common/drivers/cpg.c +++ b/drivers/renesas/rza/cpg/cpg.c @@ -7,18 +7,19 @@ #include #include -#include -#include -#include #include +#include +#include #include #define CPG_OFF (0) -#define CPG_ON (1) +#define CPG_ON (1) #define CPG_T_CLK (0) #define CPG_T_RST (1) +#define CPG_RST_DDR_OPT_VALUE (0x00000000) + typedef struct { uintptr_t reg; uintptr_t mon; @@ -52,7 +53,7 @@ typedef struct st_cpg_spi_clk_table { uint8_t divider; } cpg_spi_clk_table; -static cpg_spi_clk_table cpg_xspi_table[] = { +static const cpg_spi_clk_table cpg_xspi_table[] = { { 533000000, 0, 0 }, /* 533.0MHz */ { 400000000, 1, 0 }, /* 400.0MHz */ { 266500000, 0, 1 }, /* 266.5MHz */ @@ -66,7 +67,7 @@ static cpg_spi_clk_table cpg_xspi_table[] = { }; #if USE_SDRAM -static CPG_PLL_SETDATA_146 cpg_pll4_setdata = { +static const CPG_PLL_SETDATA_146 cpg_pll4_setdata = { #if (DDR_PLL4 == 1600) { CPG_PLL4_CLK1, 0xFAE13203 }, { CPG_PLL4_CLK2, 0x00081000 }, @@ -80,7 +81,7 @@ static CPG_PLL_SETDATA_146 cpg_pll4_setdata = { }; #endif -static CPG_PLL_SETDATA_146 cpg_pll6_setdata = { +static const CPG_PLL_SETDATA_146 cpg_pll6_setdata = { { CPG_PLL6_CLK1, 0x00003e83 }, { CPG_PLL6_CLK2, 0x00082D02 }, { CPG_PLL6_STBY, 0x00010001 }, /* SSC OFF */ @@ -97,7 +98,7 @@ static const CPG_SETUP_DATA early_setup_tbl[] = { CPG_T_RST } }; -static CPG_SETUP_DATA cpg_clk_on_tbl[] = { +static const CPG_SETUP_DATA cpg_clk_on_tbl[] = { { /* CM33 */ (uintptr_t)CPG_CLKON_CM33, (uintptr_t)CPG_CLKMON_CM33, 0x00030000, CPG_T_CLK }, @@ -186,7 +187,7 @@ static CPG_SETUP_DATA cpg_clk_on_tbl[] = { CPG_T_CLK } }; -static CPG_SETUP_DATA cpg_reset_tbl[] = { +static const CPG_SETUP_DATA cpg_reset_tbl[] = { { /* CM33 */ (uintptr_t)CPG_RST_CM33, (uintptr_t)CPG_RSTMON_CM33, 0x00070000, CPG_T_RST }, @@ -275,12 +276,12 @@ static CPG_SETUP_DATA cpg_reset_tbl[] = { CPG_T_RST }, }; -static CPG_REG_SETTING cpg_static_select_tbl[] = { +static const CPG_REG_SETTING cpg_static_select_tbl[] = { { (uintptr_t)CPG_PL3A_DDIV, 0x01000100 }, { (uintptr_t)CPG_PL3_SSEL, 0x01000000 }, }; -static CPG_REG_SETTING cpg_dynamic_select_tbl[] = { +static const CPG_REG_SETTING cpg_dynamic_select_tbl[] = { { (uintptr_t)CPG_PL4_DSEL, 0x00010001 }, #if RZA3M { (uintptr_t)CPG_PL2SDHI_DSEL, 0x00010003 }, @@ -301,10 +302,11 @@ static CPG_REG_SETTING cpg_dynamic_select_tbl[] = { #define CPG_SEL_PLL5_3_ON_OFF (7) #define CPG_SEL_PLL5_4_ON_OFF (8) -static CPG_REG_SETTING cpg_sel_pll1_on_off[] = { { (uintptr_t)CPG_CLKON_CA55, - 0x00010001 } }; +static const CPG_REG_SETTING cpg_sel_pll1_on_off[] = { + { (uintptr_t)CPG_CLKON_CA55, 0x00010001 } +}; -static CPG_REG_SETTING cpg_sel_pll2_1_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll2_1_on_off[] = { { (uintptr_t)CPG_CLKON_ADC, 0x00010001 }, { (uintptr_t)CPG_CLKON_TSU, 0x00010001 }, #if RZA3M @@ -314,7 +316,7 @@ static CPG_REG_SETTING cpg_sel_pll2_1_on_off[] = { #endif }; -static CPG_REG_SETTING cpg_sel_pll2_2_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll2_2_on_off[] = { #if RZA3M { (uintptr_t)CPG_CLKON_SDHI, 0x000f0000 }, #else @@ -322,7 +324,7 @@ static CPG_REG_SETTING cpg_sel_pll2_2_on_off[] = { #endif }; -static CPG_REG_SETTING cpg_sel_pll3_1_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll3_1_on_off[] = { { (uintptr_t)CPG_CLKON_AXI_ACPU_BUS, 0x000F000F }, { (uintptr_t)CPG_CLKON_AXI_COM_BUS, 0x00030003 }, { (uintptr_t)CPG_CLKON_AXI_DEFAULT_SLV, 0x00010001 }, @@ -362,27 +364,29 @@ static CPG_REG_SETTING cpg_sel_pll3_1_on_off[] = { { (uintptr_t)CPG_CLKON_USB, 0x000F000F } }; -static CPG_REG_SETTING cpg_sel_pll3_2_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll3_2_on_off[] = { { (uintptr_t)CPG_CLKON_CRU, 0x00030003 }, { (uintptr_t)CPG_CLKON_SPI_MULTI, 0x00030003 }, { (uintptr_t)CPG_CLKON_AXI_MCPU_BUS, 0x02080208 }, }; -static CPG_REG_SETTING cpg_sel_pll3_3_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll3_3_on_off[] = { { (uintptr_t)CPG_CLKON_SPI_MULTI, 0x00030003 }, { (uintptr_t)CPG_CLKON_AXI_MCPU_BUS, 0x02080208 }, }; -static CPG_REG_SETTING cpg_sel_pll5_1_on_off[] = { +static const CPG_REG_SETTING cpg_sel_pll5_1_on_off[] = { { (uintptr_t)CPG_CLKON_CRU, 0x00100010 }, { (uintptr_t)CPG_CLKON_LCDC, 0x00020002 } }; -static CPG_REG_SETTING cpg_sel_pll5_3_on_off[] = { { (uintptr_t)CPG_CLKON_LCDC, - 0x00020002 } }; +static const CPG_REG_SETTING cpg_sel_pll5_3_on_off[] = { + { (uintptr_t)CPG_CLKON_LCDC, 0x00020002 } +}; -static CPG_REG_SETTING cpg_sel_pll5_4_on_off[] = { { (uintptr_t)CPG_CLKON_LCDC, - 0x00020002 } }; +static const CPG_REG_SETTING cpg_sel_pll5_4_on_off[] = { + { (uintptr_t)CPG_CLKON_LCDC, 0x00020002 } +}; static void cpg_ctrl_clkrst(CPG_SETUP_DATA const *array, uint32_t num) { @@ -407,7 +411,7 @@ static void cpg_selector_on_off(uint32_t sel, uint8_t flag) { uint32_t cnt; uint32_t tbl_num; - CPG_REG_SETTING *ptr; + CPG_REG_SETTING const *ptr; switch (sel) { case CPG_SEL_PLL1_ON_OFF: @@ -462,7 +466,7 @@ static void cpg_selector_on_off(uint32_t sel, uint8_t flag) } } -static void cpg_pll_start_146(CPG_PLL_SETDATA_146 *pdata) +static void cpg_pll_start_146(CPG_PLL_SETDATA_146 const *pdata) { mmio_write_32(pdata->clk1_dat.reg, pdata->clk1_dat.val); mmio_write_32(pdata->clk2_dat.reg, pdata->clk2_dat.val); @@ -513,7 +517,7 @@ static void cpg_pll_setup(void) #endif } -static void cpg_div_sel_setup(CPG_REG_SETTING *tbl, uint32_t size) +static void cpg_div_sel_setup(CPG_REG_SETTING const *tbl, uint32_t size) { int cnt; @@ -644,6 +648,7 @@ void cpg_early_setup(void) void cpg_wdtrst_sel_setup(void) { uint32_t reg; + reg = mmio_read_32(CPG_WDTRST_SEL); reg |= WDTRST_SEL_WDTRSTSEL0 | WDTRST_SEL_WDTRSTSEL0_WEN; @@ -677,7 +682,8 @@ void cpg_setup(void) static int cpg_search_spi_clk_table(int frequency) { - int tables = sizeof(cpg_xspi_table) / sizeof(cpg_xspi_table[0]); + int tables = ARRAY_SIZE(cpg_xspi_table); + for (int i = 0; i < tables; i++) { if (frequency >= cpg_xspi_table[i].frequency) { return i; @@ -688,7 +694,8 @@ static int cpg_search_spi_clk_table(int frequency) static int cpg_rsearch_spi_clk_table(uint8_t selector, uint8_t divider) { - int tables = sizeof(cpg_xspi_table) / sizeof(cpg_xspi_table[0]); + int tables = ARRAY_SIZE(cpg_xspi_table); + for (int i = 0; i < tables; i++) { if (selector == cpg_xspi_table[i].selector && divider == cpg_xspi_table[i].divider) { @@ -709,6 +716,7 @@ static void cpg_stop_xspi_clock(xspi_clock spi) int onoff_pos; uintptr_t clkon_ctrl; uintptr_t clkmon_ctrl; + switch (spi) { case XSPI_CLOCK_SPIM: onoff_pos = 9; @@ -737,6 +745,7 @@ static void cpg_start_xspi_clock(xspi_clock spi) int onoff_pos; uintptr_t clkon_ctrl; uintptr_t clkmon_ctrl; + switch (spi) { case XSPI_CLOCK_SPIM: onoff_pos = 9; @@ -781,6 +790,7 @@ int cpg_set_xspi_clock(xspi_clock spi, int frequency_hz) } int index = cpg_search_spi_clk_table(frequency_hz); + if (index == -1) ERROR("Not recognized frequency value %u passed to %s.", frequency_hz, __func__); @@ -792,6 +802,7 @@ int cpg_set_xspi_clock(xspi_clock spi, int frequency_hz) /* Changing static selector */ cpg_stop_xspi_clock(spi); uint32_t sel = cpg_xspi_table[index].selector << seldiv_pos; + sel |= 0x10000 << seldiv_pos; mmio_write_32(CPG_PL3_SSEL, sel); cpg_start_xspi_clock(spi); @@ -801,6 +812,7 @@ int cpg_set_xspi_clock(xspi_clock spi, int frequency_hz) /* Changing dynamic divider */ wait_until_32(CPG_CLKSTATUS, 1u << status_pos, 0); uint32_t div = cpg_xspi_table[index].divider << seldiv_pos; + div |= 0x10000 << seldiv_pos; mmio_write_32(CPG_PL3A_DDIV, div); wait_until_32(CPG_CLKSTATUS, 1u << status_pos, 0); @@ -832,6 +844,7 @@ int cpg_get_xspi_clock(xspi_clock spi) div = (uint8_t)((mmio_read_32(CPG_PL3A_DDIV) >> seldiv_pos) & 7); int frequency = cpg_rsearch_spi_clk_table(sel, div); + if (frequency == -1) ERROR("CPG register value error (sel=%d, div=%d) in %s", sel, div, __func__); diff --git a/plat/renesas/rza/common/drivers/ddr/ddr.c b/drivers/renesas/rza/ddr/ddr.c similarity index 93% rename from plat/renesas/rza/common/drivers/ddr/ddr.c rename to drivers/renesas/rza/ddr/ddr.c index 7eaae34836..4f33439922 100644 --- a/plat/renesas/rza/common/drivers/ddr/ddr.c +++ b/drivers/renesas/rza/ddr/ddr.c @@ -6,9 +6,9 @@ // include #include -#include -#include #include +#include +#include #include #define CEIL(a, div) (((a) + ((div) - 1)) / (div)) @@ -561,23 +561,18 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) vref_training_value = sweep_range; continue; } else { - current_vref = vref_mid_level_code - - vref_training_value; + current_vref = vref_mid_level_code - vref_training_value; } } else { - if ((vref_mid_level_code + vref_training_value - - sweep_range) > 126) { + if ((vref_mid_level_code + vref_training_value - sweep_range) > 126) { break; - } else { - current_vref = vref_mid_level_code + - vref_training_value - - sweep_range; } + + current_vref = vref_mid_level_code + vref_training_value - sweep_range; } for (i = 0; i < byte_lanes; i++) { write_phy_reg(DDRPHY_R29, 7 * i); - write_phy_reg(DDRPHY_R66, - (current_vref << 4) | 0x00000001); + write_phy_reg(DDRPHY_R66, (current_vref << 4) | 0x00000001); } // Step5.2 @@ -587,15 +582,13 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) // Step5.3 for (i = 0; i < byte_lanes; i++) { - if (((read_phy_reg(DDRPHY_R59) >> (14 + i)) & 0x1) == - 0x0) { + if (((read_phy_reg(DDRPHY_R59) >> (14 + i)) & 0x1) == 0x0) { RZA_PRINTF_INFO( "PHY side VREF training passed on lane %0d, current_vref = %0d\n", i, current_vref); write_phy_reg(DDRPHY_R29, i * 6); window_0 = read_phy_reg(DDRPHY_R69) & 0x3F; - window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & - 0x3F; + window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & 0x3F; window_diff = (window_0 > window_1) ? window_0 - window_1 : window_1 - window_0; @@ -603,21 +596,16 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) "window_0 = %0d, window_1 = %0d, window_diff = %0d\n", window_0, window_1, window_diff); if (window_diff < best_window_diff_so_far[i]) { - best_window_diff_so_far[i] = - window_diff; - all_best_vref_matches[i][0] = - current_vref; + best_window_diff_so_far[i] = window_diff; + all_best_vref_matches[i][0] = current_vref; num_best_vref_matches[i] = 1; RZA_PRINTF_INFO( "CURRENT BEST VREF PHY side :%d\n", current_vref); - } else if ((window_diff == - best_window_diff_so_far[i]) && - (num_best_vref_matches[i] < - MAX_BEST_VREF_SAVED)) { - all_best_vref_matches - [i][num_best_vref_matches[i]] = - current_vref; + } else if ((window_diff == best_window_diff_so_far[i]) && + (num_best_vref_matches[i] < MAX_BEST_VREF_SAVED)) { + all_best_vref_matches[i][num_best_vref_matches[i]] = + current_vref; num_best_vref_matches[i] += 1; } } else { @@ -634,14 +622,12 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) highest_best_vref_val = 0x0; lowest_best_vref_val = 0x7F; for (j = 0; j < num_best_vref_matches[i]; j++) { - highest_best_vref_val = - _MAX(all_best_vref_matches[i][j], - highest_best_vref_val); + highest_best_vref_val = _MAX(all_best_vref_matches[i][j], + highest_best_vref_val); lowest_best_vref_val = _MIN(all_best_vref_matches[i][j], lowest_best_vref_val); } - current_vref = (highest_best_vref_val + lowest_best_vref_val) >> - 1; + current_vref = (highest_best_vref_val + lowest_best_vref_val) >> 1; write_phy_reg(DDRPHY_R29, 7 * i); write_phy_reg(DDRPHY_R66, current_vref << 4); } @@ -693,14 +679,11 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) vref_training_value = sweep_range; continue; } else { - current_vref = vref_mid_level_code - - vref_training_value; + current_vref = vref_mid_level_code - vref_training_value; } } else { - if ((vref_mid_level_code + vref_training_value - - sweep_range) <= 73) { - current_vref = vref_mid_level_code + - vref_training_value - + if ((vref_mid_level_code + vref_training_value - sweep_range) <= 73) { + current_vref = vref_mid_level_code + vref_training_value - sweep_range; } else { break; @@ -722,8 +705,7 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) current_vref); write_phy_reg(DDRPHY_R29, i * 6); window_0 = read_phy_reg(DDRPHY_R69) & 0x3F; - window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & - 0x3F; + window_1 = (read_phy_reg(DDRPHY_R69) >> 8) & 0x3F; window_diff = (window_0 > window_1) ? window_0 - window_1 : window_1 - window_0; @@ -731,21 +713,16 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) "window_0 = %0d, window_1 = %0d, window_diff = %0d\n", window_0, window_1, window_diff); if (window_diff < best_window_diff_so_far[i]) { - best_window_diff_so_far[i] = - window_diff; - all_best_vref_matches[i][0] = - current_vref; + best_window_diff_so_far[i] = window_diff; + all_best_vref_matches[i][0] = current_vref; num_best_vref_matches[i] = 1; RZA_PRINTF_INFO( "CURRENT BEST VREF DRAM side :%d\n", current_vref); - } else if ((window_diff == - best_window_diff_so_far[i]) && - (num_best_vref_matches[i] < - MAX_BEST_VREF_SAVED)) { - all_best_vref_matches - [i][num_best_vref_matches[i]] = - current_vref; + } else if ((window_diff == best_window_diff_so_far[i]) && + (num_best_vref_matches[i] < MAX_BEST_VREF_SAVED)) { + all_best_vref_matches[i][num_best_vref_matches[i]] = + current_vref; num_best_vref_matches[i] += 1; } } else { @@ -762,9 +739,8 @@ static void exec_trainingVREF(uint32_t sl_lanes, uint32_t byte_lanes) lowest_best_vref_val = 0x7F; for (i = 0; i < byte_lanes; i++) { for (j = 0; j < num_best_vref_matches[i]; j++) { - highest_best_vref_val = - _MAX(all_best_vref_matches[i][j], - highest_best_vref_val); + highest_best_vref_val = _MAX(all_best_vref_matches[i][j], + highest_best_vref_val); lowest_best_vref_val = _MIN(all_best_vref_matches[i][j], lowest_best_vref_val); } @@ -1062,8 +1038,7 @@ static void program_phy2(void) // Step3 rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x04000000); rmw_phy_reg(DDRPHY_R27, 0xFC0000FF, - _MIN(1000000000000 / (dram_clk_period * 256), 0x3FFFF) - << 8); + _MIN(1000000000000 / (dram_clk_period * 256), 0x3FFFF) << 8); rmw_phy_reg(DDRPHY_R27, 0xFBFFFFFF, 0x00000000); } diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c b/drivers/renesas/rza/ddr/param_swizzle_T1.c similarity index 100% rename from plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c rename to drivers/renesas/rza/ddr/param_swizzle_T1.c diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c b/drivers/renesas/rza/ddr/param_swizzle_T3bcud2.c similarity index 96% rename from plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c rename to drivers/renesas/rza/ddr/param_swizzle_T3bcud2.c index b7a57fd36b..60e55454c5 100644 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c +++ b/drivers/renesas/rza/ddr/param_swizzle_T3bcud2.c @@ -6,7 +6,7 @@ #include -#include +#include const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, 0x00000000 }; diff --git a/plat/renesas/rza/common/drivers/pfc.c b/drivers/renesas/rza/pfc/pfc.c similarity index 97% rename from plat/renesas/rza/common/drivers/pfc.c rename to drivers/renesas/rza/pfc/pfc.c index 8f139ce402..3b2bc272d0 100644 --- a/plat/renesas/rza/common/drivers/pfc.c +++ b/drivers/renesas/rza/pfc/pfc.c @@ -8,10 +8,10 @@ #include #include +#include #include -#include -static PFC_REGS pfc_mux_reg_tbl[] = { +static const PFC_REGS pfc_mux_reg_tbl[] = { #if RZA3M /* P22(sd0) */ { @@ -75,7 +75,7 @@ static PFC_REGS pfc_mux_reg_tbl[] = { #endif /* RZA3M */ }; -static PFC_REGS pfc_qspi_reg_tbl[] = { +static const PFC_REGS pfc_qspi_reg_tbl[] = { #if RZA3M /* QSPI0 */ { diff --git a/plat/renesas/rza/common/drivers/xspi/octa.c b/drivers/renesas/rza/xspi/octa.c similarity index 98% rename from plat/renesas/rza/common/drivers/xspi/octa.c rename to drivers/renesas/rza/xspi/octa.c index bac7d51bd6..6519c0c7fb 100644 --- a/plat/renesas/rza/common/drivers/xspi/octa.c +++ b/drivers/renesas/rza/xspi/octa.c @@ -10,14 +10,14 @@ #include #include -#include -#include #include +#include +#include +#include +#include #include #include #include -#include -#include #include /* Defaults */ @@ -155,6 +155,7 @@ static void select_octa(octa_ctrl_t *myctrl, xspi_cfg_t const *const cfg) if (RZ_XSPI_EXCLUSIVE_SELECTOR) { /* Check if SPIM selected */ uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + if ((ipcont_spi_octa & IPCONT_SEL_SPI_OCTA) == IPCONT_SEL_SPI_OCTA_SPI) { /* Reset SPIM controller */ @@ -180,6 +181,7 @@ static void select_octa(octa_ctrl_t *myctrl, xspi_cfg_t const *const cfg) * Note: This is required if the boot mode is neither 3 nor 4. */ uint8_t voltage = DEFAULT_VOLTAGE_IS_1800MV; + mmio_write_8(PFC_QSPI, voltage); mmio_read_8(PFC_QSPI); } @@ -193,6 +195,7 @@ static void select_octa(octa_ctrl_t *myctrl, xspi_cfg_t const *const cfg) if (RZ_XSPI_EXCLUSIVE_SELECTOR) { /* Select OCTA for SPI controller */ uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + ipcont_spi_octa &= ~IPCONT_SEL_SPI_OCTA; ipcont_spi_octa |= IPCONT_SEL_SPI_OCTA_OCTA << IPCONT_SEL_SPI_OCTA_POS; @@ -227,13 +230,13 @@ static void octa_init(octa_ctrl_t *myctrl) static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) { - int result = -1; assert(ctrl); assert(cfg); assert(cfg->channel == 0 || cfg->channel == 1); + assert(cfg->base); + int result = -1; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; octa_ext_t *ext = (octa_ext_t *)cfg->extend; - assert(cfg->base); if (myctrl->opened) return -1; @@ -253,6 +256,7 @@ static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) /* Initialize MMAP base and initial size */ size_t mmap_size; + if (myctrl->channel) { myctrl->mmap_base = ch1_mmap_base; mmap_size = ch1_mmap_size; @@ -271,6 +275,7 @@ static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) /* Set device type and calibrate address */ uint8_t device_type; + if (myctrl->channel) { device_type = OCTA_DSR_TYP_RAM; /* Override calibration base if specified */ @@ -299,6 +304,7 @@ static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) /* Sets DVnSZ only first per channel */ if (!initialised[myctrl->channel]) { uint32_t dsr; + if (ext) { dsr = ext->device_size; } else { @@ -307,6 +313,7 @@ static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) if (myctrl->channel) { uint32_t aer; + if (dsr <= 8 * 1024 * 1024) aer = OCTA_AER_LE64MB; else if (dsr <= 16 * 1024 * 1024) @@ -334,9 +341,10 @@ static int octa_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) static int octa_close(xspi_ctrl_t *const ctrl) { - int result = -1; assert(ctrl); + int result = -1; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + if (myctrl->opened) { myctrl->opened = false; result = 0; @@ -396,8 +404,8 @@ static void octa_set_auto_calibration(octa_ctrl_t *myctrl) static int octa_post_init(xspi_ctrl_t *const ctrl) { - int result = 0; assert(ctrl); + int result = 0; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; if (!post_init_done) { @@ -440,6 +448,7 @@ static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, assert(!!op); int res; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + res = octa_test_ddr(op); if (!!res) return res; @@ -454,10 +463,11 @@ static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, uint32_t dcstr; uint32_t dcsr_clear, dcsr_set; - dcsr_clear = dcsr_set = 0; uint32_t cdsr_clear, cdsr_set, save_cdsr; - cdsr_clear = cdsr_set = 0; uint32_t mdtr_clear, mdtr_set, save_mdtr; + + dcsr_clear = dcsr_set = 0; + cdsr_clear = cdsr_set = 0; mdtr_clear = mdtr_set = 0; /* change write flag if no transfer phase required */ @@ -467,6 +477,7 @@ static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, /* select and check memory type */ int transfer_type; int enable_counter; + switch (op->form) { case SPI_FORM_8_8_8: if (op->op_is_ddr) { @@ -599,6 +610,7 @@ static int octa_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, uint32_t tmp = mmio_read_32(myctrl->reg_base + OCTA_CRR); uint8_t *u8p = (uint8_t *)op->transfer_buffer; + u8p[0] = tmp & 0xff; u8p[1] = tmp & 0xff00 >> 8; u8p[2] = tmp & 0xff0000 >> 16; @@ -625,14 +637,16 @@ static void octa_configure_xip_ch1(octa_ctrl_t *const myctrl, xspi_op_t const *const wop) { uint32_t mdlr_clear, mdlr_set; - mdlr_clear = mdlr_set = 0; uint32_t mrwcr_clear, mrwcr_set; - mrwcr_clear = mrwcr_set = 0; uint32_t mrwcsr_clear, mrwcsr_set; + + mdlr_clear = mdlr_set = 0; + mrwcr_clear = mrwcr_set = 0; mrwcsr_clear = mrwcsr_set = 0; if (rop) { uint32_t drcstr_clear, drcstr_set; + drcstr_clear = drcstr_set = 0; drcstr_clear |= OCTA_DRCSTR_DVRDLO1 | OCTA_DRCSTR_DVRDHI1 | OCTA_DRCSTR_DVRDCMD1; @@ -656,6 +670,7 @@ static void octa_configure_xip_ch1(octa_ctrl_t *const myctrl, } if (wop) { uint32_t dwcstr_clear, dwcstr_set; + dwcstr_clear = dwcstr_set = 0; dwcstr_clear |= OCTA_DWCSTR_DVWLO1 | OCTA_DWCSTR_DVWHI1 | OCTA_DWCSTR_DVWCMD1; @@ -689,14 +704,16 @@ static void octa_configure_xip_ch0(octa_ctrl_t *const myctrl, xspi_op_t const *const wop) { uint32_t mdlr_clear, mdlr_set; - mdlr_clear = mdlr_set = 0; uint32_t mrwcr_clear, mrwcr_set; - mrwcr_clear = mrwcr_set = 0; uint32_t mrwcsr_clear, mrwcsr_set; + + mdlr_clear = mdlr_set = 0; + mrwcr_clear = mrwcr_set = 0; mrwcsr_clear = mrwcsr_set = 0; if (rop) { uint32_t drcstr_clear, drcstr_set; + drcstr_clear = drcstr_set = 0; drcstr_clear |= OCTA_DRCSTR_DVRDLO0 | OCTA_DRCSTR_DVRDHI0 | OCTA_DRCSTR_DVRDCMD0; @@ -720,6 +737,7 @@ static void octa_configure_xip_ch0(octa_ctrl_t *const myctrl, } if (wop) { uint32_t dwcstr_clear, dwcstr_set; + dwcstr_clear = dwcstr_set = 0; dwcstr_clear |= OCTA_DWCSTR_DVWLO0 | OCTA_DWCSTR_DVWHI0 | OCTA_DWCSTR_DVWCMD0; @@ -758,6 +776,7 @@ static int octa_configure_xip(xspi_ctrl_t *const ctrl, return -1; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; xspi_op_t const *op = NULL; + if (wop) { op = wop; octa_test_ddr(wop); @@ -776,6 +795,7 @@ static int octa_configure_xip(xspi_ctrl_t *const ctrl, } uint32_t cdsr_clear, cdsr_set, mdtr_clear, mdtr_set; + cdsr_clear = cdsr_set = mdtr_clear = mdtr_set = 0; int transfer_type; @@ -941,6 +961,7 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) uint32_t mdtr = mmio_read_32(myctrl->reg_base + OCTA_MDTR); uint32_t mdtr_save = mdtr; int mdtr_pos; + if (myctrl->channel) { mdtr &= ~OCTA_MDTR_DV1DEL; mdtr_pos = OCTA_MDTR_DV1DEL_POS; @@ -951,6 +972,7 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) /* detect ok/ng area */ uintptr_t offset = (uintptr_t)myctrl->calibration_base; + offset += myctrl->mmap_base; p_preamble = (uint32_t *)offset; for (index = 0; index < DELAY_LEVELS; index++) { @@ -971,7 +993,7 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) } /* Store the judgement result in the table */ - if (0 == judge_result) { + if (judge_result == 0) { is_ok[index] = true; } else { /* Continuous OK region */ is_ok[index] = false; @@ -980,7 +1002,7 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) /* Search for the start index of the OK area */ index_start = get_ok_area_start(is_ok); - if ((-1) == index_start) { + if (index_start == (-1)) { /* restore old value */ mmio_write_32(myctrl->reg_base + OCTA_MDTR, mdtr_save); mmio_read_32(myctrl->reg_base + OCTA_MDTR); @@ -990,7 +1012,7 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) /* Find the number of OK areas */ ok_cnt = get_ok_area_count(is_ok, index_start); - if (3 < ok_cnt) { + if (ok_cnt > 3) { /* Set DQS delay value */ uint32_t delay = (index_start + (ok_cnt >> 1)) * (256 / DELAY_LEVELS); @@ -998,18 +1020,19 @@ static int octa_manual_calibration_common(octa_ctrl_t *myctrl) mdtr | delay << mdtr_pos); mmio_read_32(myctrl->reg_base + OCTA_MDTR); return 0; - } else { - /* restore old value */ - mmio_write_32(myctrl->reg_base + OCTA_MDTR, mdtr_save); - mmio_read_32(myctrl->reg_base + OCTA_MDTR); - return -1; } + + /* restore old value */ + mmio_write_32(myctrl->reg_base + OCTA_MDTR, mdtr_save); + mmio_read_32(myctrl->reg_base + OCTA_MDTR); + return -1; } static void octa_write_preamble_pattern(octa_ctrl_t *myctrl) { const uint32_t *pattern = &preamble[0]; uintptr_t wp = myctrl->mmap_base; + wp += (uintptr_t)myctrl->calibration_base; volatile uint32_t *w_pattern = (uint32_t *)wp; *w_pattern++ = *pattern++; @@ -1080,6 +1103,7 @@ static int octa_run_manual_calibration(xspi_ctrl_t *const ctrl) assert(ctrl); int result; octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + if (myctrl->channel) { /* Channel 1 */ result = octa_manual_calibration_ch1(myctrl); @@ -1159,9 +1183,12 @@ static int octa_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz) freq_request = freq[1]; int result = cpg_set_xspi_clock(XSPI_CLOCK_OCTA, freq_request * 4); + if (result != 0) return result; + int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_OCTA); + if (actual_freq == -1) return -1; spi_clock = actual_freq / 4; @@ -1173,6 +1200,7 @@ static int octa_clean_mmap(xspi_ctrl_t *const ctrl) { assert(ctrl); octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + clean_dcache_range(myctrl->mmap_base, myctrl->mmap_size); return 0; @@ -1182,6 +1210,7 @@ static int octa_inv_mmap(xspi_ctrl_t *const ctrl) { assert(ctrl); octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + inv_dcache_range(myctrl->mmap_base, myctrl->mmap_size); return 0; @@ -1191,6 +1220,7 @@ static uintptr_t octa_get_mmap_base(xspi_ctrl_t *const ctrl) { assert(ctrl); octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + return myctrl->mmap_base; } @@ -1198,6 +1228,7 @@ static size_t octa_get_mmap_size(xspi_ctrl_t *const ctrl) { assert(ctrl); octa_ctrl_t *myctrl = (octa_ctrl_t *)ctrl; + return myctrl->mmap_size; } @@ -1205,6 +1236,7 @@ static uint32_t octa_get_features(xspi_ctrl_t *const ctrl) { (void)ctrl; uint32_t features = 0; + features |= XSPI_FEATURE_FORM888; features |= XSPI_FEATURE_DDR; features |= XSPI_FEATURE_DDROP; diff --git a/plat/renesas/rza/common/drivers/xspi/spim.c b/drivers/renesas/rza/xspi/spim.c similarity index 99% rename from plat/renesas/rza/common/drivers/xspi/spim.c rename to drivers/renesas/rza/xspi/spim.c index 1884e5864e..fa0cb38559 100644 --- a/plat/renesas/rza/common/drivers/xspi/spim.c +++ b/drivers/renesas/rza/xspi/spim.c @@ -10,16 +10,16 @@ #include #include -#include -#include #include +#include +#include +#include +#include #include #include #include -#include #include #include -#include #include /* Defaults */ @@ -84,6 +84,7 @@ static void select_spim(spim_ctrl_t *myctrl, xspi_cfg_t const *const cfg) if (RZ_XSPI_EXCLUSIVE_SELECTOR) { /* Check if OCTA selected */ uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + if ((ipcont_spi_octa & IPCONT_SEL_SPI_OCTA) == IPCONT_SEL_SPI_OCTA_OCTA) { /* Reset the OCTA controller and the devices connected, @@ -110,8 +111,10 @@ static void select_spim(spim_ctrl_t *myctrl, xspi_cfg_t const *const cfg) * Note: This is required if the boot mode is neither 3 nor 4. */ uint8_t voltage = DEFAULT_VOLTAGE_IS_1800MV; + if (cfg->extend) { const spim_ext_t *ext = (const spim_ext_t *)cfg->extend; + if (ext->voltage_is_3300mv) voltage = 0; } @@ -128,6 +131,7 @@ static void select_spim(spim_ctrl_t *myctrl, xspi_cfg_t const *const cfg) if (RZ_XSPI_EXCLUSIVE_SELECTOR) { /* Select SPIM for SPI controller */ uint32_t ipcont_spi_octa = mmio_read_32(SYS_IPCONT); + ipcont_spi_octa &= ~IPCONT_SEL_SPI_OCTA; ipcont_spi_octa |= IPCONT_SEL_SPI_OCTA_SPI << IPCONT_SEL_SPI_OCTA_POS; @@ -238,9 +242,9 @@ static void spim_ip_init(spim_ctrl_t *myctrl) static int spim_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) { - int result = -1; assert(ctrl); assert(cfg); + int result = -1; spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; if (myctrl->opened) @@ -266,9 +270,10 @@ static int spim_open(xspi_ctrl_t *ctrl, xspi_cfg_t const *const cfg) static int spim_close(xspi_ctrl_t *const ctrl) { - int result = -1; assert(ctrl); + int result = -1; spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + if (myctrl->opened) { myctrl->opened = false; result = 0; @@ -343,8 +348,9 @@ static void spim_set_idlelevel(spim_ctrl_t *const myctrl, static int spim_reduce_frequency(spim_ctrl_t *const ctrl) { - int old_freq = spi_clock; assert(ctrl); + int old_freq = spi_clock; + if (spi_clock > RZ_SPIM_SDR_FREQ_LIMIT) { spi_clock = RZ_SPIM_SDR_FREQ_LIMIT; } else { @@ -353,11 +359,13 @@ static int spim_reduce_frequency(spim_ctrl_t *const ctrl) } int result = cpg_set_xspi_clock(XSPI_CLOCK_SPIM, spi_clock * 4 + 1); + if (result != 0) { return result; } int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_SPIM); + if (actual_freq == -1) return -1; spi_clock = actual_freq / 4; @@ -384,6 +392,7 @@ static int spim_stop_xip_internal(spim_ctrl_t *myctrl) { int result = 0; uint32_t drcr = mmio_read_32(myctrl->reg_base + SPIM_DRCR); + if ((drcr & (SPIM_DRCR_RBE | SPIM_DRCR_SSLE)) == (SPIM_DRCR_RBE | SPIM_DRCR_SSLE)) { /* Set SSLN and wait for sslf */ @@ -700,12 +709,14 @@ static int spim_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, } /* Dummy cycle */ + if (op->dummy_cycles == 1 || op->dummy_cycles > 20) { + ERROR("Unsupported dummy cycle count %d\n", op->dummy_cycles); + return -1; + } + if (op->dummy_cycles == 0) { smenr_set |= 0u << SPIM_SMENR_DME_POS; smdmcr_set |= 0u << SPIM_SMDMCR_DMCYC_POS; - } else if (op->dummy_cycles == 1 || op->dummy_cycles > 20) { - ERROR("Unsupported dummy cycle count %d\n", op->dummy_cycles); - return -1; } else { smenr_set |= 1u << SPIM_SMENR_DME_POS; smdmcr_set |= (op->dummy_cycles - 1) << SPIM_SMDMCR_DMCYC_POS; @@ -714,11 +725,13 @@ static int spim_exec_op(xspi_ctrl_t *const ctrl, xspi_op_t const *const op, /* PHYOFFSET1 setting */ uint32_t phyoffset1_msk = SPIM_PHYOFFSET1_DDRTMG; uint32_t phyoffset1_set; + phyoffset1_set = SPIM_PHYOFFSET1_SDR << SPIM_PHYOFFSET1_DDRTMG_POS; /* PHYCNT setting */ uint32_t phycnt_msk = SPIM_PHYCNT_PHYMEM; uint32_t phycnt_set; + phycnt_set = SPIM_PHYCNT_SDR << SPIM_PHYCNT_PHYMEM_POS; /* SLCH (SSL assert to CLK high) */ @@ -1072,13 +1085,15 @@ static int spim_configure_xip(xspi_ctrl_t *const ctrl, } /* Dummy cycle */ - if (rop->dummy_cycles == 0) { - drenr |= 0u << SPIM_DRENR_DME_POS; - drdmcr |= 0u << SPIM_DRDMCR_DMCYC_POS; - } else if (rop->dummy_cycles == 1 || rop->dummy_cycles > 20) { + if (rop->dummy_cycles == 1 || rop->dummy_cycles > 20) { ERROR("Unsupported dummy cycle count %d for rop\n", rop->dummy_cycles); return -1; + } + + if (rop->dummy_cycles == 0) { + drenr |= 0u << SPIM_DRENR_DME_POS; + drdmcr |= 0u << SPIM_DRDMCR_DMCYC_POS; } else { drenr |= 1u << SPIM_DRENR_DME_POS; drdmcr |= (rop->dummy_cycles - 1) << SPIM_DRDMCR_DMCYC_POS; @@ -1142,6 +1157,7 @@ static int spim_start_xip(xspi_ctrl_t *const ctrl) { assert(ctrl); spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + mmio_setbits_32(myctrl->reg_base + SPIM_DRCR, SPIM_DRCR_RCF); spim_start_xip_internal(myctrl); spim_inv_mmap(ctrl); @@ -1153,6 +1169,7 @@ static int spim_stop_xip(xspi_ctrl_t *const ctrl) { assert(ctrl); spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return spim_stop_xip_internal(myctrl); } @@ -1174,11 +1191,13 @@ static int spim_disable_auto_calibration(xspi_ctrl_t *const ctrl) static int spim_set_frequency(xspi_ctrl_t *const ctrl, int frequency_hz) { assert(ctrl); - int result = cpg_set_xspi_clock(XSPI_CLOCK_SPIM, frequency_hz * 4 + 1); + if (result != 0) return result; + int actual_freq = cpg_get_xspi_clock(XSPI_CLOCK_SPIM); + if (actual_freq == -1) return -1; actual_freq = actual_freq / 4; @@ -1200,6 +1219,7 @@ static int spim_inv_mmap(xspi_ctrl_t *const ctrl) { assert(ctrl); spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + inv_dcache_range(myctrl->mmap_base, myctrl->mmap_size); return 0; @@ -1209,6 +1229,7 @@ static uintptr_t spim_get_mmap_base(xspi_ctrl_t *const ctrl) { assert(ctrl); spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return myctrl->mmap_base; } @@ -1216,6 +1237,7 @@ static size_t spim_get_mmap_size(xspi_ctrl_t *const ctrl) { assert(ctrl); spim_ctrl_t *myctrl = (spim_ctrl_t *)ctrl; + return myctrl->mmap_size; } @@ -1223,6 +1245,7 @@ static uint32_t spim_get_features(xspi_ctrl_t *const ctrl) { (void)ctrl; uint32_t features = 0; + features |= XSPI_FEATURE_FORM114; features |= XSPI_FEATURE_FORM144; features |= XSPI_FEATURE_XIP_READ; diff --git a/plat/renesas/rza/soc/a3m/drivers/xspi.c b/drivers/renesas/rza/xspi/xspi.c similarity index 91% rename from plat/renesas/rza/soc/a3m/drivers/xspi.c rename to drivers/renesas/rza/xspi/xspi.c index 2ee8da56be..ef70d6f1ef 100644 --- a/plat/renesas/rza/soc/a3m/drivers/xspi.c +++ b/drivers/renesas/rza/xspi/xspi.c @@ -1,3 +1,9 @@ +/* + * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + #include #include @@ -8,6 +14,7 @@ static int sub_init_xip(const xspidevice_instance_t *inst) { int result; + result = inst->api->open(inst->ctrl, inst->cfg); if (!result) { result = inst->api->enter_xip(inst->ctrl); @@ -19,6 +26,7 @@ static int sub_init_xip(const xspidevice_instance_t *inst) static int sub_post_init_xip(const xspi_instance_t *xspi) { int result; + result = xspi->api->open(xspi->ctrl, xspi->cfg); if (!result) { xspi->api->enable_auto_calibration(xspi->ctrl); @@ -59,6 +67,7 @@ int rz_xspi_read(void *to, uint64_t offset, size_t length) { int result; const xspidevice_instance_t *inst = xspidevices[0]; + if (!inst) return -1; diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c similarity index 98% rename from plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c rename to drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c index 615a9fef97..3a253c72df 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c +++ b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw.c @@ -222,22 +222,25 @@ static const xspi_op_t op_erase_64k_dopi = { .form = SPI_FORM_8_8_8, static int flash_write_enable_spi(octaflash_mx66uw_ctrl_t *myctrl) { const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable_spi, false); } static int flash_write_enable_dopi(octaflash_mx66uw_ctrl_t *myctrl) { const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable_dopi, false); } -static int flash_read_status_register_spi(octaflash_mx66uw_ctrl_t *myctrl) +static int __unused flash_read_status_register_spi(octaflash_mx66uw_ctrl_t *myctrl) { int result; const xspi_instance_t *xspi = myctrl->xspi; uint8_t status; xspi_op_t op = op_read_status_spi; + op.transfer_buffer = &status; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result) @@ -251,6 +254,7 @@ static int flash_read_status_register_dopi(octaflash_mx66uw_ctrl_t *myctrl) const xspi_instance_t *xspi = myctrl->xspi; uint8_t status; xspi_op_t op = op_read_status_dopi; + op.transfer_buffer = &status; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result) @@ -263,6 +267,7 @@ static int flash_write_config_register2_spi(octaflash_mx66uw_ctrl_t *myctrl, { const xspi_instance_t *xspi = myctrl->xspi; xspi_op_t op = op_write_config2_spi; + op.address = add; op.transfer_buffer = &data; return xspi->api->exec_op(xspi->ctrl, &op, true); @@ -284,9 +289,6 @@ static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) result = xspi->api->open(xspi->ctrl, xspi->cfg); if (result == 0) { xspi->api->set_frequency(xspi->ctrl, spi_frequency); - if (false) - flash_read_status_register_spi( - myctrl); /* Avoiding build error */ udelay(SPI_POST_RESET_WAIT); flash_write_enable_spi(myctrl); flash_write_config_register2_spi(myctrl, 0x00000300, 5); @@ -310,6 +312,7 @@ static int flash_close(xspidevice_ctrl_t *ctrl) int result = -1; octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { result = xspi->api->close(xspi->ctrl); myctrl->opened = false; @@ -330,8 +333,8 @@ static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, static int flash_enter_xip(xspidevice_ctrl_t *ctrl) { - int result = -1; assert(ctrl); + int result = -1; octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; @@ -369,8 +372,8 @@ static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, assert(ctrl); octaflash_mx66uw_ctrl_t *myctrl = (octaflash_mx66uw_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; - uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); return 0; @@ -380,6 +383,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, size_t address, size_t length) { int result = 0; + if (RZ_XSPIFLASH_DISABLE_WRITE) { result = -1; } else { @@ -399,6 +403,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, while (length && !result) { /* Wait for previous command finished */ enum xspidevice_write_status ws; + do { ws = flash_get_write_status(ctrl); } while (ws == WRITE_STATUS_IN_PROGRESS); @@ -442,6 +447,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, static int flash_erase_4k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) { xspi_op_t op = op_erase_4k_dopi; + op.address = address; return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); } @@ -449,6 +455,7 @@ static int flash_erase_4k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) static int flash_erase_64k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) { xspi_op_t op = op_erase_64k_dopi; + op.address = address; return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); } @@ -456,6 +463,7 @@ static int flash_erase_64k(octaflash_mx66uw_ctrl_t *myctrl, size_t address) static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) { int result; + if (RZ_XSPIFLASH_DISABLE_WRITE) { result = -1; } else { @@ -469,6 +477,7 @@ static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) do { /* Wait for previous command finished */ enum xspidevice_write_status ws; + do { ws = flash_get_write_status(ctrl); } while (ws == WRITE_STATUS_IN_PROGRESS); diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h similarity index 97% rename from plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h rename to drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h index 69f7d2870f..dd654237d8 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h +++ b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/octaflash_mx66uw_api.h @@ -7,7 +7,6 @@ #ifndef _OCTAFLASH_MX66UW_API_H_ #define _OCTAFLASH_MX66UW_API_H_ #include -#include #include "xspidevice_api.h" diff --git a/drivers/renesas/rza/xspidevice/octaflash_mx66uw/rz_xspidevice.mk b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/rz_xspidevice.mk new file mode 100644 index 0000000000..39d6137388 --- /dev/null +++ b/drivers/renesas/rza/xspidevice/octaflash_mx66uw/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := octaflash_mx66uw +PLAT_INCLUDES += -Idrivers/renesas/rza/xspidevice/octaflash_mx66uw +RZ_XSPI_HEADERS := ${RZ_XSPI_HEADERS} ${_XSPI_DEVICE}_api.h +RZ_XSPI_SOURCES := ${RZ_XSPI_SOURCES} \ + drivers/renesas/rza/xspidevice/${_XSPI_DEVICE}/${_XSPI_DEVICE}.c diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c b/drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx.c similarity index 99% rename from plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c rename to drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx.c index e38fcbe904..baa2506607 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx.c +++ b/drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx.c @@ -117,6 +117,7 @@ static int octaram_write_mode_register(octaram_apsxx_ctrl_t *myctrl, { const xspi_instance_t *xspi = myctrl->xspi; xspi_op_t op = op_write_mode; + op.transfer_buffer = &data; return xspi->api->exec_op(xspi->ctrl, &op, true); } @@ -158,6 +159,7 @@ static int octaram_close(xspidevice_ctrl_t *ctrl) int result = -1; octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { result = xspi->api->close(xspi->ctrl); myctrl->opened = false; @@ -178,8 +180,8 @@ static int octaram_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, static int octaram_enter_xip(xspidevice_ctrl_t *ctrl) { - int result = -1; assert(ctrl); + int result = -1; octaram_apsxx_ctrl_t *myctrl = (octaram_apsxx_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h b/drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx_api.h similarity index 96% rename from plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h rename to drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx_api.h index 81e9a67fa5..3cfa2d593b 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/octaram_apsxx_api.h +++ b/drivers/renesas/rza/xspidevice/octaram_apsxx/octaram_apsxx_api.h @@ -7,7 +7,6 @@ #ifndef _OCTARAM_APSXX_API_H_ #define _OCTARAM_APSXX_API_H_ #include -#include #include "xspidevice_api.h" diff --git a/drivers/renesas/rza/xspidevice/octaram_apsxx/rz_xspidevice.mk b/drivers/renesas/rza/xspidevice/octaram_apsxx/rz_xspidevice.mk new file mode 100644 index 0000000000..e23ce4b1f8 --- /dev/null +++ b/drivers/renesas/rza/xspidevice/octaram_apsxx/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := octaram_apsxx +PLAT_INCLUDES += -Idrivers/renesas/rza/xspidevice/octaram_apsxx +RZ_XSPI_HEADERS := ${RZ_XSPI_HEADERS} ${_XSPI_DEVICE}_api.h +RZ_XSPI_SOURCES := ${RZ_XSPI_SOURCES} \ + drivers/renesas/rza/xspidevice/${_XSPI_DEVICE}/${_XSPI_DEVICE}.c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c b/drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25.c similarity index 99% rename from plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c rename to drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25.c index c794e6c91e..5c2e68acc5 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25.c +++ b/drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25.c @@ -254,6 +254,7 @@ static const xspi_op_t op_erase_64k = { static int flash_write_enable(qspiflash_at25_ctrl_t *myctrl) { const xspi_instance_t *xspi = myctrl->xspi; + return xspi->api->exec_op(xspi->ctrl, &op_write_enable, false); } @@ -264,6 +265,7 @@ static int flash_read_status_register1(qspiflash_at25_ctrl_t *myctrl) uint8_t status; xspi_op_t op = op_read_status1; + op.transfer_buffer = &status; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result) @@ -278,6 +280,7 @@ static int flash_read_status_register2(qspiflash_at25_ctrl_t *myctrl) uint8_t status; xspi_op_t op = op_read_status2; + op.transfer_buffer = &status; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result) @@ -290,6 +293,7 @@ static int flash_write_status_register2(qspiflash_at25_ctrl_t *myctrl, { const xspi_instance_t *xspi = myctrl->xspi; xspi_op_t op = op_write_status2; + op.transfer_buffer = &status; return xspi->api->exec_op(xspi->ctrl, &op, true); } @@ -297,6 +301,7 @@ static int flash_write_status_register2(qspiflash_at25_ctrl_t *myctrl, static int flash_set_qe(qspiflash_at25_ctrl_t *myctrl) { int result; + result = flash_read_status_register2(myctrl); if (result < 0) return result; @@ -352,6 +357,7 @@ static int flash_close(xspidevice_ctrl_t *ctrl) int result = -1; qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { result = xspi->api->close(xspi->ctrl); myctrl->opened = false; @@ -371,8 +377,8 @@ static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, static int flash_enter_xip(xspidevice_ctrl_t *ctrl) { - int result = -1; assert(ctrl); + int result = -1; qspiflash_at25_ctrl_t *myctrl = (qspiflash_at25_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; @@ -413,6 +419,7 @@ static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, const xspi_instance_t *xspi = myctrl->xspi; uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); return 0; @@ -422,6 +429,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, size_t address, size_t length) { int result = 0; + if (RZ_XSPIFLASH_DISABLE_WRITE) { result = -1; } else { @@ -437,6 +445,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, while (length && !result) { /* Wait for previous command finished */ enum xspidevice_write_status ws; + do { ws = flash_get_write_status(ctrl); } while (ws == WRITE_STATUS_IN_PROGRESS); @@ -477,6 +486,7 @@ static int flash_write(xspidevice_ctrl_t *ctrl, void const *buffer, static int flash_erase_4k(qspiflash_at25_ctrl_t *myctrl, size_t address) { xspi_op_t op = op_erase_4k; + op.address = address; return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); } @@ -484,6 +494,7 @@ static int flash_erase_4k(qspiflash_at25_ctrl_t *myctrl, size_t address) static int flash_erase_32k(qspiflash_at25_ctrl_t *myctrl, size_t address) { xspi_op_t op = op_erase_32k; + op.address = address; return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); } @@ -491,6 +502,7 @@ static int flash_erase_32k(qspiflash_at25_ctrl_t *myctrl, size_t address) static int flash_erase_64k(qspiflash_at25_ctrl_t *myctrl, size_t address) { xspi_op_t op = op_erase_64k; + op.address = address; return myctrl->xspi->api->exec_op(myctrl->xspi->ctrl, &op, true); } @@ -498,6 +510,7 @@ static int flash_erase_64k(qspiflash_at25_ctrl_t *myctrl, size_t address) static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) { int result; + if (RZ_XSPIFLASH_DISABLE_WRITE) { result = -1; } else { @@ -510,6 +523,7 @@ static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) do { /* Wait for previous command finished */ enum xspidevice_write_status ws; + do { ws = flash_get_write_status(ctrl); } while (ws == WRITE_STATUS_IN_PROGRESS); diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h b/drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25_api.h similarity index 96% rename from plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h rename to drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25_api.h index a094017a71..a17a98cb89 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/qspiflash_at25_api.h +++ b/drivers/renesas/rza/xspidevice/qspiflash_at25/qspiflash_at25_api.h @@ -7,7 +7,6 @@ #ifndef _QSPIFLASH_AT25_API_H_ #define _QSPIFLASH_AT25_API_H_ #include -#include #include "xspidevice_api.h" diff --git a/drivers/renesas/rza/xspidevice/qspiflash_at25/rz_xspidevice.mk b/drivers/renesas/rza/xspidevice/qspiflash_at25/rz_xspidevice.mk new file mode 100644 index 0000000000..bb693d3678 --- /dev/null +++ b/drivers/renesas/rza/xspidevice/qspiflash_at25/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := qspiflash_at25 +PLAT_INCLUDES += -Idrivers/renesas/rza/xspidevice/qspiflash_at25 +RZ_XSPI_HEADERS := ${RZ_XSPI_HEADERS} ${_XSPI_DEVICE}_api.h +RZ_XSPI_SOURCES := ${RZ_XSPI_SOURCES} \ + drivers/renesas/rza/xspidevice/${_XSPI_DEVICE}/${_XSPI_DEVICE}.c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c similarity index 98% rename from plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c rename to drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c index ddf2dd1dfe..fcc2655e33 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c +++ b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g.c @@ -12,7 +12,7 @@ #include "errno.h" #include "lib/mmio.h" -#include "pfc_regs.h" +#include "drivers/renesas/rza/pfc/pfc_regs.h" #include "qspiflash_mx25l25645g_api.h" /* Defaults */ @@ -294,6 +294,7 @@ static int flash_write_enable(qspiflash_mx25l25645g_ctrl_t *myctrl) const xspi_instance_t *xspi = myctrl->xspi; int timeout = DEFAULT_TIMEOUT; enum xspidevice_write_status status = WRITE_STATUS_DISABLED; + while ((status != WRITE_STATUS_OK) && (timeout > 0)) { xspi->api->exec_op(xspi->ctrl, &op_write_enable, false); status = flash_get_write_status(myctrl); @@ -318,12 +319,15 @@ static int flash_check_manufacturer_id(qspiflash_mx25l25645g_ctrl_t *myctrl) uint8_t id[3]; xspi_op_t op = op_read_id; + op.transfer_buffer = id; op.transfer_size = 3; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result < 0) return result; + const uint16_t device_id = (id[1] << 8) | id[2]; + if ((id[0] != MANUFACTURER_ID) || (device_id != DEVICE_ID)) { ERROR("Flash device not found\n"); VERBOSE("Manufacturer ID: 0x%02x, Device ID: 0x%04x\n", id[0], @@ -341,6 +345,7 @@ static uint8_t flash_read_status_register(qspiflash_mx25l25645g_ctrl_t *myctrl) uint8_t status; xspi_op_t op = op_read_status; + op.transfer_buffer = &status; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result < 0) { @@ -358,6 +363,7 @@ flash_read_configuration_register(qspiflash_mx25l25645g_ctrl_t *myctrl) uint8_t configuration; xspi_op_t op = op_read_configuraton; + op.transfer_buffer = &configuration; result = xspi->api->exec_op(xspi->ctrl, &op, false); if (result < 0) { @@ -374,6 +380,7 @@ static int flash_wait_for_write_complete(qspiflash_mx25l25645g_ctrl_t *myctrl, assert(timeout > 0); uint8_t status = 0; + do { status = flash_read_status_register(myctrl); timeout--; @@ -391,10 +398,12 @@ static int flash_wait_for_write_complete(qspiflash_mx25l25645g_ctrl_t *myctrl, static int flash_reset(qspiflash_mx25l25645g_ctrl_t *myctrl) { const xspi_instance_t *xspi = myctrl->xspi; + flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); /* Reset Enable */ int result = xspi->api->exec_op(xspi->ctrl, &op_reset_enable, false); + if (result < 0) return result; @@ -438,6 +447,7 @@ static void flash_hw_protect_unlock(qspiflash_mx25l25645g_ctrl_t *myctrl) VERBOSE("Trying to unlock the flash HW protection\n"); int result = flash_reset(myctrl); + if (result < 0) { ERROR("Failed to reset the flash while unlocking HW protection\n"); goto err; @@ -471,6 +481,7 @@ static void flash_hw_protect_unlock(qspiflash_mx25l25645g_ctrl_t *myctrl) /* Verify if the status register is written correctly */ uint8_t status = flash_read_status_register(myctrl); + if ((status & 0x80) != 0) goto err; @@ -494,6 +505,7 @@ static int flash_init(qspiflash_mx25l25645g_ctrl_t *myctrl) const xspi_instance_t *xspi = myctrl->xspi; int result = flash_reset(myctrl); + if (result < 0) return result; @@ -504,12 +516,14 @@ static int flash_init(qspiflash_mx25l25645g_ctrl_t *myctrl) /* Determine status_register */ uint8_t status_register = 0; + if (DEFAULT_READ_MODE == READ_MODE_QUAD) { status_register = 1u << 6; /* QE (Quad Enable) : Enable */ } /* Determine configuration_register */ uint8_t configuration_register = 0; + if (DEFAULT_READ_MODE == READ_MODE_QUAD) { switch (DEFAULT_DUMMY_CYCLES) { case DUMMY_CYCLES_4: @@ -558,6 +572,7 @@ static int flash_init(qspiflash_mx25l25645g_ctrl_t *myctrl) /* Verify if the status register is written correctly */ uint8_t status = flash_read_status_register(myctrl); + if (status != status_register) { if ((status & 0x80) != 0) { WARN("Flash is in Hardware Protection Mode\n"); @@ -569,6 +584,7 @@ static int flash_init(qspiflash_mx25l25645g_ctrl_t *myctrl) /* Verify if the configuration register is written correctly */ uint8_t configuration = flash_read_configuration_register(myctrl); + if (configuration != configuration_register) { ERROR("Failed to write configuration register\n"); return -1; @@ -598,6 +614,7 @@ static int flash_open(xspidevice_ctrl_t *ctrl, xspidevice_cfg_t const *cfg) udelay(SPI_POST_RESET_WAIT); uint32_t retries = 0; + do { retries++; if (retries >= MAX_FLASH_UNLOCK_RETRIES) @@ -625,6 +642,7 @@ static int flash_close(xspidevice_ctrl_t *ctrl) qspiflash_mx25l25645g_ctrl_t *myctrl = (qspiflash_mx25l25645g_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; + if (myctrl->opened) { result = xspi->api->close(xspi->ctrl); myctrl->opened = false; @@ -647,8 +665,8 @@ static int flash_exec_op(xspidevice_ctrl_t *ctrl, xspi_op_t const *op, static int flash_enter_xip(xspidevice_ctrl_t *ctrl) { - int result = -1; assert(ctrl); + int result = -1; qspiflash_mx25l25645g_ctrl_t *myctrl = (qspiflash_mx25l25645g_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; @@ -659,6 +677,7 @@ static int flash_enter_xip(xspidevice_ctrl_t *ctrl) xspi_op_t op = op_burst_read; uint8_t wrap_depth = DEFAULT_BURST_READ_WRAP_DEPTH; + op.transfer_buffer = (void *)&wrap_depth; result = xspi->api->exec_op(xspi->ctrl, &op, true); @@ -695,11 +714,15 @@ static int flash_exit_xip(xspidevice_ctrl_t *ctrl) qspiflash_mx25l25645g_ctrl_t *myctrl = (qspiflash_mx25l25645g_ctrl_t *)ctrl; + int result = -1; xspi_op_t op = op_burst_read; uint8_t wrap_depth = BURST_READ_WRAP_DISABLE; - op.transfer_buffer = (void *)&wrap_depth; const xspi_instance_t *xspi = myctrl->xspi; - int result = xspi->api->exec_op(xspi->ctrl, &op, true); + + op.transfer_buffer = (void *)&wrap_depth; + result = xspi->api->exec_op(xspi->ctrl, &op, true); + if (result < 0) + return result; result = flash_wait_for_write_complete(myctrl, DEFAULT_TIMEOUT); if (result < 0) @@ -726,8 +749,8 @@ static int flash_read(xspidevice_ctrl_t *ctrl, void *buffer, size_t address, qspiflash_mx25l25645g_ctrl_t *myctrl = (qspiflash_mx25l25645g_ctrl_t *)ctrl; const xspi_instance_t *xspi = myctrl->xspi; - uintptr_t mmap_base = xspi->api->get_mmap_base(xspi->ctrl); + memcpy(buffer, (void *)(mmap_base + address), length); return 0; @@ -746,8 +769,7 @@ static int flash_erase(xspidevice_ctrl_t *ctrl, size_t address, size_t length) return -1; } -static enum xspidevice_write_status -flash_get_write_status(xspidevice_ctrl_t *ctrl) +static enum xspidevice_write_status flash_get_write_status(xspidevice_ctrl_t *ctrl) { assert(ctrl); qspiflash_mx25l25645g_ctrl_t *myctrl = @@ -755,6 +777,7 @@ flash_get_write_status(xspidevice_ctrl_t *ctrl) /* Read Flag Status Register */ uint8_t result = flash_read_status_register(myctrl); + if ((result & BIT(0)) != 0) return WRITE_STATUS_IN_PROGRESS; if ((result & BIT(1)) == 0) diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h similarity index 98% rename from plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h rename to drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h index 3e4e556e0a..60777b7bab 100644 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h +++ b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/qspiflash_mx25l25645g_api.h @@ -7,7 +7,6 @@ #ifndef _QSPIFLASH_MX25L25645G_API_H_ #define _QSPIFLASH_MX25L25645G_API_H_ #include -#include #include "xspidevice_api.h" diff --git a/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk new file mode 100644 index 0000000000..3fd6933442 --- /dev/null +++ b/drivers/renesas/rza/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk @@ -0,0 +1,11 @@ +# +# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +_XSPI_DEVICE := qspiflash_mx25l25645g +PLAT_INCLUDES += -Idrivers/renesas/rza/xspidevice/qspiflash_mx25l25645g +RZ_XSPI_HEADERS := ${RZ_XSPI_HEADERS} ${_XSPI_DEVICE}_api.h +RZ_XSPI_SOURCES := ${RZ_XSPI_SOURCES} \ + drivers/renesas/rza/xspidevice/${_XSPI_DEVICE}/${_XSPI_DEVICE}.c diff --git a/plat/renesas/rza/common/include/drivers/auth/auth_common.h b/include/drivers/renesas/rza/auth/auth_common.h similarity index 62% rename from plat/renesas/rza/common/include/drivers/auth/auth_common.h rename to include/drivers/renesas/rza/auth/auth_common.h index df240eef35..078498fabf 100644 --- a/plat/renesas/rza/common/include/drivers/auth/auth_common.h +++ b/include/drivers/renesas/rza/auth/auth_common.h @@ -18,12 +18,12 @@ */ typedef enum auth_param_type_enum { AUTH_PARAM_NONE, - AUTH_PARAM_RAW_DATA, /* Raw image data */ - AUTH_PARAM_SIG, /* The image signature */ - AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ - AUTH_PARAM_HASH, /* A hash (including the algorithm) */ - AUTH_PARAM_PUB_KEY, /* A public key */ - AUTH_PARAM_NV_CTR, /* A non-volatile counter */ + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ + AUTH_PARAM_NV_CTR, /* A non-volatile counter */ } auth_param_type_t; /* @@ -56,37 +56,37 @@ typedef struct auth_param_desc_s { */ typedef enum auth_method_type_enum { AUTH_METHOD_NONE = 0, - AUTH_METHOD_HASH, /* Authenticate by hash matching */ - AUTH_METHOD_SIG, /* Authenticate by PK operation */ - AUTH_METHOD_NV_CTR, /* Authenticate by Non-Volatile Counter */ - AUTH_METHOD_SBLIB, /* Authenticate by Renesas RZ/G2L SBLib */ - AUTH_METHOD_NUM /* Number of methods */ + AUTH_METHOD_HASH, /* Authenticate by hash matching */ + AUTH_METHOD_SIG, /* Authenticate by PK operation */ + AUTH_METHOD_NV_CTR, /* Authenticate by Non-Volatile Counter */ + AUTH_METHOD_SBLIB, /* Authenticate by Renesas RZ/A SBLib */ + AUTH_METHOD_NUM /* Number of methods */ } auth_method_type_t; /* * Parameters for authentication by hash matching */ typedef struct auth_method_param_hash_s { - auth_param_type_desc_t *data; /* Data to hash */ - auth_param_type_desc_t *hash; /* Hash to match with */ + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ } auth_method_param_hash_t; /* * Parameters for authentication by signature */ typedef struct auth_method_param_sig_s { - auth_param_type_desc_t *pk; /* Public key */ - auth_param_type_desc_t *sig; /* Signature to check */ - auth_param_type_desc_t *alg; /* Signature algorithm */ - auth_param_type_desc_t *data; /* Data signed */ + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *data; /* Data signed */ } auth_method_param_sig_t; /* * Parameters for authentication by NV counter */ typedef struct auth_method_param_nv_ctr_s { - auth_param_type_desc_t *cert_nv_ctr; /* NV counter in certificate */ - auth_param_type_desc_t *plat_nv_ctr; /* NV counter in platform */ + auth_param_type_desc_t *cert_nv_ctr; /* NV counter in certificate */ + auth_param_type_desc_t *plat_nv_ctr; /* NV counter in platform */ } auth_method_param_nv_ctr_t; typedef struct auth_method_param_sblib_s { @@ -111,17 +111,19 @@ typedef struct auth_method_desc_s { /* * Helper macro to define an authentication parameter type descriptor */ -#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \ - { \ - .type = _type, .cookie = (void *)_cookie \ +#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \ + { \ + .type = _type, \ + .cookie = (void *)_cookie \ } /* * Helper macro to define an authentication parameter data descriptor */ -#define AUTH_PARAM_DATA_DESC(_ptr, _len) \ - { \ - .ptr = (void *)_ptr, .len = (unsigned int)_len \ +#define AUTH_PARAM_DATA_DESC(_ptr, _len) \ + { \ + .ptr = (void *)_ptr, \ + .len = (unsigned int)_len \ } #endif /* AUTH_COMMON_H */ diff --git a/plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h b/include/drivers/renesas/rza/auth/sblib/crypto_sblib.h similarity index 58% rename from plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h rename to include/drivers/renesas/rza/auth/sblib/crypto_sblib.h index 592de41470..5c7033a315 100644 --- a/plat/renesas/rza/common/include/drivers/auth/sblib/crypto_sblib.h +++ b/include/drivers/renesas/rza/auth/sblib/crypto_sblib.h @@ -9,8 +9,7 @@ void crypto_sblib_init(void); -int crypto_sblib_auth(void *data_ptr, size_t len, const void *key_cert, - unsigned int key_cert_len, const void *content_cert, - unsigned int content_cert_len); +int crypto_sblib_auth(const void *key_cert, unsigned int key_cert_len, + const void *content_cert, unsigned int content_cert_len); #endif /* CRYPTO_SBLIB_H */ diff --git a/plat/renesas/rza/common/include/scifa.h b/include/drivers/renesas/rza/console/scifa.h similarity index 74% rename from plat/renesas/rza/common/include/scifa.h rename to include/drivers/renesas/rza/console/scifa.h index 80636c6991..394d6d67a2 100644 --- a/plat/renesas/rza/common/include/scifa.h +++ b/include/drivers/renesas/rza/console/scifa.h @@ -12,8 +12,8 @@ #include #include -int console_rza_register(uintptr_t baseaddr, uint32_t clock, - uint32_t baud, console_t *console); +int console_scifa_register(uintptr_t baseaddr, uint32_t clock, + uint32_t baud, console_t *console); #endif /* __ASSEMBLER__ */ diff --git a/plat/renesas/rza/common/include/cpg.h b/include/drivers/renesas/rza/cpg/cpg.h similarity index 97% rename from plat/renesas/rza/common/include/cpg.h rename to include/drivers/renesas/rza/cpg/cpg.h index 575d39693b..c0e62fb632 100644 --- a/plat/renesas/rza/common/include/cpg.h +++ b/include/drivers/renesas/rza/cpg/cpg.h @@ -37,19 +37,19 @@ static inline void cpg_reset_onoff(int clkid, uint32_t mask, uint32_t val) } #define CPG_CLKRSTONOFF_START(id) switch (id) { -#define CPG_CLKRSTONOFF_END(a) } +#define CPG_CLKRSTONOFF_END() } #define CPG_CLKON_DEF(id, mask) CPG_CLKONOFF_DEF(id, mask, 1) #define CPG_CLKOFF_DEF(id, mask) CPG_CLKONOFF_DEF(id, mask, 0) #define CPG_CLKONOFF_DEF(id, mask, value) \ case id: \ cpg_clock_onoff(id, mask, value); \ - break; + break #define CPG_RSTON_DEF(id, mask) CPG_RSTONOFF_DEF(id, mask, 1) #define CPG_RSTOFF_DEF(id, mask) CPG_RSTONOFF_DEF(id, mask, 0) #define CPG_RSTONOFF_DEF(id, mask, value) \ case id: \ cpg_reset_onoff(id, mask, value); \ - break; + break static inline void cpg_clock_on(enum clock_id_t clkid) { diff --git a/plat/renesas/rza/common/include/cpg_regs.h b/include/drivers/renesas/rza/cpg/cpg_regs.h similarity index 60% rename from plat/renesas/rza/common/include/cpg_regs.h rename to include/drivers/renesas/rza/cpg/cpg_regs.h index f43d1fd45e..7ec9b940b0 100644 --- a/plat/renesas/rza/common/include/cpg_regs.h +++ b/include/drivers/renesas/rza/cpg/cpg_regs.h @@ -9,22 +9,22 @@ #define CPG_BASE (0x11010000) /* CPG base address */ -#define CPG_PLL1_STBY (CPG_BASE + 0x0000) /* PLL1 (SSCG) standby control register */ -#define CPG_PLL1_CLK1 (CPG_BASE + 0x0004) /* PLL1 (SSCG) output clock setting register 1 */ -#define CPG_PLL1_CLK2 (CPG_BASE + 0x0008) /* PLL1 (SSCG) output clock setting register 2 */ -#define CPG_PLL1_MON (CPG_BASE + 0x000C) /* PLL1 (SSCG) monitor register */ -#define CPG_PLL4_STBY (CPG_BASE + 0x0010) /* PLL4 (SSCG) standby control register */ -#define CPG_PLL4_CLK1 (CPG_BASE + 0x0014) /* PLL4 (SSCG) output clock setting register 1 */ -#define CPG_PLL4_CLK2 (CPG_BASE + 0x0018) /* PLL4 (SSCG) output clock setting register 2 */ -#define CPG_PLL4_MON (CPG_BASE + 0x001C) /* PLL4 (SSCG) monitor register */ -#define CPG_PLL6_STBY (CPG_BASE + 0x0020) /* PLL6 (SSCG) standby control register */ -#define CPG_PLL6_CLK1 (CPG_BASE + 0x0024) /* PLL6 (SSCG) output clock setting register 1 */ -#define CPG_PLL6_CLK2 (CPG_BASE + 0x0028) /* PLL6 (SSCG) output clock setting register 2 */ -#define CPG_PLL6_MON (CPG_BASE + 0x002C) /* PLL6 (SSCG) monitor register */ -#define CPG_PLL1_SETTING (CPG_BASE + 0x0040) /* PLL1_SEL_SETTING */ -#define CPG_OTPPLL0_MON (CPG_BASE + 0x0044) /* OTP_OTPPLL0 monitor register */ -#define CPG_OTPPLL1_MON (CPG_BASE + 0x0048) /* OTP_OTPPLL1 monitor register */ -#define CPG_OTPPLL2_MON (CPG_BASE + 0x004C) /* OTP_OTPPLL2 monitor register */ +#define CPG_PLL1_STBY (CPG_BASE + 0x0000) /* PLL1 (SSCG) standby control register */ +#define CPG_PLL1_CLK1 (CPG_BASE + 0x0004) /* PLL1 (SSCG) output clock setting register 1 */ +#define CPG_PLL1_CLK2 (CPG_BASE + 0x0008) /* PLL1 (SSCG) output clock setting register 2 */ +#define CPG_PLL1_MON (CPG_BASE + 0x000C) /* PLL1 (SSCG) monitor register */ +#define CPG_PLL4_STBY (CPG_BASE + 0x0010) /* PLL4 (SSCG) standby control register */ +#define CPG_PLL4_CLK1 (CPG_BASE + 0x0014) /* PLL4 (SSCG) output clock setting register 1 */ +#define CPG_PLL4_CLK2 (CPG_BASE + 0x0018) /* PLL4 (SSCG) output clock setting register 2 */ +#define CPG_PLL4_MON (CPG_BASE + 0x001C) /* PLL4 (SSCG) monitor register */ +#define CPG_PLL6_STBY (CPG_BASE + 0x0020) /* PLL6 (SSCG) standby control register */ +#define CPG_PLL6_CLK1 (CPG_BASE + 0x0024) /* PLL6 (SSCG) output clock setting register 1 */ +#define CPG_PLL6_CLK2 (CPG_BASE + 0x0028) /* PLL6 (SSCG) output clock setting register 2 */ +#define CPG_PLL6_MON (CPG_BASE + 0x002C) /* PLL6 (SSCG) monitor register */ +#define CPG_PLL1_SETTING (CPG_BASE + 0x0040) /* PLL1_SEL_SETTING */ +#define CPG_OTPPLL0_MON (CPG_BASE + 0x0044) /* OTP_OTPPLL0 monitor register */ +#define CPG_OTPPLL1_MON (CPG_BASE + 0x0048) /* OTP_OTPPLL1 monitor register */ +#define CPG_OTPPLL2_MON (CPG_BASE + 0x004C) /* OTP_OTPPLL2 monitor register */ #define CPG_PLL2_STBY (CPG_BASE + 0x0100) /* PLL2 (SSCG) standby control register */ #define CPG_PLL2_CLK1 (CPG_BASE + 0x0104) /* PLL2 (SSCG) output clock setting register 1 */ @@ -67,117 +67,117 @@ #define CPG_PL6_ETH_SSEL (CPG_BASE + 0x0418) /* Source clock setting register */ #define CPG_PL5_SDIV (CPG_BASE + 0x0420) /* Division ratio setting register */ -#define CPG_CLKON_CA55 (CPG_BASE + 0x0500) /* Clock ON/OFF register CA55 */ -#define CPG_CLKON_CM33 (CPG_BASE + 0x0504) /* Clock ON/OFF register CM33 */ -#define CPG_CLKON_SRAM_ACPU (CPG_BASE + 0x0508) /* Clock ON/OFF register SRAM_ACPU */ -#define CPG_CLKON_SRAM_MCPU (CPG_BASE + 0x050C) /* Clock ON/OFF register SRAM_MCPU */ -#define CPG_CLKON_ROM (CPG_BASE + 0x0510) /* Clock ON/OFF register ROM */ -#define CPG_CLKON_GIC600 (CPG_BASE + 0x0514) /* Clock ON/OFF register GIC600 */ -#define CPG_CLKON_IA55 (CPG_BASE + 0x0518) /* Clock ON/OFF register IA55 */ -#define CPG_CLKON_IM33 (CPG_BASE + 0x051C) /* Clock ON/OFF register IM33 */ -#define CPG_CLKON_MHU (CPG_BASE + 0x0520) /* Clock ON/OFF register MHU */ -#define CPG_CLKON_CST (CPG_BASE + 0x0524) /* Clock ON/OFF register CST */ -#define CPG_CLKON_SYC (CPG_BASE + 0x0528) /* Clock ON/OFF register SYC */ -#define CPG_CLKON_DAMC_REG (CPG_BASE + 0x052C) /* Clock ON/OFF register DAMC_REG */ -#define CPG_CLKON_SYSC (CPG_BASE + 0x0530) /* Clock ON/OFF register SYSC */ -#define CPG_CLKON_OSTM (CPG_BASE + 0x0534) /* Clock ON/OFF register OSTM */ -#define CPG_CLKON_MTU (CPG_BASE + 0x0538) /* Clock ON/OFF register MTU */ -#define CPG_CLKON_POE3 (CPG_BASE + 0x053C) /* Clock ON/OFF register POE3 */ -#define CPG_CLKON_WDT (CPG_BASE + 0x0548) /* Clock ON/OFF register WDT */ -#define CPG_CLKON_DDR (CPG_BASE + 0x054C) /* Clock ON/OFF register DDR */ -#define CPG_CLKON_SPI_MULTI (CPG_BASE + 0x0550) /* Clock ON/OFF register SPI_MULTI */ -#define CPG_CLKON_SDHI (CPG_BASE + 0x0554) /* Clock ON/OFF register SDHI */ -#define CPG_CLKON_ISU (CPG_BASE + 0x055C) /* Clock ON/OFF register ISU */ -#define CPG_CLKON_CRU (CPG_BASE + 0x0564) /* Clock ON/OFF register CRU */ -#define CPG_CLKON_MIPI_DSI (CPG_BASE + 0x0568) /* Clock ON/OFF register MIPI_DSI */ -#define CPG_CLKON_LCDC (CPG_BASE + 0x056C) /* Clock ON/OFF register LCDC */ -#define CPG_CLKON_SSI (CPG_BASE + 0x0570) /* Clock ON/OFF register SSI */ -#define CPG_CLKON_SRC (CPG_BASE + 0x0574) /* Clock ON/OFF register SRC */ -#define CPG_CLKON_USB (CPG_BASE + 0x0578) /* Clock ON/OFF register USB */ -#define CPG_CLKON_ETH (CPG_BASE + 0x057C) /* Clock ON/OFF register ETH */ -#define CPG_CLKON_I2C (CPG_BASE + 0x0580) /* Clock ON/OFF register I2C */ -#define CPG_CLKON_SCIF (CPG_BASE + 0x0584) /* Clock ON/OFF register SCIF */ -#define CPG_CLKON_SCI (CPG_BASE + 0x0588) /* Clock ON/OFF register SCI */ -#define CPG_CLKON_IRDA (CPG_BASE + 0x058C) /* Clock ON/OFF register IRDA */ -#define CPG_CLKON_RSPI (CPG_BASE + 0x0590) /* Clock ON/OFF register RSPI */ -#define CPG_CLKON_CANFD (CPG_BASE + 0x0594) /* Clock ON/OFF register CANFD */ -#define CPG_CLKON_GPIO (CPG_BASE + 0x0598) /* Clock ON/OFF register GPIO */ -#define CPG_CLKON_TSIPG (CPG_BASE + 0x059C) /* Clock ON/OFF register TSIPG */ -#define CPG_CLKON_JAUTH (CPG_BASE + 0x05A0) /* Clock ON/OFF register JAUTH */ -#define CPG_CLKON_OTP (CPG_BASE + 0x05A4) /* Clock ON/OFF register OTP */ -#define CPG_CLKON_ADC (CPG_BASE + 0x05A8) /* Clock ON/OFF register ADC */ -#define CPG_CLKON_TSU (CPG_BASE + 0x05AC) /* Clock ON/OFF register TSU */ -#define CPG_CLKON_BBGU (CPG_BASE + 0x05B0) /* Clock ON/OFF register BBGU */ -#define CPG_CLKON_AXI_ACPU_BUS (CPG_BASE + 0x05B4) /* Clock ON/OFF register AXI_ACPU_BUS */ -#define CPG_CLKON_AXI_MCPU_BUS (CPG_BASE + 0x05B8) /* Clock ON/OFF register AXI_MCPU_BUS */ -#define CPG_CLKON_AXI_COM_BUS (CPG_BASE + 0x05BC) /* Clock ON/OFF register AXI_COM_BUS */ -#define CPG_CLKON_AXI_VIDEO_BUS (CPG_BASE + 0x05C0) /* Clock ON/OFF register AXI_VIDEO_BUS */ -#define CPG_CLKON_PERI_COM (CPG_BASE + 0x05C4) /* Clock ON/OFF register PERI_COM */ -#define CPG_CLKON_REG1_BUS (CPG_BASE + 0x05C8) /* Clock ON/OFF register REG1_BUS */ -#define CPG_CLKON_REG0_BUS (CPG_BASE + 0x05CC) /* Clock ON/OFF register REG0_BUS */ -#define CPG_CLKON_PERI_CPU (CPG_BASE + 0x05D0) /* Clock ON/OFF register PERI_CPU */ -#define CPG_CLKON_PERI_VIDEO (CPG_BASE + 0x05D4) /* Clock ON/OFF register PERI_VIDEO */ -#define CPG_CLKON_PERI_DDR (CPG_BASE + 0x05D8) /* Clock ON/OFF register PERI_DDR */ -#define CPG_CLKON_AXI_TZCDDR (CPG_BASE + 0x05DC) /* Clock ON/OFF register AXI_TZCDDR */ -#define CPG_CLKON_MTGPGS (CPG_BASE + 0x05E0) /* Clock ON/OFF register MTGPGS */ -#define CPG_CLKON_AXI_DEFAULT_SLV (CPG_BASE + 0x05E4) /* Clock ON/OFF register AXI_DEFAULT_SLV */ -#define CPG_CLKON_OCTA (CPG_BASE + 0x05F4) /* Clock ON/OFF register OCTA */ +#define CPG_CLKON_CA55 (CPG_BASE + 0x0500) /* Clock ON/OFF register CA55 */ +#define CPG_CLKON_CM33 (CPG_BASE + 0x0504) /* Clock ON/OFF register CM33 */ +#define CPG_CLKON_SRAM_ACPU (CPG_BASE + 0x0508) /* Clock ON/OFF register SRAM_ACPU */ +#define CPG_CLKON_SRAM_MCPU (CPG_BASE + 0x050C) /* Clock ON/OFF register SRAM_MCPU */ +#define CPG_CLKON_ROM (CPG_BASE + 0x0510) /* Clock ON/OFF register ROM */ +#define CPG_CLKON_GIC600 (CPG_BASE + 0x0514) /* Clock ON/OFF register GIC600 */ +#define CPG_CLKON_IA55 (CPG_BASE + 0x0518) /* Clock ON/OFF register IA55 */ +#define CPG_CLKON_IM33 (CPG_BASE + 0x051C) /* Clock ON/OFF register IM33 */ +#define CPG_CLKON_MHU (CPG_BASE + 0x0520) /* Clock ON/OFF register MHU */ +#define CPG_CLKON_CST (CPG_BASE + 0x0524) /* Clock ON/OFF register CST */ +#define CPG_CLKON_SYC (CPG_BASE + 0x0528) /* Clock ON/OFF register SYC */ +#define CPG_CLKON_DAMC_REG (CPG_BASE + 0x052C) /* Clock ON/OFF register DAMC_REG */ +#define CPG_CLKON_SYSC (CPG_BASE + 0x0530) /* Clock ON/OFF register SYSC */ +#define CPG_CLKON_OSTM (CPG_BASE + 0x0534) /* Clock ON/OFF register OSTM */ +#define CPG_CLKON_MTU (CPG_BASE + 0x0538) /* Clock ON/OFF register MTU */ +#define CPG_CLKON_POE3 (CPG_BASE + 0x053C) /* Clock ON/OFF register POE3 */ +#define CPG_CLKON_WDT (CPG_BASE + 0x0548) /* Clock ON/OFF register WDT */ +#define CPG_CLKON_DDR (CPG_BASE + 0x054C) /* Clock ON/OFF register DDR */ +#define CPG_CLKON_SPI_MULTI (CPG_BASE + 0x0550) /* Clock ON/OFF register SPI_MULTI */ +#define CPG_CLKON_SDHI (CPG_BASE + 0x0554) /* Clock ON/OFF register SDHI */ +#define CPG_CLKON_ISU (CPG_BASE + 0x055C) /* Clock ON/OFF register ISU */ +#define CPG_CLKON_CRU (CPG_BASE + 0x0564) /* Clock ON/OFF register CRU */ +#define CPG_CLKON_MIPI_DSI (CPG_BASE + 0x0568) /* Clock ON/OFF register MIPI_DSI */ +#define CPG_CLKON_LCDC (CPG_BASE + 0x056C) /* Clock ON/OFF register LCDC */ +#define CPG_CLKON_SSI (CPG_BASE + 0x0570) /* Clock ON/OFF register SSI */ +#define CPG_CLKON_SRC (CPG_BASE + 0x0574) /* Clock ON/OFF register SRC */ +#define CPG_CLKON_USB (CPG_BASE + 0x0578) /* Clock ON/OFF register USB */ +#define CPG_CLKON_ETH (CPG_BASE + 0x057C) /* Clock ON/OFF register ETH */ +#define CPG_CLKON_I2C (CPG_BASE + 0x0580) /* Clock ON/OFF register I2C */ +#define CPG_CLKON_SCIF (CPG_BASE + 0x0584) /* Clock ON/OFF register SCIF */ +#define CPG_CLKON_SCI (CPG_BASE + 0x0588) /* Clock ON/OFF register SCI */ +#define CPG_CLKON_IRDA (CPG_BASE + 0x058C) /* Clock ON/OFF register IRDA */ +#define CPG_CLKON_RSPI (CPG_BASE + 0x0590) /* Clock ON/OFF register RSPI */ +#define CPG_CLKON_CANFD (CPG_BASE + 0x0594) /* Clock ON/OFF register CANFD */ +#define CPG_CLKON_GPIO (CPG_BASE + 0x0598) /* Clock ON/OFF register GPIO */ +#define CPG_CLKON_TSIPG (CPG_BASE + 0x059C) /* Clock ON/OFF register TSIPG */ +#define CPG_CLKON_JAUTH (CPG_BASE + 0x05A0) /* Clock ON/OFF register JAUTH */ +#define CPG_CLKON_OTP (CPG_BASE + 0x05A4) /* Clock ON/OFF register OTP */ +#define CPG_CLKON_ADC (CPG_BASE + 0x05A8) /* Clock ON/OFF register ADC */ +#define CPG_CLKON_TSU (CPG_BASE + 0x05AC) /* Clock ON/OFF register TSU */ +#define CPG_CLKON_BBGU (CPG_BASE + 0x05B0) /* Clock ON/OFF register BBGU */ +#define CPG_CLKON_AXI_ACPU_BUS (CPG_BASE + 0x05B4) /* Clock ON/OFF register AXI_ACPU_BUS */ +#define CPG_CLKON_AXI_MCPU_BUS (CPG_BASE + 0x05B8) /* Clock ON/OFF register AXI_MCPU_BUS */ +#define CPG_CLKON_AXI_COM_BUS (CPG_BASE + 0x05BC) /* Clock ON/OFF register AXI_COM_BUS */ +#define CPG_CLKON_AXI_VIDEO_BUS (CPG_BASE + 0x05C0) /* Clock ON/OFF register AXI_VIDEO_BUS */ +#define CPG_CLKON_PERI_COM (CPG_BASE + 0x05C4) /* Clock ON/OFF register PERI_COM */ +#define CPG_CLKON_REG1_BUS (CPG_BASE + 0x05C8) /* Clock ON/OFF register REG1_BUS */ +#define CPG_CLKON_REG0_BUS (CPG_BASE + 0x05CC) /* Clock ON/OFF register REG0_BUS */ +#define CPG_CLKON_PERI_CPU (CPG_BASE + 0x05D0) /* Clock ON/OFF register PERI_CPU */ +#define CPG_CLKON_PERI_VIDEO (CPG_BASE + 0x05D4) /* Clock ON/OFF register PERI_VIDEO */ +#define CPG_CLKON_PERI_DDR (CPG_BASE + 0x05D8) /* Clock ON/OFF register PERI_DDR */ +#define CPG_CLKON_AXI_TZCDDR (CPG_BASE + 0x05DC) /* Clock ON/OFF register AXI_TZCDDR */ +#define CPG_CLKON_MTGPGS (CPG_BASE + 0x05E0) /* Clock ON/OFF register MTGPGS */ +#define CPG_CLKON_AXI_DEFAULT_SLV (CPG_BASE + 0x05E4) /* Clock ON/OFF register AXI_DEFAULT_SLV */ +#define CPG_CLKON_OCTA (CPG_BASE + 0x05F4) /* Clock ON/OFF register OCTA */ -#define CPG_CLKMON_CA55 (CPG_BASE + 0x0680) /* Clock monitor register CA55 */ -#define CPG_CLKMON_CM33 (CPG_BASE + 0x0684) /* Clock monitor register CM33 */ -#define CPG_CLKMON_SRAM_ACPU (CPG_BASE + 0x0688) /* Clock monitor register SRAM_ACPU */ -#define CPG_CLKMON_SRAM_MCPU (CPG_BASE + 0x068C) /* Clock monitor register SRAM_MCPU */ -#define CPG_CLKMON_ROM (CPG_BASE + 0x0690) /* Clock monitor register ROM */ -#define CPG_CLKMON_GIC600 (CPG_BASE + 0x0694) /* Clock monitor register GIC600 */ -#define CPG_CLKMON_IA55 (CPG_BASE + 0x0698) /* Clock monitor register IA55 */ -#define CPG_CLKMON_IM33 (CPG_BASE + 0x069C) /* Clock monitor register IM33 */ -#define CPG_CLKMON_MHU (CPG_BASE + 0x06A0) /* Clock monitor register MHU */ -#define CPG_CLKMON_CST (CPG_BASE + 0x06A4) /* Clock monitor register CST */ -#define CPG_CLKMON_SYC (CPG_BASE + 0x06A8) /* Clock monitor register SYC */ -#define CPG_CLKMON_DAMC_REG (CPG_BASE + 0x06AC) /* Clock monitor register DAMC_REG */ -#define CPG_CLKMON_SYSC (CPG_BASE + 0x06B0) /* Clock monitor register SYSC */ -#define CPG_CLKMON_OSTM (CPG_BASE + 0x06B4) /* Clock monitor register OSTM */ -#define CPG_CLKMON_MTU (CPG_BASE + 0x06B8) /* Clock monitor register MTU */ -#define CPG_CLKMON_POE3 (CPG_BASE + 0x06BC) /* Clock monitor register POE3 */ -#define CPG_CLKMON_WDT (CPG_BASE + 0x06C8) /* Clock monitor register WDT */ -#define CPG_CLKMON_DDR (CPG_BASE + 0x06CC) /* Clock monitor register DDR */ -#define CPG_CLKMON_SPI_MULTI (CPG_BASE + 0x06D0) /* Clock monitor register SPI_MULTI */ -#define CPG_CLKMON_SDHI (CPG_BASE + 0x06D4) /* Clock monitor register SDHI */ -#define CPG_CLKMON_ISU (CPG_BASE + 0x06DC) /* Clock monitor register ISU */ -#define CPG_CLKMON_CRU (CPG_BASE + 0x06E4) /* Clock monitor register CRU */ -#define CPG_CLKMON_MIPI_DSI (CPG_BASE + 0x06E8) /* Clock monitor register MIPI_DSI */ -#define CPG_CLKMON_LCDC (CPG_BASE + 0x06EC) /* Clock monitor register LCDC */ -#define CPG_CLKMON_SSI (CPG_BASE + 0x06F0) /* Clock monitor register SSI */ -#define CPG_CLKMON_SRC (CPG_BASE + 0x06F4) /* Clock monitor register SRC */ -#define CPG_CLKMON_USB (CPG_BASE + 0x06F8) /* Clock monitor register USB */ -#define CPG_CLKMON_ETH (CPG_BASE + 0x06FC) /* Clock monitor register ETH */ -#define CPG_CLKMON_I2C (CPG_BASE + 0x0700) /* Clock monitor register I2C */ -#define CPG_CLKMON_SCIF (CPG_BASE + 0x0704) /* Clock monitor register SCIF */ -#define CPG_CLKMON_SCI (CPG_BASE + 0x0708) /* Clock monitor register SCI */ -#define CPG_CLKMON_IRDA (CPG_BASE + 0x070C) /* Clock monitor register IRDA */ -#define CPG_CLKMON_RSPI (CPG_BASE + 0x0710) /* Clock monitor register RSPI */ -#define CPG_CLKMON_CANFD (CPG_BASE + 0x0714) /* Clock monitor register CANFD */ -#define CPG_CLKMON_GPIO (CPG_BASE + 0x0718) /* Clock monitor register GPIO */ -#define CPG_CLKMON_TSIPG (CPG_BASE + 0x071C) /* Clock monitor register TSIPG */ -#define CPG_CLKMON_JAUTH (CPG_BASE + 0x0720) /* Clock monitor register JAUTH */ -#define CPG_CLKMON_OTP (CPG_BASE + 0x0724) /* Clock monitor register OTP */ -#define CPG_CLKMON_ADC (CPG_BASE + 0x0728) /* Clock monitor register ADC */ -#define CPG_CLKMON_TSU (CPG_BASE + 0x072C) /* Clock monitor register TSU */ -#define CPG_CLKMON_BBGU (CPG_BASE + 0x0730) /* Clock monitor register BBGU */ -#define CPG_CLKMON_AXI_ACPU_BUS (CPG_BASE + 0x0734) /* Clock monitor register AXI_ACPU_BUS */ -#define CPG_CLKMON_AXI_MCPU_BUS (CPG_BASE + 0x0738) /* Clock monitor register AXI_MCPU_BUS */ -#define CPG_CLKMON_AXI_COM_BUS (CPG_BASE + 0x073C) /* Clock monitor register AXI_COM_BUS */ -#define CPG_CLKMON_AXI_VIDEO_BUS (CPG_BASE + 0x0740) /* Clock monitor register AXI_VIDEO_BUS */ -#define CPG_CLKMON_PERI_COM (CPG_BASE + 0x0744) /* Clock monitor register PERI_COM */ -#define CPG_CLKMON_REG1_BUS (CPG_BASE + 0x0748) /* Clock monitor register REG1_BUS */ -#define CPG_CLKMON_REG0_BUS (CPG_BASE + 0x074C) /* Clock monitor register REG0_BUS */ -#define CPG_CLKMON_PERI_CPU (CPG_BASE + 0x0750) /* Clock monitor register PERI_CPU */ -#define CPG_CLKMON_PERI_VIDEO (CPG_BASE + 0x0754) /* Clock monitor register PERI_VIDEO */ -#define CPG_CLKMON_PERI_DDR (CPG_BASE + 0x0758) /* Clock monitor register PERI_DDR */ -#define CPG_CLKMON_AXI_TZCDDR (CPG_BASE + 0x075C) /* Clock monitor register AXI_TZCDDR */ -#define CPG_CLKMON_MTGPGS (CPG_BASE + 0x0760) /* Clock monitor register MTGPGS */ -#define CPG_CLKMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0764) /* Clock monitor register AXI_DEFAULT_SLV */ -#define CPG_CLKMON_OCTA (CPG_BASE + 0x0774) /* Clock monitor register OCTA */ +#define CPG_CLKMON_CA55 (CPG_BASE + 0x0680) /* Clock monitor register CA55 */ +#define CPG_CLKMON_CM33 (CPG_BASE + 0x0684) /* Clock monitor register CM33 */ +#define CPG_CLKMON_SRAM_ACPU (CPG_BASE + 0x0688) /* Clock monitor register SRAM_ACPU */ +#define CPG_CLKMON_SRAM_MCPU (CPG_BASE + 0x068C) /* Clock monitor register SRAM_MCPU */ +#define CPG_CLKMON_ROM (CPG_BASE + 0x0690) /* Clock monitor register ROM */ +#define CPG_CLKMON_GIC600 (CPG_BASE + 0x0694) /* Clock monitor register GIC600 */ +#define CPG_CLKMON_IA55 (CPG_BASE + 0x0698) /* Clock monitor register IA55 */ +#define CPG_CLKMON_IM33 (CPG_BASE + 0x069C) /* Clock monitor register IM33 */ +#define CPG_CLKMON_MHU (CPG_BASE + 0x06A0) /* Clock monitor register MHU */ +#define CPG_CLKMON_CST (CPG_BASE + 0x06A4) /* Clock monitor register CST */ +#define CPG_CLKMON_SYC (CPG_BASE + 0x06A8) /* Clock monitor register SYC */ +#define CPG_CLKMON_DAMC_REG (CPG_BASE + 0x06AC) /* Clock monitor register DAMC_REG */ +#define CPG_CLKMON_SYSC (CPG_BASE + 0x06B0) /* Clock monitor register SYSC */ +#define CPG_CLKMON_OSTM (CPG_BASE + 0x06B4) /* Clock monitor register OSTM */ +#define CPG_CLKMON_MTU (CPG_BASE + 0x06B8) /* Clock monitor register MTU */ +#define CPG_CLKMON_POE3 (CPG_BASE + 0x06BC) /* Clock monitor register POE3 */ +#define CPG_CLKMON_WDT (CPG_BASE + 0x06C8) /* Clock monitor register WDT */ +#define CPG_CLKMON_DDR (CPG_BASE + 0x06CC) /* Clock monitor register DDR */ +#define CPG_CLKMON_SPI_MULTI (CPG_BASE + 0x06D0) /* Clock monitor register SPI_MULTI */ +#define CPG_CLKMON_SDHI (CPG_BASE + 0x06D4) /* Clock monitor register SDHI */ +#define CPG_CLKMON_ISU (CPG_BASE + 0x06DC) /* Clock monitor register ISU */ +#define CPG_CLKMON_CRU (CPG_BASE + 0x06E4) /* Clock monitor register CRU */ +#define CPG_CLKMON_MIPI_DSI (CPG_BASE + 0x06E8) /* Clock monitor register MIPI_DSI */ +#define CPG_CLKMON_LCDC (CPG_BASE + 0x06EC) /* Clock monitor register LCDC */ +#define CPG_CLKMON_SSI (CPG_BASE + 0x06F0) /* Clock monitor register SSI */ +#define CPG_CLKMON_SRC (CPG_BASE + 0x06F4) /* Clock monitor register SRC */ +#define CPG_CLKMON_USB (CPG_BASE + 0x06F8) /* Clock monitor register USB */ +#define CPG_CLKMON_ETH (CPG_BASE + 0x06FC) /* Clock monitor register ETH */ +#define CPG_CLKMON_I2C (CPG_BASE + 0x0700) /* Clock monitor register I2C */ +#define CPG_CLKMON_SCIF (CPG_BASE + 0x0704) /* Clock monitor register SCIF */ +#define CPG_CLKMON_SCI (CPG_BASE + 0x0708) /* Clock monitor register SCI */ +#define CPG_CLKMON_IRDA (CPG_BASE + 0x070C) /* Clock monitor register IRDA */ +#define CPG_CLKMON_RSPI (CPG_BASE + 0x0710) /* Clock monitor register RSPI */ +#define CPG_CLKMON_CANFD (CPG_BASE + 0x0714) /* Clock monitor register CANFD */ +#define CPG_CLKMON_GPIO (CPG_BASE + 0x0718) /* Clock monitor register GPIO */ +#define CPG_CLKMON_TSIPG (CPG_BASE + 0x071C) /* Clock monitor register TSIPG */ +#define CPG_CLKMON_JAUTH (CPG_BASE + 0x0720) /* Clock monitor register JAUTH */ +#define CPG_CLKMON_OTP (CPG_BASE + 0x0724) /* Clock monitor register OTP */ +#define CPG_CLKMON_ADC (CPG_BASE + 0x0728) /* Clock monitor register ADC */ +#define CPG_CLKMON_TSU (CPG_BASE + 0x072C) /* Clock monitor register TSU */ +#define CPG_CLKMON_BBGU (CPG_BASE + 0x0730) /* Clock monitor register BBGU */ +#define CPG_CLKMON_AXI_ACPU_BUS (CPG_BASE + 0x0734) /* Clock monitor register AXI_ACPU_BUS */ +#define CPG_CLKMON_AXI_MCPU_BUS (CPG_BASE + 0x0738) /* Clock monitor register AXI_MCPU_BUS */ +#define CPG_CLKMON_AXI_COM_BUS (CPG_BASE + 0x073C) /* Clock monitor register AXI_COM_BUS */ +#define CPG_CLKMON_AXI_VIDEO_BUS (CPG_BASE + 0x0740) /* Clock monitor register AXI_VIDEO_BUS */ +#define CPG_CLKMON_PERI_COM (CPG_BASE + 0x0744) /* Clock monitor register PERI_COM */ +#define CPG_CLKMON_REG1_BUS (CPG_BASE + 0x0748) /* Clock monitor register REG1_BUS */ +#define CPG_CLKMON_REG0_BUS (CPG_BASE + 0x074C) /* Clock monitor register REG0_BUS */ +#define CPG_CLKMON_PERI_CPU (CPG_BASE + 0x0750) /* Clock monitor register PERI_CPU */ +#define CPG_CLKMON_PERI_VIDEO (CPG_BASE + 0x0754) /* Clock monitor register PERI_VIDEO */ +#define CPG_CLKMON_PERI_DDR (CPG_BASE + 0x0758) /* Clock monitor register PERI_DDR */ +#define CPG_CLKMON_AXI_TZCDDR (CPG_BASE + 0x075C) /* Clock monitor register AXI_TZCDDR */ +#define CPG_CLKMON_MTGPGS (CPG_BASE + 0x0760) /* Clock monitor register MTGPGS */ +#define CPG_CLKMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0764) /* Clock monitor register AXI_DEFAULT_SLV */ +#define CPG_CLKMON_OCTA (CPG_BASE + 0x0774) /* Clock monitor register OCTA */ #define CPG_RST_CA55 (CPG_BASE + 0x0800) /* Reset ONOFF register CA55 */ #define CPG_RST_CM33 (CPG_BASE + 0x0804) /* Reset ONOFF register CM33 */ @@ -235,85 +235,85 @@ #define CPG_RST_AXI_DEFAULT_SLV (CPG_BASE + 0x08E4) /* Reset ONOFF register AXI_DEFAULT_SLV */ #define CPG_RST_OCTA (CPG_BASE + 0x08F4) /* Reset ONOFF register OCTA */ -#define CPG_RSTMON_CA55 (CPG_BASE + 0x0980) /* Reset monitor register CA55 */ -#define CPG_RSTMON_CM33 (CPG_BASE + 0x0984) /* Reset monitor register CM33 */ -#define CPG_RSTMON_SRAM_ACPU (CPG_BASE + 0x0988) /* Reset monitor register SRAM_ACPU */ -#define CPG_RSTMON_SRAM_MCPU (CPG_BASE + 0x098C) /* Reset monitor register SRAM_MCPU */ -#define CPG_RSTMON_ROM (CPG_BASE + 0x0990) /* Reset monitor register ROM */ -#define CPG_RSTMON_GIC600 (CPG_BASE + 0x0994) /* Reset monitor register GIC600 */ -#define CPG_RSTMON_IA55 (CPG_BASE + 0x0998) /* Reset monitor register IA55 */ -#define CPG_RSTMON_IM33 (CPG_BASE + 0x099C) /* Reset monitor register IM33 */ -#define CPG_RSTMON_MHU (CPG_BASE + 0x09A0) /* Reset monitor register MHU */ -#define CPG_RSTMON_CST (CPG_BASE + 0x09A4) /* Reset monitor register CST */ -#define CPG_RSTMON_SYC (CPG_BASE + 0x09A8) /* Reset monitor register SYC */ -#define CPG_RSTMON_DMAC (CPG_BASE + 0x09AC) /* Reset monitor register DMAC */ -#define CPG_RSTMON_SYSC (CPG_BASE + 0x09B0) /* Reset monitor register SYSC */ -#define CPG_RSTMON_OSTM (CPG_BASE + 0x09B4) /* Reset monitor register OSTM */ -#define CPG_RSTMON_MTU (CPG_BASE + 0x09B8) /* Reset monitor register MTU */ -#define CPG_RSTMON_POE3 (CPG_BASE + 0x09BC) /* Reset monitor register POE3 */ -#define CPG_RSTMON_WDT (CPG_BASE + 0x09C8) /* Reset monitor register WDT */ -#define CPG_RSTMON_DDR (CPG_BASE + 0x09CC) /* Reset monitor register DDR */ -#define CPG_RSTMON_SPI (CPG_BASE + 0x09D0) /* Reset monitor register SPI */ -#define CPG_RSTMON_SDHI (CPG_BASE + 0x09D4) /* Reset monitor register SDHI */ -#define CPG_RSTMON_ISU (CPG_BASE + 0x09DC) /* Reset monitor register ISU */ -#define CPG_RSTMON_CRU (CPG_BASE + 0x09E4) /* Reset monitor register CRU */ -#define CPG_RSTMON_MIPI_DSI (CPG_BASE + 0x09E8) /* Reset monitor register MIPI_DSI */ -#define CPG_RSTMON_LCDC (CPG_BASE + 0x09EC) /* Reset monitor register LCDC */ -#define CPG_RSTMON_SSIF (CPG_BASE + 0x09F0) /* Reset monitor register SSIF */ -#define CPG_RSTMON_SRC (CPG_BASE + 0x09F4) /* Reset monitor register SRC */ -#define CPG_RSTMON_USB (CPG_BASE + 0x09F8) /* Reset monitor register USB */ -#define CPG_RSTMON_ETH (CPG_BASE + 0x09FC) /* Reset monitor register ETH */ -#define CPG_RSTMON_I2C (CPG_BASE + 0x0A00) /* Reset monitor register I2C */ -#define CPG_RSTMON_SCIF (CPG_BASE + 0x0A04) /* Reset monitor register SCIF */ -#define CPG_RSTMON_SCI (CPG_BASE + 0x0A08) /* Reset monitor register SCI */ -#define CPG_RSTMON_IRDA (CPG_BASE + 0x0A0C) /* Reset monitor register IRDA */ -#define CPG_RSTMON_RSPI (CPG_BASE + 0x0A10) /* Reset monitor register RSPI */ -#define CPG_RSTMON_CANFD (CPG_BASE + 0x0A14) /* Reset monitor register CANFD */ -#define CPG_RSTMON_GPIO (CPG_BASE + 0x0A18) /* Reset monitor register GPIO */ -#define CPG_RSTMON_TSIPG (CPG_BASE + 0x0A1C) /* Reset monitor register TSIPG */ -#define CPG_RSTMON_JAUTH (CPG_BASE + 0x0A20) /* Reset monitor register JAUTH */ -#define CPG_RSTMON_OTP (CPG_BASE + 0x0A24) /* Reset monitor register OTP */ -#define CPG_RSTMON_ADC (CPG_BASE + 0x0A28) /* Reset monitor register ADC */ -#define CPG_RSTMON_TSU (CPG_BASE + 0x0A2C) /* Reset monitor register TSU */ -#define CPG_RSTMON_BBGU (CPG_BASE + 0x0A30) /* Reset monitor register BBGU */ -#define CPG_RSTMON_AXI_ACPU_BUS (CPG_BASE + 0x0A34) /* Reset monitor register AXI_ACPU_BUS */ -#define CPG_RSTMON_AXI_MCPU_BUS (CPG_BASE + 0x0A38) /* Reset monitor register AXI_MCPU_BUS */ -#define CPG_RSTMON_AXI_COM_BUS (CPG_BASE + 0x0A3C) /* Reset monitor register AXI_COM_BUS */ -#define CPG_RSTMON_AXI_VIDEO_BUS (CPG_BASE + 0x0A40) /* Reset monitor register AXI_VIDEO_BUS */ -#define CPG_RSTMON_PERI_COM (CPG_BASE + 0x0A44) /* Reset monitor register PERI_COM */ -#define CPG_RSTMON_REG1_BUS (CPG_BASE + 0x0A48) /* Reset monitor register REG1_BUS */ -#define CPG_RSTMON_REG0_BUS (CPG_BASE + 0x0A4C) /* Reset monitor register REG0_BUS */ -#define CPG_RSTMON_PERI_CPU (CPG_BASE + 0x0A50) /* Reset monitor register PERI_CPU */ -#define CPG_RSTMON_PERI_VIDEO (CPG_BASE + 0x0A54) /* Reset monitor register PERI_VIDEO */ -#define CPG_RSTMON_PERI_DDR (CPG_BASE + 0x0A58) /* Reset monitor register PERI_DDR */ -#define CPG_RSTMON_AXI_TZCDDR (CPG_BASE + 0x0A5C) /* Reset monitor register AXI_TZCDDR */ -#define CPG_RSTMON_MTGPGS (CPG_BASE + 0x0A60) /* Reset monitor register MTGPGS */ -#define CPG_RSTMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0A64) /* Reset monitor register AXI_DEFAULT_SLV */ -#define CPG_RSTMON_OCTA (CPG_BASE + 0x0A74) /* Reset monitor register OCTA */ +#define CPG_RSTMON_CA55 (CPG_BASE + 0x0980) /* Reset monitor register CA55 */ +#define CPG_RSTMON_CM33 (CPG_BASE + 0x0984) /* Reset monitor register CM33 */ +#define CPG_RSTMON_SRAM_ACPU (CPG_BASE + 0x0988) /* Reset monitor register SRAM_ACPU */ +#define CPG_RSTMON_SRAM_MCPU (CPG_BASE + 0x098C) /* Reset monitor register SRAM_MCPU */ +#define CPG_RSTMON_ROM (CPG_BASE + 0x0990) /* Reset monitor register ROM */ +#define CPG_RSTMON_GIC600 (CPG_BASE + 0x0994) /* Reset monitor register GIC600 */ +#define CPG_RSTMON_IA55 (CPG_BASE + 0x0998) /* Reset monitor register IA55 */ +#define CPG_RSTMON_IM33 (CPG_BASE + 0x099C) /* Reset monitor register IM33 */ +#define CPG_RSTMON_MHU (CPG_BASE + 0x09A0) /* Reset monitor register MHU */ +#define CPG_RSTMON_CST (CPG_BASE + 0x09A4) /* Reset monitor register CST */ +#define CPG_RSTMON_SYC (CPG_BASE + 0x09A8) /* Reset monitor register SYC */ +#define CPG_RSTMON_DMAC (CPG_BASE + 0x09AC) /* Reset monitor register DMAC */ +#define CPG_RSTMON_SYSC (CPG_BASE + 0x09B0) /* Reset monitor register SYSC */ +#define CPG_RSTMON_OSTM (CPG_BASE + 0x09B4) /* Reset monitor register OSTM */ +#define CPG_RSTMON_MTU (CPG_BASE + 0x09B8) /* Reset monitor register MTU */ +#define CPG_RSTMON_POE3 (CPG_BASE + 0x09BC) /* Reset monitor register POE3 */ +#define CPG_RSTMON_WDT (CPG_BASE + 0x09C8) /* Reset monitor register WDT */ +#define CPG_RSTMON_DDR (CPG_BASE + 0x09CC) /* Reset monitor register DDR */ +#define CPG_RSTMON_SPI (CPG_BASE + 0x09D0) /* Reset monitor register SPI */ +#define CPG_RSTMON_SDHI (CPG_BASE + 0x09D4) /* Reset monitor register SDHI */ +#define CPG_RSTMON_ISU (CPG_BASE + 0x09DC) /* Reset monitor register ISU */ +#define CPG_RSTMON_CRU (CPG_BASE + 0x09E4) /* Reset monitor register CRU */ +#define CPG_RSTMON_MIPI_DSI (CPG_BASE + 0x09E8) /* Reset monitor register MIPI_DSI */ +#define CPG_RSTMON_LCDC (CPG_BASE + 0x09EC) /* Reset monitor register LCDC */ +#define CPG_RSTMON_SSIF (CPG_BASE + 0x09F0) /* Reset monitor register SSIF */ +#define CPG_RSTMON_SRC (CPG_BASE + 0x09F4) /* Reset monitor register SRC */ +#define CPG_RSTMON_USB (CPG_BASE + 0x09F8) /* Reset monitor register USB */ +#define CPG_RSTMON_ETH (CPG_BASE + 0x09FC) /* Reset monitor register ETH */ +#define CPG_RSTMON_I2C (CPG_BASE + 0x0A00) /* Reset monitor register I2C */ +#define CPG_RSTMON_SCIF (CPG_BASE + 0x0A04) /* Reset monitor register SCIF */ +#define CPG_RSTMON_SCI (CPG_BASE + 0x0A08) /* Reset monitor register SCI */ +#define CPG_RSTMON_IRDA (CPG_BASE + 0x0A0C) /* Reset monitor register IRDA */ +#define CPG_RSTMON_RSPI (CPG_BASE + 0x0A10) /* Reset monitor register RSPI */ +#define CPG_RSTMON_CANFD (CPG_BASE + 0x0A14) /* Reset monitor register CANFD */ +#define CPG_RSTMON_GPIO (CPG_BASE + 0x0A18) /* Reset monitor register GPIO */ +#define CPG_RSTMON_TSIPG (CPG_BASE + 0x0A1C) /* Reset monitor register TSIPG */ +#define CPG_RSTMON_JAUTH (CPG_BASE + 0x0A20) /* Reset monitor register JAUTH */ +#define CPG_RSTMON_OTP (CPG_BASE + 0x0A24) /* Reset monitor register OTP */ +#define CPG_RSTMON_ADC (CPG_BASE + 0x0A28) /* Reset monitor register ADC */ +#define CPG_RSTMON_TSU (CPG_BASE + 0x0A2C) /* Reset monitor register TSU */ +#define CPG_RSTMON_BBGU (CPG_BASE + 0x0A30) /* Reset monitor register BBGU */ +#define CPG_RSTMON_AXI_ACPU_BUS (CPG_BASE + 0x0A34) /* Reset monitor register AXI_ACPU_BUS */ +#define CPG_RSTMON_AXI_MCPU_BUS (CPG_BASE + 0x0A38) /* Reset monitor register AXI_MCPU_BUS */ +#define CPG_RSTMON_AXI_COM_BUS (CPG_BASE + 0x0A3C) /* Reset monitor register AXI_COM_BUS */ +#define CPG_RSTMON_AXI_VIDEO_BUS (CPG_BASE + 0x0A40) /* Reset monitor register AXI_VIDEO_BUS */ +#define CPG_RSTMON_PERI_COM (CPG_BASE + 0x0A44) /* Reset monitor register PERI_COM */ +#define CPG_RSTMON_REG1_BUS (CPG_BASE + 0x0A48) /* Reset monitor register REG1_BUS */ +#define CPG_RSTMON_REG0_BUS (CPG_BASE + 0x0A4C) /* Reset monitor register REG0_BUS */ +#define CPG_RSTMON_PERI_CPU (CPG_BASE + 0x0A50) /* Reset monitor register PERI_CPU */ +#define CPG_RSTMON_PERI_VIDEO (CPG_BASE + 0x0A54) /* Reset monitor register PERI_VIDEO */ +#define CPG_RSTMON_PERI_DDR (CPG_BASE + 0x0A58) /* Reset monitor register PERI_DDR */ +#define CPG_RSTMON_AXI_TZCDDR (CPG_BASE + 0x0A5C) /* Reset monitor register AXI_TZCDDR */ +#define CPG_RSTMON_MTGPGS (CPG_BASE + 0x0A60) /* Reset monitor register MTGPGS */ +#define CPG_RSTMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0A64) /* Reset monitor register AXI_DEFAULT_SLV */ +#define CPG_RSTMON_OCTA (CPG_BASE + 0x0A74) /* Reset monitor register OCTA */ -#define CPG_EN_OSTM (CPG_BASE + 0x0B00) /* Enable ONOFF register_OSTM */ -#define CPG_WDTOVF_RST (CPG_BASE + 0x0B10) /* WDT overflow system reset register */ -#define CPG_WDTRST_SEL (CPG_BASE + 0x0B14) /* WDT reset selector register */ -#define CPG_DBGRST (CPG_BASE + 0x0B20) /* Reset ONOFF register DBGRST */ -#define CPG_CLUSTER_PCHMON (CPG_BASE + 0x0B30) /* CA55 Cluster Power Status Monitor Register */ -#define CPG_CLUSTER_PCHCTL (CPG_BASE + 0x0B34) /* CA55 Cluster Power Status Control Register */ -#define CPG_CORE0_PCHMON (CPG_BASE + 0x0B38) /* CA55 Core0 Power Status Monitor Register */ -#define CPG_CORE0_PCHCTL (CPG_BASE + 0x0B3C) /* CA55 Core0 Power Status Control Register */ -#define CPG_CORE1_PCHMON (CPG_BASE + 0x0B40) /* CA55 Core1 Power Status Monitor Register */ -#define CPG_CORE1_PCHCTL (CPG_BASE + 0x0B44) /* CA55 Core1 Power Status Control Register */ -#define CPG_BUS_ACPU_MSTOP (CPG_BASE + 0x0B60) /* MSTOP registerBUS_ACPU */ -#define CPG_BUS_MCPU1_MSTOP (CPG_BASE + 0x0B64) /* MSTOP registerBUS_MCPU1 */ -#define CPG_BUS_MCPU2_MSTOP (CPG_BASE + 0x0B68) /* MSTOP registerBUS_MCPU2 */ -#define CPG_BUS_PERI_COM_MSTOP (CPG_BASE + 0x0B6C) /* MSTOP registerBUS_PERI_COM */ -#define CPG_BUS_PERI_CPU_MSTOP (CPG_BASE + 0x0B70) /* MSTOP registerBUS_PERI_CPU */ -#define CPG_BUS_PERI_DDR_MSTOP (CPG_BASE + 0x0B74) /* MSTOP registerBUS_PERI_DDR */ -#define CPG_BUS_PERI_VIDEO_MSTOP (CPG_BASE + 0x0B78) /* MSTOP registerBUS_PERI_VIDEO */ -#define CPG_BUS_REG0_MSTOP (CPG_BASE + 0x0B7C) /* MSTOP registerBUS_REG0 */ -#define CPG_BUS_REG1_MSTOP (CPG_BASE + 0x0B80) /* MSTOP registerBUS_REG1 */ -#define CPG_BUS_TZCDDR_MSTOP (CPG_BASE + 0x0B84) /* MSTOP registerBUS_TZCDDR */ -#define CPG_MHU_MSTOP (CPG_BASE + 0x0B88) /* MSTOP registerMHU */ -#define CPG_BUS_PERI_STP_MSTOP (CPG_BASE + 0x0B8C) /* MSTOP registerBUS_PERI_STP */ -#define CPG_BUS_MCPU3_MSTOP (CPG_BASE + 0x0B90) /* MSTOP register BUS_MCPU3 */ +#define CPG_EN_OSTM (CPG_BASE + 0x0B00) /* Enable ONOFF register_OSTM */ +#define CPG_WDTOVF_RST (CPG_BASE + 0x0B10) /* WDT overflow system reset register */ +#define CPG_WDTRST_SEL (CPG_BASE + 0x0B14) /* WDT reset selector register */ +#define CPG_DBGRST (CPG_BASE + 0x0B20) /* Reset ONOFF register DBGRST */ +#define CPG_CLUSTER_PCHMON (CPG_BASE + 0x0B30) /* CA55 Cluster Power Status Monitor */ +#define CPG_CLUSTER_PCHCTL (CPG_BASE + 0x0B34) /* CA55 Cluster Power Status Control */ +#define CPG_CORE0_PCHMON (CPG_BASE + 0x0B38) /* CA55 Core0 Power Status Monitor */ +#define CPG_CORE0_PCHCTL (CPG_BASE + 0x0B3C) /* CA55 Core0 Power Status Control */ +#define CPG_CORE1_PCHMON (CPG_BASE + 0x0B40) /* CA55 Core1 Power Status Monitor */ +#define CPG_CORE1_PCHCTL (CPG_BASE + 0x0B44) /* CA55 Core1 Power Status Control */ +#define CPG_BUS_ACPU_MSTOP (CPG_BASE + 0x0B60) /* MSTOP register BUS_ACPU */ +#define CPG_BUS_MCPU1_MSTOP (CPG_BASE + 0x0B64) /* MSTOP register BUS_MCPU1 */ +#define CPG_BUS_MCPU2_MSTOP (CPG_BASE + 0x0B68) /* MSTOP register BUS_MCPU2 */ +#define CPG_BUS_PERI_COM_MSTOP (CPG_BASE + 0x0B6C) /* MSTOP register BUS_PERI_COM */ +#define CPG_BUS_PERI_CPU_MSTOP (CPG_BASE + 0x0B70) /* MSTOP register BUS_PERI_CPU */ +#define CPG_BUS_PERI_DDR_MSTOP (CPG_BASE + 0x0B74) /* MSTOP register BUS_PERI_DDR */ +#define CPG_BUS_PERI_VIDEO_MSTOP (CPG_BASE + 0x0B78) /* MSTOP register BUS_PERI_VIDEO */ +#define CPG_BUS_REG0_MSTOP (CPG_BASE + 0x0B7C) /* MSTOP register BUS_REG0 */ +#define CPG_BUS_REG1_MSTOP (CPG_BASE + 0x0B80) /* MSTOP register BUS_REG1 */ +#define CPG_BUS_TZCDDR_MSTOP (CPG_BASE + 0x0B84) /* MSTOP register BUS_TZCDDR */ +#define CPG_MHU_MSTOP (CPG_BASE + 0x0B88) /* MSTOP register MHU */ +#define CPG_BUS_PERI_STP_MSTOP (CPG_BASE + 0x0B8C) /* MSTOP register BUS_PERI_STP */ +#define CPG_BUS_MCPU3_MSTOP (CPG_BASE + 0x0B90) /* MSTOP register BUS_MCPU3 */ #define CPG_OTHERFUNC1_REG (CPG_BASE + 0x0BE8) /* Other function registers1 */ #define CPG_OTHERFUNC2_REG (CPG_BASE + 0x0BEC) /* Other function registers2 */ diff --git a/plat/renesas/rza/common/include/ddr.h b/include/drivers/renesas/rza/ddr/ddr.h similarity index 100% rename from plat/renesas/rza/common/include/ddr.h rename to include/drivers/renesas/rza/ddr/ddr.h diff --git a/plat/renesas/rza/common/include/ddr_internal.h b/include/drivers/renesas/rza/ddr/ddr_internal.h similarity index 91% rename from plat/renesas/rza/common/include/ddr_internal.h rename to include/drivers/renesas/rza/ddr/ddr_internal.h index 7dca21c49a..b3ba5be5c0 100644 --- a/plat/renesas/rza/common/include/ddr_internal.h +++ b/include/drivers/renesas/rza/ddr/ddr_internal.h @@ -11,9 +11,9 @@ #include #include -#define MC_PHYSET_NUM (4) -#define SWIZZLE_MC_NUM (9) -#define SIZZLE_PHY_NUM (16) +#define MC_PHYSET_NUM (4) +#define SWIZZLE_MC_NUM (9) +#define SIZZLE_PHY_NUM (16) static inline uint32_t read_mc_reg(uint32_t offset) { diff --git a/plat/renesas/rza/common/include/octa.h b/include/drivers/renesas/rza/octal/octa.h similarity index 100% rename from plat/renesas/rza/common/include/octa.h rename to include/drivers/renesas/rza/octal/octa.h diff --git a/plat/renesas/rza/common/include/octa_regs.h b/include/drivers/renesas/rza/octal/octa_regs.h similarity index 100% rename from plat/renesas/rza/common/include/octa_regs.h rename to include/drivers/renesas/rza/octal/octa_regs.h diff --git a/plat/renesas/rza/common/include/pfc.h b/include/drivers/renesas/rza/pfc/pfc.h similarity index 99% rename from plat/renesas/rza/common/include/pfc.h rename to include/drivers/renesas/rza/pfc/pfc.h index 429076bfe8..9f3ea92ec8 100644 --- a/plat/renesas/rza/common/include/pfc.h +++ b/include/drivers/renesas/rza/pfc/pfc.h @@ -9,5 +9,4 @@ void pfc_setup(void); - #endif /* __PFC_H__ */ diff --git a/include/drivers/renesas/rza/pfc/pfc_regs.h b/include/drivers/renesas/rza/pfc/pfc_regs.h new file mode 100644 index 0000000000..f2f422edbc --- /dev/null +++ b/include/drivers/renesas/rza/pfc/pfc_regs.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PFC_REGS_H__ +#define __PFC_REGS_H__ + +#define PFC_BASE (0x11030000) /* PFC base address */ + +#define PFC_P05 (PFC_BASE + 0x0005) /* Port register */ +#define PFC_P10 (PFC_BASE + 0x0010) /* Port register */ +#define PFC_P11 (PFC_BASE + 0x0011) /* Port register */ +#define PFC_P12 (PFC_BASE + 0x0012) /* Port register */ +#define PFC_P13 (PFC_BASE + 0x0013) /* Port register */ +#define PFC_P14 (PFC_BASE + 0x0014) /* Port register */ +#define PFC_P15 (PFC_BASE + 0x0015) /* Port register */ +#define PFC_P16 (PFC_BASE + 0x0016) /* Port register */ +#define PFC_P17 (PFC_BASE + 0x0017) /* Port register */ +#define PFC_P18 (PFC_BASE + 0x0018) /* Port register */ +#define PFC_P19 (PFC_BASE + 0x0019) /* Port register */ +#define PFC_P1A (PFC_BASE + 0x001A) /* Port register */ +#define PFC_P1B (PFC_BASE + 0x001B) /* Port register */ +#define PFC_P1C (PFC_BASE + 0x001C) /* Port register */ +#define PFC_P1D (PFC_BASE + 0x001D) /* Port register */ +#define PFC_P1E (PFC_BASE + 0x001E) /* Port register */ +#define PFC_P1F (PFC_BASE + 0x001F) /* Port register */ +#define PFC_P20 (PFC_BASE + 0x0020) /* Port register */ +#define PFC_P21 (PFC_BASE + 0x0021) /* Port register */ +#define PFC_P22 (PFC_BASE + 0x0022) /* Port register */ +#define PFC_P23 (PFC_BASE + 0x0023) /* Port register */ +#define PFC_P24 (PFC_BASE + 0x0024) /* Port register */ +#define PFC_P25 (PFC_BASE + 0x0025) /* Port register */ +#define PFC_P26 (PFC_BASE + 0x0026) /* Port register */ +#define PFC_P27 (PFC_BASE + 0x0027) /* Port register */ +#define PFC_P28 (PFC_BASE + 0x0028) /* Port register */ +#define PFC_P29 (PFC_BASE + 0x0029) /* Port register */ +#define PFC_P2A (PFC_BASE + 0x002A) /* Port register */ +#define PFC_P2B (PFC_BASE + 0x002B) /* Port register */ +#define PFC_P2C (PFC_BASE + 0x002C) /* Port register */ +#define PFC_P2D (PFC_BASE + 0x002D) /* Port register */ +#define PFC_P2E (PFC_BASE + 0x002E) /* Port register */ +#define PFC_P2F (PFC_BASE + 0x002F) /* Port register */ +#define PFC_P30 (PFC_BASE + 0x0030) /* Port register */ +#define PFC_P31 (PFC_BASE + 0x0031) /* Port register */ +#define PFC_P32 (PFC_BASE + 0x0032) /* Port register */ +#define PFC_P33 (PFC_BASE + 0x0033) /* Port register */ +#define PFC_P34 (PFC_BASE + 0x0034) /* Port register */ +#define PFC_P35 (PFC_BASE + 0x0035) /* Port register */ +#define PFC_P36 (PFC_BASE + 0x0036) /* Port register */ +#define PFC_P37 (PFC_BASE + 0x0037) /* Port register */ +#define PFC_P38 (PFC_BASE + 0x0038) /* Port register */ +#define PFC_P39 (PFC_BASE + 0x0039) /* Port register */ +#define PFC_P3A (PFC_BASE + 0x003A) /* Port register */ +#define PFC_P3B (PFC_BASE + 0x003B) /* Port register */ +#define PFC_P3C (PFC_BASE + 0x003C) /* Port register */ +#define PFC_P3D (PFC_BASE + 0x003D) /* Port register */ +#define PFC_P3E (PFC_BASE + 0x003E) /* Port register */ +#define PFC_P3F (PFC_BASE + 0x003F) /* Port register */ +#define PFC_P40 (PFC_BASE + 0x0040) /* Port register */ +#define PFC_PM10 (PFC_BASE + 0x0120) /* Port mode register */ +#define PFC_PM11 (PFC_BASE + 0x0122) /* Port mode register */ +#define PFC_PM12 (PFC_BASE + 0x0124) /* Port mode register */ +#define PFC_PM13 (PFC_BASE + 0x0126) /* Port mode register */ +#define PFC_PM14 (PFC_BASE + 0x0128) /* Port mode register */ +#define PFC_PM15 (PFC_BASE + 0x012A) /* Port mode register */ +#define PFC_PM16 (PFC_BASE + 0x012C) /* Port mode register */ +#define PFC_PM17 (PFC_BASE + 0x012E) /* Port mode register */ +#define PFC_PM18 (PFC_BASE + 0x0130) /* Port mode register */ +#define PFC_PM19 (PFC_BASE + 0x0132) /* Port mode register */ +#define PFC_PM1A (PFC_BASE + 0x0134) /* Port mode register */ +#define PFC_PM1B (PFC_BASE + 0x0136) /* Port mode register */ +#define PFC_PM1C (PFC_BASE + 0x0138) /* Port mode register */ +#define PFC_PM1D (PFC_BASE + 0x013A) /* Port mode register */ +#define PFC_PM1E (PFC_BASE + 0x013C) /* Port mode register */ +#define PFC_PM1F (PFC_BASE + 0x013E) /* Port mode register */ +#define PFC_PM20 (PFC_BASE + 0x0140) /* Port mode register */ +#define PFC_PM21 (PFC_BASE + 0x0142) /* Port mode register */ +#define PFC_PM22 (PFC_BASE + 0x0144) /* Port mode register */ +#define PFC_PM23 (PFC_BASE + 0x0146) /* Port mode register */ +#define PFC_PM24 (PFC_BASE + 0x0148) /* Port mode register */ +#define PFC_PM25 (PFC_BASE + 0x014A) /* Port mode register */ +#define PFC_PM26 (PFC_BASE + 0x014C) /* Port mode register */ +#define PFC_PM27 (PFC_BASE + 0x014E) /* Port mode register */ +#define PFC_PM28 (PFC_BASE + 0x0150) /* Port mode register */ +#define PFC_PM29 (PFC_BASE + 0x0152) /* Port mode register */ +#define PFC_PM2A (PFC_BASE + 0x0154) /* Port mode register */ +#define PFC_PM2B (PFC_BASE + 0x0156) /* Port mode register */ +#define PFC_PM2C (PFC_BASE + 0x0158) /* Port mode register */ +#define PFC_PM2D (PFC_BASE + 0x015A) /* Port mode register */ +#define PFC_PM2E (PFC_BASE + 0x015C) /* Port mode register */ +#define PFC_PM2F (PFC_BASE + 0x015E) /* Port mode register */ +#define PFC_PM30 (PFC_BASE + 0x0160) /* Port mode register */ +#define PFC_PM31 (PFC_BASE + 0x0162) /* Port mode register */ +#define PFC_PM32 (PFC_BASE + 0x0164) /* Port mode register */ +#define PFC_PM33 (PFC_BASE + 0x0166) /* Port mode register */ +#define PFC_PM34 (PFC_BASE + 0x0168) /* Port mode register */ +#define PFC_PM35 (PFC_BASE + 0x016A) /* Port mode register */ +#define PFC_PM36 (PFC_BASE + 0x016C) /* Port mode register */ +#define PFC_PM37 (PFC_BASE + 0x016E) /* Port mode register */ +#define PFC_PM38 (PFC_BASE + 0x0170) /* Port mode register */ +#define PFC_PM39 (PFC_BASE + 0x0172) /* Port mode register */ +#define PFC_PM3A (PFC_BASE + 0x0174) /* Port mode register */ +#define PFC_PM3B (PFC_BASE + 0x0176) /* Port mode register */ +#define PFC_PM3C (PFC_BASE + 0x0178) /* Port mode register */ +#define PFC_PM3D (PFC_BASE + 0x017A) /* Port mode register */ +#define PFC_PM3E (PFC_BASE + 0x017C) /* Port mode register */ +#define PFC_PM3F (PFC_BASE + 0x017E) /* Port mode register */ +#define PFC_PM40 (PFC_BASE + 0x0180) /* Port mode register */ +#define PFC_PMC04 (PFC_BASE + 0x0204) /* Port mode control register */ +#define PFC_PMC05 (PFC_BASE + 0x0205) /* Port mode control register */ +#define PFC_PMC10 (PFC_BASE + 0x0210) /* Port mode control register */ +#define PFC_PMC11 (PFC_BASE + 0x0211) /* Port mode control register */ +#define PFC_PMC12 (PFC_BASE + 0x0212) /* Port mode control register */ +#define PFC_PMC13 (PFC_BASE + 0x0213) /* Port mode control register */ +#define PFC_PMC14 (PFC_BASE + 0x0214) /* Port mode control register */ +#define PFC_PMC15 (PFC_BASE + 0x0215) /* Port mode control register */ +#define PFC_PMC16 (PFC_BASE + 0x0216) /* Port mode control register */ +#define PFC_PMC17 (PFC_BASE + 0x0217) /* Port mode control register */ +#define PFC_PMC18 (PFC_BASE + 0x0218) /* Port mode control register */ +#define PFC_PMC19 (PFC_BASE + 0x0219) /* Port mode control register */ +#define PFC_PMC1A (PFC_BASE + 0x021A) /* Port mode control register */ +#define PFC_PMC1B (PFC_BASE + 0x021B) /* Port mode control register */ +#define PFC_PMC1C (PFC_BASE + 0x021C) /* Port mode control register */ +#define PFC_PMC1D (PFC_BASE + 0x021D) /* Port mode control register */ +#define PFC_PMC1E (PFC_BASE + 0x021E) /* Port mode control register */ +#define PFC_PMC1F (PFC_BASE + 0x021F) /* Port mode control register */ +#define PFC_PMC20 (PFC_BASE + 0x0220) /* Port mode control register */ +#define PFC_PMC21 (PFC_BASE + 0x0221) /* Port mode control register */ +#define PFC_PMC22 (PFC_BASE + 0x0222) /* Port mode control register */ +#define PFC_PMC23 (PFC_BASE + 0x0223) /* Port mode control register */ +#define PFC_PMC24 (PFC_BASE + 0x0224) /* Port mode control register */ +#define PFC_PMC25 (PFC_BASE + 0x0225) /* Port mode control register */ +#define PFC_PMC26 (PFC_BASE + 0x0226) /* Port mode control register */ +#define PFC_PMC27 (PFC_BASE + 0x0227) /* Port mode control register */ +#define PFC_PMC28 (PFC_BASE + 0x0228) /* Port mode control register */ +#define PFC_PMC29 (PFC_BASE + 0x0229) /* Port mode control register */ +#define PFC_PMC2A (PFC_BASE + 0x022A) /* Port mode control register */ +#define PFC_PMC2B (PFC_BASE + 0x022B) /* Port mode control register */ +#define PFC_PMC2C (PFC_BASE + 0x022C) /* Port mode control register */ +#define PFC_PMC2D (PFC_BASE + 0x022D) /* Port mode control register */ +#define PFC_PMC2E (PFC_BASE + 0x022E) /* Port mode control register */ +#define PFC_PMC2F (PFC_BASE + 0x022F) /* Port mode control register */ +#define PFC_PMC30 (PFC_BASE + 0x0230) /* Port mode control register */ +#define PFC_PMC31 (PFC_BASE + 0x0231) /* Port mode control register */ +#define PFC_PMC32 (PFC_BASE + 0x0232) /* Port mode control register */ +#define PFC_PMC33 (PFC_BASE + 0x0233) /* Port mode control register */ +#define PFC_PMC34 (PFC_BASE + 0x0234) /* Port mode control register */ +#define PFC_PMC35 (PFC_BASE + 0x0235) /* Port mode control register */ +#define PFC_PMC36 (PFC_BASE + 0x0236) /* Port mode control register */ +#define PFC_PMC37 (PFC_BASE + 0x0237) /* Port mode control register */ +#define PFC_PMC38 (PFC_BASE + 0x0238) /* Port mode control register */ +#define PFC_PMC39 (PFC_BASE + 0x0239) /* Port mode control register */ +#define PFC_PMC3A (PFC_BASE + 0x023A) /* Port mode control register */ +#define PFC_PMC3B (PFC_BASE + 0x023B) /* Port mode control register */ +#define PFC_PMC3C (PFC_BASE + 0x023C) /* Port mode control register */ +#define PFC_PMC3D (PFC_BASE + 0x023D) /* Port mode control register */ +#define PFC_PMC3E (PFC_BASE + 0x023E) /* Port mode control register */ +#define PFC_PMC3F (PFC_BASE + 0x023F) /* Port mode control register */ +#define PFC_PMC40 (PFC_BASE + 0x0240) /* Port mode control register */ +#define PFC_PFC04 (PFC_BASE + 0x0410) /* Port function control register */ +#define PFC_PFC05 (PFC_BASE + 0x0414) /* Port function control register */ +#define PFC_PFC10 (PFC_BASE + 0x0440) /* Port function control register */ +#define PFC_PFC11 (PFC_BASE + 0x0444) /* Port function control register */ +#define PFC_PFC12 (PFC_BASE + 0x0448) /* Port function control register */ +#define PFC_PFC13 (PFC_BASE + 0x044C) /* Port function control register */ +#define PFC_PFC14 (PFC_BASE + 0x0450) /* Port function control register */ +#define PFC_PFC15 (PFC_BASE + 0x0454) /* Port function control register */ +#define PFC_PFC16 (PFC_BASE + 0x0458) /* Port function control register */ +#define PFC_PFC17 (PFC_BASE + 0x045C) /* Port function control register */ +#define PFC_PFC18 (PFC_BASE + 0x0460) /* Port function control register */ +#define PFC_PFC19 (PFC_BASE + 0x0464) /* Port function control register */ +#define PFC_PFC1A (PFC_BASE + 0x0468) /* Port function control register */ +#define PFC_PFC1B (PFC_BASE + 0x046C) /* Port function control register */ +#define PFC_PFC1C (PFC_BASE + 0x0470) /* Port function control register */ +#define PFC_PFC1D (PFC_BASE + 0x0474) /* Port function control register */ +#define PFC_PFC1E (PFC_BASE + 0x0478) /* Port function control register */ +#define PFC_PFC1F (PFC_BASE + 0x047C) /* Port function control register */ +#define PFC_PFC20 (PFC_BASE + 0x0480) /* Port function control register */ +#define PFC_PFC21 (PFC_BASE + 0x0484) /* Port function control register */ +#define PFC_PFC22 (PFC_BASE + 0x0488) /* Port function control register */ +#define PFC_PFC23 (PFC_BASE + 0x048C) /* Port function control register */ +#define PFC_PFC24 (PFC_BASE + 0x0490) /* Port function control register */ +#define PFC_PFC25 (PFC_BASE + 0x0494) /* Port function control register */ +#define PFC_PFC26 (PFC_BASE + 0x0498) /* Port function control register */ +#define PFC_PFC27 (PFC_BASE + 0x049C) /* Port function control register */ +#define PFC_PFC28 (PFC_BASE + 0x04A0) /* Port function control register */ +#define PFC_PFC29 (PFC_BASE + 0x04A4) /* Port function control register */ +#define PFC_PFC2A (PFC_BASE + 0x04A8) /* Port function control register */ +#define PFC_PFC2B (PFC_BASE + 0x04AC) /* Port function control register */ +#define PFC_PFC2C (PFC_BASE + 0x04B0) /* Port function control register */ +#define PFC_PFC2D (PFC_BASE + 0x04B4) /* Port function control register */ +#define PFC_PFC2E (PFC_BASE + 0x04B8) /* Port function control register */ +#define PFC_PFC2F (PFC_BASE + 0x04BC) /* Port function control register */ +#define PFC_PFC30 (PFC_BASE + 0x04C0) /* Port function control register */ +#define PFC_PFC31 (PFC_BASE + 0x04C4) /* Port function control register */ +#define PFC_PFC32 (PFC_BASE + 0x04C8) /* Port function control register */ +#define PFC_PFC33 (PFC_BASE + 0x04CC) /* Port function control register */ +#define PFC_PFC34 (PFC_BASE + 0x04D0) /* Port function control register */ +#define PFC_PFC35 (PFC_BASE + 0x04D4) /* Port function control register */ +#define PFC_PFC36 (PFC_BASE + 0x04D8) /* Port function control register */ +#define PFC_PFC37 (PFC_BASE + 0x04DC) /* Port function control register */ +#define PFC_PFC38 (PFC_BASE + 0x04E0) /* Port function control register */ +#define PFC_PFC39 (PFC_BASE + 0x04E4) /* Port function control register */ +#define PFC_PFC3A (PFC_BASE + 0x04E8) /* Port function control register */ +#define PFC_PFC3B (PFC_BASE + 0x04EC) /* Port function control register */ +#define PFC_PFC3C (PFC_BASE + 0x04F0) /* Port function control register */ +#define PFC_PFC3D (PFC_BASE + 0x04F4) /* Port function control register */ +#define PFC_PFC3E (PFC_BASE + 0x04F8) /* Port function control register */ +#define PFC_PFC3F (PFC_BASE + 0x04FC) /* Port function control register */ +#define PFC_PFC40 (PFC_BASE + 0x0500) /* Port function control register */ +#define PFC_IOLH02 (PFC_BASE + 0x1010) /* IOLH switch register */ +#define PFC_IOLH03 (PFC_BASE + 0x1018) /* IOLH switch register */ +#define PFC_IOLH04 (PFC_BASE + 0x1020) /* IOLH switch register */ +#define PFC_IOLH05 (PFC_BASE + 0x1028) /* IOLH switch register */ +#define PFC_IOLH06 (PFC_BASE + 0x1030) /* IOLH switch register */ +#define PFC_IOLH07 (PFC_BASE + 0x1038) /* IOLH switch register */ +#define PFC_IOLH08 (PFC_BASE + 0x1040) /* IOLH switch register */ +#define PFC_IOLH09 (PFC_BASE + 0x1048) /* IOLH switch register */ +#define PFC_IOLH0A (PFC_BASE + 0x1050) /* IOLH switch register */ +#define PFC_IOLH0B (PFC_BASE + 0x1058) /* IOLH switch register */ +#define PFC_IOLH0C (PFC_BASE + 0x1060) /* IOLH switch register */ +#define PFC_IOLH0D (PFC_BASE + 0x1068) /* IOLH switch register */ +#define PFC_IOLH10 (PFC_BASE + 0x1080) /* IOLH switch register */ +#define PFC_IOLH11 (PFC_BASE + 0x1088) /* IOLH switch register */ +#define PFC_IOLH12 (PFC_BASE + 0x1090) /* IOLH switch register */ +#define PFC_IOLH13 (PFC_BASE + 0x1098) /* IOLH switch register */ +#define PFC_IOLH14 (PFC_BASE + 0x10A0) /* IOLH switch register */ +#define PFC_IOLH15 (PFC_BASE + 0x10A8) /* IOLH switch register */ +#define PFC_IOLH16 (PFC_BASE + 0x10B0) /* IOLH switch register */ +#define PFC_IOLH17 (PFC_BASE + 0x10B8) /* IOLH switch register */ +#define PFC_IOLH18 (PFC_BASE + 0x10C0) /* IOLH switch register */ +#define PFC_IOLH19 (PFC_BASE + 0x10C8) /* IOLH switch register */ +#define PFC_IOLH1A (PFC_BASE + 0x10D0) /* IOLH switch register */ +#define PFC_IOLH1B (PFC_BASE + 0x10D8) /* IOLH switch register */ +#define PFC_IOLH1C (PFC_BASE + 0x10E0) /* IOLH switch register */ +#define PFC_IOLH1D (PFC_BASE + 0x10E8) /* IOLH switch register */ +#define PFC_IOLH1E (PFC_BASE + 0x10F0) /* IOLH switch register */ +#define PFC_IOLH1F (PFC_BASE + 0x10F8) /* IOLH switch register */ +#define PFC_IOLH20 (PFC_BASE + 0x1100) /* IOLH switch register */ +#define PFC_IOLH21 (PFC_BASE + 0x1108) /* IOLH switch register */ +#define PFC_IOLH22 (PFC_BASE + 0x1120) /* IOLH switch register */ +#define PFC_IOLH23 (PFC_BASE + 0x1128) /* IOLH switch register */ +#define PFC_IOLH36 (PFC_BASE + 0x11B0) /* IOLH switch register */ +#define PFC_IOLH37 (PFC_BASE + 0x11B8) /* IOLH switch register */ +#define PFC_IOLH38 (PFC_BASE + 0x11C0) /* IOLH switch register */ +#define PFC_IOLH39 (PFC_BASE + 0x11C8) /* IOLH switch register */ +#define PFC_IOLH3A (PFC_BASE + 0x11D0) /* IOLH switch register */ +#define PFC_IOLH3B (PFC_BASE + 0x11D8) /* IOLH switch register */ +#define PFC_IOLH3C (PFC_BASE + 0x11E0) /* IOLH switch register */ +#define PFC_IOLH3D (PFC_BASE + 0x11E8) /* IOLH switch register */ +#define PFC_IOLH3E (PFC_BASE + 0x11F0) /* IOLH switch register */ +#define PFC_IOLH3F (PFC_BASE + 0x11F8) /* IOLH switch register */ +#define PFC_IOLH40 (PFC_BASE + 0x1200) /* IOLH switch register */ +#define PFC_SR04 (PFC_BASE + 0x1420) /* Slew-Rate switch register */ +#define PFC_SR05 (PFC_BASE + 0x1428) /* Slew-Rate switch register */ +#define PFC_SR06 (PFC_BASE + 0x1430) /* Slew-Rate switch register */ +#define PFC_SR07 (PFC_BASE + 0x1438) /* Slew-Rate switch register */ +#define PFC_SR08 (PFC_BASE + 0x1440) /* Slew-Rate switch register */ +#define PFC_SR09 (PFC_BASE + 0x1448) /* Slew-Rate switch register */ +#define PFC_SR0A (PFC_BASE + 0x1450) /* Slew-Rate switch register */ +#define PFC_SR0B (PFC_BASE + 0x1458) /* Slew-Rate switch register */ +#define PFC_SR0C (PFC_BASE + 0x1460) /* Slew-Rate switch register */ +#define PFC_SR10 (PFC_BASE + 0x1480) /* Slew-Rate switch register */ +#define PFC_SR15 (PFC_BASE + 0x14A8) /* Slew-Rate switch register */ +#define PFC_SR16 (PFC_BASE + 0x14B0) /* Slew-Rate switch register */ +#define PFC_SR1A (PFC_BASE + 0x14D0) /* Slew-Rate switch register */ +#define PFC_SR1B (PFC_BASE + 0x14D8) /* Slew-Rate switch register */ +#define PFC_SR1C (PFC_BASE + 0x14E0) /* Slew-Rate switch register */ +#define PFC_SR1D (PFC_BASE + 0x14E8) /* Slew-Rate switch register */ +#define PFC_SR1E (PFC_BASE + 0x14F0) /* Slew-Rate switch register */ +#define PFC_SR1F (PFC_BASE + 0x14F8) /* Slew-Rate switch register */ +#define PFC_SR20 (PFC_BASE + 0x1500) /* Slew-Rate switch register */ +#define PFC_SR21 (PFC_BASE + 0x1508) /* Slew-Rate switch register */ +#define PFC_SR22 (PFC_BASE + 0x1510) /* Slew-Rate switch register */ +#define PFC_SR23 (PFC_BASE + 0x1518) /* Slew-Rate switch register */ +#define PFC_SR36 (PFC_BASE + 0x15B0) /* Slew-Rate switch register */ +#define PFC_SR37 (PFC_BASE + 0x15B8) /* Slew-Rate switch register */ +#define PFC_IEN06 (PFC_BASE + 0x1830) /* IEN switch register */ +#define PFC_IEN07 (PFC_BASE + 0x1838) /* IEN switch register */ +#define PFC_IEN08 (PFC_BASE + 0x1840) /* IEN switch register */ +#define PFC_IEN09 (PFC_BASE + 0x1848) /* IEN switch register */ +#define PFC_PUPD04 (PFC_BASE + 0x1C20) /* PU/PD switch register */ +#define PFC_PUPD05 (PFC_BASE + 0x1C28) /* PU/PD switch register */ +#define PFC_PUPD06 (PFC_BASE + 0x1C30) /* PU/PD switch register */ +#define PFC_PUPD07 (PFC_BASE + 0x1C38) /* PU/PD switch register */ +#define PFC_PUPD08 (PFC_BASE + 0x1C40) /* PU/PD switch register */ +#define PFC_PUPD09 (PFC_BASE + 0x1C48) /* PU/PD switch register */ +#define PFC_PUPD0A (PFC_BASE + 0x1C50) /* PU/PD switch register */ +#define PFC_PUPD0B (PFC_BASE + 0x1C58) /* PU/PD switch register */ +#define PFC_PUPD0C (PFC_BASE + 0x1C60) /* PU/PD switch register */ +#define PFC_PUPD10 (PFC_BASE + 0x1C80) /* PU/PD switch register */ +#define PFC_PUPD15 (PFC_BASE + 0x1CA8) /* PU/PD switch register */ +#define PFC_PUPD16 (PFC_BASE + 0x1CB0) /* PU/PD switch register */ +#define PFC_PUPD1A (PFC_BASE + 0x1CD0) /* PU/PD switch register */ +#define PFC_PUPD1B (PFC_BASE + 0x1CD8) /* PU/PD switch register */ +#define PFC_PUPD1C (PFC_BASE + 0x1CE0) /* PU/PD switch register */ +#define PFC_PUPD1D (PFC_BASE + 0x1CE8) /* PU/PD switch register */ +#define PFC_PUPD1E (PFC_BASE + 0x1CF0) /* PU/PD switch register */ +#define PFC_PUPD1F (PFC_BASE + 0x1CF8) /* PU/PD switch register */ +#define PFC_PUPD20 (PFC_BASE + 0x1D00) /* PU/PD switch register */ +#define PFC_PUPD21 (PFC_BASE + 0x1D08) /* PU/PD switch register */ +#define PFC_PUPD22 (PFC_BASE + 0x1D10) /* PU/PD switch register */ +#define PFC_PUPD23 (PFC_BASE + 0x1D18) /* PU/PD switch register */ +#define PFC_PUPD36 (PFC_BASE + 0x1DB0) /* PU/PD switch register */ +#define PFC_PUPD37 (PFC_BASE + 0x1DB8) /* PU/PD switch register */ +#define PFC_SD_ch0 (PFC_BASE + 0x3000) /* SD ch0 IO voltage control register */ +#define PFC_SD_ch1 (PFC_BASE + 0x3004) /* SD ch1 IO voltage control register */ +#define PFC_QSPI (PFC_BASE + 0x3008) /* QSPI IO voltage control register */ +#define PFC_ETH_ch0 (PFC_BASE + 0x300C) /* ETH ch0 voltage control register */ +#define PFC_ETH_ch1 (PFC_BASE + 0x3010) /* ETH ch1 voltage control register */ +#define PFC_PWPR (PFC_BASE + 0x3014) /* Write protect */ +#define PFC_FILONOFF01 (PFC_BASE + 0x2008) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF10 (PFC_BASE + 0x2080) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF11 (PFC_BASE + 0x2088) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF12 (PFC_BASE + 0x2090) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF13 (PFC_BASE + 0x2098) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF14 (PFC_BASE + 0x20A0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF15 (PFC_BASE + 0x20A8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF16 (PFC_BASE + 0x20B0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF17 (PFC_BASE + 0x20B8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF18 (PFC_BASE + 0x20C0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF19 (PFC_BASE + 0x20C8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1A (PFC_BASE + 0x20D0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1B (PFC_BASE + 0x20D8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1C (PFC_BASE + 0x20E0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1D (PFC_BASE + 0x20E8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1E (PFC_BASE + 0x20F0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF1F (PFC_BASE + 0x20F8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF20 (PFC_BASE + 0x2100) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF21 (PFC_BASE + 0x2108) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF22 (PFC_BASE + 0x2110) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF23 (PFC_BASE + 0x2118) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF24 (PFC_BASE + 0x2120) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF25 (PFC_BASE + 0x2128) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF26 (PFC_BASE + 0x2130) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF27 (PFC_BASE + 0x2138) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF28 (PFC_BASE + 0x2140) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF29 (PFC_BASE + 0x2148) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2A (PFC_BASE + 0x2150) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2B (PFC_BASE + 0x2158) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2C (PFC_BASE + 0x2160) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2D (PFC_BASE + 0x2168) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2E (PFC_BASE + 0x2170) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF2F (PFC_BASE + 0x2178) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF30 (PFC_BASE + 0x2180) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF31 (PFC_BASE + 0x2188) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF32 (PFC_BASE + 0x2190) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF33 (PFC_BASE + 0x2198) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF34 (PFC_BASE + 0x21A0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF35 (PFC_BASE + 0x21A8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF36 (PFC_BASE + 0x21B0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF37 (PFC_BASE + 0x21B8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF38 (PFC_BASE + 0x21C0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF39 (PFC_BASE + 0x21C8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3A (PFC_BASE + 0x21D0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3B (PFC_BASE + 0x21D8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3C (PFC_BASE + 0x21E0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3D (PFC_BASE + 0x21E8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3E (PFC_BASE + 0x21F0) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF3F (PFC_BASE + 0x21F8) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILONOFF40 (PFC_BASE + 0x2200) /* Digital noise filter (FILONOFF) register */ +#define PFC_FILNUM01 (PFC_BASE + 0x2408) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM10 (PFC_BASE + 0x2480) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM11 (PFC_BASE + 0x2488) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM12 (PFC_BASE + 0x2490) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM13 (PFC_BASE + 0x2498) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM14 (PFC_BASE + 0x24A0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM15 (PFC_BASE + 0x24A8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM16 (PFC_BASE + 0x24B0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM17 (PFC_BASE + 0x24B8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM18 (PFC_BASE + 0x24C0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM19 (PFC_BASE + 0x24C8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1A (PFC_BASE + 0x24D0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1B (PFC_BASE + 0x24D8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1C (PFC_BASE + 0x24E0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1D (PFC_BASE + 0x24E8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1E (PFC_BASE + 0x24F0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM1F (PFC_BASE + 0x24F8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM20 (PFC_BASE + 0x2500) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM21 (PFC_BASE + 0x2508) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM22 (PFC_BASE + 0x2510) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM23 (PFC_BASE + 0x2518) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM24 (PFC_BASE + 0x2520) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM25 (PFC_BASE + 0x2528) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM26 (PFC_BASE + 0x2530) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM27 (PFC_BASE + 0x2538) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM28 (PFC_BASE + 0x2540) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM29 (PFC_BASE + 0x2548) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2A (PFC_BASE + 0x2550) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2B (PFC_BASE + 0x2558) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2C (PFC_BASE + 0x2560) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2D (PFC_BASE + 0x2568) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2E (PFC_BASE + 0x2570) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM2F (PFC_BASE + 0x2578) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM30 (PFC_BASE + 0x2580) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM31 (PFC_BASE + 0x2588) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM32 (PFC_BASE + 0x2590) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM33 (PFC_BASE + 0x2598) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM34 (PFC_BASE + 0x25A0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM35 (PFC_BASE + 0x25A8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM36 (PFC_BASE + 0x25B0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM37 (PFC_BASE + 0x25B8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM38 (PFC_BASE + 0x25C0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM39 (PFC_BASE + 0x25C8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3A (PFC_BASE + 0x25D0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3B (PFC_BASE + 0x25D8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3C (PFC_BASE + 0x25E0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3D (PFC_BASE + 0x25E8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3E (PFC_BASE + 0x25F0) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM3F (PFC_BASE + 0x25F8) /* Digital noise filter (FILNUM) register */ +#define PFC_FILNUM40 (PFC_BASE + 0x2600) /* Digital noise filter (FILNUM) register */ +#define PFC_FILCLKSEL01 (PFC_BASE + 0x2808) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL10 (PFC_BASE + 0x2880) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL11 (PFC_BASE + 0x2888) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL12 (PFC_BASE + 0x2890) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL13 (PFC_BASE + 0x2898) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL14 (PFC_BASE + 0x28A0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL15 (PFC_BASE + 0x28A8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL16 (PFC_BASE + 0x28B0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL17 (PFC_BASE + 0x28B8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL18 (PFC_BASE + 0x28C0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL19 (PFC_BASE + 0x28C8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1A (PFC_BASE + 0x28D0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1B (PFC_BASE + 0x28D8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1C (PFC_BASE + 0x28E0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1D (PFC_BASE + 0x28E8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1E (PFC_BASE + 0x28F0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL1F (PFC_BASE + 0x28F8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL20 (PFC_BASE + 0x2900) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL21 (PFC_BASE + 0x2908) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL22 (PFC_BASE + 0x2910) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL23 (PFC_BASE + 0x2918) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL24 (PFC_BASE + 0x2920) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL25 (PFC_BASE + 0x2928) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL26 (PFC_BASE + 0x2930) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL27 (PFC_BASE + 0x2938) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL28 (PFC_BASE + 0x2940) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL29 (PFC_BASE + 0x2948) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2A (PFC_BASE + 0x2950) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2B (PFC_BASE + 0x2958) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2C (PFC_BASE + 0x2960) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2D (PFC_BASE + 0x2968) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2E (PFC_BASE + 0x2970) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL2F (PFC_BASE + 0x2978) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL30 (PFC_BASE + 0x2980) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL31 (PFC_BASE + 0x2988) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL32 (PFC_BASE + 0x2990) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL33 (PFC_BASE + 0x2998) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL34 (PFC_BASE + 0x29A0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL35 (PFC_BASE + 0x29A8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL36 (PFC_BASE + 0x29B0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL37 (PFC_BASE + 0x29B8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL38 (PFC_BASE + 0x29C0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL39 (PFC_BASE + 0x29C8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3A (PFC_BASE + 0x29D0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3B (PFC_BASE + 0x29D8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3C (PFC_BASE + 0x29E0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3D (PFC_BASE + 0x29E8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3E (PFC_BASE + 0x29F0) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL3F (PFC_BASE + 0x29F8) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_FILCLKSEL40 (PFC_BASE + 0x2A00) /* Digital noise filter (FILCLKSEL) register */ +#define PFC_ETH_MII (PFC_BASE + 0x3018) /* Register for setting the mode of ETH MII/RGMII */ + +/* Combined terminal setting */ +/* Definition for port register */ +#define P_P0 (1 << 0) +#define P_P1 (1 << 1) +#define P_P2 (1 << 2) +#define P_P3 (1 << 3) +#define P_P4 (1 << 4) +#define P_P5 (1 << 5) +#define P_P6 (1 << 6) +#define P_P7 (1 << 7) +/* Definition for port mode register */ +#define PM0_HIZ (0 << 0) +#define PM0_IN (1 << 0) +#define PM0_OUT_DIS (2 << 0) +#define PM0_OUT_EN (3 << 0) +#define PM1_HIZ (0 << 2) +#define PM1_IN (1 << 2) +#define PM1_OUT_DIS (2 << 2) +#define PM1_OUT_EN (3 << 2) +#define PM2_HIZ (0 << 4) +#define PM2_IN (1 << 4) +#define PM2_OUT_DIS (2 << 4) +#define PM2_OUT_EN (3 << 4) +#define PM3_HIZ (0 << 6) +#define PM3_IN (1 << 6) +#define PM3_OUT_DIS (2 << 6) +#define PM3_OUT_EN (3 << 6) +#define PM4_HIZ (0 << 8) +#define PM4_IN (1 << 8) +#define PM4_OUT_DIS (2 << 8) +#define PM4_OUT_EN (3 << 8) +/* Definition for port mode control register */ +#define PMC_PMC0 (1 << 0) +#define PMC_PMC1 (1 << 1) +#define PMC_PMC2 (1 << 2) +#define PMC_PMC3 (1 << 3) +#define PMC_PMC4 (1 << 4) +#define PMC_PMC5 (1 << 5) +#define PMC_PMC6 (1 << 6) +#define PMC_PMC7 (1 << 7) +/* Definition for port function control register */ +#define PFC0_MODE0 (0 << 0) +#define PFC0_MODE1 (1 << 0) +#define PFC0_MODE2 (2 << 0) +#define PFC0_MODE3 (3 << 0) +#define PFC0_MODE4 (4 << 0) +#define PFC0_MODE5 (5 << 0) +#define PFC1_MODE0 (0 << 4) +#define PFC1_MODE1 (1 << 4) +#define PFC1_MODE2 (2 << 4) +#define PFC1_MODE3 (3 << 4) +#define PFC1_MODE4 (4 << 4) +#define PFC1_MODE5 (5 << 4) +#define PFC2_MODE0 (0 << 8) +#define PFC2_MODE1 (1 << 8) +#define PFC2_MODE2 (2 << 8) +#define PFC2_MODE3 (3 << 8) +#define PFC2_MODE4 (4 << 8) +#define PFC2_MODE5 (5 << 8) +#define PFC3_MODE0 (0 << 12) +#define PFC3_MODE1 (1 << 12) +#define PFC3_MODE2 (2 << 12) +#define PFC3_MODE3 (3 << 12) +#define PFC3_MODE4 (4 << 12) +#define PFC3_MODE5 (5 << 12) +#define PFC4_MODE0 (0 << 16) +#define PFC4_MODE1 (1 << 16) +#define PFC4_MODE2 (2 << 16) +#define PFC4_MODE3 (3 << 16) +#define PFC4_MODE4 (4 << 16) +#define PFC4_MODE5 (5 << 16) +/* Definition for IOLH switch register */ +#define IOLH0_2MA (0 << 0) +#define IOLH0_4MA (1 << 0) +#define IOLH0_8MA (2 << 0) +#define IOLH0_12MA (3 << 0) +#define IOLH1_2MA (0 << 8) +#define IOLH1_4MA (1 << 8) +#define IOLH1_8MA (2 << 8) +#define IOLH1_12MA (3 << 8) +#define IOLH2_2MA (0 << 16) +#define IOLH2_4MA (1 << 16) +#define IOLH2_8MA (2 << 16) +#define IOLH2_12MA (3 << 16) +#define IOLH3_2MA (0 << 24) +#define IOLH3_4MA (1 << 24) +#define IOLH3_8MA (2 << 24) +#define IOLH3_12MA (3 << 24) +#define IOLH4_2MA (0 << 32) +#define IOLH4_4MA (1 << 32) +#define IOLH4_8MA (2 << 32) +#define IOLH4_12MA (3 << 32) +#define IOLH5_2MA (0 << 40) +#define IOLH5_4MA (1 << 40) +#define IOLH5_8MA (2 << 40) +#define IOLH5_12MA (3 << 40) +#define IOLH6_2MA (0 << 48) +#define IOLH6_4MA (1 << 48) +#define IOLH6_8MA (2 << 48) +#define IOLH6_12MA (3 << 48) +#define IOLH7_2MA (0 << 56) +#define IOLH7_4MA (1 << 56) +#define IOLH7_8MA (2 << 56) +#define IOLH7_12MA (3 << 56) +/* Definition for Slew-Rate switch register */ +#define SR0_FAST (1 << 0) +#define SR1_FAST (1 << 8) +#define SR2_FAST (1 << 16) +#define SR3_FAST (1 << 24) +#define SR4_FAST (1 << 32) +#define SR5_FAST (1 << 40) +#define SR6_FAST (1 << 48) +#define SR7_FAST (1 << 56) +/* Definition for IEN switching register */ +#define IEN0_ENABLE (1 << 0) +#define IEN1_ENABLE (1 << 8) +#define IEN2_ENABLE (1 << 16) +#define IEN3_ENABLE (1 << 24) +#define IEN4_ENABLE (1 << 32) +#define IEN5_ENABLE (1 << 40) +#define IEN6_ENABLE (1 << 48) +#define IEN7_ENABLE (1 << 56) +/* Definition for PUPD switching register */ +#define PUPD0_NO (0 << 0) +#define PUPD0_UP (1 << 0) +#define PUPD0_DOWN (2 << 0) +#define PUPD1_NO (0 << 8) +#define PUPD1_UP (1 << 8) +#define PUPD1_DOWN (2 << 8) +#define PUPD2_NO (0 << 16) +#define PUPD2_UP (1 << 16) +#define PUPD2_DOWN (2 << 16) +#define PUPD3_NO (0 << 24) +#define PUPD3_UP (1 << 24) +#define PUPD3_DOWN (2 << 24) +#define PUPD4_NO (0 << 32) +#define PUPD4_UP (1 << 32) +#define PUPD4_DOWN (2 << 32) +#define PUPD5_NO (0 << 40) +#define PUPD5_UP (1 << 40) +#define PUPD5_DOWN (2 << 40) +#define PUPD6_NO (0 << 48) +#define PUPD6_UP (1 << 48) +#define PUPD6_DOWN (2 << 48) +#define PUPD7_NO (0 << 56) +#define PUPD7_UP (1 << 56) +#define PUPD7_DOWN (2 << 56) +/* SD ch0 IO Definition for voltage control register */ +#define SD0_PVDD (1 << 0) +/* SD ch1 IO Definition for voltage control register */ +#define SD1_PVDD (1 << 0) +/* Definition for QSPI IO voltage control register */ +#define QSPI_PVDD (1 << 0) +/* ETH ch0 voltage control register */ +#define ETH_ch0_3_3 (0 << 0) +#define ETH_ch0_1_8 (1 << 0) +#define ETH_ch0_2_5 (2 << 0) +/* ETH ch1 voltage control register */ +#define ETH_ch1_3_3 (0 << 0) +#define ETH_ch1_1_8 (1 << 0) +#define ETH_ch1_2_5 (2 << 0) +/* Write protection definition */ +#define PWPR_B0Wl (1 << 7) +#define PWPR_PFCWE (1 << 6) +/* Digital noise filter (FILONOFF) register */ +#define FILONOFF_FILON0 (1 << 0) +#define FILONOFF_FILON1 (1 << 8) +#define FILONOFF_FILON2 (1 << 16) +#define FILONOFF_FILON3 (1 << 24) +#define FILONOFF_FILON4 (1 << 32) +#define FILONOFF_FILON5 (1 << 40) +#define FILONOFF_FILON6 (1 << 48) +#define FILONOFF_FILON7 (1 << 56) +/* Digital noise filter (FILNUM) register */ +#define FILNUM_FILNUM0_4 (0 << 0) +#define FILNUM_FILNUM0_8 (1 << 0) +#define FILNUM_FILNUM0_12 (2 << 0) +#define FILNUM_FILNUM0_16 (3 << 0) +#define FILNUM_FILNUM1_4 (0 << 8) +#define FILNUM_FILNUM1_8 (1 << 8) +#define FILNUM_FILNUM1_12 (2 << 8) +#define FILNUM_FILNUM1_16 (3 << 8) +#define FILNUM_FILNUM2_4 (0 << 16) +#define FILNUM_FILNUM2_8 (1 << 16) +#define FILNUM_FILNUM2_12 (2 << 16) +#define FILNUM_FILNUM2_16 (3 << 16) +#define FILNUM_FILNUM3_4 (0 << 24) +#define FILNUM_FILNUM3_8 (1 << 24) +#define FILNUM_FILNUM3_12 (2 << 24) +#define FILNUM_FILNUM3_16 (3 << 24) +#define FILNUM_FILNUM4_4 (0 << 32) +#define FILNUM_FILNUM4_8 (1 << 32) +#define FILNUM_FILNUM4_12 (2 << 32) +#define FILNUM_FILNUM4_16 (3 << 32) +#define FILNUM_FILNUM5_4 (0 << 40) +#define FILNUM_FILNUM5_8 (1 << 40) +#define FILNUM_FILNUM5_12 (2 << 40) +#define FILNUM_FILNUM5_16 (3 << 40) +#define FILNUM_FILNUM6_4 (0 << 48) +#define FILNUM_FILNUM6_8 (1 << 48) +#define FILNUM_FILNUM6_12 (2 << 48) +#define FILNUM_FILNUM6_16 (3 << 48) +#define FILNUM_FILNUM7_4 (0 << 56) +#define FILNUM_FILNUM7_8 (1 << 56) +#define FILNUM_FILNUM7_12 (2 << 56) +#define FILNUM_FILNUM7_16 (3 << 56) +/* Digital noise filter (FILCLKSEL) register */ +#define FILCLKSEL_FILCLK0_0 (0 << 0) +#define FILCLKSEL_FILCLK0_1 (1 << 0) +#define FILCLKSEL_FILCLK0_2 (2 << 0) +#define FILCLKSEL_FILCLK0_3 (3 << 0) +#define FILCLKSEL_FILCLK1_0 (0 << 8) +#define FILCLKSEL_FILCLK1_1 (1 << 8) +#define FILCLKSEL_FILCLK1_2 (2 << 8) +#define FILCLKSEL_FILCLK1_3 (3 << 8) +#define FILCLKSEL_FILCLK2_0 (0 << 16) +#define FILCLKSEL_FILCLK2_1 (1 << 16) +#define FILCLKSEL_FILCLK2_2 (2 << 16) +#define FILCLKSEL_FILCLK2_3 (3 << 16) +#define FILCLKSEL_FILCLK3_0 (0 << 24) +#define FILCLKSEL_FILCLK3_1 (1 << 24) +#define FILCLKSEL_FILCLK3_2 (2 << 24) +#define FILCLKSEL_FILCLK3_3 (3 << 24) +#define FILCLKSEL_FILCLK4_0 (0 << 32) +#define FILCLKSEL_FILCLK4_1 (1 << 32) +#define FILCLKSEL_FILCLK4_2 (2 << 32) +#define FILCLKSEL_FILCLK4_3 (3 << 32) +#define FILCLKSEL_FILCLK5_0 (0 << 40) +#define FILCLKSEL_FILCLK5_1 (1 << 40) +#define FILCLKSEL_FILCLK5_2 (2 << 40) +#define FILCLKSEL_FILCLK5_3 (3 << 40) +#define FILCLKSEL_FILCLK6_0 (0 << 48) +#define FILCLKSEL_FILCLK6_1 (1 << 48) +#define FILCLKSEL_FILCLK6_2 (2 << 48) +#define FILCLKSEL_FILCLK6_3 (3 << 48) +#define FILCLKSEL_FILCLK7_0 (0 << 56) +#define FILCLKSEL_FILCLK7_1 (1 << 56) +#define FILCLKSEL_FILCLK7_2 (2 << 56) +#define FILCLKSEL_FILCLK7_3 (3 << 56) +/* Register for setting the mode of ETH MII / RGMII */ +#define ETH_MII_0_MII (1 << 0) +#define ETH_MII_1_MII (1 << 1) + +#define PFC_SET_TBL_NUM (11) +#define PFC_OFF (0) +#define PFC_ON (1) + +#define PFC_MUX_TBL_NUM (4) +#define PFC_QSPI_TBL_NUM (3) +#define PFC_SD_TBL_NUM (4) + +typedef struct { + int flg; + uintptr_t reg; + uint8_t val; +} PFC_REG_UINT8; + +typedef struct { + int flg; + uintptr_t reg; + uint32_t val; +} PFC_REG_UINT32; + +typedef struct { + int flg; + uintptr_t reg; + uint64_t val; +} PFC_REG_UINT64; + + +typedef struct { + PFC_REG_UINT8 pmc; + PFC_REG_UINT32 pfc; + PFC_REG_UINT64 iolh; + PFC_REG_UINT64 pupd; + PFC_REG_UINT64 sr; + PFC_REG_UINT64 ien; +} PFC_REGS; + + +#endif /* __PFC_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/spim.h b/include/drivers/renesas/rza/spim/spim.h similarity index 100% rename from plat/renesas/rza/common/include/spim.h rename to include/drivers/renesas/rza/spim/spim.h diff --git a/plat/renesas/rza/common/include/spim_regs.h b/include/drivers/renesas/rza/spim/spim_regs.h similarity index 100% rename from plat/renesas/rza/common/include/spim_regs.h rename to include/drivers/renesas/rza/spim/spim_regs.h diff --git a/plat/renesas/rza/common/include/syc.h b/include/drivers/renesas/rza/syc/syc.h similarity index 100% rename from plat/renesas/rza/common/include/syc.h rename to include/drivers/renesas/rza/syc/syc.h diff --git a/plat/renesas/rza/common/include/sys.h b/include/drivers/renesas/rza/sys/sys.h similarity index 100% rename from plat/renesas/rza/common/include/sys.h rename to include/drivers/renesas/rza/sys/sys.h diff --git a/plat/renesas/rza/common/include/sys_regs.h b/include/drivers/renesas/rza/sys/sys_regs.h similarity index 65% rename from plat/renesas/rza/common/include/sys_regs.h rename to include/drivers/renesas/rza/sys/sys_regs.h index 5512375c3e..7579e47952 100644 --- a/plat/renesas/rza/common/include/sys_regs.h +++ b/include/drivers/renesas/rza/sys/sys_regs.h @@ -7,146 +7,146 @@ #ifndef __SYS_REGS_H__ #define __SYS_REGS_H__ -#define SYS_BASE (0x11020000) +#define SYS_BASE (0x11020000) -#define SYS_MSTACCCTL0 (SYS_BASE + 0x00000000) -#define SYS_MSTACCCTL1 (SYS_BASE + 0x00000004) -#define SYS_MSTACCCTL2 (SYS_BASE + 0x00000008) -#define SYS_MSTACCCTL3 (SYS_BASE + 0x0000000C) -#define SYS_MSTACCCTL4 (SYS_BASE + 0x00000010) -#define SYS_MSTACCCTL5 (SYS_BASE + 0x00000014) -#define SYS_SLVACCCTL0 (SYS_BASE + 0x00000100) -#define SYS_SLVACCCTL1 (SYS_BASE + 0x00000104) -#define SYS_SLVACCCTL2 (SYS_BASE + 0x00000108) -#define SYS_SLVACCCTL3 (SYS_BASE + 0x0000010C) -#define SYS_SLVACCCTL4 (SYS_BASE + 0x00000110) -#define SYS_SLVACCCTL5 (SYS_BASE + 0x00000114) -#define SYS_SLVACCCTL6 (SYS_BASE + 0x00000118) -#define SYS_SLVACCCTL7 (SYS_BASE + 0x0000011C) -#define SYS_SLVACCCTL8 (SYS_BASE + 0x00000120) -#define SYS_SLVACCCTL9 (SYS_BASE + 0x00000124) -#define SYS_SLVACCCTL10 (SYS_BASE + 0x00000128) -#define SYS_SLVACCCTL11 (SYS_BASE + 0x0000012C) -#define SYS_SLVACCCTL12 (SYS_BASE + 0x00000130) -#define SYS_SLVACCCTL13 (SYS_BASE + 0x00000134) -#define SYS_SLVACCCTL14 (SYS_BASE + 0x00000138) -#define SYS_SLVACCCTL15 (SYS_BASE + 0x0000013C) -#define SYS_RAM0_ECC (SYS_BASE + 0x00000200) -#define SYS_RAM0_EN (SYS_BASE + 0x00000204) -#define SYS_RAM0_TEST (SYS_BASE + 0x00000208) -#define SYS_RAM0_MON (SYS_BASE + 0x0000020C) -#define SYS_RAM1_ECC (SYS_BASE + 0x00000210) -#define SYS_RAM1_EN (SYS_BASE + 0x00000214) -#define SYS_RAM1_TEST (SYS_BASE + 0x00000218) -#define SYS_RAM1_MON (SYS_BASE + 0x0000021C) -#define SYS_WDT0_CTRL (SYS_BASE + 0x00000220) -#define SYS_WDT1_CTRL (SYS_BASE + 0x00000230) -#define SYS_WDT2_CTRL (SYS_BASE + 0x00000240) -#define SYS_WDT3_CTRL (SYS_BASE + 0x00000250) -#define SYS_GPU_COHE (SYS_BASE + 0x00000300) -#define SYS_GPU_STRP (SYS_BASE + 0x00000304) -#define SYS_GPU_TEXT (SYS_BASE + 0x00000308) -#define SYS_H264_CFG0 (SYS_BASE + 0x00000310) -#define SYS_H264_CFG1 (SYS_BASE + 0x00000314) -#define SYS_H264_CFG2 (SYS_BASE + 0x00000318) -#define SYS_H264_MON (SYS_BASE + 0x0000031C) -#define SYS_H264_BSTOP (SYS_BASE + 0x00000320) -#define SYS_GETH0_CFG (SYS_BASE + 0x00000330) -#define SYS_GETH1_CFG (SYS_BASE + 0x00000340) -#define SYS_I2C0_CFG (SYS_BASE + 0x00000400) -#define SYS_I2C1_CFG (SYS_BASE + 0x00000410) -#define SYS_I2C2_CFG (SYS_BASE + 0x00000420) -#define SYS_I2C3_CFG (SYS_BASE + 0x00000430) -#define SYS_CANFD_CFG (SYS_BASE + 0x00000440) -#define SYS_SCIF0_CFG (SYS_BASE + 0x00000450) -#define SYS_SCIF1_CFG (SYS_BASE + 0x00000460) -#define SYS_SCIF2_CFG (SYS_BASE + 0x00000470) -#define SYS_SCIF3_CFG (SYS_BASE + 0x00000480) -#define SYS_SCIF4_CFG (SYS_BASE + 0x00000490) -#define SYS_SCI0_CFG (SYS_BASE + 0x000004A0) -#define SYS_SCI1_CFG (SYS_BASE + 0x000004B0) -#define SYS_CM33_STAT (SYS_BASE + 0x00000800) -#define SYS_CM33_CFG0 (SYS_BASE + 0x00000804) -#define SYS_CM33_CFG1 (SYS_BASE + 0x00000808) -#define SYS_CM33_CFG2 (SYS_BASE + 0x0000080C) -#define SYS_CM33_CFG3 (SYS_BASE + 0x00000810) -#define SYS_CM33_LOCK (SYS_BASE + 0x00000814) -#define SYS_CM33_CTL (SYS_BASE + 0x00000818) -#define SYS_CA55_CFG_AArch0 (SYS_BASE + 0x00000840) -#define SYS_CA55_CFG_AArch1 (SYS_BASE + 0x00000844) +#define SYS_MSTACCCTL0 (SYS_BASE + 0x00000000) +#define SYS_MSTACCCTL1 (SYS_BASE + 0x00000004) +#define SYS_MSTACCCTL2 (SYS_BASE + 0x00000008) +#define SYS_MSTACCCTL3 (SYS_BASE + 0x0000000C) +#define SYS_MSTACCCTL4 (SYS_BASE + 0x00000010) +#define SYS_MSTACCCTL5 (SYS_BASE + 0x00000014) +#define SYS_SLVACCCTL0 (SYS_BASE + 0x00000100) +#define SYS_SLVACCCTL1 (SYS_BASE + 0x00000104) +#define SYS_SLVACCCTL2 (SYS_BASE + 0x00000108) +#define SYS_SLVACCCTL3 (SYS_BASE + 0x0000010C) +#define SYS_SLVACCCTL4 (SYS_BASE + 0x00000110) +#define SYS_SLVACCCTL5 (SYS_BASE + 0x00000114) +#define SYS_SLVACCCTL6 (SYS_BASE + 0x00000118) +#define SYS_SLVACCCTL7 (SYS_BASE + 0x0000011C) +#define SYS_SLVACCCTL8 (SYS_BASE + 0x00000120) +#define SYS_SLVACCCTL9 (SYS_BASE + 0x00000124) +#define SYS_SLVACCCTL10 (SYS_BASE + 0x00000128) +#define SYS_SLVACCCTL11 (SYS_BASE + 0x0000012C) +#define SYS_SLVACCCTL12 (SYS_BASE + 0x00000130) +#define SYS_SLVACCCTL13 (SYS_BASE + 0x00000134) +#define SYS_SLVACCCTL14 (SYS_BASE + 0x00000138) +#define SYS_SLVACCCTL15 (SYS_BASE + 0x0000013C) +#define SYS_RAM0_ECC (SYS_BASE + 0x00000200) +#define SYS_RAM0_EN (SYS_BASE + 0x00000204) +#define SYS_RAM0_TEST (SYS_BASE + 0x00000208) +#define SYS_RAM0_MON (SYS_BASE + 0x0000020C) +#define SYS_RAM1_ECC (SYS_BASE + 0x00000210) +#define SYS_RAM1_EN (SYS_BASE + 0x00000214) +#define SYS_RAM1_TEST (SYS_BASE + 0x00000218) +#define SYS_RAM1_MON (SYS_BASE + 0x0000021C) +#define SYS_WDT0_CTRL (SYS_BASE + 0x00000220) +#define SYS_WDT1_CTRL (SYS_BASE + 0x00000230) +#define SYS_WDT2_CTRL (SYS_BASE + 0x00000240) +#define SYS_WDT3_CTRL (SYS_BASE + 0x00000250) +#define SYS_GPU_COHE (SYS_BASE + 0x00000300) +#define SYS_GPU_STRP (SYS_BASE + 0x00000304) +#define SYS_GPU_TEXT (SYS_BASE + 0x00000308) +#define SYS_H264_CFG0 (SYS_BASE + 0x00000310) +#define SYS_H264_CFG1 (SYS_BASE + 0x00000314) +#define SYS_H264_CFG2 (SYS_BASE + 0x00000318) +#define SYS_H264_MON (SYS_BASE + 0x0000031C) +#define SYS_H264_BSTOP (SYS_BASE + 0x00000320) +#define SYS_GETH0_CFG (SYS_BASE + 0x00000330) +#define SYS_GETH1_CFG (SYS_BASE + 0x00000340) +#define SYS_I2C0_CFG (SYS_BASE + 0x00000400) +#define SYS_I2C1_CFG (SYS_BASE + 0x00000410) +#define SYS_I2C2_CFG (SYS_BASE + 0x00000420) +#define SYS_I2C3_CFG (SYS_BASE + 0x00000430) +#define SYS_CANFD_CFG (SYS_BASE + 0x00000440) +#define SYS_SCIF0_CFG (SYS_BASE + 0x00000450) +#define SYS_SCIF1_CFG (SYS_BASE + 0x00000460) +#define SYS_SCIF2_CFG (SYS_BASE + 0x00000470) +#define SYS_SCIF3_CFG (SYS_BASE + 0x00000480) +#define SYS_SCIF4_CFG (SYS_BASE + 0x00000490) +#define SYS_SCI0_CFG (SYS_BASE + 0x000004A0) +#define SYS_SCI1_CFG (SYS_BASE + 0x000004B0) +#define SYS_CM33_STAT (SYS_BASE + 0x00000800) +#define SYS_CM33_CFG0 (SYS_BASE + 0x00000804) +#define SYS_CM33_CFG1 (SYS_BASE + 0x00000808) +#define SYS_CM33_CFG2 (SYS_BASE + 0x0000080C) +#define SYS_CM33_CFG3 (SYS_BASE + 0x00000810) +#define SYS_CM33_LOCK (SYS_BASE + 0x00000814) +#define SYS_CM33_CTL (SYS_BASE + 0x00000818) +#define SYS_CA55_CFG_AArch0 (SYS_BASE + 0x00000840) +#define SYS_CA55_CFG_AArch1 (SYS_BASE + 0x00000844) #define SYS_CA55_CFG_Endian0 (SYS_BASE + 0x00000848) #define SYS_CA55_CFG_Endian1 (SYS_BASE + 0x0000084C) -#define SYS_CA55_CFG_Thumb0 (SYS_BASE + 0x00000850) -#define SYS_CA55_CFG_Thumb1 (SYS_BASE + 0x00000854) -#define SYS_CA55_CFG_RVAL0 (SYS_BASE + 0x00000858) -#define SYS_CA55_CFG_RVAH0 (SYS_BASE + 0x0000085C) -#define SYS_CA55_CFG_RVAL1 (SYS_BASE + 0x00000860) -#define SYS_CA55_CFG_RVAH1 (SYS_BASE + 0x00000864) -#define SYS_CA55_CFG_VA0 (SYS_BASE + 0x00000868) -#define SYS_CA55_CFG_VA1 (SYS_BASE + 0x0000086C) -#define SYS_BBG_CTRL_ENABLE (SYS_BASE + 0x00000900) -#define SYS_BBG_CTRL (SYS_BASE + 0x00000904) -#define SYS_BBG_CTRL_MON (SYS_BASE + 0x00000908) -#define SYS_BBG_OFFSET0 (SYS_BASE + 0x0000090C) -#define SYS_BBG_OFFSET1 (SYS_BASE + 0x00000910) -#define SYS_BBG_OFFSET2 (SYS_BASE + 0x00000914) -#define SYS_BBG_OFFSET3 (SYS_BASE + 0x00000918) -#define SYS_BBG_OFFSET4 (SYS_BASE + 0x0000091C) -#define SYS_BBG_OFFSET5 (SYS_BASE + 0x00000920) -#define SYS_BBG_OFFSET6 (SYS_BASE + 0x00000924) -#define SYS_BBG_OFFSET7 (SYS_BASE + 0x00000928) -#define SYS_BBG_OFFSET_CTRL (SYS_BASE + 0x00000930) -#define SYS_BBG_PFREQ_MON (SYS_BASE + 0x00000934) -#define SYS_BBG_NFREQ_MON (SYS_BASE + 0x00000938) -#define SYS_BBG_TEMP_MON (SYS_BASE + 0x0000093C) -#define SYS_BBG_VOLT_MON (SYS_BASE + 0x00000940) -#define SYS_LSI_MODE (SYS_BASE + 0x00000A00) -#define SYS_LSI_DEVID (SYS_BASE + 0x00000A04) -#define SYS_LSI_PRR (SYS_BASE + 0x00000A08) -#define SYS_LSI_OTPSECEN (SYS_BASE + 0x00000A0C) -#define SYS_LSI_OTPSECMODE (SYS_BASE + 0x00000A10) -#define SYS_LSI_OTPJAM (SYS_BASE + 0x00000A14) -#define SYS_LSI_OTPCORE (SYS_BASE + 0x00000A18) -#define SYS_LSI_OTPPOC (SYS_BASE + 0x00000A20) -#define SYS_JAUTH_JUDGE (SYS_BASE + 0x00000B00) -#define SYS_AOF0 (SYS_BASE + 0x00000C00) -#define SYS_AOF1 (SYS_BASE + 0x00000C04) -#define SYS_AOF2 (SYS_BASE + 0x00000C08) -#define SYS_AOF3 (SYS_BASE + 0x00000C0C) -#define SYS_AOF4 (SYS_BASE + 0x00000C10) -#define SYS_AOF5 (SYS_BASE + 0x00000C14) -#define SYS_AOF6 (SYS_BASE + 0x00000C18) -#define SYS_AOF7 (SYS_BASE + 0x00000C1C) -#define SYS_AOF8 (SYS_BASE + 0x00000C20) -#define SYS_LP_CTL0 (SYS_BASE + 0x00000D00) -#define SYS_LP_CTL1 (SYS_BASE + 0x00000D04) -#define SYS_LP_CTL2 (SYS_BASE + 0x00000D08) -#define SYS_LP_CTL3 (SYS_BASE + 0x00000D0C) -#define SYS_LP_CTL4 (SYS_BASE + 0x00000D10) -#define SYS_LP_CTL5 (SYS_BASE + 0x00000D14) -#define SYS_LP_CTL6 (SYS_BASE + 0x00000D18) -#define SYS_LP_CTL7 (SYS_BASE + 0x00000D1C) -#define SYS_LP_CTL8 (SYS_BASE + 0x00000D20) -#define SYS_LP_CM33CTL0 (SYS_BASE + 0x00000D24) -#define SYS_LP_CM33CTL1 (SYS_BASE + 0x00000D28) -#define SYS_LP_CM33CTL2 (SYS_BASE + 0x00000D2C) -#define SYS_LP_CM33CPG (SYS_BASE + 0x00000D30) -#define SYS_LP_CA55_CTL0 (SYS_BASE + 0x00000D34) -#define SYS_LP_CA55CK_CTL1 (SYS_BASE + 0x00000D38) -#define SYS_LP_CA55CK_CTL2 (SYS_BASE + 0x00000D3C) -#define SYS_LP_CA55CK_CTL3 (SYS_BASE + 0x00000D40) -#define SYS_LP_CA55CPGC0 (SYS_BASE + 0x00000D44) -#define SYS_LP_CA55CPGC1 (SYS_BASE + 0x00000D48) -#define SYS_LP_GPU_CTL (SYS_BASE + 0x00000D50) -#define SYS_GPREG_0 (SYS_BASE + 0x00000E00) -#define SYS_GPREG_1 (SYS_BASE + 0x00000E04) -#define SYS_GPREG_2 (SYS_BASE + 0x00000E08) -#define SYS_GPREG_3 (SYS_BASE + 0x00000E0C) -#define SYS_RESREG_0 (SYS_BASE + 0x00000E10) -#define SYS_RESREG_1 (SYS_BASE + 0x00000E14) -#define SYS_RESREG_2 (SYS_BASE + 0x00000E18) -#define SYS_RESREG_3 (SYS_BASE + 0x00000E1C) -#define SYS_IPCONT (SYS_BASE + 0x00000E20) +#define SYS_CA55_CFG_Thumb0 (SYS_BASE + 0x00000850) +#define SYS_CA55_CFG_Thumb1 (SYS_BASE + 0x00000854) +#define SYS_CA55_CFG_RVAL0 (SYS_BASE + 0x00000858) +#define SYS_CA55_CFG_RVAH0 (SYS_BASE + 0x0000085C) +#define SYS_CA55_CFG_RVAL1 (SYS_BASE + 0x00000860) +#define SYS_CA55_CFG_RVAH1 (SYS_BASE + 0x00000864) +#define SYS_CA55_CFG_VA0 (SYS_BASE + 0x00000868) +#define SYS_CA55_CFG_VA1 (SYS_BASE + 0x0000086C) +#define SYS_BBG_CTRL_ENABLE (SYS_BASE + 0x00000900) +#define SYS_BBG_CTRL (SYS_BASE + 0x00000904) +#define SYS_BBG_CTRL_MON (SYS_BASE + 0x00000908) +#define SYS_BBG_OFFSET0 (SYS_BASE + 0x0000090C) +#define SYS_BBG_OFFSET1 (SYS_BASE + 0x00000910) +#define SYS_BBG_OFFSET2 (SYS_BASE + 0x00000914) +#define SYS_BBG_OFFSET3 (SYS_BASE + 0x00000918) +#define SYS_BBG_OFFSET4 (SYS_BASE + 0x0000091C) +#define SYS_BBG_OFFSET5 (SYS_BASE + 0x00000920) +#define SYS_BBG_OFFSET6 (SYS_BASE + 0x00000924) +#define SYS_BBG_OFFSET7 (SYS_BASE + 0x00000928) +#define SYS_BBG_OFFSET_CTRL (SYS_BASE + 0x00000930) +#define SYS_BBG_PFREQ_MON (SYS_BASE + 0x00000934) +#define SYS_BBG_NFREQ_MON (SYS_BASE + 0x00000938) +#define SYS_BBG_TEMP_MON (SYS_BASE + 0x0000093C) +#define SYS_BBG_VOLT_MON (SYS_BASE + 0x00000940) +#define SYS_LSI_MODE (SYS_BASE + 0x00000A00) +#define SYS_LSI_DEVID (SYS_BASE + 0x00000A04) +#define SYS_LSI_PRR (SYS_BASE + 0x00000A08) +#define SYS_LSI_OTPSECEN (SYS_BASE + 0x00000A0C) +#define SYS_LSI_OTPSECMODE (SYS_BASE + 0x00000A10) +#define SYS_LSI_OTPJAM (SYS_BASE + 0x00000A14) +#define SYS_LSI_OTPCORE (SYS_BASE + 0x00000A18) +#define SYS_LSI_OTPPOC (SYS_BASE + 0x00000A20) +#define SYS_JAUTH_JUDGE (SYS_BASE + 0x00000B00) +#define SYS_AOF0 (SYS_BASE + 0x00000C00) +#define SYS_AOF1 (SYS_BASE + 0x00000C04) +#define SYS_AOF2 (SYS_BASE + 0x00000C08) +#define SYS_AOF3 (SYS_BASE + 0x00000C0C) +#define SYS_AOF4 (SYS_BASE + 0x00000C10) +#define SYS_AOF5 (SYS_BASE + 0x00000C14) +#define SYS_AOF6 (SYS_BASE + 0x00000C18) +#define SYS_AOF7 (SYS_BASE + 0x00000C1C) +#define SYS_AOF8 (SYS_BASE + 0x00000C20) +#define SYS_LP_CTL0 (SYS_BASE + 0x00000D00) +#define SYS_LP_CTL1 (SYS_BASE + 0x00000D04) +#define SYS_LP_CTL2 (SYS_BASE + 0x00000D08) +#define SYS_LP_CTL3 (SYS_BASE + 0x00000D0C) +#define SYS_LP_CTL4 (SYS_BASE + 0x00000D10) +#define SYS_LP_CTL5 (SYS_BASE + 0x00000D14) +#define SYS_LP_CTL6 (SYS_BASE + 0x00000D18) +#define SYS_LP_CTL7 (SYS_BASE + 0x00000D1C) +#define SYS_LP_CTL8 (SYS_BASE + 0x00000D20) +#define SYS_LP_CM33CTL0 (SYS_BASE + 0x00000D24) +#define SYS_LP_CM33CTL1 (SYS_BASE + 0x00000D28) +#define SYS_LP_CM33CTL2 (SYS_BASE + 0x00000D2C) +#define SYS_LP_CM33CPG (SYS_BASE + 0x00000D30) +#define SYS_LP_CA55_CTL0 (SYS_BASE + 0x00000D34) +#define SYS_LP_CA55CK_CTL1 (SYS_BASE + 0x00000D38) +#define SYS_LP_CA55CK_CTL2 (SYS_BASE + 0x00000D3C) +#define SYS_LP_CA55CK_CTL3 (SYS_BASE + 0x00000D40) +#define SYS_LP_CA55CPGC0 (SYS_BASE + 0x00000D44) +#define SYS_LP_CA55CPGC1 (SYS_BASE + 0x00000D48) +#define SYS_LP_GPU_CTL (SYS_BASE + 0x00000D50) +#define SYS_GPREG_0 (SYS_BASE + 0x00000E00) +#define SYS_GPREG_1 (SYS_BASE + 0x00000E04) +#define SYS_GPREG_2 (SYS_BASE + 0x00000E08) +#define SYS_GPREG_3 (SYS_BASE + 0x00000E0C) +#define SYS_RESREG_0 (SYS_BASE + 0x00000E10) +#define SYS_RESREG_1 (SYS_BASE + 0x00000E14) +#define SYS_RESREG_2 (SYS_BASE + 0x00000E18) +#define SYS_RESREG_3 (SYS_BASE + 0x00000E1C) +#define SYS_IPCONT (SYS_BASE + 0x00000E20) #define MSTACCCTL0_DMAC0_AWPU (1 << 0) #define MSTACCCTL0_DMAC0_AWNS (1 << 1) @@ -160,11 +160,11 @@ #define MSTACCCTL0_DMAC1_ARRU (1 << 12) #define MSTACCCTL0_DMAC1_ARNS (1 << 13) #define MSTACCCTL0_DMAC1_ARSEL (1 << 15) -#define MSTACCCTL0_GPU_AWPU (1 << 16) -#define MSTACCCTL0_GPU_AWNS (1 << 17) +#define MSTACCCTL0_GPU_AWPU (1 << 16) +#define MSTACCCTL0_GPU_AWNS (1 << 17) #define MSTACCCTL0_GPU_AWSEL (1 << 19) -#define MSTACCCTL0_GPU_ARRU (1 << 20) -#define MSTACCCTL0_GPU_ARNS (1 << 21) +#define MSTACCCTL0_GPU_ARRU (1 << 20) +#define MSTACCCTL0_GPU_ARNS (1 << 21) #define MSTACCCTL0_GPU_ARSEL (1 << 23) #define MSTACCCTL1_SDHI0_AWPU (1 << 0) #define MSTACCCTL1_SDHI0_AWNS (1 << 1) @@ -220,17 +220,17 @@ #define MSTACCCTL3_LCDC_ARRU (1 << 12) #define MSTACCCTL3_LCDC_ARNS (1 << 13) #define MSTACCCTL3_LCDC_ARSEL (1 << 15) -#define MSTACCCTL3_DSI_AWPU (1 << 16) -#define MSTACCCTL3_DSI_AWNS (1 << 17) +#define MSTACCCTL3_DSI_AWPU (1 << 16) +#define MSTACCCTL3_DSI_AWNS (1 << 17) #define MSTACCCTL3_DSI_AWSEL (1 << 19) -#define MSTACCCTL3_DSI_ARRU (1 << 20) -#define MSTACCCTL3_DSI_ARNS (1 << 21) +#define MSTACCCTL3_DSI_ARRU (1 << 20) +#define MSTACCCTL3_DSI_ARNS (1 << 21) #define MSTACCCTL3_DSI_ARSEL (1 << 23) -#define MSTACCCTL4_ISU_AWPU (1 << 0) -#define MSTACCCTL4_ISU_AWNS (1 << 1) +#define MSTACCCTL4_ISU_AWPU (1 << 0) +#define MSTACCCTL4_ISU_AWNS (1 << 1) #define MSTACCCTL4_ISU_AWSEL (1 << 3) -#define MSTACCCTL4_ISU_ARRU (1 << 4) -#define MSTACCCTL4_ISU_ARNS (1 << 5) +#define MSTACCCTL4_ISU_ARRU (1 << 4) +#define MSTACCCTL4_ISU_ARNS (1 << 5) #define MSTACCCTL4_ISU_ARSEL (1 << 7) #define MSTACCCTL4_CRU_VD_AWPU (1 << 16) #define MSTACCCTL4_CRU_VD_AWNS (1 << 17) @@ -284,22 +284,22 @@ #define SLVACCCTL0_GPV_REG0_SL_11 (3 << 8) #define SLVACCCTL0_GPV_REG1_SL_10 (2 << 10) #define SLVACCCTL0_GPV_REG1_SL_11 (3 << 10) -#define SLVACCCTL0_GPV_PERIVIDEO_SL_10 (2 << 12) -#define SLVACCCTL0_GPV_PERIVIDEO_SL_11 (3 << 12) -#define SLVACCCTL0_GPV_PERICPU_SL_10 (2 << 14) -#define SLVACCCTL0_GPV_PERICPU_SL_11 (3 << 14) -#define SLVACCCTL0_GPV_PERIDDR_SL_10 (2 << 16) -#define SLVACCCTL0_GPV_PERIDDR_SL_11 (3 << 16) -#define SLVACCCTL0_GPV_PERICOM_SL_10 (2 << 18) -#define SLVACCCTL0_GPV_PERICOM_SL_11 (3 << 18) +#define SLVACCCTL0_GPV_PERIVIDEO_SL_10 (2 << 12) +#define SLVACCCTL0_GPV_PERIVIDEO_SL_11 (3 << 12) +#define SLVACCCTL0_GPV_PERICPU_SL_10 (2 << 14) +#define SLVACCCTL0_GPV_PERICPU_SL_11 (3 << 14) +#define SLVACCCTL0_GPV_PERIDDR_SL_10 (2 << 16) +#define SLVACCCTL0_GPV_PERIDDR_SL_11 (3 << 16) +#define SLVACCCTL0_GPV_PERICOM_SL_10 (2 << 18) +#define SLVACCCTL0_GPV_PERICOM_SL_11 (3 << 18) #define SLVACCCTL0_GPV_MXCOM_SL_10 (2 << 20) #define SLVACCCTL0_GPV_MXCOM_SL_11 (3 << 20) -#define SLVACCCTL0_GPV_MXVIDEO_SL_10 (2 << 22) -#define SLVACCCTL0_GPV_MXVIDEO_SL_11 (3 << 22) +#define SLVACCCTL0_GPV_MXVIDEO_SL_10 (2 << 22) +#define SLVACCCTL0_GPV_MXVIDEO_SL_11 (3 << 22) #define SLVACCCTL0_GPV_MXDRP_SL_10 (2 << 24) #define SLVACCCTL0_GPV_MXDRP_SL_11 (3 << 24) -#define SLVACCCTL0_GPV_PERISTP_SL_10 (2 << 26) -#define SLVACCCTL0_GPV_PERISTP_SL_11 (3 << 26) +#define SLVACCCTL0_GPV_PERISTP_SL_10 (2 << 26) +#define SLVACCCTL0_GPV_PERISTP_SL_11 (3 << 26) #define SLVACCCTL1_TZC0_SL_10 (2 << 0) #define SLVACCCTL1_TZC0_SL_11 (3 << 0) #define SLVACCCTL1_TZC1_SL_10 (2 << 2) @@ -560,10 +560,10 @@ #define SLVACCCTL12_AOF_SL_01 (1 << 0) #define SLVACCCTL12_AOF_SL_10 (2 << 0) #define SLVACCCTL12_AOF_SL_11 (3 << 0) -#define SLVACCCTL13LP_SL_00 (0 << 0) -#define SLVACCCTL13LP_SL_01 (1 << 0) -#define SLVACCCTL13LP_SL_10 (2 << 0) -#define SLVACCCTL13LP_SL_11 (3 << 0) +#define SLVACCCTL13LP_SL_00 (0 << 0) +#define SLVACCCTL13LP_SL_01 (1 << 0) +#define SLVACCCTL13LP_SL_10 (2 << 0) +#define SLVACCCTL13LP_SL_11 (3 << 0) #define SLVACCCTL14_GPREG_SL_00 (0 << 0) #define SLVACCCTL14_GPREG_SL_01 (1 << 0) #define SLVACCCTL14_GPREG_SL_10 (2 << 0) @@ -572,37 +572,37 @@ #define SLVACCCTL15_RESREG_SL_01 (1 << 0) #define SLVACCCTL15_RESREG_SL_10 (2 << 0) #define SLVACCCTL15_RESREG_SL_11 (3 << 0) -#define RAM0_ECC_VECCEN (1 << 0) -#define RAM0_ECC_EC7TERVE (1 << 1) -#define RAM0_EN_VCEN (1 << 0) -#define RAM0_EN_VLWEN (1 << 1) -#define RAM0_TEST_READTEST (1 << 0) -#define RAM0_MON_RAMON_O (1 << 0) -#define RAM1_ECC_VECCEN (1 << 0) -#define RAM1_ECC_EC7TERVE (1 << 1) -#define RAM1_EN_VCEN (1 << 0) -#define RAM1_EN_VLWEN (1 << 1) -#define RAM1_TEST_READTEST (1 << 0) -#define RAM1_MON_RAMON_O (1 << 0) -#define WDT0_CTRL_WDTSTOP (1 << 0) +#define RAM0_ECC_VECCEN (1 << 0) +#define RAM0_ECC_EC7TERVE (1 << 1) +#define RAM0_EN_VCEN (1 << 0) +#define RAM0_EN_VLWEN (1 << 1) +#define RAM0_TEST_READTEST (1 << 0) +#define RAM0_MON_RAMON_O (1 << 0) +#define RAM1_ECC_VECCEN (1 << 0) +#define RAM1_ECC_EC7TERVE (1 << 1) +#define RAM1_EN_VCEN (1 << 0) +#define RAM1_EN_VLWEN (1 << 1) +#define RAM1_TEST_READTEST (1 << 0) +#define RAM1_MON_RAMON_O (1 << 0) +#define WDT0_CTRL_WDTSTOP (1 << 0) #define WDT0_CTRL_WDTSTOPMASK (1 << 16) -#define WDT1_CTRL_WDTSTOP (1 << 0) +#define WDT1_CTRL_WDTSTOP (1 << 0) #define WDT1_CTRL_WDTSTOPMASK (1 << 16) -#define WDT2_CTRL_WDTSTOP (1 << 0) +#define WDT2_CTRL_WDTSTOP (1 << 0) #define WDT2_CTRL_WDTSTOPMASK (1 << 16) -#define WDT3_CTRL_WDTSTOP (1 << 0) +#define WDT3_CTRL_WDTSTOP (1 << 0) #define WDT3_CTRL_WDTSTOPMASK (1 << 16) -#define GPU_COHE_COHERENCY (1 << 0) +#define GPU_COHE_COHERENCY (1 << 0) #define GPU_TEXT_TEXFMTENABLE (1 << 0) -#define H264_CFG0_SYNC_AB_RAW_VCPLF_00 (0 << 24) -#define H264_CFG0_SYNC_AB_RAW_VCPLF_01 (1 << 24) -#define H264_CFG0_SYNC_AB_RAW_VCPLF_10 (2 << 24) -#define H264_CFG0_SYNC_AB_RAW_VCPLF_11 (3 << 24) -#define H264_CFG1_VPI_CAXI2_ENABLE_N (1 << 0) -#define H264_CFG2_VPI_CAXI_DPIC_STALL (1 << 0) -#define H264_MON_VPO_CAXI_DPIC_VALID (1 << 0) -#define H264_MON_VPO_CAXI_DPIC_MBL_START (1 << 8) -#define H264_MON_VPO_CAXI_DPIC_2D_START (1 << 16) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_00 (0 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_01 (1 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_10 (2 << 24) +#define H264_CFG0_SYNC_AB_RAW_VCPLF_11 (3 << 24) +#define H264_CFG1_VPI_CAXI2_ENABLE_N (1 << 0) +#define H264_CFG2_VPI_CAXI_DPIC_STALL (1 << 0) +#define H264_MON_VPO_CAXI_DPIC_VALID (1 << 0) +#define H264_MON_VPO_CAXI_DPIC_MBL_START (1 << 8) +#define H264_MON_VPO_CAXI_DPIC_2D_START (1 << 16) #define H264_BSTOP_FCI_CL_ISREQ_P (1 << 0) #define H264_BSTOP_FCO_CL_ISACK_P (1 << 16) #define GETH0_CFG_AVB_MIIMG_PIMODE (1 << 0) @@ -611,35 +611,35 @@ #define GETH1_CFG_AVB_MIIMG_PIMODE (1 << 0) #define GETH1_CFG_FEC_MIIMG_PIMODE (1 << 16) #define GETH1_CFG_FEC_GIGA_ENABLE (1 << 24) -#define I2C0_CFG_af_bypass (1 << 0) -#define I2C0_CFG_c2dloop (1 << 8) -#define I2C0_CFG_d2cloop (1 << 9) -#define I2C1_CFG_af_bypass (1 << 0) -#define I2C1_CFG_c2dloop (1 << 8) -#define I2C1_CFG_d2cloop (1 << 9) -#define I2C2_CFG_af_bypass (1 << 0) -#define I2C2_CFG_c2dloop (1 << 8) -#define I2C2_CFG_d2cloop (1 << 9) -#define I2C3_CFG_af_bypass (1 << 0) -#define I2C3_CFG_c2dloop (1 << 8) -#define I2C3_CFG_d2cloop (1 << 9) +#define I2C0_CFG_af_bypass (1 << 0) +#define I2C0_CFG_c2dloop (1 << 8) +#define I2C0_CFG_d2cloop (1 << 9) +#define I2C1_CFG_af_bypass (1 << 0) +#define I2C1_CFG_c2dloop (1 << 8) +#define I2C1_CFG_d2cloop (1 << 9) +#define I2C2_CFG_af_bypass (1 << 0) +#define I2C2_CFG_c2dloop (1 << 8) +#define I2C2_CFG_d2cloop (1 << 9) +#define I2C3_CFG_af_bypass (1 << 0) +#define I2C3_CFG_c2dloop (1 << 8) +#define I2C3_CFG_d2cloop (1 << 9) #define CANFD_CFG_RS_CANFD_MODE (1 << 0) -#define CANFD_CFG_RS_CANFD_NON_ISO_SEL (1 << 1) -#define CANFD_CFG_RS_CANFD_NON_ISO_EN (1 << 2) +#define CANFD_CFG_RS_CANFD_NON_ISO_SEL (1 << 1) +#define CANFD_CFG_RS_CANFD_NON_ISO_EN (1 << 2) #define SCIF0_CFG_e1_iotestmd (1 << 0) #define SCIF1_CFG_e1_iotestmd (1 << 0) #define SCIF2_CFG_e1_iotestmd (1 << 0) #define SCIF3_CFG_e1_iotestmd (1 << 0) #define SCIF4_CFG_e1_iotestmd (1 << 0) -#define SCI0_CFG_SY_TM32 (1 << 0) -#define SCI1_CFG__SY_TM32 (1 << 0) -#define CM33_STAT_CORECLKEN (1 << 0) +#define SCI0_CFG_SY_TM32 (1 << 0) +#define SCI1_CFG__SY_TM32 (1 << 0) +#define CM33_STAT_CORECLKEN (1 << 0) #define CM33_LOCK_LOCKSVTAIRCR (1 << 0) #define CM33_LOCK_LOCKNSVTOR (1 << 1) -#define CM33_LOCK_LOCKSMPU (1 << 2) -#define CM33_LOCK_LOCKNSMPU (1 << 3) -#define CM33_LOCK_LOCKSAU (1 << 4) -#define CM33_CTL_CPUWAIT (1 << 0) +#define CM33_LOCK_LOCKSMPU (1 << 2) +#define CM33_LOCK_LOCKNSMPU (1 << 3) +#define CM33_LOCK_LOCKSAU (1 << 4) +#define CM33_CTL_CPUWAIT (1 << 0) #define CA55_CFG_AArch0_AA64nAA32_0 (1 << 0) #define CA55_CFG_AArch1_AA64nAA32_1 (1 << 1) #define CA55_CFG_Endian0_CFGEND0 (1 << 0) @@ -649,7 +649,7 @@ #define CA55_CFG_VA0_VINITHI0 (1 << 0) #define CA55_CFG_VA1_VINITHI1 (1 << 1) #define BBG_CTRL_ENABLE_REG_EN (1 << 0) -#define BBG_CTRL_REG_EN_CP (1 << 15) +#define BBG_CTRL_REG_EN_CP (1 << 15) #define BBG_CTRL_REG_EN_VBBP (1 << 13) #define BBG_CTRL_REG_EN_VBBN (1 << 14) #define BBG_CTRL_MON_EN_CP_STATE (1 << 15) @@ -689,27 +689,27 @@ #define LSI_MODE_STAT_MD_OSCDRV_10 (2 << 14) #define LSI_MODE_STAT_MD_OSCDRV_11 (3 << 14) #define LSI_MODE_STAT_STAT_SEC_EN (1 << 16) -#define LSI_PRR_CA55_1CPU (1 << 0) -#define LSI_PRR_CM33_DIS (1 << 4) -#define LSI_PRR_GPU_DIS (1 << 8) -#define LSI_OTPSECEN_SECEN (1 << 0) +#define LSI_PRR_CA55_1CPU (1 << 0) +#define LSI_PRR_CM33_DIS (1 << 4) +#define LSI_PRR_GPU_DIS (1 << 8) +#define LSI_OTPSECEN_SECEN (1 << 0) #define LSI_OTPSECMODE_SECBT_SD (1 << 0) #define LSI_OTPSECMODE_SECBT_EMMC18 (1 << 1) #define LSI_OTPSECMODE_SECBT_EMMC33 (1 << 2) #define LSI_OTPSECMODE_SECBT_SPI18 (1 << 3) #define LSI_OTPSECMODE_SECBT_SPI33 (1 << 4) -#define LSI_OTPJAM_JAM_00 (0 << 0) -#define LSI_OTPJAM_JAM_01 (1 << 0) -#define LSI_OTPJAM_JAM_10 (2 << 0) -#define LSI_OTPJAM_JAM_11 (3 << 0) +#define LSI_OTPJAM_JAM_00 (0 << 0) +#define LSI_OTPJAM_JAM_01 (1 << 0) +#define LSI_OTPJAM_JAM_10 (2 << 0) +#define LSI_OTPJAM_JAM_11 (3 << 0) #define LSI_OTPCORE_CA55_FREQ_00 (0 << 0) #define LSI_OTPCORE_CA55_FREQ_01 (1 << 0) #define LSI_OTPCORE_CA55_FREQ_10 (2 << 0) #define LSI_OTPCORE_CA55_FREQ_11 (3 << 0) -#define LSI_OTPPOC_SD_E_00 (0 << 0) -#define LSI_OTPPOC_SD_E_01 (1 << 0) -#define LSI_OTPPOC_SD_E_10 (2 << 0) -#define LSI_OTPPOC_SD_E_11 (3 << 0) +#define LSI_OTPPOC_SD_E_00 (0 << 0) +#define LSI_OTPPOC_SD_E_01 (1 << 0) +#define LSI_OTPPOC_SD_E_10 (2 << 0) +#define LSI_OTPPOC_SD_E_11 (3 << 0) #define LSI_OTPPOC_EMMC18_E_00 (0 << 2) #define LSI_OTPPOC_EMMC18_E_01 (1 << 2) #define LSI_OTPPOC_EMMC18_E_10 (2 << 2) @@ -730,68 +730,68 @@ #define LSI_OTPPOC_SCIF_E_01 (1 << 10) #define LSI_OTPPOC_SCIF_E_10 (2 << 10) #define LSI_OTPPOC_SCIF_E_11 (3 << 10) -#define LP_CTL0_MAIN_CPU (1 << 0) -#define LP_CTL1_STBY (1 << 0) +#define LP_CTL0_MAIN_CPU (1 << 0) +#define LP_CTL1_STBY (1 << 0) #define LP_CTL1_CA55SLEEP_REQ_00 (0 << 8) #define LP_CTL1_CA55SLEEP_REQ_01 (1 << 8) #define LP_CTL1_CA55SLEEP_REQ_10 (2 << 8) #define LP_CTL1_CA55SLEEP_REQ_11 (3 << 8) #define LP_CTL1_CM33SLEEP_REQ (1 << 12) -#define LP_CTL1_STBY_CA55ST (1 << 16) -#define LP_CTL1_STBY_CM33ST (1 << 17) +#define LP_CTL1_STBY_CA55ST (1 << 16) +#define LP_CTL1_STBY_CM33ST (1 << 17) #define LP_CTL1_CA55SLEEP_ACK_00 (0 << 24) #define LP_CTL1_CA55SLEEP_ACK_01 (1 << 24) #define LP_CTL1_CA55SLEEP_ACK_10 (2 << 24) #define LP_CTL1_CA55SLEEP_ACK_11 (3 << 24) #define LP_CTL1_CM33SLEEP_ACK (1 << 28) #define LP_CTL2_CA55_STBYCTL (1 << 0) -#define LP_CTL3_U0DP_F (1 << 0) -#define LP_CTL3_U0DM_F (1 << 1) -#define LP_CTL3_U0VBUSIN_F (1 << 2) -#define LP_CTL3_U0OVRCLR_F (1 << 3) -#define LP_CTL3_U1DP_F (1 << 8) -#define LP_CTL3_U1DM_F (1 << 9) -#define LP_CTL3_U1OVRCLR_F (1 << 11) -#define LP_CTL3_NMI_F (1 << 24) -#define LP_CTL4_U0DP_E (1 << 0) -#define LP_CTL4_U0DM_E (1 << 1) -#define LP_CTL4_U0VBUSIN_E (1 << 2) -#define LP_CTL4_U0OVRCLR_E (1 << 3) -#define LP_CTL4_U1DP_E (1 << 8) -#define LP_CTL4_U1DM_E (1 << 9) -#define LP_CTL4_U1OVRCLR_E (1 << 11) -#define LP_CTL4_IRQ_E0 (1 << 16) -#define LP_CTL4_IRQ_E1 (1 << 17) -#define LP_CTL4_IRQ_E2 (1 << 18) -#define LP_CTL4_IRQ_E3 (1 << 19) -#define LP_CTL4_IRQ_E4 (1 << 20) -#define LP_CTL4_IRQ_E5 (1 << 21) -#define LP_CTL4_IRQ_E6 (1 << 22) -#define LP_CTL4_IRQ_E7 (1 << 23) -#define LP_CTL4_NMI_E (1 << 24) -#define LP_CTL5_Q4_DENY_F (1 << 0) -#define LP_CTL5_Q9_DENY_F (1 << 1) -#define LP_CTL5_Q10_DENY_F (1 << 2) -#define LP_CTL5_STBY_F (1 << 4) +#define LP_CTL3_U0DP_F (1 << 0) +#define LP_CTL3_U0DM_F (1 << 1) +#define LP_CTL3_U0VBUSIN_F (1 << 2) +#define LP_CTL3_U0OVRCLR_F (1 << 3) +#define LP_CTL3_U1DP_F (1 << 8) +#define LP_CTL3_U1DM_F (1 << 9) +#define LP_CTL3_U1OVRCLR_F (1 << 11) +#define LP_CTL3_NMI_F (1 << 24) +#define LP_CTL4_U0DP_E (1 << 0) +#define LP_CTL4_U0DM_E (1 << 1) +#define LP_CTL4_U0VBUSIN_E (1 << 2) +#define LP_CTL4_U0OVRCLR_E (1 << 3) +#define LP_CTL4_U1DP_E (1 << 8) +#define LP_CTL4_U1DM_E (1 << 9) +#define LP_CTL4_U1OVRCLR_E (1 << 11) +#define LP_CTL4_IRQ_E0 (1 << 16) +#define LP_CTL4_IRQ_E1 (1 << 17) +#define LP_CTL4_IRQ_E2 (1 << 18) +#define LP_CTL4_IRQ_E3 (1 << 19) +#define LP_CTL4_IRQ_E4 (1 << 20) +#define LP_CTL4_IRQ_E5 (1 << 21) +#define LP_CTL4_IRQ_E6 (1 << 22) +#define LP_CTL4_IRQ_E7 (1 << 23) +#define LP_CTL4_NMI_E (1 << 24) +#define LP_CTL5_Q4_DENY_F (1 << 0) +#define LP_CTL5_Q9_DENY_F (1 << 1) +#define LP_CTL5_Q10_DENY_F (1 << 2) +#define LP_CTL5_STBY_F (1 << 4) #define LP_CTL5_CA55SLEEP0_F (1 << 8) #define LP_CTL5_CA55SLEEP1_F (1 << 9) -#define LP_CTL5_CM33SLEEP_F (1 << 10) +#define LP_CTL5_CM33SLEEP_F (1 << 10) #define LP_CTL5_CA55STBYDONE_F (1 << 16) -#define LP_CTL5_CM33STBYR_F (1 << 20) -#define LP_CTL6_Q4_DENY_E (1 << 0) -#define LP_CTL6_Q9_DENY_E (1 << 1) -#define LP_CTL6_Q10_DENY_E (1 << 2) -#define LP_CTL6_STBY_E (1 << 4) +#define LP_CTL5_CM33STBYR_F (1 << 20) +#define LP_CTL6_Q4_DENY_E (1 << 0) +#define LP_CTL6_Q9_DENY_E (1 << 1) +#define LP_CTL6_Q10_DENY_E (1 << 2) +#define LP_CTL6_STBY_E (1 << 4) #define LP_CTL6_CA55STBYDONE_E (1 << 5) -#define LP_CTL6_CM33STBYR_E (1 << 6) +#define LP_CTL6_CM33STBYR_E (1 << 6) #define LP_CTL6_CA55SLEEP0_E (1 << 8) #define LP_CTL6_CA55SLEEP1_E (1 << 9) -#define LP_CTL6_CM33SLEEP_E (1 << 10) -#define LP_CTL7_IM33_MASK (1 << 0) +#define LP_CTL6_CM33SLEEP_E (1 << 10) +#define LP_CTL7_IM33_MASK (1 << 0) #define LP_CTL8_SUBCPU_RTRIG (1 << 0) #define LP_CM33CTL0_SLEEPING (1 << 0) #define LP_CM33CTL0_SLEEPDEEP (1 << 4) -#define LP_CM33CTL0_WAKEUP (1 << 8) +#define LP_CM33CTL0_WAKEUP (1 << 8) #define LP_CM33CTL0_SYSRESETREQ (1 << 9) #define LP_CM33CTL0_SLEEPHOLDREQn (1 << 16) #define LP_CM33CTL0_SLEEPHOLDACKn (1 << 17) @@ -805,28 +805,28 @@ #define LP_CM33CTL1_QDBGACCEPTn (1 << 20) #define LP_CM33CTL1_COREQDENY (1 << 24) #define LP_CM33CTL1_DBGQDENY (1 << 28) -#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_SLV (1 << 1) -#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL1_QACTIVE_Q_CLK_MST (1 << 2) #define LP_CA55CK_CTL1_PCLKQACTIVE (1 << 8) #define LP_CA55CK_CTL1_ATCLKQACTIVE (1 << 9) -#define LP_CA55CK_CTL1_GICCLKQACTIVE (1 << 10) -#define LP_CA55CK_CTL1_PDBGCLKQACTIVE (1 << 11) -#define LP_CA55CK_CTL2_QREQn_Q_CLK_SLV (1 << 1) -#define LP_CA55CK_CTL2_QREQn_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL1_GICCLKQACTIVE (1 << 10) +#define LP_CA55CK_CTL1_PDBGCLKQACTIVE (1 << 11) +#define LP_CA55CK_CTL2_QREQn_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL2_QREQn_Q_CLK_MST (1 << 2) #define LP_CA55CK_CTL2_PCLKQREQn (1 << 8) #define LP_CA55CK_CTL2_ATCLKQREQn (1 << 9) #define LP_CA55CK_CTL2_GICCLKQREQn (1 << 10) #define LP_CA55CK_CTL2_PDBGCLKQREQn (1 << 11) #define LP_CA55CK_CTL3_SCLKQACCEPTn (1 << 0) -#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_SLV (1 << 1) -#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_MST (1 << 2) +#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_SLV (1 << 1) +#define LP_CA55CK_CTL3_QACCEPTn_Q_CLK_MST (1 << 2) #define LP_CA55CK_CTL3_PCLKQACCEPTn (1 << 8) -#define LP_CA55CK_CTL3_ATCLKQACCEPTn (1 << 9) -#define LP_CA55CK_CTL3_GICCLKQACCEPTn (1 << 10) -#define LP_CA55CK_CTL3_PDBGCLKQACCEPTn (1 << 11) +#define LP_CA55CK_CTL3_ATCLKQACCEPTn (1 << 9) +#define LP_CA55CK_CTL3_GICCLKQACCEPTn (1 << 10) +#define LP_CA55CK_CTL3_PDBGCLKQACCEPTn (1 << 11) #define LP_CA55CK_CTL3_SCLKQDENY (1 << 16) -#define LP_CA55CK_CTL3_QDENY_Q_CLK_SLV (1 << 17) -#define LP_CA55CK_CTL3_QDENY_Q_CLK_MST (1 << 18) +#define LP_CA55CK_CTL3_QDENY_Q_CLK_SLV (1 << 17) +#define LP_CA55CK_CTL3_QDENY_Q_CLK_MST (1 << 18) #define LP_CA55CK_CTL3_PCLKQDENY (1 << 24) #define LP_CA55CK_CTL3_ATCLKQDENY (1 << 25) #define LP_CA55CK_CTL3_GICCLKQDENY (1 << 26) @@ -851,9 +851,9 @@ #define LP_GPU_CTL_QDENY_AXI_MST (1 << 26) #define LP_GPU_CTL_QDENY_ACE_SLV (1 << 27) #define LP_GPU_CTL_QDENY_ACE_MST (1 << 28) -#define IPCONT_SEL_SPI_OCTA_POS 0 -#define IPCONT_SEL_SPI_OCTA (1u << IPCONT_SEL_SPI_OCTA_POS) -#define IPCONT_SEL_SPI_OCTA_SPI 0u -#define IPCONT_SEL_SPI_OCTA_OCTA 1u +#define IPCONT_SEL_SPI_OCTA_POS 0 +#define IPCONT_SEL_SPI_OCTA (1u << IPCONT_SEL_SPI_OCTA_POS) +#define IPCONT_SEL_SPI_OCTA_SPI 0u +#define IPCONT_SEL_SPI_OCTA_OCTA 1u #endif /* __SYS_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/xspi_api.h b/include/drivers/renesas/rza/xspi/xspi_api.h similarity index 96% rename from plat/renesas/rza/common/include/xspi_api.h rename to include/drivers/renesas/rza/xspi/xspi_api.h index c050a9f9bc..e8cc4a1ab1 100644 --- a/plat/renesas/rza/common/include/xspi_api.h +++ b/include/drivers/renesas/rza/xspi/xspi_api.h @@ -62,7 +62,9 @@ typedef struct st_xspi_cfg { void const *extend; /* Implementation specific extended configuration */ } xspi_cfg_t; -/** xSPI control block. Allocate an implementation specific control block to pass into the xSPI API calls. */ +/** xSPI control block. + * Allocate an implementation specific control block to pass into the xSPI API calls. + */ typedef void xspi_ctrl_t; /** xSPI operation table @@ -78,11 +80,11 @@ typedef struct st_xspi_op { uint8_t additional_size; ///< Additional data size uint32_t additional_value; ///< Additional data value uint8_t dummy_cycles; ///< Dummy cycle count (as clocks) - size_t transfer_size; ///< Transfer size by bytes (ignored for configuring in-place access) - void *transfer_buffer; ///< Transfer buffer pointer (ignored for configuring in-place access) + size_t transfer_size; ///< Transfer size by bytes (ignored for in-place access) + void *transfer_buffer; ///< Transfer buffer pointer (ignored for in-place access) bool transfer_is_ddr; ///< Transfer phase is DDR uint8_t transfer_flag; ///< Additional transfer flags - uint8_t force_idle_level_mask; ///< Whether or not to force each IO level during the idle state + uint8_t force_idle_level_mask; ///< Mask to force each IO level during the idle state uint8_t force_idle_level_value; ///< IO level during the idle state uint8_t slch_value; uint8_t clsh_value; diff --git a/plat/renesas/rza/common/include/xspidevice_api.h b/include/drivers/renesas/rza/xspi/xspidevice_api.h similarity index 96% rename from plat/renesas/rza/common/include/xspidevice_api.h rename to include/drivers/renesas/rza/xspi/xspidevice_api.h index 8ed371dd9a..6589dc0759 100644 --- a/plat/renesas/rza/common/include/xspidevice_api.h +++ b/include/drivers/renesas/rza/xspi/xspidevice_api.h @@ -7,7 +7,6 @@ #ifndef _XSPIDEVICE_API_H_ #define _XSPIDEVICE_API_H_ #include -#include #include "xspi_api.h" @@ -25,7 +24,9 @@ typedef struct st_xspidevice_cfg { void const *extend; /* Implementation configuration */ } xspidevice_cfg_t; -/** xSPI device control block. Allocate an implementation specific control block to pass into the xSPI API calls. */ +/** xSPI device control block. + * Allocate an implementation specific control block to pass into the xSPI API calls. + */ typedef void xspidevice_ctrl_t; /** xSPI device write status. */ diff --git a/plat/renesas/rza/board/a3m_ek_nor/platform.mk b/plat/renesas/rza/board/a3m_ek_nor/platform.mk index e8b5bfecbd..99193696f9 100644 --- a/plat/renesas/rza/board/a3m_ek_nor/platform.mk +++ b/plat/renesas/rza/board/a3m_ek_nor/platform.mk @@ -22,11 +22,11 @@ $(eval $(call add_define,RZ_FLASH_SIZE)) ifneq (${USE_SDRAM},0) ifeq (${DDR_PLL4},1333) DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-02-1.c \ - plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c + drivers/renesas/rza/ddr/param_swizzle_T1.c else DDR_PLL4 := 1600 DDR_SOURCES += plat/renesas/rza/soc/a3m/drivers/ddr/param_mc_C-011_D3-01-1.c \ - plat/renesas/rza/common/drivers/ddr/param_swizzle_T1.c + drivers/renesas/rza/ddr/param_swizzle_T1.c endif $(eval $(call add_define,DDR_PLL4)) endif diff --git a/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk b/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk index cdb04c5588..a9bc356124 100644 --- a/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk +++ b/plat/renesas/rza/board/a3ul_smarc_octal/platform.mk @@ -24,7 +24,7 @@ $(eval $(call add_define,RZ_FLASH_SIZE)) ifneq (${USE_SDRAM},0) DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \ - plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c + drivers/renesas/rza/ddr/param_swizzle_T3bcud2.c DDR_PLL4 := 1600 $(eval $(call add_define,DDR_PLL4)) diff --git a/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk b/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk index b450b1ffa8..e223ad6f65 100644 --- a/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk +++ b/plat/renesas/rza/board/a3ul_smarc_qspi/platform.mk @@ -21,7 +21,7 @@ $(eval $(call add_define,RZ_FLASH_SIZE)) ifneq (${USE_SDRAM},0) DDR_SOURCES += plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D4-01-2.c \ - plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud2.c + drivers/renesas/rza/ddr/param_swizzle_T3bcud2.c DDR_PLL4 := 1600 $(eval $(call add_define,DDR_PLL4)) diff --git a/plat/renesas/rza/common/bl2_plat_setup.c b/plat/renesas/rza/common/bl2_plat_setup.c index 738d067328..36f02b68de 100644 --- a/plat/renesas/rza/common/bl2_plat_setup.c +++ b/plat/renesas/rza/common/bl2_plat_setup.c @@ -5,7 +5,6 @@ */ #include -#include #include #include @@ -15,22 +14,31 @@ #include #include #include -#include -#include #include +#include +#include +#include +#include +#include +#include +#include #include -#include -#include +#include #include #include -#include #include -#include -#include -#include static console_t console; +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_mmap[] = { + MAP_REGION_FLAT(0x00000000, 0x00200000, MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(0x10000000, 0x10000000, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(0x20000000, 0x10000000, MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(0x40000000, 0x40000000, MT_MEMORY | MT_RW | MT_SECURE), + { 0 } +}; + int bl2_plat_handle_pre_image_load(unsigned int image_id) { return 0; @@ -86,8 +94,8 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, cpg_setup(); /* initialize console driver */ - ret = console_rza_register(PLAT_SCIF0_BASE, PLAT_UART_INCK_HZ, - PLAT_UART_BARDRATE, &console); + ret = console_scifa_register(PLAT_SCIF0_BASE, PLAT_UART_INCK_HZ, + PLAT_UART_BARDRATE, &console); if (!ret) panic(); @@ -98,32 +106,20 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, void bl2_el3_plat_arch_setup(void) { - rza_mmu_pgtbl_cfg_t g_mmu_pagetable_array[] = { - /* vaddress, paddress, size, attribute */ - { 0x00000000, 0x00000000, 0x00200000, - RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, - { 0x00200000, 0x00200000, 0x0FE00000, - RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, - { 0x10000000, 0x10000000, 0x10000000, - RZA_MMU_ATTRIBUTE_DEVICE }, - { 0x20000000, 0x20000000, 0x10000000, - RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, - { 0x30000000, 0x30000000, 0x10000000, - RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, - { 0x40000000, 0x40000000, 0x40000000, - RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE }, - { 0x80000000, 0x80000000, 0x40000000, - RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, - { 0xC0000000, 0xC0000000, 0x40000000, - RZA_MMU_ATTRIBUTE_ACCESS_FAULT }, - { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - RZA_MMU_ATTRIBUTE_CONFIG_END } + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, + BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + { 0 }, }; - if (0 != plat_mmu_init(g_mmu_pagetable_array)) { - panic(); - } - plat_mmu_enable(); + setup_page_tables(bl_regions, plat_mmap); + + enable_mmu_el3(0); } void bl2_platform_setup(void) @@ -136,7 +132,9 @@ void bl2_platform_setup(void) ddr_setup(); #endif /* DEBUG_FPGA */ - rz_io_setup(); + xspi_setup(); + + plat_rza_io_setup(); RZ_RUN_TESTS(); diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c deleted file mode 100644 index e103f016ff..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1b.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x57630BB8 }, - { DDRMC_R041, 0x00002828 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00102611 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, - { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, - { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, - { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c deleted file mode 100644 index e103f016ff..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1bc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x57630BB8 }, - { DDRMC_R041, 0x00002828 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00102611 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, - { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, - { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, - { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c deleted file mode 100644 index 523323fa7b..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1c.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x576E08E8 }, - { DDRMC_R041, 0x00003C22 }, - { DDRMC_R042, 0x22227822 }, - { DDRMC_R043, 0x00123312 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00001502 }, { DDRMC_R031, 0x00000A06 }, - { DDRMC_R032, 0x170D1112 }, { DDRMC_R033, 0x1900130B }, - { DDRMC_R034, 0x1F09180C }, { DDRMC_R035, 0x161C0E14 }, - { DDRMC_R036, 0x01101B1A }, { DDRMC_R037, 0x001D051E }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x1B03150E }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x16001706 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D050807 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1901020B }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0F090418 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A0A1D14 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c deleted file mode 100644 index 8084bbf476..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vbc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/V2L DDR config generation tool v1.13.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x57630BB8 }, - { DDRMC_R041, 0x00002828 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00102611 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000B02 }, { DDRMC_R031, 0x00000106 }, - { DDRMC_R032, 0x11131C0D }, { DDRMC_R033, 0x12001F15 }, - { DDRMC_R034, 0x1D19140E }, { DDRMC_R035, 0x17091B1A }, - { DDRMC_R036, 0x0A10160C }, { DDRMC_R037, 0x0018051E }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x14001816 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x010D0608 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x02190403 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1705150B }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x07090F0E }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D0A1B }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c deleted file mode 100644 index b431ccb485..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T1vc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/V2L DDR config generation tool v1.13.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x576E08E8 }, - { DDRMC_R041, 0x00003C22 }, - { DDRMC_R042, 0x22227822 }, - { DDRMC_R043, 0x00123312 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00001502 }, { DDRMC_R031, 0x00000A06 }, - { DDRMC_R032, 0x170D1112 }, { DDRMC_R033, 0x1900130B }, - { DDRMC_R034, 0x1F09180C }, { DDRMC_R035, 0x161C0E14 }, - { DDRMC_R036, 0x01101B1A }, { DDRMC_R037, 0x001D051E }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x1B03150E }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x16001706 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D050807 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x1901020B }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0F090418 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A0A1D14 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c deleted file mode 100644 index 7c56f4fcef..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2c.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x576E08E8 }, - { DDRMC_R041, 0x00003C22 }, - { DDRMC_R042, 0x22227822 }, - { DDRMC_R043, 0x00123312 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000A02 }, { DDRMC_R031, 0x00000106 }, - { DDRMC_R032, 0x171E120B }, { DDRMC_R033, 0x1800000C }, - { DDRMC_R034, 0x00161C00 }, { DDRMC_R035, 0x0D1F1319 }, - { DDRMC_R036, 0x15101B1A }, { DDRMC_R037, 0x001D0509 }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A020419 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x03161701 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D000807 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F0B0518 }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x14091506 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D1B0E }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c deleted file mode 100644 index d926320749..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T2vc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/V2L DDR config generation tool v1.13.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000002, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000200 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000001C }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x576E08E8 }, - { DDRMC_R041, 0x00003C22 }, - { DDRMC_R042, 0x22227822 }, - { DDRMC_R043, 0x00123312 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000A02 }, { DDRMC_R031, 0x00000106 }, - { DDRMC_R032, 0x171E120B }, { DDRMC_R033, 0x1800000C }, - { DDRMC_R034, 0x00161C00 }, { DDRMC_R035, 0x0D1F1319 }, - { DDRMC_R036, 0x15101B1A }, { DDRMC_R037, 0x001D0509 }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A020419 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x03161701 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D000807 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F0B0518 }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x14091506 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1A1D1B0E }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1C0C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c deleted file mode 100644 index 9281ec8aa9..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x57630BB8 }, - { DDRMC_R041, 0x00002828 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00102611 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, - { DDRMC_R032, 0x1C191E13 }, { DDRMC_R033, 0x12000A18 }, - { DDRMC_R034, 0x100B1D00 }, { DDRMC_R035, 0x1F0C1B09 }, - { DDRMC_R036, 0x151A1614 }, { DDRMC_R037, 0x000D0E17 }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0A070E16 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x18140B08 }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x00170409 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F030619 }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x05020C0D }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A1501 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c deleted file mode 100644 index d7d27f7fd5..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcud.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000706, 0x00000100 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000E00, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x000001C0, 0x000001C0 }; - -const uint32_t mc_mr6_tbl[2] = { 0x0000007F, 0x0000000F }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x57630BB8 }, - { DDRMC_R041, 0x00002828 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00102611 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, - { DDRMC_R032, 0x18171D1C }, { DDRMC_R033, 0x0D000A09 }, - { DDRMC_R034, 0x1F0B1000 }, { DDRMC_R035, 0x1E140E0C }, - { DDRMC_R036, 0x191A121B }, { DDRMC_R037, 0x00131516 }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x0C050D08 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0A17180B }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x190E0709 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F140206 }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x03000416 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A1501 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c deleted file mode 100644 index e9daf72ff2..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3bcul.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000001, 0x00000000, 0x00000000, - 0x00000000 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000266, 0x00000006 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000600, 0x00000000 }; - -const uint32_t mc_mr5_tbl[2] = { 0x00000000, 0x00000000 }; - -const uint32_t mc_mr6_tbl[2] = { 0x00000000, 0x00000000 }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x4F7F06E8 }, - { DDRMC_R041, 0x00002822 }, - { DDRMC_R042, 0x00003C22 }, - { DDRMC_R043, 0x00000000 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000000 }, { DDRMC_R031, 0x00000000 }, - { DDRMC_R032, 0x151A2100 }, { DDRMC_R033, 0x00200014 }, - { DDRMC_R034, 0x1F1E1900 }, { DDRMC_R035, 0x000B120C }, - { DDRMC_R036, 0x000A1B17 }, { DDRMC_R037, 0x161D0F13 }, - { DDRMC_R038, 0x0000000D } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x17140B04 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0006070E }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x0D0A0818 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x19160201 }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x030C150F }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x1B1A0905 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E1D1C } -}; diff --git a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c b/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c deleted file mode 100644 index 9fcb87a46d..0000000000 --- a/plat/renesas/rza/common/drivers/ddr/param_swizzle_T3cl.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const uint32_t mc_odt_pins_tbl[4] = { 0x00000002, 0x00000001, 0x00000002, - 0x00000001 }; - -const uint32_t mc_mr1_tbl[2] = { 0x00000266, 0x00000206 }; - -const uint32_t mc_mr2_tbl[2] = { 0x00000600, 0x00000200 }; - -const uint32_t mc_mr5_tbl[2] = { 0x00000000, 0x00000000 }; - -const uint32_t mc_mr6_tbl[2] = { 0x00000000, 0x00000000 }; - -const uint32_t mc_phy_settings_tbl[MC_PHYSET_NUM][2] = { - { DDRMC_R040, 0x4F7F01E8 }, - { DDRMC_R041, 0x00007822 }, - { DDRMC_R042, 0x1E1E3C22 }, - { DDRMC_R043, 0x00000000 } -}; - -const uint32_t swizzle_mc_tbl[SWIZZLE_MC_NUM][2] = { - { DDRMC_R030, 0x00000A00 }, { DDRMC_R031, 0x00001E00 }, - { DDRMC_R032, 0x1D131500 }, { DDRMC_R033, 0x00001217 }, - { DDRMC_R034, 0x180E2000 }, { DDRMC_R035, 0x0D1F0B1B }, - { DDRMC_R036, 0x021A1400 }, { DDRMC_R037, 0x0C1C0616 }, - { DDRMC_R038, 0x00000000 } -}; - -const uint32_t swizzle_phy_tbl[SIZZLE_PHY_NUM][2] = { - { DDRPHY_R29, 0x00000000 }, { DDRPHY_R11, 0x19081815 }, - { DDRPHY_R29, 0x00000001 }, { DDRPHY_R11, 0x0702140B }, - { DDRPHY_R29, 0x00000002 }, { DDRPHY_R11, 0x170D0309 }, - { DDRPHY_R29, 0x00000003 }, { DDRPHY_R11, 0x0F00051D }, - { DDRPHY_R29, 0x00000004 }, { DDRPHY_R11, 0x13121110 }, - { DDRPHY_R29, 0x00000005 }, { DDRPHY_R11, 0x0E160106 }, - { DDRPHY_R29, 0x00000006 }, { DDRPHY_R11, 0x0A1A1B04 }, - { DDRPHY_R29, 0x00000007 }, { DDRPHY_R11, 0x001E0C1C } -}; diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c b/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c deleted file mode 100644 index 31ddf58bfa..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_cmd.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -static void emmc_little_to_big(uint8_t *p, uint32_t value) -{ - if (p == NULL) - return; - - p[0] = (uint8_t)(value >> 24); - p[1] = (uint8_t)(value >> 16); - p[2] = (uint8_t)(value >> 8); - p[3] = (uint8_t)value; -} - -static void emmc_softreset(void) -{ - int32_t loop = 10000; - int32_t retry = 1000; - - /* flag clear */ - mmc_drv_obj.during_cmd_processing = FALSE; - mmc_drv_obj.during_transfer = FALSE; - mmc_drv_obj.during_dma_transfer = FALSE; - mmc_drv_obj.state_machine_blocking = FALSE; - mmc_drv_obj.force_terminate = FALSE; - mmc_drv_obj.dma_error_flag = FALSE; - - /* during operation ? */ - if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) - goto reset; - - /* wait CMDSEQ = 0 */ - while (loop > 0) { - if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) - break; /* ready */ - - loop--; - if ((loop == 0) && (retry > 0)) { - udelay(1000U); /* wait 1ms */ - loop = 10000; - retry--; - } - } - -reset: - /* reset */ - SETR_32(SOFT_RST, (GETR_32(SOFT_RST) & (~SOFT_RST_SDRST))); - SETR_32(SOFT_RST, (GETR_32(SOFT_RST) | SOFT_RST_SDRST)); - - /* initialize */ - SETR_32(SD_INFO1, 0x00000000U); - SETR_32(SD_INFO2, SD_INFO2_CLEAR); - SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ -} - -static void emmc_read_response(uint32_t *response) -{ - uint8_t *p; - - if (response == NULL) - return; - - /* read response */ - if (mmc_drv_obj.response_length != EMMC_MAX_RESPONSE_LENGTH) { - *response = GETR_32(SD_RSP10); /* [39:8] */ - return; - } - - /* CSD or CID */ - p = (uint8_t *)(response); - emmc_little_to_big(p, ((GETR_32(SD_RSP76) << 8) | - (GETR_32(SD_RSP54) >> 24))); /* [127:96] */ - emmc_little_to_big(p + 4, - ((GETR_32(SD_RSP54) << 8) | - (GETR_32(SD_RSP32) >> 24))); /* [95:64] */ - emmc_little_to_big(p + 8, - ((GETR_32(SD_RSP32) << 8) | - (GETR_32(SD_RSP10) >> 24))); /* [63:32] */ - emmc_little_to_big(p + 12, (GETR_32(SD_RSP10) << 8)); -} - -static EMMC_ERROR_CODE emmc_response_check(uint32_t *response, - uint32_t error_mask) -{ - HAL_MEMCARD_RESPONSE_TYPE response_type = - ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & - HAL_MEMCARD_RESPONSE_TYPE_MASK); - - if (response == NULL) - return EMMC_ERR_PARAM; - - if (response_type == HAL_MEMCARD_RESPONSE_NONE) - return EMMC_SUCCESS; - - if (response_type <= HAL_MEMCARD_RESPONSE_R1b) { - /* R1 or R1b */ - mmc_drv_obj.current_state = - (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> - EMMC_R1_STATE_SHIFT); - if ((*response & error_mask) != 0) { - if ((0x80 & *response) != 0) { - ERROR("BL2: emmc SWITCH_ERROR\n"); - } - return EMMC_ERR_CARD_STATUS_BIT; - } - return EMMC_SUCCESS; - } - - if (response_type == HAL_MEMCARD_RESPONSE_R4) { - if ((*response & EMMC_R4_STATUS) != 0) - return EMMC_ERR_CARD_STATUS_BIT; - } - - return EMMC_SUCCESS; -} - -static void emmc_WaitCmd2Cmd_8Cycle(void) -{ - uint32_t dataL, wait = 0; - - dataL = GETR_32(SD_CLK_CTRL); - dataL &= 0x000000FF; - - switch (dataL) { - case 0xFF: - case 0x00: - case 0x01: - case 0x02: - case 0x04: - case 0x08: - case 0x10: - case 0x20: - wait = 10U; - break; - case 0x40: - wait = 20U; - break; - case 0x80: - wait = 30U; - break; - } - - udelay(wait); -} - -static void cmdErrSdInfo2Log(void) -{ - ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2); -} - -static void emmc_data_transfer_dma(void) -{ - mmc_drv_obj.during_dma_transfer = TRUE; - mmc_drv_obj.dma_error_flag = FALSE; - - SETR_32(SD_INFO1_MASK, 0x00000000U); - SETR_32(SD_INFO2_MASK, (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); - - /* DMAC setting */ - if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { - /* transfer complete interrupt enable */ - SETR_32(DM_CM_INFO1_MASK, - (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); - SETR_32(DM_CM_INFO2_MASK, - (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE)); - /* BUFF --> FIFO */ - SETR_32(DM_CM_DTRAN_MODE, - (DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH)); - } else { - /* transfer complete interrupt enable */ - SETR_32(DM_CM_INFO1_MASK, - (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); - SETR_32(DM_CM_INFO2_MASK, - (DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE)); - /* FIFO --> BUFF */ - SETR_32(DM_CM_DTRAN_MODE, - (DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH)); - } - SETR_32(DM_DTRAN_ADDR, (((uintptr_t)mmc_drv_obj.buff_address_virtual & - DM_DTRAN_ADDR_WRITE_MASK))); - - SETR_32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); -} - -EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) -{ - EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS; - HAL_MEMCARD_RESPONSE_TYPE response_type; - HAL_MEMCARD_COMMAND_TYPE cmd_type; - EMMC_INT_STATE state; - uint32_t err_not_care_flag = FALSE; - - /* parameter check */ - if (response == NULL) { - emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* state check */ - if (mmc_drv_obj.clock_enable != TRUE) { - emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - if (mmc_drv_obj.state_machine_blocking == TRUE) { - emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR); - return EMMC_ERR; - } - - state = ESTATE_BEGIN; - response_type = ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & - HAL_MEMCARD_RESPONSE_TYPE_MASK); - cmd_type = ((HAL_MEMCARD_COMMAND_TYPE)mmc_drv_obj.cmd_info.cmd & - HAL_MEMCARD_COMMAND_TYPE_MASK); - - /* state machine */ - while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { - /* The interrupt factor flag is observed. */ - emmc_interrupt(); - - /* wait interrupt */ - if (mmc_drv_obj.state_machine_blocking == TRUE) - continue; - - switch (state) { - case ESTATE_BEGIN: - /* Busy check */ - if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != - 0) { - emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, - EMMC_ERR_CARD_BUSY); - return EMMC_ERR_CARD_BUSY; - } - - /* clear register */ - SETR_32(SD_INFO1, 0x00000000U); - SETR_32(SD_INFO2, SD_INFO2_CLEAR); - SETR_32(SD_INFO1_MASK, SD_INFO1_INFO0); - SETR_32(SD_INFO2_MASK, - (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); - - state = ESTATE_ISSUE_CMD; - /* fallthrough */ - - case ESTATE_ISSUE_CMD: - /* ARG */ - SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg); - /* issue cmd */ - SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw); - /* Set driver flag */ - mmc_drv_obj.during_cmd_processing = TRUE; - mmc_drv_obj.state_machine_blocking = TRUE; - - if (response_type == HAL_MEMCARD_RESPONSE_NONE) { - state = ESTATE_NON_RESP_CMD; - } else { - state = ESTATE_RCV_RESP; - } - - break; - - case ESTATE_NON_RESP_CMD: - /* interrupt disable */ - SETR_32(SD_INFO1_MASK, 0x00000000U); - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); - - /* check interrupt */ - if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { - /* error interrupt */ - cmdErrSdInfo2Log(); - rtn_code = EMMC_ERR_INFO2; - state = ESTATE_ERROR; - } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == - 0) { - /* not receive expected interrupt */ - rtn_code = EMMC_ERR_RESPONSE; - state = ESTATE_ERROR; - } else { - emmc_WaitCmd2Cmd_8Cycle(); - state = ESTATE_END; - } - break; - - case ESTATE_RCV_RESP: - /* interrupt disable */ - SETR_32(SD_INFO1_MASK, 0x00000000U); - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); - - /* check interrupt */ - if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { - if ((mmc_drv_obj.get_partition_access_flag == - TRUE) && - ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6) != - 0U)) { - err_not_care_flag = TRUE; - rtn_code = EMMC_ERR_CMD_TIMEOUT; - } else { - /* error interrupt */ - cmdErrSdInfo2Log(); - rtn_code = EMMC_ERR_INFO2; - } - state = ESTATE_ERROR; - break; - } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == - 0) { - /* not receive expected interrupt */ - rtn_code = EMMC_ERR_RESPONSE; - state = ESTATE_ERROR; - break; - } - - /* read response */ - emmc_read_response(response); - - /* check response */ - rtn_code = emmc_response_check(response, error_mask); - if (rtn_code != EMMC_SUCCESS) { - state = ESTATE_ERROR; - break; - } - - if (response_type == HAL_MEMCARD_RESPONSE_R1b) { - /* R1b */ - SETR_32(SD_INFO2_MASK, - (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); - state = ESTATE_RCV_RESPONSE_BUSY; - } else { - state = ESTATE_CHECK_RESPONSE_COMPLETE; - } - break; - - case ESTATE_RCV_RESPONSE_BUSY: - /* check interrupt */ - if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { - /* error interrupt */ - cmdErrSdInfo2Log(); - rtn_code = EMMC_ERR_INFO2; - state = ESTATE_ERROR; - break; - } - /* DAT0 not Busy */ - if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != - 0) { - state = ESTATE_CHECK_RESPONSE_COMPLETE; - break; - } - break; - - case ESTATE_CHECK_RESPONSE_COMPLETE: - if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) { - state = ESTATE_DATA_TRANSFER; - } else { - emmc_WaitCmd2Cmd_8Cycle(); - state = ESTATE_END; - } - break; - - case ESTATE_DATA_TRANSFER: - /* ADTC command */ - mmc_drv_obj.during_transfer = TRUE; - mmc_drv_obj.state_machine_blocking = TRUE; - - if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { - /* DMA */ - emmc_data_transfer_dma(); - } else { - /* PIO */ - /* interrupt enable (FIFO read/write enable) */ - if (mmc_drv_obj.cmd_info.dir == - HAL_MEMCARD_WRITE) { - SETR_32(SD_INFO2_MASK, - (SD_INFO2_BWE | - SD_INFO2_ALL_ERR | - SD_INFO2_CLEAR)); - } else { - SETR_32(SD_INFO2_MASK, - (SD_INFO2_BRE | - SD_INFO2_ALL_ERR | - SD_INFO2_CLEAR)); - } - } - state = ESTATE_DATA_TRANSFER_COMPLETE; - break; - - case ESTATE_DATA_TRANSFER_COMPLETE: - /* check interrupt */ - if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) { - /* error interrupt */ - cmdErrSdInfo2Log(); - rtn_code = EMMC_ERR_INFO2; - state = ESTATE_TRANSFER_ERROR; - break; - } - - /* DMAC error ? */ - if (mmc_drv_obj.dma_error_flag == TRUE) { - /* Error occurred in DMAC driver. */ - rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; - state = ESTATE_TRANSFER_ERROR; - } else if (mmc_drv_obj.during_dma_transfer == TRUE) { - /* DMAC not finished. unknown error */ - rtn_code = EMMC_ERR; - state = ESTATE_TRANSFER_ERROR; - } else { - SETR_32(SD_INFO1_MASK, SD_INFO1_INFO2); - SETR_32(SD_INFO2_MASK, - (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR)); - - mmc_drv_obj.state_machine_blocking = TRUE; - - state = ESTATE_ACCESS_END; - } - break; - - case ESTATE_ACCESS_END: - - /* clear flag */ - if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { - /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ - SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); - SETR_32(SD_STOP, 0x00000000U); - mmc_drv_obj.during_dma_transfer = FALSE; - } - - SETR_32(SD_INFO1_MASK, 0x00000000U); - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); - SETR_32(SD_INFO1, 0x00000000U); - SETR_32(SD_INFO2, SD_INFO2_CLEAR); - - if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0) { - emmc_WaitCmd2Cmd_8Cycle(); - state = ESTATE_END; - } else { - state = ESTATE_ERROR; - } - break; - - case ESTATE_TRANSFER_ERROR: - /* The error occurred in the Data transfer. */ - if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { - /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ - SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); - SETR_32(SD_STOP, 0x00000000U); - mmc_drv_obj.during_dma_transfer = FALSE; - } - /* fallthrough */ - - case ESTATE_ERROR: - if (err_not_care_flag == TRUE) { - mmc_drv_obj.during_cmd_processing = FALSE; - } else { - emmc_softreset(); - emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, - rtn_code); - } - return rtn_code; - - default: - state = ESTATE_END; - break; - } /* switch (state) */ - } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ - - /* force terminate */ - if (mmc_drv_obj.force_terminate == TRUE) { - /* timeout timer is expired. Or, PIO data transfer error. */ - /* Timeout occurred in the DMA transfer. */ - if (mmc_drv_obj.during_dma_transfer == TRUE) { - mmc_drv_obj.during_dma_transfer = FALSE; - } - ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n"); - emmc_softreset(); - - return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ - } - - /* success */ - mmc_drv_obj.during_cmd_processing = FALSE; - mmc_drv_obj.during_transfer = FALSE; - - return EMMC_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_config.h b/plat/renesas/rza/common/drivers/emmc/emmc_config.h deleted file mode 100644 index 16b6b8aa9a..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_config.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef EMMC_CONFIG_H -#define EMMC_CONFIG_H - -/* RCA */ -#define EMMC_RCA 1UL -/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ -#define EMMC_RW_DATA_TIMEOUT 0x40UL -/* how many times to try after fail. Don't change. */ -#define EMMC_RETRY_COUNT 0 -#define EMMC_CMD_MAX 60UL /* Don't change. */ - -#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL - -#endif /* EMMC_CONFIG_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_def.h b/plat/renesas/rza/common/drivers/emmc/emmc_def.h deleted file mode 100644 index 46c45745f3..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_def.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/** - * @file emmc_def.h - * @brief eMMC boot is expecting this header file - * - */ - -#ifndef EMMC_DEF_H -#define EMMC_DEF_H - -#include "emmc_std.h" - -/* ************************ HEADER (INCLUDE) SECTION *********************** */ - -/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ -#define EMMC_POWER_ON (1U) - -/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ - -/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ -extern st_mmc_base mmc_drv_obj; - -/* ************************** FUNCTION PROTOTYPES ************************** */ - -/** @brief for assembler program - */ -uint32_t _rom_emmc_finalize(void); - -/** @brief eMMC driver API - */ -EMMC_ERROR_CODE emmc_init(void); -EMMC_ERROR_CODE emmc_terminate(void); -EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode); -EMMC_ERROR_CODE emmc_mount(void); -EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq); -EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg); -EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); -EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, - uint32_t sector_number, uint32_t count, - uint32_t feature_flags); -EMMC_ERROR_CODE emmc_write_sector(uint32_t *buff_address_virtual, - uint32_t sector_number, uint32_t count, - uint32_t feature_flags); -EMMC_ERROR_CODE emmc_erase_sector(uint32_t *start_address, - uint32_t *end_address); -uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom); - -/** @brief interrupt service - */ -uint32_t emmc_interrupt(void); - -/** @brief DMA - */ - -/** @brief send command API - */ -EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response); -void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg); -void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, - uint32_t *buff_address_virtual, uint32_t len, - HAL_MEMCARD_OPERATION dir, - HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); -EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); - -/** @brief for error information - */ -void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code); -void emmc_write_error_info_func_no(uint16_t func_no); - -/* ********************************* CODE ********************************** */ - -#endif /* EMMC_DEF_H */ -/* ******************************** END ************************************ */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_hal.h b/plat/renesas/rza/common/drivers/emmc/emmc_hal.h deleted file mode 100644 index 0a8551719f..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_hal.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef EMMC_HAL_H -#define EMMC_HAL_H - -/* memory card error/status types */ -#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L -#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L -#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L -#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L -#define HAL_MEMCARD_ERASE_PARAM 0x08000000L -#define HAL_MEMCARD_WP_VIOLATION 0x04000000L -#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L -#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L -#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L -#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L -#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L -#define HAL_MEMCARD_CC_ERROR 0x00100000L -#define HAL_MEMCARD_ERROR 0x00080000L -#define HAL_MEMCARD_UNDERRUN 0x00040000L -#define HAL_MEMCARD_OVERRUN 0x00020000L -#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L -#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L -#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L -#define HAL_MEMCARD_ERASE_RESET 0x00002000L -#define HAL_MEMCARD_CARD_STATE 0x00001E00L -#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L -#define HAL_MEMCARD_APP_CMD 0x00000020L -#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L -#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L -#define HAL_MEMCARD_NO_ERRORS 0x00000000L - -/* Memory card response types */ -#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f - -/* Type of the return value. */ -typedef enum { - HAL_MEMCARD_FAIL = 0U, - HAL_MEMCARD_OK = 1U, - HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /* DMA channel allocation failed */ - HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /* DMA transfer failed */ - HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /* card status non-masked error */ - HAL_MEMCARD_CMD_TIMEOUT = 5U, /* Command timeout occurred */ - HAL_MEMCARD_DATA_TIMEOUT = 6U, /* Data timeout occurred */ - HAL_MEMCARD_CMD_CRC_ERROR = 7U, /* Command CRC error occurred */ - HAL_MEMCARD_DATA_CRC_ERROR = 8U /* Data CRC error occurred */ -} HAL_MEMCARD_RETURN; - -/* memory access operation */ -typedef enum { - HAL_MEMCARD_READ = 0U, /* read */ - HAL_MEMCARD_WRITE = 1U /* write */ -} HAL_MEMCARD_OPERATION; - -/* Type of data width on memorycard bus */ -typedef enum { - HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, - HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, - HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U -} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */ - -/* Presence of the memory card */ -typedef enum { - HAL_MEMCARD_CARD_IS_IN = 0U, - HAL_MEMCARD_CARD_IS_OUT = 1U -} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */ - -/* mode of data transfer */ -typedef enum { - HAL_MEMCARD_DMA = 0U, - HAL_MEMCARD_NOT_DMA = 1U -} HAL_MEMCARD_DATA_TRANSFER_MODE; - -/* Memory card response types. */ -typedef enum hal_memcard_response_type { - HAL_MEMCARD_RESPONSE_NONE = 0x00000U, - HAL_MEMCARD_RESPONSE_R1 = 0x00100U, - HAL_MEMCARD_RESPONSE_R1b = 0x00200U, - HAL_MEMCARD_RESPONSE_R2 = 0x00300U, - HAL_MEMCARD_RESPONSE_R3 = 0x00400U, - HAL_MEMCARD_RESPONSE_R4 = 0x00500U, - HAL_MEMCARD_RESPONSE_R5 = 0x00600U, - HAL_MEMCARD_RESPONSE_R6 = 0x00700U, - HAL_MEMCARD_RESPONSE_R7 = 0x00800U, - HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U -} HAL_MEMCARD_RESPONSE_TYPE; - -/* Memory card command types. */ -typedef enum hal_memcard_command_type { - HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, - HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, - HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, - HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, - HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, - HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U -} HAL_MEMCARD_COMMAND_TYPE; - -/* Type of memory card */ -typedef enum hal_memcard_command_card_type { - HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, - HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, - HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, - HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U -} HAL_MEMCARD_COMMAND_CARD_TYPE; - -/* Memory card application command. */ -typedef enum hal_memcard_command_app_norm { - HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, - HAL_MEMCARD_COMMAND_APP = 0x20000U, - HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U -} HAL_MEMCARD_COMMAND_APP_NORM; - -/* Memory card command codes. */ -typedef enum { -/* class 0 and class 1 */ - /* CMD0 */ - CMD0_GO_IDLE_STATE = - 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC | - (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD1 */ - CMD1_SEND_OP_COND = - 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD2 */ - CMD2_ALL_SEND_CID_MMC = - 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD2_ALL_SEND_CID_SD = - 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD3 */ - CMD3_SET_RELATIVE_ADDR = - 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD3_SEND_RELATIVE_ADDR = - 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD4 */ - CMD4_SET_DSR = - 4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD5 */ - CMD5_SLEEP_AWAKE = - 5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD6 */ - CMD6_SWITCH = - 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD6_SWITCH_FUNC = - 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - ACMD6_SET_BUS_WIDTH = - 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - /* CMD7 */ - CMD7_SELECT_CARD = - 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD7(from Disconnected State to Programming State) */ - CMD7_SELECT_CARD_PROG = - 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD7_DESELECT_CARD = - 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD8 */ - CMD8_SEND_EXT_CSD = - 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD8_SEND_IF_COND = - 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD9 */ - CMD9_SEND_CSD = - 9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD10 */ - CMD10_SEND_CID = - 10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD11 */ - CMD11_READ_DAT_UNTIL_STOP = - 11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD12 */ - CMD12_STOP_TRANSMISSION = - 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD12(R1b : write case) */ - CMD12_STOP_TRANSMISSION_WRITE = - 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD13 */ - CMD13_SEND_STATUS = - 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - ACMD13_SD_STATUS = - 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - /* CMD14 */ - CMD14_BUSTEST_R = - 14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD15 */ - CMD15_GO_INACTIVE_STATE = - 15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - -/* class 2 */ - /* CMD16 */ - CMD16_SET_BLOCKLEN = - 16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD17 */ - CMD17_READ_SINGLE_BLOCK = - 17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD18 */ - CMD18_READ_MULTIPLE_BLOCK = - 18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD19 */ - CMD19_BUS_TEST_W = - 19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - -/* class 3 */ - /* CMD20 */ - CMD20_WRITE_DAT_UNTIL_STOP = - 20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD21 */ - CMD21 = 21U, - /* CMD22 */ - CMD22 = 22U, - ACMD22_SEND_NUM_WR_BLOCKS = - 22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - -/* class 4 */ - /* CMD23 */ - CMD23_SET_BLOCK_COUNT = - 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - ACMD23_SET_WR_BLK_ERASE_COUNT = - 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - /* CMD24 */ - CMD24_WRITE_BLOCK = - 24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD25 */ - CMD25_WRITE_MULTIPLE_BLOCK = - 25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD26 */ - CMD26_PROGRAM_CID = - 26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD27 */ - CMD27_PROGRAM_CSD = - 27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - -/* class 6 */ - /* CMD28 */ - CMD28_SET_WRITE_PROT = - 28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD29 */ - CMD29_CLR_WRITE_PROT = - 29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD30 */ - CMD30_SEND_WRITE_PROT = - 30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD31 */ - CMD30_SEND_WRITE_PROT_TYPE = - 31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - -/* class 5 */ - /* CMD32 */ - CMD32_ERASE_WR_BLK_START = - 32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD33 */ - CMD33_ERASE_WR_BLK_END = - 33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD34 */ - CMD34 = 34U, - /* CMD35 */ - CMD35_ERASE_GROUP_START = - 35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD36 */ - CMD36_ERASE_GROUP_END = - 36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD37 */ - CMD37 = 37U, - /* CMD38 */ - CMD38_ERASE = - 38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - -/* class 9 */ - /* CMD39 */ - CMD39_FASTIO = - 39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD40 */ - CMD40_GO_IRQSTATE = - 40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD41 */ - CMD41 = 41, - ACMD41_SD_SEND_OP_COND = - 41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - -/* class 7 */ - /* CMD42 */ - CMD42_LOCK_UNLOCK = - 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - ACMD42_SET_CLR_CARD_DETECT = - 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - CMD43 = 43U, /* CMD43 */ - CMD44 = 44U, /* CMD44 */ - CMD45 = 45U, /* CMD45 */ - CMD46 = 46U, /* CMD46 */ - CMD47 = 47U, /* CMD47 */ - CMD48 = 48U, /* CMD48 */ - CMD49 = 49U, /* CMD49 */ - CMD50 = 50U, /* CMD50 */ - CMD51 = 51U, /* CMD51 */ - ACMD51_SEND_SCR = - 51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD | - (uint32_t)HAL_MEMCARD_COMMAND_APP, - CMD52 = 52U, /* CMD52 */ - CMD53 = 53U, /* CMD53 */ - CMD54 = 54U, /* CMD54 */ - -/* class 8 */ - /* CMD55 */ - CMD55_APP_CMD = - 55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - /* CMD56 */ - CMD56_GEN_CMD = - 56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 | - (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | - (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | - (uint32_t)HAL_MEMCARD_COMMAND_NORMAL, - CMD57 = 57U, /* CMD57 */ - CMD58 = 58U, /* CMD58 */ - CMD59 = 59U, /* CMD59 */ - CMD60 = 60U, /* CMD60 */ - CMD61 = 61U, /* CMD61 */ - CMD62 = 62U, /* CMD62 */ - CMD63 = 63U /* CMD63 */ -} HAL_MEMCARD_COMMAND; - -/* - * Configuration structure from HAL layer. - * - * If some field is not available it should be filled with 0xFF. - * The API version is 32-bit unsigned integer telling the version of the API. - * The integer is divided to four sections which each can be treated as a 8-bit - * unsigned number: - * Bits 31-24 make the most significant part of the version number. This number - * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This - * number changes only, if the API itself changes so much that it is not - * compatible anymore with older releases. - * Bits 23-16 API minor version number. For example API version 2.1 would be - * 0x0201xxxx. - * Bits 15-8 are the number of the year when release is done. The 0 is year - * 2000, 1 is year 2001 and so on - * Bits 7- are the week number when release is done. First full week of the - * year is 1 - * - * Example: let's assume that release 2.1 is done on week 10 year 2008 - * the version will get the value 0x0201080A - */ -typedef struct { - /* - * Version of the chipset API implementation - * - * bits [31:24] API specification major version number.
- * bits [23:16] API specification minor version number.
- * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...) - * bits [7:0] API implementation week. - * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E - */ - uint32_t api_version; - - /* maximum block count which can be transferred at once */ - uint32_t max_block_count; - - /* maximum clock frequence in Hz supported by HW */ - uint32_t max_clock_freq; - - /* maximum data bus width supported by HW */ - uint16_t max_data_width; - - /* Is high-speed mode supported by HW (yes=1, no=0) */ - uint8_t hs_mode_supported; - - /* Is memory card removable (yes=1, no=0) */ - uint8_t card_removable; - -} HAL_MEMCARD_HW_CONF; - -/* Configuration structure to HAL layer. */ -typedef struct { - /* how many times to try after fail, for instance sending command */ - uint32_t retries_after_fail; -} HAL_MEMCARD_INIT_CONF; - -#endif /* EMMC_HAL_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_init.c b/plat/renesas/rza/common/drivers/emmc/emmc_init.c deleted file mode 100644 index 49f687f8c4..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_init.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -st_mmc_base mmc_drv_obj; - -EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode) -{ - if (mode == TRUE) { - /* power on (Vcc&Vccq is always power on) */ - mmc_drv_obj.card_power_enable = TRUE; - } else { - /* power off (Vcc&Vccq is always power on) */ - mmc_drv_obj.card_power_enable = FALSE; - mmc_drv_obj.mount = FALSE; - mmc_drv_obj.selected = FALSE; - } - - return EMMC_SUCCESS; -} -static inline void emmc_set_retry_count(uint32_t retry) -{ - mmc_drv_obj.retries_after_fail = retry; -} - -static inline void emmc_set_data_timeout(uint32_t data_timeout) -{ - mmc_drv_obj.data_timeout = data_timeout; -} - -static void emmc_memset(uint8_t *buff, uint8_t data, uint32_t cnt) -{ - if (buff == NULL) { - return; - } - - while (cnt > 0) { - *buff++ = data; - cnt--; - } -} - -static void emmc_driver_config(void) -{ - emmc_set_retry_count(EMMC_RETRY_COUNT); - emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); -} - -static void emmc_drv_init(void) -{ - emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); - mmc_drv_obj.card_present = HAL_MEMCARD_CARD_IS_IN; - mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; - mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; -} - -static EMMC_ERROR_CODE emmc_dev_finalize(void) -{ - EMMC_ERROR_CODE result; - - /* - * MMC power off - * the power supply of eMMC device is always turning on. - * RST_n : Hi --> Low level. - */ - result = emmc_memcard_power(FALSE); - - /* host controller reset */ - SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ - SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ - SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ - SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ - - return result; -} - -static EMMC_ERROR_CODE emmc_dev_init(void) -{ - /* MMCIF initialize */ - SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ - SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ - SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ - - SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ - SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ - SETR_32(SD_CLK_CTRL, - 0x00000000U); /* Disable Automatic Control & Clock Output */ - - return EMMC_SUCCESS; -} - -static EMMC_ERROR_CODE emmc_reset_controller(void) -{ - EMMC_ERROR_CODE result; - - /* initialize mmc driver */ - emmc_drv_init(); - - /* initialize H/W */ - result = emmc_dev_init(); - if (result == EMMC_SUCCESS) { - mmc_drv_obj.initialize = TRUE; - } - - return result; -} - -EMMC_ERROR_CODE emmc_terminate(void) -{ - EMMC_ERROR_CODE result; - - result = emmc_dev_finalize(); - - emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); - - return result; -} - -EMMC_ERROR_CODE emmc_init(void) -{ - EMMC_ERROR_CODE result; - - result = emmc_reset_controller(); - if (result == EMMC_SUCCESS) { - emmc_driver_config(); - } - - return result; -} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c b/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c deleted file mode 100644 index 2c3c67663d..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights - * reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); - -uint32_t emmc_interrupt(void) -{ - EMMC_ERROR_CODE result; - uint32_t end_bit = BIT20; - - /* SD_INFO */ - mmc_drv_obj.error_info.info1 = GETR_32(SD_INFO1); - mmc_drv_obj.error_info.info2 = GETR_32(SD_INFO2); - - /* SD_INFO EVENT */ - mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & - GETR_32(SD_INFO1_MASK); - mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & - GETR_32(SD_INFO2_MASK); - - /* ERR_STS */ - mmc_drv_obj.error_info.status1 = GETR_32(SD_ERR_STS1); - mmc_drv_obj.error_info.status2 = GETR_32(SD_ERR_STS2); - - /* DM_CM_INFO */ - mmc_drv_obj.error_info.dm_info1 = GETR_32(DM_CM_INFO1); - mmc_drv_obj.error_info.dm_info2 = GETR_32(DM_CM_INFO2); - - /* DM_CM_INFO EVENT */ - mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & - GETR_32(DM_CM_INFO1_MASK); - mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & - GETR_32(DM_CM_INFO2_MASK); - - /* ERR SD_INFO2 */ - if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0) { - SETR_32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ - SETR_32(SD_INFO1, 0x00000000U); /* interrupt clear */ - SETR_32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ - mmc_drv_obj.state_machine_blocking = FALSE; - } - - /* PIO Transfer */ - /* BWE/BRE */ - else if (((SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2)) { - /* BWE */ - if (SD_INFO2_BWE & mmc_drv_obj.int_event2) { - SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE)); - } - /* BRE */ - else { - SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE)); - } - - result = emmc_trans_sector(mmc_drv_obj.buff_address_virtual); - mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; - mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; - - if (result != EMMC_SUCCESS) { - /* data transfer error */ - emmc_write_error_info(EMMC_FUNCNO_NONE, result); - - /* Panic */ - SETR_32(SD_INFO1_MASK, 0x00000000U); - SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); - SETR_32(SD_INFO1, 0x00000000U); - /* interrupt clear */ - SETR_32(SD_INFO2, SD_INFO2_CLEAR); - mmc_drv_obj.force_terminate = TRUE; - } else { - mmc_drv_obj.during_transfer = FALSE; - } - mmc_drv_obj.state_machine_blocking = FALSE; - } - - /* DMA_TRANSFER */ - /* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */ - else if ((BIT16 & mmc_drv_obj.dm_event1) != 0) { - SETR_32(DM_CM_INFO1, 0x00000000U); - SETR_32(DM_CM_INFO2, 0x00000000U); - /* interrupt clear */ - SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE)); - /* DM_CM_INFO2: DMA-ch0 error occurred */ - if ((BIT16 & mmc_drv_obj.dm_event2) != 0) { - mmc_drv_obj.dma_error_flag = TRUE; - } else { - mmc_drv_obj.during_dma_transfer = FALSE; - mmc_drv_obj.during_transfer = FALSE; - } - /* wait next interrupt */ - mmc_drv_obj.state_machine_blocking = FALSE; - } - /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */ - else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) { - SETR_32(DM_CM_INFO1, 0x00000000U); - SETR_32(DM_CM_INFO2, 0x00000000U); - /* interrupt clear */ - SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE)); - /* DM_CM_INFO2: DMA-ch1 error occurred */ - if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { - mmc_drv_obj.dma_error_flag = TRUE; - } else { - mmc_drv_obj.during_dma_transfer = FALSE; - mmc_drv_obj.during_transfer = FALSE; - } - /* wait next interrupt */ - mmc_drv_obj.state_machine_blocking = FALSE; - } - - /* Response end */ - else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0) { - /* interrupt clear */ - SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO0)); - mmc_drv_obj.state_machine_blocking = FALSE; - } - /* Access end */ - else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0) { - /* interrupt clear */ - SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO2)); - mmc_drv_obj.state_machine_blocking = FALSE; - } else { - /* nothing to do. */ - } - - return (uint32_t)0; -} - -static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) -{ - uint32_t length, i; - uint64_t *bufPtrLL; - - if (buff_address_virtual == NULL) { - return EMMC_ERR_PARAM; - } - - if ((mmc_drv_obj.during_transfer != TRUE) || - (mmc_drv_obj.remain_size == 0)) { - return EMMC_ERR_STATE; - } - - bufPtrLL = (uint64_t *)buff_address_virtual; - length = mmc_drv_obj.remain_size; - - /* data transefer */ - for (i = 0; i < (length >> 3); i++) { - /* Write */ - if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { - SETR_64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ - } - /* Read */ - else { - /* Checks when the read data reaches SD_SIZE. */ - /* The BRE bit is cleared at emmc_interrupt function. */ - if (((i % (uint32_t)(EMMC_BLOCK_LENGTH >> - EMMC_BUF_SIZE_SHIFT)) == 0U) && - (i != 0U)) { - /* BRE check */ - while (((GETR_32(SD_INFO2)) & SD_INFO2_BRE) == - 0U) { - /* ERROR check */ - if (((GETR_32(SD_INFO2)) & - SD_INFO2_ALL_ERR) != 0U) { - return EMMC_ERR_TRANSFER; - } - } - /* BRE clear */ - SETR_32(SD_INFO2, (uint32_t)(GETR_32(SD_INFO2) & - ~SD_INFO2_BRE)); - } - *bufPtrLL = GETR_64(SD_BUF0); /* FIFO --> buffer */ - } - bufPtrLL++; - } - - return EMMC_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_mount.c b/plat/renesas/rza/common/drivers/emmc/emmc_mount.c deleted file mode 100644 index ff01f7cb1d..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_mount.c +++ /dev/null @@ -1,664 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode); -static EMMC_ERROR_CODE emmc_card_init(void); -static EMMC_ERROR_CODE emmc_high_speed(void); -static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); -static uint32_t emmc_set_timeout_register_value(uint32_t freq); -static void set_sd_clk(uint32_t clkDiv); -static uint32_t emmc_calc_tran_speed(uint32_t *freq); -static void emmc_get_partition_access(void); -static void emmc_set_bootpartition(void); - -static void emmc_set_bootpartition(void) -{ - mmc_drv_obj.boot_partition_en = - (EMMC_PARTITION_ID)((mmc_drv_obj.ext_csd_data[179] & - EMMC_BOOT_PARTITION_EN_MASK) >> - EMMC_BOOT_PARTITION_EN_SHIFT); -} - -static EMMC_ERROR_CODE emmc_card_init(void) -{ - int32_t retry; - uint32_t freq = MMC_400KHZ; /* 390KHz */ - EMMC_ERROR_CODE result; - uint32_t result_calc; - - /* state check */ - if ((mmc_drv_obj.initialize != TRUE) || - (mmc_drv_obj.card_power_enable != TRUE) || - ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)) { - emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* clock on (force change) */ - mmc_drv_obj.current_freq = 0; - mmc_drv_obj.max_freq = MMC_20MHZ; - result = emmc_set_request_mmc_clock(&freq); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return EMMC_ERR; - } - - udelay(1000U); /* wait 1ms */ - - /* Get current access partition */ - emmc_get_partition_access(); - - /* CMD0, arg=0x00000000 */ - result = emmc_send_idle_cmd(0x00000000); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - udelay(200U); /* wait 74clock 390kHz(189.74us) */ - - /* CMD1 */ - emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); - for (retry = 300; retry > 0; retry--) { - result = - emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0) { - break; /* card is ready. exit loop */ - } - udelay(1000U); /* wait 1ms */ - } - - if (retry == 0) { - emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_TIMEOUT); - return EMMC_ERR_TIMEOUT; - } - - switch (mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) { - case EMMC_OCR_ACCESS_MODE_SECT: - mmc_drv_obj.access_mode = TRUE; /* sector mode */ - break; - default: - /* unknown value */ - emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR); - return EMMC_ERR; - } - - /* CMD2 */ - emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000); - mmc_drv_obj.response = - (uint32_t *)(&mmc_drv_obj - .cid_data[0]); /* use CID special buffer */ - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - /* CMD3 */ - emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - /* CMD9 (CSD) */ - emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16); - mmc_drv_obj.response = - (uint32_t *)(&mmc_drv_obj - .csd_data[0]); /* use CSD special buffer */ - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - /* card version check */ - if (EMMC_CSD_SPEC_VARS() < 4) { - emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, - EMMC_ERR_ILLEGAL_CARD); - return EMMC_ERR_ILLEGAL_CARD; - } - - /* CMD7 (select card) */ - emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - mmc_drv_obj.selected = TRUE; - - /* - * card speed check - * Card spec is calculated from TRAN_SPEED(CSD) - */ - result_calc = emmc_calc_tran_speed(&freq); - if (result_calc == 0) { - emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, - EMMC_ERR_ILLEGAL_CARD); - return EMMC_ERR_ILLEGAL_CARD; - } - mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ - - result = emmc_set_request_mmc_clock(&freq); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return EMMC_ERR; - } - - /* set read/write timeout */ - mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); - SETR_32(SD_OPTION, - ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | - mmc_drv_obj.data_timeout)); - - /* SET_BLOCKLEN(512byte) */ - /* CMD16 */ - emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - /* Transfer Data Length */ - SETR_32(SD_SIZE, EMMC_BLOCK_LENGTH); - - /* CMD8 (EXT_CSD) */ - emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, - (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), - EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, - HAL_MEMCARD_NOT_DMA); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - /* - * CMD12 is not send. - * If BUS initialization is failed, user must be execute Bus initialization again. - * Bus initialization is start CMD0(soft reset command). - */ - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - return result; - } - - /* Set boot partition */ - emmc_set_bootpartition(); - - return EMMC_SUCCESS; -} - -static EMMC_ERROR_CODE emmc_high_speed(void) -{ - uint32_t freq; /* High speed mode clock frequency */ - EMMC_ERROR_CODE result; - uint8_t cardType; - - /* state check */ - if (mmc_drv_obj.selected != TRUE) { - emmc_write_error_info(EMMC_FUNCNO_HIGH_SPEED, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* max frequency */ - cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; - if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0) - freq = MMC_52MHZ; - else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0) - freq = MMC_26MHZ; - else - freq = MMC_20MHZ; - - /* Hi-Speed-mode selection */ - if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) { - /* CMD6 */ - emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); - result = - emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); - return result; - } - - mmc_drv_obj.hs_timing = TIMING_HIGH_SPEED; /* High-Speed */ - } - - /* set mmc clock */ - mmc_drv_obj.max_freq = freq; - result = emmc_set_request_mmc_clock(&freq); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); - return EMMC_ERR; - } - - /* set read/write timeout */ - mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); - SETR_32(SD_OPTION, - ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | - mmc_drv_obj.data_timeout)); - - /* CMD13 */ - emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, - mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); - return result; - } - - return EMMC_SUCCESS; -} - -static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode) -{ - uint32_t value; - - /* busy check */ - if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) { - emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, - EMMC_ERR_CARD_BUSY); - return EMMC_ERR; - } - - if (mode == TRUE) { - /* clock ON */ - value = ((GETR_32(SD_CLK_CTRL) | MMC_SD_CLK_START) & - SD_CLK_WRITE_MASK); - SETR_32(SD_CLK_CTRL, value); /* on */ - mmc_drv_obj.clock_enable = TRUE; - } else { - /* clock OFF */ - value = ((GETR_32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & - SD_CLK_WRITE_MASK); - SETR_32(SD_CLK_CTRL, value); /* off */ - mmc_drv_obj.clock_enable = FALSE; - } - - return EMMC_SUCCESS; -} - -static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) -{ - EMMC_ERROR_CODE result = EMMC_ERR; - - /* parameter check */ - if ((width != 8) && (width != 4) && (width != 1)) { - emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* state check */ - if (mmc_drv_obj.selected != TRUE) { - emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* 2 = 8bit, 1 = 4bit, 0 =1bit */ - mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2); - - /* CMD6 */ - emmc_make_nontrans_cmd(CMD6_SWITCH, (EMMC_SWITCH_BUS_WIDTH_1 | - (mmc_drv_obj.bus_width << 8))); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - /* occurred error */ - mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; - goto EXIT; - } - - switch (mmc_drv_obj.bus_width) { - case HAL_MEMCARD_DATA_WIDTH_1_BIT: - SETR_32(SD_OPTION, - ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT15)); - break; - case HAL_MEMCARD_DATA_WIDTH_4_BIT: - SETR_32(SD_OPTION, (GETR_32(SD_OPTION) & ~(BIT15 | BIT13))); - break; - case HAL_MEMCARD_DATA_WIDTH_8_BIT: - SETR_32(SD_OPTION, - ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT13)); - break; - default: - goto EXIT; - } - - /* CMD13 */ - emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - goto EXIT; - } - - /* CMD8 (EXT_CSD) */ - emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, - (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), - EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, - HAL_MEMCARD_NOT_DMA); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - goto EXIT; - } - - return EMMC_SUCCESS; - -EXIT: - emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result); - ERROR("BL2: emmc bus_width error end\n"); - return result; -} - -EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) -{ - EMMC_ERROR_CODE result; - uint32_t arg; - uint32_t partition_config; - - /* state check */ - if (mmc_drv_obj.mount != TRUE) { - emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* id = PARTITION_ACCESS(Bit[2:0]) */ - if ((id & ~PARTITION_ID_MASK) != 0) { - emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* EXT_CSD[179] value */ - partition_config = - (uint32_t) - mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; - if ((partition_config & PARTITION_ID_MASK) == id) { - result = EMMC_SUCCESS; - } else { - partition_config = - (uint32_t)((partition_config & ~PARTITION_ID_MASK) | - id); - arg = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8); - - result = emmc_set_ext_csd(arg); - } - - return result; -} - -static void set_sd_clk(uint32_t clkDiv) -{ - uint32_t dataL; - - dataL = (GETR_32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); - - switch (clkDiv) { - case 1: - dataL |= 0x000000FFU; - break; /* 1/1 */ - case 2: - dataL |= 0x00000000U; - break; /* 1/2 */ - case 4: - dataL |= 0x00000001U; - break; /* 1/4 */ - case 8: - dataL |= 0x00000002U; - break; /* 1/8 */ - case 16: - dataL |= 0x00000004U; - break; /* 1/16 */ - case 32: - dataL |= 0x00000008U; - break; /* 1/32 */ - case 64: - dataL |= 0x00000010U; - break; /* 1/64 */ - case 128: - dataL |= 0x00000020U; - break; /* 1/128 */ - case 256: - dataL |= 0x00000040U; - break; /* 1/256 */ - case 512: - dataL |= 0x00000080U; - break; /* 1/512 */ - } - - SETR_32(SD_CLK_CTRL, dataL); - mmc_drv_obj.current_freq = (uint32_t)clkDiv; -} - -static void emmc_get_partition_access(void) -{ - EMMC_ERROR_CODE result; - - SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */ - /* CMD8 (EXT_CSD) */ - emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, - (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), - EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, - HAL_MEMCARD_NOT_DMA); - mmc_drv_obj.get_partition_access_flag = TRUE; - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - mmc_drv_obj.get_partition_access_flag = FALSE; - if (result == EMMC_SUCCESS) { - mmc_drv_obj.partition_access = - (EMMC_PARTITION_ID)(mmc_drv_obj.ext_csd_data[179] & - PARTITION_ID_MASK); - } else if (result == EMMC_ERR_CMD_TIMEOUT) { - mmc_drv_obj.partition_access = PARTITION_ID_BOOT_1; - } else { - emmc_write_error_info(EMMC_FUNCNO_GET_PERTITION_ACCESS, result); - panic(); - } - SETR_32(SD_OPTION, 0x0000C0EEU); /* Initialize */ -} - -static uint32_t emmc_calc_tran_speed(uint32_t *freq) -{ - const uint32_t unit[8] = { - 10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U - }; /* frequency unit (1/10) */ - const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, - 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U }; - uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); - uint32_t max_freq; - uint32_t result; - - /* - * tran_speed = 0x32 - * unit[tran_speed&0x7] = uint[0x2] = 1000000 - * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 - * 1000000 * 26 = 26000000 (26MHz) - */ - - result = 1; - max_freq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] * - mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> - EMMC_TRANSPEED_MULT_SHIFT]; - - if (max_freq == 0) { - result = 0; - } else if (max_freq >= MMC_FREQ_52MHZ) { - *freq = MMC_52MHZ; - } else if (max_freq >= MMC_FREQ_26MHZ) { - *freq = MMC_26MHZ; - } else if (max_freq >= MMC_FREQ_20MHZ) { - *freq = MMC_20MHZ; - } else { - *freq = MMC_400KHZ; - } - - return result; -} - -static uint32_t emmc_set_timeout_register_value(uint32_t freq) -{ - uint32_t timeout_cnt; /* SD_OPTION - Timeout Counter */ - - switch (freq) { - case 1U: - timeout_cnt = 0xE0U; - break; /* SDCLK * 2^27 */ - case 2U: - timeout_cnt = 0xE0U; - break; /* SDCLK * 2^27 */ - case 4U: - timeout_cnt = 0xD0U; - break; /* SDCLK * 2^26 */ - case 8U: - timeout_cnt = 0xC0U; - break; /* SDCLK * 2^25 */ - case 16U: - timeout_cnt = 0xB0U; - break; /* SDCLK * 2^24 */ - case 32U: - timeout_cnt = 0xA0U; - break; /* SDCLK * 2^23 */ - case 64U: - timeout_cnt = 0x90U; - break; /* SDCLK * 2^22 */ - case 128U: - timeout_cnt = 0x80U; - break; /* SDCLK * 2^21 */ - case 256U: - timeout_cnt = 0x70U; - break; /* SDCLK * 2^20 */ - case 512U: - timeout_cnt = 0x70U; - break; /* SDCLK * 2^20 */ - default: - timeout_cnt = 0xE0U; - break; /* SDCLK * 2^27 */ - } - - return timeout_cnt; -} - -EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) -{ - EMMC_ERROR_CODE result; - - /* CMD6 */ - emmc_make_nontrans_cmd(CMD6_SWITCH, arg); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - - /* CMD13 */ - emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - - /* CMD8 (EXT_CSD) */ - emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, - (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), - EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, - HAL_MEMCARD_NOT_DMA); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - return EMMC_SUCCESS; -} - -EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq) -{ - /* parameter check */ - if (freq == NULL) { - emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* state check */ - if ((mmc_drv_obj.initialize != TRUE) || - (mmc_drv_obj.card_power_enable != TRUE)) { - emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* clock is already running in the desired frequency. */ - if ((mmc_drv_obj.clock_enable == TRUE) && - (mmc_drv_obj.current_freq == *freq)) { - return EMMC_SUCCESS; - } - - /* busy check */ - if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) { - emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, - EMMC_ERR_CARD_BUSY); - return EMMC_ERR; - } - - set_sd_clk(*freq); - mmc_drv_obj.clock_enable = FALSE; - - return emmc_clock_ctrl(TRUE); /* clock on */ -} - -EMMC_ERROR_CODE emmc_mount(void) -{ - EMMC_ERROR_CODE result; - - /* state check */ - if ((mmc_drv_obj.initialize != TRUE) || - (mmc_drv_obj.card_power_enable != TRUE) || - ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)) { - emmc_write_error_info(EMMC_FUNCNO_MOUNT, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* initialize card (IDLE state --> Transfer state) */ - result = emmc_card_init(); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); - if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { - /* nothing to do. */ - } - return result; - } - - /* Switching high speed mode */ - result = emmc_high_speed(); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); - if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { - /* nothing to do. */ - } - return result; - } - - /* Changing the data bus width */ - result = emmc_bus_width(8); - if (result != EMMC_SUCCESS) { - emmc_write_error_info_func_no(EMMC_FUNCNO_BUS_WIDTH); - if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) { - /* nothing to do. */ - } - return result; - } - - /* mount complete */ - mmc_drv_obj.mount = TRUE; - - return EMMC_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_read.c b/plat/renesas/rza/common/drivers/emmc/emmc_read.c deleted file mode 100644 index 03153827d1..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_read.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b)) -#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU - -static EMMC_ERROR_CODE -emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, - uint32_t count, - HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) -{ - EMMC_ERROR_CODE result; - - /* parameter check */ - if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0) || - ((transfer_mode != HAL_MEMCARD_DMA) && - (transfer_mode != HAL_MEMCARD_NOT_DMA))) { - emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* CMD23 */ - emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - SETR_32(SD_SECCNT, count); - SETR_32(SD_STOP, 0x00000100); - /* SD_BUF Read/Write DMA Transfer enable */ - SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); - - /* CMD18 */ - emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, - buff_address_virtual, - count << EMMC_SECTOR_SIZE_SHIFT, HAL_MEMCARD_READ, - transfer_mode); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; /* CMD18 error code */ - } - - /* CMD13 */ - emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16); - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - - if (transfer_mode == HAL_MEMCARD_NOT_DMA) { - flush_dcache_range((uint64_t)buff_address_virtual, - ((size_t)count << EMMC_SECTOR_SIZE_SHIFT)); - } - - /* ready status check */ - if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0) { - emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, - EMMC_ERR_CARD_BUSY); - return EMMC_ERR_CARD_BUSY; - } - - /* state check */ - if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) { - emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, - EMMC_ERR_CARD_STATE); - return EMMC_ERR_CARD_STATE; - } - - return EMMC_SUCCESS; -} - -EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, - uint32_t sector_number, uint32_t count, - uint32_t feature_flags) -{ - uint32_t trans_count; - uint32_t remain; - EMMC_ERROR_CODE result; - HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; - - /* parameter check */ - if (count == 0) { - emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); - return EMMC_ERR_PARAM; - } - - /* state check */ - if (mmc_drv_obj.mount != TRUE) { - emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_STATE); - return EMMC_ERR_STATE; - } - - /* DMA? */ - if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0) { - transfer_mode = HAL_MEMCARD_DMA; - } else { - transfer_mode = HAL_MEMCARD_NOT_DMA; - } - - remain = count; - while (remain != 0) { - trans_count = MIN_EMMC(remain, EMMC_RW_SECTOR_COUNT_MAX); - result = emmc_multiple_block_read(buff_address_virtual, - sector_number, trans_count, - transfer_mode); - if (result != EMMC_SUCCESS) { - return result; - } - - buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); - sector_number += trans_count; - remain -= trans_count; - } - - return EMMC_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_registers.h b/plat/renesas/rza/common/drivers/emmc/emmc_registers.h deleted file mode 100644 index 0c28bc3626..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_registers.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef EMMC_REGISTERS_H -#define EMMC_REGISTERS_H - -/* MMC channel select */ -#define MMC_CH0 (0U) /* SDHI2/MMC0 */ -#define MMC_CH1 (1U) /* SDHI3/MMC1 */ - -#define USE_MMC_CH (MMC_CH0) - -#define BIT0 (0x00000001U) -#define BIT1 (0x00000002U) -#define BIT2 (0x00000004U) -#define BIT3 (0x00000008U) -#define BIT4 (0x00000010U) -#define BIT5 (0x00000020U) -#define BIT6 (0x00000040U) -#define BIT7 (0x00000080U) -#define BIT8 (0x00000100U) -#define BIT9 (0x00000200U) -#define BIT10 (0x00000400U) -#define BIT11 (0x00000800U) -#define BIT12 (0x00001000U) -#define BIT13 (0x00002000U) -#define BIT14 (0x00004000U) -#define BIT15 (0x00008000U) -#define BIT16 (0x00010000U) -#define BIT17 (0x00020000U) -#define BIT18 (0x00040000U) -#define BIT19 (0x00080000U) -#define BIT20 (0x00100000U) -#define BIT21 (0x00200000U) -#define BIT22 (0x00400000U) -#define BIT23 (0x00800000U) -#define BIT24 (0x01000000U) -#define BIT25 (0x02000000U) -#define BIT26 (0x04000000U) -#define BIT27 (0x08000000U) -#define BIT28 (0x10000000U) -#define BIT29 (0x20000000U) -#define BIT30 (0x40000000U) -#define BIT31 (0x80000000U) - - -/* eMMC registers */ -#define MMC0_SD_BASE (0x11C00000U) -#define MMC1_SD_BASE (0x11C10000U) - -#if USE_MMC_CH == MMC_CH0 -#define MMC_SD_BASE (MMC0_SD_BASE) -#else /* USE_MMC_CH == MMC_CH0 */ -#define MMC_SD_BASE (MMC1_SD_BASE) -#endif /* USE_MMC_CH == MMC_CH0 */ - -#define SD_CMD (MMC_SD_BASE + 0x0000U) -#define SD_PORTSEL (MMC_SD_BASE + 0x0008U) -#define SD_ARG (MMC_SD_BASE + 0x0010U) -#define SD_ARG1 (MMC_SD_BASE + 0x0018U) -#define SD_STOP (MMC_SD_BASE + 0x0020U) -#define SD_SECCNT (MMC_SD_BASE + 0x0028U) -#define SD_RSP10 (MMC_SD_BASE + 0x0030U) -#define SD_RSP1 (MMC_SD_BASE + 0x0038U) -#define SD_RSP32 (MMC_SD_BASE + 0x0040U) -#define SD_RSP3 (MMC_SD_BASE + 0x0048U) -#define SD_RSP54 (MMC_SD_BASE + 0x0050U) -#define SD_RSP5 (MMC_SD_BASE + 0x0058U) -#define SD_RSP76 (MMC_SD_BASE + 0x0060U) -#define SD_RSP7 (MMC_SD_BASE + 0x0068U) -#define SD_INFO1 (MMC_SD_BASE + 0x0070U) -#define SD_INFO2 (MMC_SD_BASE + 0x0078U) -#define SD_INFO1_MASK (MMC_SD_BASE + 0x0080U) -#define SD_INFO2_MASK (MMC_SD_BASE + 0x0088U) -#define SD_CLK_CTRL (MMC_SD_BASE + 0x0090U) -#define SD_SIZE (MMC_SD_BASE + 0x0098U) -#define SD_OPTION (MMC_SD_BASE + 0x00A0U) -#define SD_ERR_STS1 (MMC_SD_BASE + 0x00B0U) -#define SD_ERR_STS2 (MMC_SD_BASE + 0x00B8U) -#define SD_BUF0 (MMC_SD_BASE + 0x00C0U) -#define SDIO_MODE (MMC_SD_BASE + 0x00D0U) -#define SDIO_INFO1 (MMC_SD_BASE + 0x00D8U) -#define SDIO_INFO1_MASK (MMC_SD_BASE + 0x00E0U) -#define CC_EXT_MODE (MMC_SD_BASE + 0x0360U) -#define SOFT_RST (MMC_SD_BASE + 0x0380U) -#define VERSION (MMC_SD_BASE + 0x0388U) -#define HOST_MODE (MMC_SD_BASE + 0x0390U) -#define DM_CM_DTRAN_MODE (MMC_SD_BASE + 0x0820U) -#define DM_CM_DTRAN_CTRL (MMC_SD_BASE + 0x0828U) -#define DM_CM_RST (MMC_SD_BASE + 0x0830U) -#define DM_CM_INFO1 (MMC_SD_BASE + 0x0840U) -#define DM_CM_INFO1_MASK (MMC_SD_BASE + 0x0848U) -#define DM_CM_INFO2 (MMC_SD_BASE + 0x0850U) -#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U) -#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U) - -/* SD_INFO1 Registers */ -#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */ -#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */ -#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */ -#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */ -#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */ -#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */ -#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */ -#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */ -#define SD_INFO1_INFO2 0x00000004UL /* Access end */ -#define SD_INFO1_INFO0 0x00000001UL /* Response end */ - -/* SD_INFO2 Registers */ -#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */ -#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */ -#define SD_INFO2_SCLKDIVEN 0x00002000UL -#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */ -#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */ -#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */ -#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */ -#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */ -#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */ -#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */ -#define SD_INFO2_ERR2 0x00000004UL /* END Error */ -#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */ -#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */ -#define SD_INFO2_ALL_ERR 0x0000807FUL -#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */ - -/* SOFT_RST */ -#define SOFT_RST_SDRST 0x00000001UL - -/* SD_CLK_CTRL */ -#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL -#define SD_CLK_CTRL_SCLKEN 0x00000100UL -#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL -#define SD_CLOCK_ENABLE 0x00000100UL -#define SD_CLOCK_DISABLE 0x00000000UL -#define SD_CLK_WRITE_MASK 0x000003FFUL -#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL - -/* SD_OPTION */ -#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL - -/* - * MMC Clock Frequency - * (533MHz/4) * 1/x = output clock - */ -#define MMC_CLK_OFF 0UL /* Clock output is disabled */ -#define MMC_400KHZ 512UL /* (533MHz/4) * 1/512 = 260 KHz */ -#define MMC_20MHZ 8UL /* (533MHz/4) * 1/8 = 16.7 MHz Normal speed mode */ -#define MMC_26MHZ 8UL /* (533MHz/4) * 1/8 = 16.7 MHz High speed mode 26Mhz */ -#define MMC_52MHZ 4UL /* (533MHz/4) * 1/4 = 33.3 MHz High speed mode 52Mhz */ -#define MMC_100MHZ 2UL /* (533MHz/4) * 1/2 = 66.6 MHz */ -#define MMC_200MHZ 1UL /* (533MHz/4) * 1/1 = 133.3 MHz */ - -#define MMC_FREQ_52MHZ 52000000UL -#define MMC_FREQ_26MHZ 26000000UL -#define MMC_FREQ_20MHZ 20000000UL - -/* MMC Clock DIV */ -#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */ -#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ -#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */ -#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */ -#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */ -#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */ -#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */ -#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */ -#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */ -#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */ -#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */ -#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */ - -/* DM_CM_DTRAN_MODE */ -#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */ -#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */ -#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL - -/* CC_EXT_MODE */ -#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */ -#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */ - -/* DM_CM_INFO_MASK */ -#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL -#define DM_CM_INFO_CH0_ENABLE 0x00010001UL -#define DM_CM_INFO_CH1_ENABLE 0x00020001UL - -/* DM_DTRAN_ADDR */ -#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL - -/* DM_CM_DTRAN_CTRL */ -#define DM_CM_DTRAN_CTRL_START 0x00000001UL - -#endif /* EMMC_REGISTERS_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_std.h b/plat/renesas/rza/common/drivers/emmc/emmc_std.h deleted file mode 100644 index 47d021c9ba..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_std.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef EMMC_STD_H -#define EMMC_STD_H - -#include "emmc_hal.h" - -#ifndef FALSE -#define FALSE 0U -#endif -#ifndef TRUE -#define TRUE 1U -#endif - -/* 64bit registers */ -#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) -#define GETR_64(r) (*(volatile uint64_t *)(r)) - -/* 32bit registers */ -#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) -#define GETR_32(r) (*(volatile uint32_t *)(r)) - -/* 16bit registers */ -#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) -#define GETR_16(r) (*(volatile uint16_t *)(r)) - -/* 8bit registers */ -#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) -#define GETR_8(r) (*(volatile uint8_t *)(r)) - -/* CSD register Macros */ -#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) - -#define EMMC_CID_MID() (EMMC_GET_CID(127, 120)) -#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112)) -#define EMMC_CID_OID() (EMMC_GET_CID(111, 104)) -#define EMMC_CID_PNM1() (EMMC_GET_CID(103, 88)) -#define EMMC_CID_PNM2() (EMMC_GET_CID(87, 56)) -#define EMMC_CID_PRV() (EMMC_GET_CID(55, 48)) -#define EMMC_CID_PSN() (EMMC_GET_CID(47, 16)) -#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8)) -#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1)) - -/* CSD register Macros */ -#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) - -#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126)) -#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122)) -#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112)) -#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104)) -#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96)) -#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84)) -#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80)) -#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79)) -#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78)) -#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77)) -#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76)) -#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62)) -#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59)) -#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56)) -#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53)) -#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50)) -#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47)) -#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42)) -#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37)) -#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32)) -#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31)) -#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29)) -#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26)) -#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22)) -#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21)) -#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16)) -#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15)) -#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14)) -#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13)) -#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12)) -#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10)) -#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8)) -#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1)) - -/* sector access */ -#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 -#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */ -#define EMMC_SECTOR_SIZE 512 -#define EMMC_BLOCK_LENGTH 512 -#define EMMC_BLOCK_LENGTH_DW 128 -#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */ - -/* eMMC specification clock */ -#define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */ -#define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */ -#define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */ -#define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */ -#define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */ - -/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ -typedef enum { - EMMC_ERR = 0, /* unknown error */ - EMMC_SUCCESS, /* OK */ - EMMC_ERR_FROM_DMAC, /* DMAC allocation error */ - EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */ - EMMC_ERR_CARD_STATUS_BIT, /* card status error */ - EMMC_ERR_CMD_TIMEOUT, /* command timeout error */ - EMMC_ERR_DATA_TIMEOUT, /* data timeout error */ - EMMC_ERR_CMD_CRC, /* command CRC error */ - EMMC_ERR_DATA_CRC, /* data CRC error */ - EMMC_ERR_PARAM, /* parameter error */ - EMMC_ERR_RESPONSE, /* response error */ - EMMC_ERR_RESPONSE_BUSY, /* response busy error */ - EMMC_ERR_TRANSFER, /* data transfer error */ - EMMC_ERR_READ_SECTOR, /* read sector error */ - EMMC_ERR_WRITE_SECTOR, /* write sector error */ - EMMC_ERR_STATE, /* state error */ - EMMC_ERR_TIMEOUT, /* timeout error */ - EMMC_ERR_ILLEGAL_CARD, /* illegal card */ - EMMC_ERR_CARD_BUSY, /* Busy state */ - EMMC_ERR_CARD_STATE, /* card state error */ - EMMC_ERR_SET_TRACE, /* trace information error */ - EMMC_ERR_FROM_TIMER, /* Timer error */ - EMMC_ERR_FORCE_TERMINATE, /* Force terminate */ - EMMC_ERR_CARD_POWER, /* card power fail */ - EMMC_ERR_ERASE_SECTOR, /* erase sector error */ - EMMC_ERR_INFO2 /* exec cmd error info2 */ -} EMMC_ERROR_CODE; - -/* Function number */ -#define EMMC_FUNCNO_NONE 0U -#define EMMC_FUNCNO_DRIVER_INIT 1U -#define EMMC_FUNCNO_CARD_POWER_ON 2U -#define EMMC_FUNCNO_MOUNT 3U -#define EMMC_FUNCNO_CARD_INIT 4U -#define EMMC_FUNCNO_HIGH_SPEED 5U -#define EMMC_FUNCNO_BUS_WIDTH 6U -#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U -#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U -#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U -#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U -#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U -#define EMMC_FUNCNO_SET_CLOCK 12U -#define EMMC_FUNCNO_EXEC_CMD 13U -#define EMMC_FUNCNO_READ_SECTOR 14U -#define EMMC_FUNCNO_WRITE_SECTOR 15U -#define EMMC_FUNCNO_ERASE_SECTOR 16U -#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U -/* - * Response - * R1 - * Type 'E' bit and bit14(must be 0). ignore bit22 - */ -#define EMMC_R1_ERROR_MASK 0xFDBFE080U -/* Ignore bit23 (Not check CRC error) */ -#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) -#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */ -#define EMMC_R1_READY 0x00000100U /* bit8 */ -#define EMMC_R1_STATE_SHIFT 9 - -/* R4 */ -#define EMMC_R4_RCA_MASK 0xFFFF0000UL -#define EMMC_R4_STATUS 0x00008000UL - -/* CSD */ -#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */ -#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0 -#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */ -#define EMMC_TRANSPEED_MULT_SHIFT 3 - -/* OCR */ -#define EMMC_HOST_OCR_VALUE 0x40FF8080 -#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */ -#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */ -#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L -#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L - -/* EXT_CSD */ -#define EMMC_EXT_CSD_S_CMD_SET 504 -#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241 -#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239 -#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238 -#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235 -#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234 -#define EMMC_EXT_CSD_TRIM_MULT 232 -#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231 -#define EMMC_EXT_CSD_SEC_ERASE_MULT 229 -#define EMMC_EXT_CSD_BOOT_INFO 228 -#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226 -#define EMMC_EXT_CSD_ACC_SIZE 225 -#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224 -#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223 -#define EMMC_EXT_CSD_PEL_WR_SEC_C 222 -#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221 -#define EMMC_EXT_CSD_S_C_VCC 220 -#define EMMC_EXT_CSD_S_C_VCCQ 219 -#define EMMC_EXT_CSD_S_A_TIMEOUT 217 -#define EMMC_EXT_CSD_SEC_COUNT 215 -#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210 -#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209 -#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208 -#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207 -#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206 -#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205 -#define EMMC_EXT_CSD_PWR_CL_26_360 203 -#define EMMC_EXT_CSD_PWR_CL_52_360 202 -#define EMMC_EXT_CSD_PWR_CL_26_195 201 -#define EMMC_EXT_CSD_PWR_CL_52_195 200 -#define EMMC_EXT_CSD_CARD_TYPE 196 -#define EMMC_EXT_CSD_CSD_STRUCTURE 194 -#define EMMC_EXT_CSD_EXT_CSD_REV 192 -#define EMMC_EXT_CSD_CMD_SET 191 -#define EMMC_EXT_CSD_CMD_SET_REV 189 -#define EMMC_EXT_CSD_POWER_CLASS 187 -#define EMMC_EXT_CSD_HS_TIMING 185 -#define EMMC_EXT_CSD_BUS_WIDTH 183 -#define EMMC_EXT_CSD_ERASED_MEM_CONT 181 -#define EMMC_EXT_CSD_PARTITION_CONFIG 179 -#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178 -#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177 -#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175 -#define EMMC_EXT_CSD_BOOT_WP 173 -#define EMMC_EXT_CSD_USER_WP 171 -#define EMMC_EXT_CSD_FW_CONFIG 169 -#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168 -#define EMMC_EXT_CSD_RST_n_FUNCTION 162 -#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160 -#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159 -#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156 -#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155 -#define EMMC_EXT_CSD_GP_SIZE_MULT 154 -#define EMMC_EXT_CSD_ENH_SIZE_MULT 142 -#define EMMC_EXT_CSD_ENH_START_ADDR 139 -#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134 - -#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01 -#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02 -#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04 -#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08 -#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e - -/* SWITCH (CMD6) argument */ -#define EXTCSD_ACCESS_BYTE (BIT25 | BIT24) -#define EXTCSD_SET_BITS BIT24 - -#define HS_TIMING_ADD (185 << 16) /* H'b9 */ -#define HS_TIMING_1 (1 << 8) -#define HS_TIMING_HS200 (2 << 8) -#define HS_TIMING_HS400 (3 << 8) - -#define BUS_WIDTH_ADD (183 << 16) /* H'b7 */ -#define BUS_WIDTH_1 (0 << 8) -#define BUS_WIDTH_4 (1 << 8) -#define BUS_WIDTH_8 (2 << 8) -#define BUS_WIDTH_4DDR (5 << 8) -#define BUS_WIDTH_8DDR (6 << 8) - -#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\ - HS_TIMING_1) /* H'03b90100 */ -#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\ - HS_TIMING_ADD) /* H'03b90000 */ - -#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ - BUS_WIDTH_1) /* H'03b70000 */ -#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ - BUS_WIDTH_4) /* H'03b70100 */ -#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ - BUS_WIDTH_8) /* H'03b70200 */ -#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ - BUS_WIDTH_4DDR) /* H'03b70500 */ -#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\ - BUS_WIDTH_8DDR) /* H'03b70600 */ -/* Partition config = 0x00 */ -#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL - -#define TIMING_HIGH_SPEED 1UL -#define EMMC_BOOT_PARTITION_EN_MASK 0x38U -#define EMMC_BOOT_PARTITION_EN_SHIFT 3U - -/* Bus width */ -#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT -#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT -#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT - -/* for st_mmc_base */ -#define EMMC_MAX_RESPONSE_LENGTH 17 -#define EMMC_MAX_CID_LENGTH 16 -#define EMMC_MAX_CSD_LENGTH 16 -#define EMMC_MAX_EXT_CSD_LENGTH 512U -#define EMMC_RES_REG_ALIGNED 4U -#define EMMC_BUF_REG_ALIGNED 8U - -/* TAAC mask */ -#define TAAC_TIME_UNIT_MASK (0x07) -#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) - -/* Partition id */ -typedef enum { - PARTITION_ID_USER = 0x0, /* User Area */ - PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */ - PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */ - PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */ - PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */ - PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */ - PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */ - PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */ - PARTITION_ID_MASK = 0x7, /* [2:0] */ -} EMMC_PARTITION_ID; - -/* card state in R1 response [12:9] */ -typedef enum { - EMMC_R1_STATE_IDLE = 0, - EMMC_R1_STATE_READY, - EMMC_R1_STATE_IDENT, - EMMC_R1_STATE_STBY, - EMMC_R1_STATE_TRAN, - EMMC_R1_STATE_DATA, - EMMC_R1_STATE_RCV, - EMMC_R1_STATE_PRG, - EMMC_R1_STATE_DIS, - EMMC_R1_STATE_BTST, - EMMC_R1_STATE_SLEP -} EMMC_R1_STATE; - -typedef enum { - ESTATE_BEGIN = 0, - ESTATE_ISSUE_CMD, - ESTATE_NON_RESP_CMD, - ESTATE_RCV_RESP, - ESTATE_RCV_RESPONSE_BUSY, - ESTATE_CHECK_RESPONSE_COMPLETE, - ESTATE_DATA_TRANSFER, - ESTATE_DATA_TRANSFER_COMPLETE, - ESTATE_ACCESS_END, - ESTATE_TRANSFER_ERROR, - ESTATE_ERROR, - ESTATE_END -} EMMC_INT_STATE; - -/* eMMC boot driver error information */ -typedef struct { - uint16_t num; /* error no */ - uint16_t code; /* error code */ - - volatile uint32_t info1; /* SD_INFO1. (hw dependent) */ - volatile uint32_t info2; /* SD_INFO2. (hw dependent) */ - volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */ - volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */ - volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */ - volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */ -} st_error_info; - -/* Command information */ -typedef struct { - HAL_MEMCARD_COMMAND cmd; /* Command information */ - uint32_t arg; /* argument */ - HAL_MEMCARD_OPERATION dir; /* direction */ - uint32_t hw; /* SD_CMD register value. */ -} st_command_info; - -/* MMC driver base */ -typedef struct { - st_error_info error_info; /* error information */ - st_command_info cmd_info; /* command information */ - - /* for data transfer */ - uint32_t *buff_address_virtual; /* Dest or Src buff */ - uint32_t *buff_address_physical; /* Dest or Src buff */ - HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */ - - uint32_t trans_size; /* transfer size for this command */ - uint32_t remain_size; /* remain size for this command */ - uint32_t response_length; /* response length for this command */ - uint32_t sector_size; /* sector_size */ - - /* clock */ - uint32_t base_clock; /* MMC host controller clock */ - /* - * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and - * EXT_CSD. - */ - uint32_t max_freq; - /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */ - uint32_t request_freq; - /* current MMC clock[Hz] (the closest frequency supported by HW) */ - uint32_t current_freq; - - /* state flag */ - /* presence status of the memory card */ - HAL_MEMCARD_PRESENCE_STATUS card_present; - - uint32_t card_power_enable; - uint32_t clock_enable; - /* True : initialize complete. */ - uint32_t initialize; - /* True : sector access, FALSE : byte access */ - uint32_t access_mode; - /* True : mount complete. */ - uint32_t mount; - /* True : selected card. */ - uint32_t selected; - /* 0: DMA, 1:PIO */ - HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; - - /* loaded ISSW image No. ISSW have copy image. */ - uint32_t image_num; - /* card state */ - EMMC_R1_STATE current_state; - /* True : during command processing */ - volatile uint32_t during_cmd_processing; - /* True : during transfer */ - volatile uint32_t during_transfer; - /* True : during transfer (DMA) */ - volatile uint32_t during_dma_transfer; - /* True : occurred DMAC error */ - volatile uint32_t dma_error_flag; - /* force terminate flag */ - volatile uint32_t force_terminate; - /* state machine blocking flag : True or False */ - volatile uint32_t state_machine_blocking; - /* True : get partition access processing */ - volatile uint32_t get_partition_access_flag; - - EMMC_PARTITION_ID boot_partition_en; /* Boot partition */ - EMMC_PARTITION_ID partition_access; /* Current access partition */ - - /* timeout */ - uint32_t hs_timing; - - /* read and write data timeout */ - uint32_t data_timeout; - - /* retry */ - uint32_t retries_after_fail; - - /* interrupt */ - volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */ - volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */ - volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */ - volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */ - - /* response */ - uint32_t *response; /* buffer ptr for executing command. */ - uint32_t r1_card_status; /* R1 response data */ - uint32_t r3_ocr; /* R3 response data */ - uint32_t r4_resp; /* R4 response data */ - uint32_t r5_resp; /* R5 response data */ - - /* True : clock mode is low. (MMC clock = Max26MHz) */ - uint32_t low_clock_mode_enable; - - uint32_t reserved2; - uint32_t reserved3; - uint32_t reserved4; - - /* CSD registers (4byte align) */ - uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */ - __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); - /* CID registers (4byte align) */ - uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */ - __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); - /* EXT CSD registers (8byte align) */ - uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */ - __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED))); - /* Response registers (4byte align) */ - uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */ - __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); -} st_mmc_base; - -typedef int (*func) (void); - -uint32_t emmc_get_csd_time(void); - -#define MMC_DEBUG -#endif /* EMMC_STD_H */ diff --git a/plat/renesas/rza/common/drivers/emmc/emmc_utility.c b/plat/renesas/rza/common/drivers/emmc/emmc_utility.c deleted file mode 100644 index 632ba73c66..0000000000 --- a/plat/renesas/rza/common/drivers/emmc/emmc_utility.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_registers.h" -#include "emmc_std.h" - -static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = { - 0x00000000, /* CMD0 */ - 0x00000701, /* CMD1 */ - 0x00000002, /* CMD2 */ - 0x00000003, /* CMD3 */ - 0x00000004, /* CMD4 */ - 0x00000505, /* CMD5 */ - 0x00000406, /* CMD6 */ - 0x00000007, /* CMD7 */ - 0x00001C08, /* CMD8 */ - 0x00000009, /* CMD9 */ - 0x0000000A, /* CMD10 */ - 0x00000000, /* reserved */ - 0x0000000C, /* CMD12 */ - 0x0000000D, /* CMD13 */ - 0x00001C0E, /* CMD14 */ - 0x0000000F, /* CMD15 */ - 0x00000010, /* CMD16 */ - 0x00000011, /* CMD17 */ - 0x00007C12, /* CMD18 */ - 0x00000C13, /* CMD19 */ - 0x00000000, 0x00001C15, /* CMD21 */ - 0x00000000, 0x00000017, /* CMD23 */ - 0x00000018, /* CMD24 */ - 0x00006C19, /* CMD25 */ - 0x00000C1A, /* CMD26 */ - 0x0000001B, /* CMD27 */ - 0x0000001C, /* CMD28 */ - 0x0000001D, /* CMD29 */ - 0x0000001E, /* CMD30 */ - 0x00001C1F, /* CMD31 */ - 0x00000000, 0x00000000, 0x00000000, 0x00000423, /* CMD35 */ - 0x00000424, /* CMD36 */ - 0x00000000, 0x00000026, /* CMD38 */ - 0x00000427, /* CMD39 */ - 0x00000428, /* CMD40(send cmd) */ - 0x00000000, 0x0000002A, /* CMD42 */ - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000C31, 0x00000000, 0x00000000, 0x00000000, - 0x00007C35, 0x00006C36, 0x00000037, /* CMD55 */ - 0x00000038, /* CMD56(Read) */ - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}; - -uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom) -{ - uint32_t value; - - uint32_t index_top = (uint32_t)(15 - (top >> 3)); - uint32_t index_bottom = (uint32_t)(15 - (bottom >> 3)); - - if (index_top == index_bottom) { - value = data[index_top]; - } else if ((index_top + 1) == index_bottom) { - value = (uint32_t)((data[index_top] << 8) | data[index_bottom]); - } else if ((index_top + 2) == index_bottom) { - value = (uint32_t)((data[index_top] << 16) | - (data[index_top + 1] << 8) | - data[index_top + 2]); - } else { - value = (uint32_t)((data[index_top] << 24) | - (data[index_top + 1] << 16) | - (data[index_top + 2] << 8) | - data[index_top + 3]); - } - - value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1)); - - return value; -} - -void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code) -{ - mmc_drv_obj.error_info.num = func_no; - mmc_drv_obj.error_info.code = (uint16_t)error_code; - - ERROR("BL2: emmc err:func_no=0x%x code=0x%x\n", func_no, error_code); -} - -void emmc_write_error_info_func_no(uint16_t func_no) -{ - mmc_drv_obj.error_info.num = func_no; - - ERROR("BL2: emmc err:func_no=0x%x\n", func_no); -} - -void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) -{ - /* command information */ - mmc_drv_obj.cmd_info.cmd = cmd; - mmc_drv_obj.cmd_info.arg = arg; - mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; - mmc_drv_obj.cmd_info.hw = - cmd_reg_hw[cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; - - /* clear data transfer information */ - mmc_drv_obj.trans_size = 0; - mmc_drv_obj.remain_size = 0; - mmc_drv_obj.buff_address_virtual = NULL; - mmc_drv_obj.buff_address_physical = NULL; - - /* response information */ - mmc_drv_obj.response_length = 6; - - switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) { - case HAL_MEMCARD_RESPONSE_NONE: - mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; - mmc_drv_obj.response_length = 0; - break; - case HAL_MEMCARD_RESPONSE_R1: - mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; - break; - case HAL_MEMCARD_RESPONSE_R1b: - mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */ - mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; - break; - case HAL_MEMCARD_RESPONSE_R2: - mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; - mmc_drv_obj.response_length = 17; - break; - case HAL_MEMCARD_RESPONSE_R3: - mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; - break; - case HAL_MEMCARD_RESPONSE_R4: - mmc_drv_obj.response = &mmc_drv_obj.r4_resp; - break; - case HAL_MEMCARD_RESPONSE_R5: - mmc_drv_obj.response = &mmc_drv_obj.r5_resp; - break; - default: - mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; - break; - } -} - -void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, - uint32_t *buff_address_virtual, uint32_t len, - HAL_MEMCARD_OPERATION dir, - HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) -{ - emmc_make_nontrans_cmd(cmd, arg); /* update common information */ - - /* for data transfer command */ - mmc_drv_obj.cmd_info.dir = dir; - mmc_drv_obj.buff_address_virtual = buff_address_virtual; - mmc_drv_obj.buff_address_physical = buff_address_virtual; - mmc_drv_obj.trans_size = len; - mmc_drv_obj.remain_size = len; - mmc_drv_obj.transfer_mode = transfer_mode; -} - -EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) -{ - EMMC_ERROR_CODE result; - uint32_t freq; - - /* initialize state */ - mmc_drv_obj.mount = FALSE; - mmc_drv_obj.selected = FALSE; - mmc_drv_obj.during_transfer = FALSE; - mmc_drv_obj.during_cmd_processing = FALSE; - mmc_drv_obj.during_dma_transfer = FALSE; - mmc_drv_obj.dma_error_flag = FALSE; - mmc_drv_obj.force_terminate = FALSE; - mmc_drv_obj.state_machine_blocking = FALSE; - - mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; - mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ - mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; - - /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ - emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ - result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); - if (result != EMMC_SUCCESS) { - return result; - } - - /* change MMC clock(400KHz) */ - freq = MMC_400KHZ; - result = emmc_set_request_mmc_clock(&freq); - if (result != EMMC_SUCCESS) { - return result; - } - - return EMMC_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/io/io_emmcdrv.c b/plat/renesas/rza/common/drivers/io/io_emmcdrv.c deleted file mode 100644 index dd14c68ff5..0000000000 --- a/plat/renesas/rza/common/drivers/io/io_emmcdrv.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -#include "emmc_config.h" -#include "emmc_def.h" -#include "emmc_hal.h" -#include "emmc_std.h" -#include "io_common.h" -#include "io_emmcdrv.h" -#include "io_private.h" - -static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__((unused)), - io_dev_info_t **dev_info); -static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info); - -typedef struct { - uint32_t in_use; - uintptr_t base; - signed long long file_pos; - EMMC_PARTITION_ID partition; -} file_state_t; - -static file_state_t current_file = { 0 }; - -static io_type_t device_type_emmcdrv(void) -{ - return IO_TYPE_MEMMAP; -} - -static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, - signed long long offset) -{ - if (mode != IO_SEEK_SET) { - return IO_FAIL; - } - - ((file_state_t *)entity->info)->file_pos = offset; - - return IO_SUCCESS; -} - -static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, - size_t length, size_t *length_read) -{ - file_state_t *fp = (file_state_t *)entity->info; - uint32_t first_sector, last_sector, sector_count, emmc_dma = 0; - uint8_t sector_buf[EMMC_SECTOR_SIZE]; - size_t buffer_offset = 0; - int32_t result = IO_SUCCESS; - - first_sector = (fp->base + fp->file_pos) >> EMMC_SECTOR_SIZE_SHIFT; - last_sector = (fp->base + fp->file_pos + length - 1) >> - EMMC_SECTOR_SIZE_SHIFT; - sector_count = last_sector - first_sector + 1; - - NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%llx(%d) len=0x%lx(%d)\n", - buffer, fp->partition, (fp->base + fp->file_pos), first_sector, - length, sector_count); - - // Temporarily disable DMA. - // if ((buffer + length - 1U) <= (uintptr_t)UINT32_MAX) { - // emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE; - // } - - // first sector - uint32_t first_offset = (fp->base + fp->file_pos) % EMMC_SECTOR_SIZE; - if (0 < first_offset) { - memset(sector_buf, 0x00, EMMC_SECTOR_SIZE); - if (emmc_read_sector((uint32_t *)sector_buf, first_sector, 1, - emmc_dma) != EMMC_SUCCESS) { - result = IO_FAIL; - goto block_read_done; - } else { - buffer_offset = EMMC_SECTOR_SIZE - first_offset; - buffer_offset = (length < buffer_offset) ? - length : - buffer_offset; - - memcpy((uint8_t *)buffer, §or_buf[first_offset], - buffer_offset); - - first_sector++; - sector_count--; - } - } - - // last sector - uint32_t last_offset = - (fp->base + fp->file_pos + length) % EMMC_SECTOR_SIZE; - if (0 < sector_count && 0 < last_offset) { - memset(sector_buf, 0x00, EMMC_SECTOR_SIZE); - if (emmc_read_sector((uint32_t *)sector_buf, last_sector, 1, - emmc_dma) != EMMC_SUCCESS) { - result = IO_FAIL; - goto block_read_done; - } else { - memcpy((uint8_t *)buffer + (length - last_offset), - §or_buf[0], last_offset); - sector_count--; - } - } - - // middle sector - if (0 < sector_count) { - if (emmc_read_sector((uint32_t *)(buffer + buffer_offset), - first_sector, sector_count, - emmc_dma) != EMMC_SUCCESS) { - result = IO_FAIL; - goto block_read_done; - } - } - - *length_read = length; - fp->file_pos += (signed long long)length; -block_read_done: - return result; -} - -static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, - io_entity_t *entity) -{ - const io_drv_spec_t *block_spec = (io_drv_spec_t *)spec; - - if (current_file.in_use != 0U) { - WARN("mmc_block: Only one open spec at a time\n"); - return IO_RESOURCES_EXHAUSTED; - } - - current_file.base = block_spec->offset; - current_file.file_pos = 0; - current_file.in_use = 1; - - current_file.partition = mmc_drv_obj.boot_partition_en; - NOTICE("BL2: eMMC boot from partition %d\n", current_file.partition); - - if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS) { - return IO_FAIL; - } - - entity->info = (uintptr_t)¤t_file; - - return IO_SUCCESS; -} - -static int32_t emmcdrv_block_close(io_entity_t *entity) -{ - memset((void *)¤t_file, 0, sizeof(current_file)); - entity->info = 0U; - - return IO_SUCCESS; -} - -static const io_dev_funcs_t emmcdrv_dev_funcs = { .type = &device_type_emmcdrv, - .open = &emmcdrv_block_open, - .seek = &emmcdrv_block_seek, - .size = NULL, - .read = &emmcdrv_block_read, - .write = NULL, - .close = &emmcdrv_block_close, - .dev_init = NULL, - .dev_close = - &emmcdrv_dev_close }; - -static const io_dev_info_t emmcdrv_dev_info = { .funcs = &emmcdrv_dev_funcs, - .info = (uintptr_t)0 }; - -static const io_dev_connector_t emmcdrv_dev_connector = { - &emmcdrv_dev_open, -}; - -static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__((unused)), - io_dev_info_t **dev_info) -{ - *dev_info = (io_dev_info_t *)&emmcdrv_dev_info; - - return IO_SUCCESS; -} - -static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info) -{ - return IO_SUCCESS; -} - -int32_t register_io_dev_emmcdrv(const io_dev_connector_t **dev_con) -{ - int32_t rc; - - rc = io_register_device(&emmcdrv_dev_info); - if (rc == IO_SUCCESS) { - *dev_con = &emmcdrv_dev_connector; - } - - return rc; -} diff --git a/plat/renesas/rza/common/drivers/io/io_emmcdrv.h b/plat/renesas/rza/common/drivers/io/io_emmcdrv.h deleted file mode 100644 index 71c6f515ed..0000000000 --- a/plat/renesas/rza/common/drivers/io/io_emmcdrv.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef IO_EMMCDRV_H -#define IO_EMMCDRV_H - -struct io_dev_connector; -int32_t register_io_dev_emmcdrv(const io_dev_connector_t **connector); - -#endif /* IO_EMMCDRV_H */ diff --git a/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c b/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c deleted file mode 100644 index 64b161bc5a..0000000000 --- a/plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include - -#include -#include -#include - -static int rz_mmu_check_tbl(const rza_mmu_pgtbl_cfg_t *config_table); -static void rz_mmu_write_tbl(const rza_mmu_pgtbl_cfg_t *config_table); -static void rz_mmu_write_ttbr0_el3(const uint64_t addr); -static void rz_mmu_write_mair_el3(const uint64_t mair); -static void rz_mmu_write_tcr_el3(const uint64_t tcr); -static uint32_t rz_mmu_get_current_el(void); - -/* MMU allocation area */ -uint64_t __attribute__((section("base_xlat_table"))) - mmu_level1_table[RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; -uint64_t __attribute__((section("xlat_table"), aligned(0x1000))) -mmu_level2_table[RZA_MMU_TABLE_ENTRY * RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; -uint64_t level2_table[RZA_MMU_LEVEL2_TABLE_INDEX_MAX]; - -int plat_mmu_init(const rza_mmu_pgtbl_cfg_t *config_table) -{ - int ret; - int index; - uint64_t mair; - uint64_t tcr; - int t0sz; - uintptr_t virtual_addr_space_size; - - ret = rz_mmu_check_tbl(config_table); - - if (0 == ret) { - /* get the start address for each Level2 MMU table entry */ - for (index = 0; index < RZA_MMU_LEVEL2_TABLE_INDEX_MAX; index++) { - level2_table[index] = - (uint64_t)&mmu_level2_table[RZA_MMU_TABLE_ENTRY * index]; - } - - /* Set the address of the level 2 MMU table in the level 1 MMU table */ - for (index = 0; index < RZA_MMU_LEVEL2_TABLE_INDEX_MAX; index++) { - *((uint64_t *)&mmu_level1_table[index]) = - (level2_table[index] | RZA_MMU_ATTR_NEXT_TBL); - } - - rz_mmu_write_tbl(config_table); - - /* create a pattern of attributes to set in the MAIR register */ - mair = RZA_MMU_MAIR_ATTR_SET(RZA_MMU_ATTR_DEVICE, - RZA_MMU_ATTR_DEVICE_INDEX); - mair |= RZA_MMU_MAIR_ATTR_SET( - RZA_MMU_ATTR_IWBWA_OWBWA_NTR, - RZA_MMU_ATTR_IWBWA_OWBWA_NTR_INDEX); - mair |= RZA_MMU_MAIR_ATTR_SET(RZA_MMU_ATTR_NON_CACHEABLE, - RZA_MMU_ATTR_NON_CACHEABLE_INDEX); - - /* create TTB operation settings to set in TCR register */ - tcr = TCR_EL3_RES1; - - virtual_addr_space_size = (uintptr_t)RZA_MMU_VIRT_SIZE_MAX; - - t0sz = 64 - __builtin_ctzll(virtual_addr_space_size); - - tcr |= (uint64_t)t0sz << TCR_T0SZ_SHIFT; - - /* TTB cache enable */ - tcr |= (TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA); - - /* address range check */ - if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_40_TO_41) != 0U) { - tcr |= TCR_PS_BITS_4TB << TCR_EL3_PS_SHIFT; /* 42bit */ - } else if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_36_TO_39) != 0U) { - tcr |= TCR_PS_BITS_1TB << TCR_EL3_PS_SHIFT; /* 40bit */ - } - /* 36 bits address */ - else if ((RZA_MMU_PHY_ADDR_MAX & ADDR_MASK_32_TO_35) != 0U) { - tcr |= TCR_PS_BITS_64GB << TCR_EL3_PS_SHIFT; /* 36 bit */ - } - /* 32bits address */ - else { - tcr |= TCR_PS_BITS_4GB << TCR_EL3_PS_SHIFT; /* 32 bit */ - } - - __asm__ volatile("tlbi alle3\n"); - - rz_mmu_write_mair_el3(mair); - - rz_mmu_write_tcr_el3(tcr); - - rz_mmu_write_ttbr0_el3(((uint64_t)mmu_level1_table | TTBR_CNP_BIT)); - } - - return ret; -} - -void plat_mmu_enable(void) -{ - /* set MMU and data cache enable, Disable the function to forcibly - * set the execute-never attribute when setting the writable memory - */ - __asm__ volatile(".equ SCTLR_C, (1 << 2)\n" - ".equ SCTLR_M, (1 << 0)\n" - ".equ SCTLR_WXN, (1 << 19)\n" - - "dsb ish\n" - "isb\n" - "mrs x0, SCTLR_EL3\n" - "mov x1, #(SCTLR_C | SCTLR_M)\n" - "orr x0, x0, x1\n" - "bic x0, x0, SCTLR_WXN\n" - "msr SCTLR_EL3, x0\n" - "isb\n" - : - : - : "x0", "x1"); -} - -int rz_mmu_check_tbl(const rza_mmu_pgtbl_cfg_t *config_table) -{ - int ret = 0; - int index; - uint32_t current_el; - - current_el = rz_mmu_get_current_el(); - if (RZA_MMU_CURRENT_EL3 == current_el) { - for (index = 0; ((0 == ret) && (RZA_MMU_ATTRIBUTE_CONFIG_END != - config_table[index].attribute)); - index++) { - if ((config_table[index].vaddress % RZA_MMU_L2_ENTRY_SIZE) != 0) { - ret = -1; - } - - if ((config_table[index].paddress % RZA_MMU_L2_ENTRY_SIZE) != 0) { - ret = -1; - } - - if ((config_table[index].size % RZA_MMU_L2_ENTRY_SIZE) != 0) { - ret = -1; - } - - if (RZA_MMU_PHY_SIZE_MAX < - (uint64_t)(config_table[index].paddress + config_table[index].size)) { - ret = -1; - } - - if (RZA_MMU_VIRT_SIZE_MAX < - (uint64_t)(config_table[index].vaddress + config_table[index].size)) { - ret = -1; - } - } - } else { - ret = -1; - } - - return ret; -} - -void rz_mmu_write_tbl(const rza_mmu_pgtbl_cfg_t *config_table) -{ - int desc; - int num_of_desc; - int ttb_index; - int ttb_num; - int index; - uint64_t *desc_ptr; - uint64_t paddress; - uint64_t ttb_base_ptr; - uint64_t ttb_start_vaddr; - uint64_t attribute; - - for (index = 0; RZA_MMU_ATTRIBUTE_CONFIG_END != config_table[index].attribute; index++) { - /* get target TTB block number - * RZA_MMU_TTB_BLOCK_WIDTH is TTB block width(0x40000000) - */ - ttb_num = config_table[index].vaddress / RZA_MMU_TTB_BLOCK_WIDTH; - /* get target TTB block pointer */ - ttb_base_ptr = (uint64_t)&mmu_level2_table[RZA_MMU_TABLE_ENTRY * ttb_num]; - /* get first virtual address on target TTB block */ - ttb_start_vaddr = RZA_MMU_TTB_BLOCK_WIDTH * ttb_num; - - /* get number of descriptor for setting attribute - * RZA_MMU_L2_ENTRY_SIZE is virtual address entry size per descriptor - */ - num_of_desc = config_table[index].size / RZA_MMU_L2_ENTRY_SIZE; - /* get index of descriptor for setting attribute */ - ttb_index = (config_table[index].vaddress - ttb_start_vaddr) / - RZA_MMU_L2_ENTRY_SIZE; - /* get pointer of descriptor */ - desc_ptr = (uint64_t *)(ttb_base_ptr + (ttb_index * RZA_MMU_TABLE_DESC_SIZE)); - - /* set attribute to descriptor */ - if (RZA_MMU_ATTRIBUTE_ACCESS_FAULT != config_table[index].attribute) { - attribute = (config_table[index].attribute | RZA_MMU_DESC_BLOCK_ENTRY_L12); - paddress = config_table[index].paddress; - for (desc = 0; desc < num_of_desc; desc++) { - *desc_ptr++ = paddress | attribute; - paddress += RZA_MMU_L2_ENTRY_SIZE; - } - } else { - for (desc = 0; desc < num_of_desc; desc++) { - *desc_ptr++ = 0; - } - } - } -} - -void rz_mmu_write_ttbr0_el3(const uint64_t addr) -{ - __asm__ volatile("msr TTBR0_EL3, %0\n" : : "r"(addr) :); -} - -void rz_mmu_write_mair_el3(const uint64_t mair) -{ - __asm__ volatile("msr MAIR_EL3, %0\n" : : "r"(mair) :); -} - -void rz_mmu_write_tcr_el3(const uint64_t tcr) -{ - __asm__ volatile("msr TCR_EL3, %0\n" : : "r"(tcr) :); -} - -uint32_t rz_mmu_get_current_el(void) -{ - uint32_t current_el; - - __asm__ volatile("mrs %0, CurrentEL\n" : "=r"(current_el) : :); - - return current_el; -} diff --git a/plat/renesas/rza/common/drivers/spi_multi/AT25QL128A/spi_multi_device.c b/plat/renesas/rza/common/drivers/spi_multi/AT25QL128A/spi_multi_device.c deleted file mode 100644 index 8709867a1a..0000000000 --- a/plat/renesas/rza/common/drivers/spi_multi/AT25QL128A/spi_multi_device.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include - -#include -#include -#include -#include -#include -#include -#include - -void spi_multi_setup_device(void) -{ - uint32_t val; - uint8_t read_status; - - mmio_write_32(SPIM_PHYOFFSET1, SPIM_PHYOFFSET1_SET_VALUE); - mmio_write_32(SPIM_PHYOFFSET2, SPIM_PHYOFFSET2_SET_VALUE); - spi_multi_timing_set(); - - /* Set Data read option */ - /* Required when command 0xEB is specified. - * Not required when a command other than is specified, - * but there is no problem in operation. - */ - val = SPIM_DROPR_SET_VALUE; - mmio_write_32(SPIM_DROPR, val); - - read_status = spi_multi_cmd_read(SMCMR_CMD_READ_STATUS_REGISTER_2); - if ((read_status & STATUS_2_QE) == STATUS_2_QE) { - return; - } - /* Write Enable Command */ - spi_multi_cmd_write(SMCMR_CMD_WRITE_ENABLE, SPI_MANUAL_COMMAND_SIZE_0, - 0); - /* Write Status Register-2 Command Quad Enable */ - val = ((STATUS_2_QE | read_status) << SMWDR0_1BYTE_DATA_BIT_SHIFT); - spi_multi_cmd_write(SMCMR_CMD_WRITE_STATUS_REGISTER_2, - SPI_MANUAL_COMMAND_SIZE_8_BIT, val); - /* status 1 BUSY check */ - while (1) { - read_status = - spi_multi_cmd_read(SMCMR_CMD_READ_STATUS_REGISTER_1); - if ((read_status & STATUS_1_BUSY_BIT) == STATUS_1_BUSY) { - udelay(STATUS_BUSY_READ_DELAY_TIME); - continue; - } else { - break; - } - } -} diff --git a/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c b/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c deleted file mode 100644 index 5ff4ce4679..0000000000 --- a/plat/renesas/rza/common/drivers/spi_multi/MT25QU512ABB/spi_multi_device.c +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -void spi_multi_setup_device(void) -{ - /* Do nothing */ -} diff --git a/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c b/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c deleted file mode 100644 index 80a26a375f..0000000000 --- a/plat/renesas/rza/common/drivers/spi_multi/spi_multi.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include -#include -#include - -void spi_multi_timing_set(void) -{ - /* Timing adjustment register setting */ - mmio_write_32(SPIM_PHYADJ2, 0xA5390000); - mmio_write_32(SPIM_PHYADJ1, 0x80000000); - mmio_write_32(SPIM_PHYADJ2, 0x00008080); - mmio_write_32(SPIM_PHYADJ1, 0x80000022); - mmio_write_32(SPIM_PHYADJ2, 0x00008080); - mmio_write_32(SPIM_PHYADJ1, 0x80000024); - - /* SDR mode serial flash settings */ - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); - - /* Timing adjustment register setting */ - mmio_write_32(SPIM_PHYADJ2, 0x00000030); - mmio_write_32(SPIM_PHYADJ1, 0x80000032); - - dmbsy(); -} - -uint8_t spi_multi_cmd_read(uint8_t command) -{ - uint32_t val; - uint8_t r_status; - - /* SDR mode serial flash settings */ - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); - - /* Set the QSPIn_SSL setting value & Manual Mode */ - mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_MANUAL_SET_VALUE); - - val = command << SMCMR_CMD_BIT_SHIFT; - mmio_write_32(SPIM_SMCMR, val); - - /* Set the Transfer Data size setting value & command output enable */ - val = SMENR_CDE | SPI_MANUAL_COMMAND_SIZE_16_BIT; - mmio_write_32(SPIM_SMENR, val); - - /* Set the SDR transfer & SPI flash mode setting value */ - mmio_write_32(SPIM_SMDRENR, SPIM_SMDRENR_SET_VALUE); - - val = SMCR_SPIE | SMCR_SPIRE; - mmio_write_32(SPIM_SMCR, val); - - /* Wait until the transfer is complete */ - do { - val = mmio_read_32(SPIM_CMNSR); - } while ((val & CMNSR_TEND) == 0); - - val = mmio_read_32(SPIM_SMRDR0); - - r_status = (uint8_t)val; - return r_status; -} - -void spi_multi_cmd_write(uint8_t command, uint8_t size, uint32_t data) -{ - uint32_t val; - - /* SDR mode serial flash settings */ - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE); - - /* Set the QSPIn_SSL setting value & Manual Mode */ - mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_MANUAL_SET_VALUE); - - /* Set the Manual Mode Command */ - val = command << SMCMR_CMD_BIT_SHIFT; - mmio_write_32(SPIM_SMCMR, val); - - /* Set the Transfer Data size setting value & command output enable */ - val = SMENR_CDE | size; - mmio_write_32(SPIM_SMENR, val); - - /* Set the write data in Manual mode */ - mmio_write_32(SPIM_SMWDR0, data); - - /* Set the SDR transfer & SPI flash mode setting value */ - mmio_write_32(SPIM_SMDRENR, SPIM_SMDRENR_SET_VALUE); - - /* Set the data transfer enable & data write enable */ - if (size == SPI_MANUAL_COMMAND_SIZE_0) { - val = SMCR_SPIE; - } else { - val = SMCR_SPIE | SMCR_SPIWE; - } - mmio_write_32(SPIM_SMCR, val); - - /* Wait until the transfer is complete */ - do { - val = mmio_read_32(SPIM_CMNSR); - } while ((val & CMNSR_TEND) == 0); -} - -int spi_multi_setup(void) -{ - uint32_t val; - - /* Wait until the transfer is complete */ - do { - val = mmio_read_32(SPIM_CMNSR); - } while ((val & CMNSR_TEND) == 0); - - /* Device-specific settings */ - spi_multi_setup_device(); - /* SDR mode serial flash settings */ - mmio_write_32(SPIM_PHYCNT, SPIM_PHYCNT_SET_VALUE); - - /* Read timing setting */ - mmio_write_32(SPIM_PHYOFFSET1, SPIM_PHYOFFSET1_SET_VALUE); - mmio_write_32(SPIM_PHYOFFSET2, SPIM_PHYOFFSET2_SET_VALUE); - - /* Set the QSPIn_SSL setting value */ - mmio_write_32(SPIM_CMNCR, SPIM_CMNCR_EXTREAD_SET_VALUE); - /* Set SSL delay setting value */ - mmio_write_32(SPIM_SSLDR, SPIM_SSLDR_SET_VALUE); - - /* Clear the RBE bit */ - mmio_write_32(SPIM_DRCR, SPIM_DRCR_SET_VALUE); - mmio_read_32(SPIM_DRCR); - - /* Set the data read command */ - mmio_write_32(SPIM_DRCMR, SPIM_DRCMR_SET_VALUE); - - /* Extended external address setting */ - mmio_write_32(SPIM_DREAR, SPIM_DREAR_SET_VALUE); - - /* Set the bit width of command and address output to 1 bit and */ - /* the address size to 4 byte */ - mmio_write_32(SPIM_DRENR, SPIM_DRENR_SET_VALUE); - - /* Dummy cycle setting */ - mmio_write_32(SPIM_DRDMCR, SPIM_DRDMCR_SET_VALUE); - - /* Change to SPI flash mode */ - mmio_write_32(SPIM_DRDRENR, SPIM_DRDRENR_SET_VALUE); - - /* Timing adjustment register setting */ - spi_multi_timing_set(); - - return SPI_MULTI_SUCCESS; -} diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk deleted file mode 100644 index a1d8fe3832..0000000000 --- a/plat/renesas/rza/common/drivers/xspidevice/octaflash_mx66uw/rz_xspidevice.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -_XSPI_DEVICE := octaflash_mx66uw -PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) -RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h -RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ - plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk deleted file mode 100644 index 01345e2036..0000000000 --- a/plat/renesas/rza/common/drivers/xspidevice/octaram_apsxx/rz_xspidevice.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -_XSPI_DEVICE := octaram_apsxx -PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) -RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h -RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ - plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk deleted file mode 100644 index 7352fd8c08..0000000000 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_at25/rz_xspidevice.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -_XSPI_DEVICE := qspiflash_at25 -PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) -RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h -RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ - plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk b/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk deleted file mode 100644 index f4092bcc3a..0000000000 --- a/plat/renesas/rza/common/drivers/xspidevice/qspiflash_mx25l25645g/rz_xspidevice.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2024-2025, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -_XSPI_DEVICE := qspiflash_mx25l25645g -PLAT_INCLUDES += -Iplat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE) -RZ_XSPI_HEADERS := $(RZ_XSPI_HEADERS) $(_XSPI_DEVICE)_api.h -RZ_XSPI_SOURCES := $(RZ_XSPI_SOURCES) \ - plat/renesas/rza/common/drivers/xspidevice/$(_XSPI_DEVICE)/$(_XSPI_DEVICE).c diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h b/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h deleted file mode 100644 index 9d44841b98..0000000000 --- a/plat/renesas/rza/common/include/drivers/spi_multi/AT25QL128A/spi_multi_reg_values.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* Dialog AT25QL128A */ -#ifndef _SPI_MULTI_REG_VALUES_H_ -#define _SPI_MULTI_REG_VALUES_H_ -/* - * Selectable definitions - */ -/* In the case of addr width 24bit */ -#define SET_DRENR_ADE_VALUE DRENR_ADE_ADD23_OUT -#define SET_DREAR_EAC_VALUE DREAR_EAC_EXADDR24 - -/* In the case of bit width 1-4-4 and addr width 24bi */ -#define SET_DRCMR_CMD_VALUE DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B -#define SET_DRENR_ADB_VALUE DRENR_ADB_4BIT -#define SET_DRENR_DRDB_VALUE DRENR_DRDB_4BIT -#define SET_DRDMCR_VALUE SPI_MULTI_DUMMY_4CYCLE -#define SET_DRENR_SET_VALUE \ - (DRENR_CDB_1BIT | DRENR_OCDB_1BIT | SET_DRENR_ADB_VALUE | \ - DRENR_OPDB_1BIT | SET_DRENR_DRDB_VALUE | DRENR_CDE | DRENR_DME | \ - SET_DRENR_ADE_VALUE | DRENR_OPDB_4BIT | DRENR_OPDE_OPD3_OUT) - -/* SDR mode serial flash settings */ -#define SPIM_PHYCNT_SET_VALUE \ - (PHYCNT_DEF_DATA | PHYCNT_PHYMEM_SDR_MODE | PHYCNT_WBUF_NOT_USED | \ - PHYCNT_WBUF2_NOT_USED | PHYCNT_CKSEL_SLOW | PHYCNT_HS_OTHER_MODE | \ - PHYCNT_OCT_OTHER_MODE | PHYCNT_EXDS_NOT_USED | \ - PHYCNT_OCTA_HYPER_FLASH | PHYCNT_ALT_ALIGN_NOT_SUPPORTED | \ - PHYCNT_CAL_NOT_PERFOMED) -#define SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE \ - (SPIM_PHYCNT_SET_VALUE | PHYCNT_CKSEL_FAST) -/* Read timing setting */ -#define SPIM_PHYOFFSET1_SET_VALUE \ - (PHYOFFSET1_DEF_DATA | PHYOFFSET1_DDRTMG_SPIDRE_0) -#define SPIM_PHYOFFSET2_SET_VALUE \ - (PHYOFFSET2_DEF_DATA | PHYOFFSET2_OCTTMG_HYPER_FLASH) - -/* Set the QSPIn_SSL setting value */ -#define SPIM_CMNCR_EXTREAD_SET_VALUE \ - (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ - CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ - CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_EXT_READ) - -#define SPIM_CMNCR_MANUAL_SET_VALUE \ - (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ - CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ - CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_MANUAL) - -/* Set SSL delay setting value */ -#define SPIM_SSLDR_SET_VALUE \ - (SSLDR_SCKDL_4_5 | SSLDR_SLNDL_4QSPIn | SSLDR_SPNDL_4QSPIn) - -/* Set the RBE bit and RCF bit and RBURST */ -#define SPIM_DRCR_SET_VALUE (DRCR_RBE | DRCR_RCF | DRCR_RBURST_32_DATALEN) - -/* Set the data read command */ -#define SPIM_DRCMR_SET_VALUE (SET_DRCMR_CMD_VALUE) - -/* Extended external address setting */ -#define SPIM_DREAR_SET_VALUE (SET_DREAR_EAC_VALUE) - -/* Set the bit width of command and address output to 1 bit and */ -/* the address size to 4 byte */ -#define SPIM_DRENR_SET_VALUE (SET_DRENR_SET_VALUE) -/* Dummy cycle setting */ -#define SPIM_DRDMCR_SET_VALUE (SET_DRDMCR_VALUE) - -/* Change to SPI flash mode */ -#define SPIM_DRDRENR_SET_VALUE \ - (DRDRENR_DRDRE_SDR | DRDRENR_OPDRE_SDR | DRDRENR_ADDRE_SDR | \ - DRDRENR_HYPE_SPI) -/* Set the SDR transfer & SPI flash mode */ -#define SPIM_SMDRENR_SET_VALUE (SMDRENR_HYPE_SPI_FLASH) - -/* Set the option data */ -#define SPIM_DROPR_SET_VALUE (0) - -/* Manual Command */ -#define SMCMR_CMD_WRITE_ENABLE (0x06) -#define SMCMR_CMD_WRITE_STATUS_REGISTER_2 (0x31) -#define SMCMR_CMD_READ_STATUS_REGISTER_1 (0x05) -#define SMCMR_CMD_READ_STATUS_REGISTER_2 (0x35) -#define SMCMR_CMD_BIT_SHIFT (16) -#define SMWDR0_1BYTE_DATA_BIT_SHIFT (24) - -/* Manual Command Configure Length */ -#define SPI_MANUAL_COMMAND_SIZE_0 SMENR_SPIDE_NO_SEND -#define SPI_MANUAL_COMMAND_SIZE_8_BIT SMENR_SPIDE_8BIT_SEND -#define SPI_MANUAL_COMMAND_SIZE_16_BIT SMENR_SPIDE_16BIT_SEND -#define SPI_MANUAL_COMMAND_SIZE_32_BIT SMENR_SPIDE_32BIT_SEND -/* Read Status Register-1(05h) */ -#define STATUS_1_BUSY_BIT (1 << 0) -#define STATUS_1_WEL_BIT (1 << 1) -#define STATUS_1_BUSY (1 << 0) -#define STATUS_1_WEL (1 << 1) -/* Read Status Register-1(BUSY flag) read delay time(micro sec) */ -#define STATUS_BUSY_READ_DELAY_TIME (100) -/* Read Status Register-2(35h) */ -/* Write Status Register-2(31h) */ -#define STATUS_2_QE (1 << 1) - -#endif /* _SPI_MULTI_REG_VALUES_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h b/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h deleted file mode 100644 index 3449a76be0..0000000000 --- a/plat/renesas/rza/common/include/drivers/spi_multi/MT25QU512ABB/spi_multi_reg_values.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* MICRON MT25QU512ABB */ -#ifndef _SPI_MULTI_REG_VALUES_H_ -#define _SPI_MULTI_REG_VALUES_H_ -/* - * Selectable definitions - */ - -/* In the case of addr width 24bit */ -#define SET_DRENR_ADE_VALUE DRENR_ADE_ADD23_OUT -#define SET_DREAR_EAC_VALUE DREAR_EAC_EXADDR24 - -/* In the case of bit width 1-4-4 and addr width 24bit */ -#define SET_DRCMR_CMD_VALUE DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B -#define SET_DRENR_ADB_VALUE DRENR_ADB_4BIT -#define SET_DRENR_DRDB_VALUE DRENR_DRDB_4BIT - -/* dummy cycle SPI_MULTI_DUMMY_1CYCLE - SPI_MULTI_DUMMY_20CYCLE */ -#define SET_DRDMCR_VALUE SPI_MULTI_DUMMY_10CYCLE - -/* SDR mode serial flash settings */ -#define SPIM_PHYCNT_SET_VALUE \ - (PHYCNT_DEF_DATA | PHYCNT_PHYMEM_SDR_MODE | PHYCNT_WBUF_NOT_USED | \ - PHYCNT_WBUF2_NOT_USED | PHYCNT_CKSEL_SLOW | PHYCNT_HS_OTHER_MODE | \ - PHYCNT_OCT_OTHER_MODE | PHYCNT_EXDS_NOT_USED | \ - PHYCNT_OCTA_HYPER_FLASH | PHYCNT_ALT_ALIGN_NOT_SUPPORTED | \ - PHYCNT_CAL_NOT_PERFOMED) -#define SPIM_PHYCNT_SDR_TIM_ADJ_SET_VALUE \ - (SPIM_PHYCNT_SET_VALUE | PHYCNT_CKSEL_FAST) - -/* Read timing setting */ -#define SPIM_PHYOFFSET1_SET_VALUE \ - (PHYOFFSET1_DEF_DATA | PHYOFFSET1_DDRTMG_SPIDRE_0) -#define SPIM_PHYOFFSET2_SET_VALUE \ - (PHYOFFSET2_DEF_DATA | PHYOFFSET2_OCTTMG_HYPER_FLASH) - -/* Set the QSPIn_SSL setting value */ -#define SPIM_CMNCR_EXTREAD_SET_VALUE \ - (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ - CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ - CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_EXT_READ) - -#define SPIM_CMNCR_MANUAL_SET_VALUE \ - (CMNCR_IO0FV_OUT_PREV | CMNCR_IO2FV_OUT_PREV | CMNCR_IO3FV_OUT_PREV | \ - CMNCR_MOIIO0_OUT1 | CMNCR_MOIIO1_OUT1 | CMNCR_MOIIO2_OUT1 | \ - CMNCR_MOIIO3_OUT1 | CMNCR_DEF_DATA | CMNCR_MD_MANUAL) -/* Set SSL delay setting value */ -#define SPIM_SSLDR_SET_VALUE \ - (SSLDR_SCKDL_4_5 | SSLDR_SLNDL_4QSPIn | SSLDR_SPNDL_4QSPIn) - -/* Set the RBE bit and RCF bit and RBURST */ -#define SPIM_DRCR_SET_VALUE (DRCR_RBE | DRCR_RCF | DRCR_RBURST_32_DATALEN) - -/* Set the data read command */ -#define SPIM_DRCMR_SET_VALUE (SET_DRCMR_CMD_VALUE) - -/* Extended external address setting */ -#define SPIM_DREAR_SET_VALUE (SET_DREAR_EAC_VALUE) - -/* Set the bit width of command and address output to 1 bit and */ -/* the address size to 4 byte */ -#define SPIM_DRENR_SET_VALUE \ - (DRENR_CDB_1BIT | DRENR_OCDB_1BIT | SET_DRENR_ADB_VALUE | \ - DRENR_OPDB_1BIT | SET_DRENR_DRDB_VALUE | DRENR_CDE | DRENR_DME | \ - SET_DRENR_ADE_VALUE | DRENR_OPDE_NO_OUT) -/* Dummy cycle setting */ -#define SPIM_DRDMCR_SET_VALUE (SET_DRDMCR_VALUE) - -/* Change to SPI flash mode */ -#define SPIM_DRDRENR_SET_VALUE \ - (DRDRENR_DRDRE_SDR | DRDRENR_OPDRE_SDR | DRDRENR_ADDRE_SDR | \ - DRDRENR_HYPE_SPI) -/* Set the SDR transfer & SPI flash mode */ -#define SPIM_SMDRENR_SET_VALUE (SMDRENR_HYPE_SPI_FLASH) -/* Manual Command */ -#define SMCMR_CMD_READ_STATUS_REGISTER (0x05) -#define SMCMR_CMD_BIT_SHIFT (16) -#define SMWDR0_1BYTE_DATA_BIT_SHIFT (24) - -/* Manual Command Configure Length */ -#define SPI_MANUAL_COMMAND_SIZE_0 SMENR_SPIDE_NO_SEND -#define SPI_MANUAL_COMMAND_SIZE_8_BIT SMENR_SPIDE_8BIT_SEND -#define SPI_MANUAL_COMMAND_SIZE_16_BIT SMENR_SPIDE_16BIT_SEND -#define SPI_MANUAL_COMMAND_SIZE_32_BIT SMENR_SPIDE_32BIT_SEND - -#endif /* _SPI_MULTI_REG_VALUES_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h deleted file mode 100644 index 03f5101459..0000000000 --- a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SPI_MULTI_H_ -#define _SPI_MULTI_H_ - -#define SPI_MULTI_ADDR_WIDES_24 (0) -#define SPI_MULTI_ADDR_WIDES_32 (1) - -#define SPI_MULTI_DQ_WIDES_1_1_1 (0) -#define SPI_MULTI_DQ_WIDES_1_1_4 (1) -#define SPI_MULTI_DQ_WIDES_1_4_4 (2) - -#define SPI_MULTI_DUMMY_2CYCLE (1) -#define SPI_MULTI_DUMMY_3CYCLE (2) -#define SPI_MULTI_DUMMY_4CYCLE (3) -#define SPI_MULTI_DUMMY_5CYCLE (4) -#define SPI_MULTI_DUMMY_6CYCLE (5) -#define SPI_MULTI_DUMMY_7CYCLE (6) -#define SPI_MULTI_DUMMY_8CYCLE (7) -#define SPI_MULTI_DUMMY_9CYCLE (8) -#define SPI_MULTI_DUMMY_10CYCLE (9) -#define SPI_MULTI_DUMMY_11CYCLE (10) -#define SPI_MULTI_DUMMY_12CYCLE (11) -#define SPI_MULTI_DUMMY_13CYCLE (12) -#define SPI_MULTI_DUMMY_14CYCLE (13) -#define SPI_MULTI_DUMMY_15CYCLE (14) -#define SPI_MULTI_DUMMY_16CYCLE (15) -#define SPI_MULTI_DUMMY_17CYCLE (16) -#define SPI_MULTI_DUMMY_18CYCLE (17) -#define SPI_MULTI_DUMMY_19CYCLE (18) -#define SPI_MULTI_DUMMY_20CYCLE (19) - -#define SPI_MULTI_SUCCESS (0) -#define SPI_MULTI_ERROR (-1) - -int spi_multi_setup(void); -void spi_multi_setup_device(void); -void spi_multi_timing_set(void); -uint8_t spi_multi_cmd_read(uint8_t command); -void spi_multi_cmd_write(uint8_t command, uint8_t size, uint32_t data); - -#endif /* _SPI_MULTI_H_ */ diff --git a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h b/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h deleted file mode 100644 index 7e18d3a7a4..0000000000 --- a/plat/renesas/rza/common/include/drivers/spi_multi/spi_multi_regs.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SPI_MULTI_REG_H_ -#define _SPI_MULTI_REG_H_ - -#define SPI_MULTI_BASE (0x10060000) -#define SPI_MULTI_BUF (0x10070000) - -#define SPIM_CMNCR (SPI_MULTI_BASE + 0x00000000) /* Common control register */ -#define SPIM_SSLDR (SPI_MULTI_BASE + 0x00000004) /* SSL delay register */ -#define SPIM_DRCR (SPI_MULTI_BASE + 0x0000000C) /* Data read control register */ -#define SPIM_DRCMR (SPI_MULTI_BASE + 0x00000010) /* Data read command setting register */ -#define SPIM_DREAR (SPI_MULTI_BASE + 0x00000014) /* Data read extended address setting register */ -#define SPIM_DROPR (SPI_MULTI_BASE + 0x00000018) /* Data read option setting register */ -#define SPIM_DRENR (SPI_MULTI_BASE + 0x0000001C) /* Data read enable setting register */ -#define SPIM_SMCR (SPI_MULTI_BASE + 0x00000020) /* Manual mode control register */ -#define SPIM_SMCMR (SPI_MULTI_BASE + 0x00000024) /* Manual mode command setting register */ -#define SPIM_SMADR (SPI_MULTI_BASE + 0x00000028) /* Manual mode address setting register */ -#define SPIM_SMOPR (SPI_MULTI_BASE + 0x0000002C) /* Manual mode option setting register */ -#define SPIM_SMENR (SPI_MULTI_BASE + 0x00000030) /* Manual mode enable setting register */ -#define SPIM_SMRDR0 (SPI_MULTI_BASE + 0x00000038) /* Manual mode read data register 0 */ -#define SPIM_SMRDR1 (SPI_MULTI_BASE + 0x0000003C) /* Manual mode read data register 1 */ -#define SPIM_SMWDR0 (SPI_MULTI_BASE + 0x00000040) /* Manual mode write data register 0 */ -#define SPIM_SMWDR1 (SPI_MULTI_BASE + 0x00000044) /* Manual mode write data register 1 */ -#define SPIM_CMNSR (SPI_MULTI_BASE + 0x00000048) /* Common status register */ -#define SPIM_DRDMCR (SPI_MULTI_BASE + 0x00000058) /* Data read dummy cycle setting register */ -#define SPIM_DRDRENR (SPI_MULTI_BASE + 0x0000005C) /* Data read DDR enable register */ -#define SPIM_SMDMCR (SPI_MULTI_BASE + 0x00000060) /* Manual mode dummy cycle setting register */ -#define SPIM_SMDRENR (SPI_MULTI_BASE + 0x00000064) /* Manual mode DDR enable register */ -#define SPIM_PHYCNT (SPI_MULTI_BASE + 0x0000007C) /* PHY control register */ -#define SPIM_PHYOFFSET1 (SPI_MULTI_BASE + 0x00000080) /* PHY offset register 1 */ -#define SPIM_PHYOFFSET2 (SPI_MULTI_BASE + 0x00000084) /* PHY offset register 2 */ -#define SPIM_PHYINT (SPI_MULTI_BASE + 0x00000088) /* PHY interrupt register */ -#define SPIM_PHYADJ1 (SPI_MULTI_BASE + 0x00000070) /* PHY adjustment register 1 */ -#define SPIM_PHYADJ2 (SPI_MULTI_BASE + 0x00000074) /* PHY adjustment register 2 */ - -#define CMNCR_BSZ_FLASH_NUM_1 (0 << 0) -#define CMNCR_BSZ_FLASH_NUM_2 (1 << 0) -#define CMNCR_IO0FV_OUT0 (0 << 8) -#define CMNCR_IO0FV_OUT1 (1 << 8) -#define CMNCR_IO0FV_OUT_PREV (2 << 8) -#define CMNCR_IO0FV_HIZ (3 << 8) -#define CMNCR_IO2FV_OUT0 (0 << 12) -#define CMNCR_IO2FV_OUT1 (1 << 12) -#define CMNCR_IO2FV_OUT_PREV (2 << 12) -#define CMNCR_IO2FV_HIZ (3 << 12) -#define CMNCR_IO3FV_OUT0 (0 << 14) -#define CMNCR_IO3FV_OUT1 (1 << 14) -#define CMNCR_IO3FV_OUT_PREV (2 << 14) -#define CMNCR_IO3FV_HIZ (3 << 14) -#define CMNCR_DEF_DATA (1 << 24) -#define CMNCR_MOIIO0_OUT0 (0 << 16) -#define CMNCR_MOIIO0_OUT1 (1 << 16) -#define CMNCR_MOIIO0_OUT_PREV (2 << 16) -#define CMNCR_MOIIO0_HIZ (3 << 16) -#define CMNCR_MOIIO1_OUT0 (0 << 18) -#define CMNCR_MOIIO1_OUT1 (1 << 18) -#define CMNCR_MOIIO1_OUT_PREV (2 << 18) -#define CMNCR_MOIIO1_HIZ (3 << 18) -#define CMNCR_MOIIO2_OUT0 (0 << 20) -#define CMNCR_MOIIO2_OUT1 (1 << 20) -#define CMNCR_MOIIO2_OUT_PREV (2 << 20) -#define CMNCR_MOIIO2_HIZ (3 << 20) -#define CMNCR_MOIIO3_OUT0 (0 << 22) -#define CMNCR_MOIIO3_OUT1 (1 << 22) -#define CMNCR_MOIIO3_OUT_PREV (2 << 22) -#define CMNCR_MOIIO3_HIZ (3 << 22) -#define CMNCR_MD_MANUAL (U(1) << 31) -#define CMNCR_MD_EXT_READ (0 << 31) -#define SSLDR_SCKDL_1_5 (0 << 0) -#define SSLDR_SCKDL_2_5 (1 << 0) -#define SSLDR_SCKDL_3_5 (2 << 0) -#define SSLDR_SCKDL_4_5 (3 << 0) -#define SSLDR_SCKDL_5_5 (4 << 0) -#define SSLDR_SCKDL_6_5 (5 << 0) -#define SSLDR_SCKDL_7_5 (6 << 0) -#define SSLDR_SCKDL_8_5 (7 << 0) -#define SSLDR_SLNDL_1QSPIn (0 << 8) -#define SSLDR_SLNDL_2QSPIn (1 << 8) -#define SSLDR_SLNDL_3QSPIn (2 << 8) -#define SSLDR_SLNDL_4QSPIn (3 << 8) -#define SSLDR_SLNDL_5QSPIn (4 << 8) -#define SSLDR_SLNDL_6QSPIn (5 << 8) -#define SSLDR_SLNDL_7QSPIn (6 << 8) -#define SSLDR_SLNDL_8QSPIn (7 << 8) -#define SSLDR_SPNDL_1QSPIn (0 << 16) -#define SSLDR_SPNDL_2QSPIn (1 << 16) -#define SSLDR_SPNDL_3QSPIn (2 << 16) -#define SSLDR_SPNDL_4QSPIn (3 << 16) -#define SSLDR_SPNDL_5QSPIn (4 << 16) -#define SSLDR_SPNDL_6QSPIn (5 << 16) -#define SSLDR_SPNDL_7QSPIn (6 << 16) -#define SSLDR_SPNDL_8QSPIn (7 << 16) -#define DRCR_SSLE (1 << 0) -#define DRCR_RBE (1 << 8) -#define DRCR_RCF (1 << 9) -#define DRCR_RBURST_1_DATALEN (0 << 16) -#define DRCR_RBURST_2_DATALEN (1 << 16) -#define DRCR_RBURST_3_DATALEN (2 << 16) -#define DRCR_RBURST_4_DATALEN (3 << 16) -#define DRCR_RBURST_5_DATALEN (4 << 16) -#define DRCR_RBURST_6_DATALEN (5 << 16) -#define DRCR_RBURST_7_DATALEN (6 << 16) -#define DRCR_RBURST_8_DATALEN (7 << 16) -#define DRCR_RBURST_9_DATALEN (8 << 16) -#define DRCR_RBURST_10_DATALEN (9 << 16) -#define DRCR_RBURST_11_DATALEN (10 << 16) -#define DRCR_RBURST_12_DATALEN (11 << 16) -#define DRCR_RBURST_13_DATALEN (12 << 16) -#define DRCR_RBURST_14_DATALEN (13 << 16) -#define DRCR_RBURST_15_DATALEN (14 << 16) -#define DRCR_RBURST_16_DATALEN (15 << 16) -#define DRCR_RBURST_17_DATALEN (16 << 16) -#define DRCR_RBURST_18_DATALEN (17 << 16) -#define DRCR_RBURST_19_DATALEN (18 << 16) -#define DRCR_RBURST_20_DATALEN (19 << 16) -#define DRCR_RBURST_21_DATALEN (20 << 16) -#define DRCR_RBURST_22_DATALEN (21 << 16) -#define DRCR_RBURST_23_DATALEN (22 << 16) -#define DRCR_RBURST_24_DATALEN (23 << 16) -#define DRCR_RBURST_25_DATALEN (24 << 16) -#define DRCR_RBURST_26_DATALEN (25 << 16) -#define DRCR_RBURST_27_DATALEN (26 << 16) -#define DRCR_RBURST_28_DATALEN (27 << 16) -#define DRCR_RBURST_29_DATALEN (28 << 16) -#define DRCR_RBURST_30_DATALEN (29 << 16) -#define DRCR_RBURST_31_DATALEN (30 << 16) -#define DRCR_RBURST_32_DATALEN (31 << 16) -#define DRCR_SSLN (1 << 24) -#define DREAR_EAC_EXADDR24 (0 << 0) -#define DREAR_EAC_EXADDR25 (1 << 0) -#define DREAR_EAC_EXADDR26 (2 << 0) -#define DREAR_EAC_EXADDR27 (3 << 0) -#define DRENR_OPDE_NO_OUT (0 << 4) -#define DRENR_OPDE_OPD3_OUT (8 << 4) -#define DRENR_OPDE_OPD32_OUT (12 << 4) -#define DRENR_OPDE_OPD321_OUT (14 << 4) -#define DRENR_OPDE_OPD3210_OUT (15 << 4) -#define DRENR_ADE_NO_OUT (0 << 8) -#define DRENR_ADE_ADD23_OUT (7 << 8) -#define DRENR_ADE_ADD31_OUT (15 << 8) -#define DRENR_ADE_OCTA_FLASH (12 << 8) -#define DRENR_ADE_HYPER_FLASH (4 << 8) -#define DRENR_OCDE (1 << 12) -#define DRENR_CDE (1 << 14) -#define DRENR_DME (1 << 15) -#define DRENR_DRDB_1BIT (0 << 16) -#define DRENR_DRDB_4BIT (2 << 16) -#define DRENR_OPDB_1BIT (0 << 20) -#define DRENR_OPDB_4BIT (2 << 20) -#define DRENR_ADB_1BIT (0 << 24) -#define DRENR_ADB_4BIT (2 << 24) -#define DRENR_OCDB_1BIT (0 << 28) -#define DRENR_OCDB_4BIT (2 << 28) -#define DRENR_CDB_1BIT (0 << 30) -#define DRENR_CDB_4BIT (0x80000000) -#define SMCR_SPIE (1 << 0) -#define SMCR_SPIWE (1 << 1) -#define SMCR_SPIRE (1 << 2) -#define SMCR_SSLKP (1 << 8) -#define SMENR_SPIDE_NO_SEND (0 << 0) -#define SMENR_SPIDE_8BIT_SEND (8 << 0) -#define SMENR_SPIDE_16BIT_SEND (12 << 0) -#define SMENR_SPIDE_32BIT_SEND (15 << 0) -#define SMENR_OPDE_NO_OUT (0 << 4) -#define SMENR_OPDE_OPD3_OUT (8 << 4) -#define SMENR_OPDE_OPD32_OUT (12 << 4) -#define SMENR_OPDE_OPD321_OUT (14 << 4) -#define SMENR_OPDE_OPD3210_OUT (15 << 4) -#define SMENR_ADE_NO_OUT (0 << 8) -#define SMENR_ADE_ADR23_16_OUT (4 << 8) -#define SMENR_ADE_ADR23_8_OUT (6 << 8) -#define SMENR_ADE_ADR23_0_OUT (7 << 8) -#define SMENR_ADE_ADR31_0_OUT (15 << 8) -#define SMENR_OCDE (1 << 12) -#define SMENR_CDE (1 << 14) -#define SMENR_DME (1 << 15) -#define SMENR_SPIDB_1BIT (0 << 16) -#define SMENR_SPIDB_4BIT (2 << 16) -#define SMENR_OPDB_1BIT (0 << 20) -#define SMENR_OPDB_4BIT (2 << 20) -#define SMENR_ADB_1BIT (0 << 24) -#define SMENR_ADB_4BIT (2 << 24) -#define SMENR_OCDB_1BIT (0 << 28) -#define SMENR_OCDB_4BIT (2 << 28) -#define SMENR_CDB_1BIT (0 << 30) -#define SMENR_CDB_4BIT (U(2) << 30) -#define CMNSR_TEND (1 << 0) -#define CMNSR_SSLF (1 << 1) -#define DRDRENR_DRDRE_DDR (1 << 0) -#define DRDRENR_DRDRE_SDR (0 << 0) -#define DRDRENR_OPDRE_DDR (1 << 4) -#define DRDRENR_OPDRE_SDR (0 << 4) -#define DRDRENR_ADDRE_DDR (1 << 8) -#define DRDRENR_ADDRE_SDR (0 << 8) -#define DRDRENR_HYPE_HYPER (5 << 12) -#define DRDRENR_HYPE_OCTA (4 << 12) -#define DRDRENR_HYPE_SPI (0 << 12) -#define SMDRENR_SPIDRE (1 << 0) -#define SMDRENR_OPDRE (1 << 4) -#define SMDRENR_ADDRE (1 << 8) -#define SMDRENR_HYPE_HYPER_FLASH (5 << 12) -#define SMDRENR_HYPE_OCTA_FLASH (4 << 12) -#define SMDRENR_HYPE_SPI_FLASH (0 << 12) -#define PHYCNT_PHYMEM_SDR_MODE (0 << 0) -#define PHYCNT_PHYMEM_DDR_MODE (1 << 0) -#define PHYCNT_PHYMEM_HYPER_FLASH (3 << 0) -#define PHYCNT_WBUF_USED (1 << 2) -#define PHYCNT_WBUF_NOT_USED (0 << 2) -#define PHYCNT_WBUF2_USED (1 << 4) -#define PHYCNT_WBUF2_NOT_USED (0 << 4) -#define PHYCNT_CKSEL_SLOW (0 << 16) -#define PHYCNT_CKSEL_FAST (3 << 16) -#define PHYCNT_HS_MODE (1 << 18) -#define PHYCNT_HS_OTHER_MODE (0 << 18) -#define PHYCNT_OCT_MODE (1 << 20) -#define PHYCNT_OCT_OTHER_MODE (0 << 20) -#define PHYCNT_EXDS_USED (1 << 21) -#define PHYCNT_EXDS_NOT_USED (0 << 21) -#define PHYCNT_OCTA_HYPER_FLASH (0 << 22) -#define PHYCNT_OCTA_ALTE (1 << 22) -#define PHYCNT_OCTA_ORDER (2 << 22) -#define PHYCNT_ALT_ALIGN_SUPPORTED (1 << 30) -#define PHYCNT_ALT_ALIGN_NOT_SUPPORTED (0 << 30) -#define PHYCNT_CAL_PERFOMED (U(1) << 31) -#define PHYCNT_CAL_NOT_PERFOMED (0 << 31) -#define PHYCNT_DEF_DATA (0x00000260) -#define PHYOFFSET1_DDRTMG_SPIDRE_1 (2 << 28) -#define PHYOFFSET1_DDRTMG_SPIDRE_0 (3 << 28) -#define PHYOFFSET1_DEF_DATA (0x01511144) -#define PHYOFFSET2_OCTTMG_HYPER_FLASH (4 << 8) -#define PHYOFFSET2_OCTTMG_OCTA_FLASH (3 << 8) -#define PHYOFFSET2_DEF_DATA (0x00000031) -#define PHYINT_INT (1 << 0) -#define PHYINT_WPVAL (1 << 1) -#define PHYINT_RSTVAL (1 << 2) -#define PHYINT_INTEN (1 << 24) -#define PHYINT_WPEN (1 << 25) -#define PHYINT_RSTEN (1 << 26) - -#define DREAR_EAV_ADDRE_DATA (2 << 16) - -#define DRCMR_CMD_FAST_READ_3B (0x0B << 16) -#define DRCMR_CMD_QUAD_OUTPUT_FAST_READ_3B (0x6B << 16) -#define DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_3B (0xEB << 16) -#define DRCMR_CMD_FAST_READ_4B (0x0C << 16) -#define DRCMR_CMD_QUAD_OUTPUT_FAST_READ_4B (0x6C << 16) -#define DRCMR_CMD_QUAD_INPUT_OUTPUT_FAST_READ_4B (0xEC << 16) - -#endif /* _SPI_MULTI_REG_H_ */ - diff --git a/plat/renesas/rza/common/include/pfc_regs.h b/plat/renesas/rza/common/include/pfc_regs.h deleted file mode 100644 index 6fe8b30ebd..0000000000 --- a/plat/renesas/rza/common/include/pfc_regs.h +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __PFC_REGS_H__ -#define __PFC_REGS_H__ - -#define PFC_BASE (0x11030000) /* PFC base address */ - -#define PFC_P05 (PFC_BASE + 0x0005) /* Port register */ -#define PFC_P10 (PFC_BASE + 0x0010) /* Port register */ -#define PFC_P11 (PFC_BASE + 0x0011) /* Port register */ -#define PFC_P12 (PFC_BASE + 0x0012) /* Port register */ -#define PFC_P13 (PFC_BASE + 0x0013) /* Port register */ -#define PFC_P14 (PFC_BASE + 0x0014) /* Port register */ -#define PFC_P15 (PFC_BASE + 0x0015) /* Port register */ -#define PFC_P16 (PFC_BASE + 0x0016) /* Port register */ -#define PFC_P17 (PFC_BASE + 0x0017) /* Port register */ -#define PFC_P18 (PFC_BASE + 0x0018) /* Port register */ -#define PFC_P19 (PFC_BASE + 0x0019) /* Port register */ -#define PFC_P1A (PFC_BASE + 0x001A) /* Port register */ -#define PFC_P1B (PFC_BASE + 0x001B) /* Port register */ -#define PFC_P1C (PFC_BASE + 0x001C) /* Port register */ -#define PFC_P1D (PFC_BASE + 0x001D) /* Port register */ -#define PFC_P1E (PFC_BASE + 0x001E) /* Port register */ -#define PFC_P1F (PFC_BASE + 0x001F) /* Port register */ -#define PFC_P20 (PFC_BASE + 0x0020) /* Port register */ -#define PFC_P21 (PFC_BASE + 0x0021) /* Port register */ -#define PFC_P22 (PFC_BASE + 0x0022) /* Port register */ -#define PFC_P23 (PFC_BASE + 0x0023) /* Port register */ -#define PFC_P24 (PFC_BASE + 0x0024) /* Port register */ -#define PFC_P25 (PFC_BASE + 0x0025) /* Port register */ -#define PFC_P26 (PFC_BASE + 0x0026) /* Port register */ -#define PFC_P27 (PFC_BASE + 0x0027) /* Port register */ -#define PFC_P28 (PFC_BASE + 0x0028) /* Port register */ -#define PFC_P29 (PFC_BASE + 0x0029) /* Port register */ -#define PFC_P2A (PFC_BASE + 0x002A) /* Port register */ -#define PFC_P2B (PFC_BASE + 0x002B) /* Port register */ -#define PFC_P2C (PFC_BASE + 0x002C) /* Port register */ -#define PFC_P2D (PFC_BASE + 0x002D) /* Port register */ -#define PFC_P2E (PFC_BASE + 0x002E) /* Port register */ -#define PFC_P2F (PFC_BASE + 0x002F) /* Port register */ -#define PFC_P30 (PFC_BASE + 0x0030) /* Port register */ -#define PFC_P31 (PFC_BASE + 0x0031) /* Port register */ -#define PFC_P32 (PFC_BASE + 0x0032) /* Port register */ -#define PFC_P33 (PFC_BASE + 0x0033) /* Port register */ -#define PFC_P34 (PFC_BASE + 0x0034) /* Port register */ -#define PFC_P35 (PFC_BASE + 0x0035) /* Port register */ -#define PFC_P36 (PFC_BASE + 0x0036) /* Port register */ -#define PFC_P37 (PFC_BASE + 0x0037) /* Port register */ -#define PFC_P38 (PFC_BASE + 0x0038) /* Port register */ -#define PFC_P39 (PFC_BASE + 0x0039) /* Port register */ -#define PFC_P3A (PFC_BASE + 0x003A) /* Port register */ -#define PFC_P3B (PFC_BASE + 0x003B) /* Port register */ -#define PFC_P3C (PFC_BASE + 0x003C) /* Port register */ -#define PFC_P3D (PFC_BASE + 0x003D) /* Port register */ -#define PFC_P3E (PFC_BASE + 0x003E) /* Port register */ -#define PFC_P3F (PFC_BASE + 0x003F) /* Port register */ -#define PFC_P40 (PFC_BASE + 0x0040) /* Port register */ -#define PFC_PM10 (PFC_BASE + 0x0120) /* Port mode register */ -#define PFC_PM11 (PFC_BASE + 0x0122) /* Port mode register */ -#define PFC_PM12 (PFC_BASE + 0x0124) /* Port mode register */ -#define PFC_PM13 (PFC_BASE + 0x0126) /* Port mode register */ -#define PFC_PM14 (PFC_BASE + 0x0128) /* Port mode register */ -#define PFC_PM15 (PFC_BASE + 0x012A) /* Port mode register */ -#define PFC_PM16 (PFC_BASE + 0x012C) /* Port mode register */ -#define PFC_PM17 (PFC_BASE + 0x012E) /* Port mode register */ -#define PFC_PM18 (PFC_BASE + 0x0130) /* Port mode register */ -#define PFC_PM19 (PFC_BASE + 0x0132) /* Port mode register */ -#define PFC_PM1A (PFC_BASE + 0x0134) /* Port mode register */ -#define PFC_PM1B (PFC_BASE + 0x0136) /* Port mode register */ -#define PFC_PM1C (PFC_BASE + 0x0138) /* Port mode register */ -#define PFC_PM1D (PFC_BASE + 0x013A) /* Port mode register */ -#define PFC_PM1E (PFC_BASE + 0x013C) /* Port mode register */ -#define PFC_PM1F (PFC_BASE + 0x013E) /* Port mode register */ -#define PFC_PM20 (PFC_BASE + 0x0140) /* Port mode register */ -#define PFC_PM21 (PFC_BASE + 0x0142) /* Port mode register */ -#define PFC_PM22 (PFC_BASE + 0x0144) /* Port mode register */ -#define PFC_PM23 (PFC_BASE + 0x0146) /* Port mode register */ -#define PFC_PM24 (PFC_BASE + 0x0148) /* Port mode register */ -#define PFC_PM25 (PFC_BASE + 0x014A) /* Port mode register */ -#define PFC_PM26 (PFC_BASE + 0x014C) /* Port mode register */ -#define PFC_PM27 (PFC_BASE + 0x014E) /* Port mode register */ -#define PFC_PM28 (PFC_BASE + 0x0150) /* Port mode register */ -#define PFC_PM29 (PFC_BASE + 0x0152) /* Port mode register */ -#define PFC_PM2A (PFC_BASE + 0x0154) /* Port mode register */ -#define PFC_PM2B (PFC_BASE + 0x0156) /* Port mode register */ -#define PFC_PM2C (PFC_BASE + 0x0158) /* Port mode register */ -#define PFC_PM2D (PFC_BASE + 0x015A) /* Port mode register */ -#define PFC_PM2E (PFC_BASE + 0x015C) /* Port mode register */ -#define PFC_PM2F (PFC_BASE + 0x015E) /* Port mode register */ -#define PFC_PM30 (PFC_BASE + 0x0160) /* Port mode register */ -#define PFC_PM31 (PFC_BASE + 0x0162) /* Port mode register */ -#define PFC_PM32 (PFC_BASE + 0x0164) /* Port mode register */ -#define PFC_PM33 (PFC_BASE + 0x0166) /* Port mode register */ -#define PFC_PM34 (PFC_BASE + 0x0168) /* Port mode register */ -#define PFC_PM35 (PFC_BASE + 0x016A) /* Port mode register */ -#define PFC_PM36 (PFC_BASE + 0x016C) /* Port mode register */ -#define PFC_PM37 (PFC_BASE + 0x016E) /* Port mode register */ -#define PFC_PM38 (PFC_BASE + 0x0170) /* Port mode register */ -#define PFC_PM39 (PFC_BASE + 0x0172) /* Port mode register */ -#define PFC_PM3A (PFC_BASE + 0x0174) /* Port mode register */ -#define PFC_PM3B (PFC_BASE + 0x0176) /* Port mode register */ -#define PFC_PM3C (PFC_BASE + 0x0178) /* Port mode register */ -#define PFC_PM3D (PFC_BASE + 0x017A) /* Port mode register */ -#define PFC_PM3E (PFC_BASE + 0x017C) /* Port mode register */ -#define PFC_PM3F (PFC_BASE + 0x017E) /* Port mode register */ -#define PFC_PM40 (PFC_BASE + 0x0180) /* Port mode register */ -#define PFC_PMC04 (PFC_BASE + 0x0204) /* Port mode control register */ -#define PFC_PMC05 (PFC_BASE + 0x0205) /* Port mode control register */ -#define PFC_PMC10 (PFC_BASE + 0x0210) /* Port mode control register */ -#define PFC_PMC11 (PFC_BASE + 0x0211) /* Port mode control register */ -#define PFC_PMC12 (PFC_BASE + 0x0212) /* Port mode control register */ -#define PFC_PMC13 (PFC_BASE + 0x0213) /* Port mode control register */ -#define PFC_PMC14 (PFC_BASE + 0x0214) /* Port mode control register */ -#define PFC_PMC15 (PFC_BASE + 0x0215) /* Port mode control register */ -#define PFC_PMC16 (PFC_BASE + 0x0216) /* Port mode control register */ -#define PFC_PMC17 (PFC_BASE + 0x0217) /* Port mode control register */ -#define PFC_PMC18 (PFC_BASE + 0x0218) /* Port mode control register */ -#define PFC_PMC19 (PFC_BASE + 0x0219) /* Port mode control register */ -#define PFC_PMC1A (PFC_BASE + 0x021A) /* Port mode control register */ -#define PFC_PMC1B (PFC_BASE + 0x021B) /* Port mode control register */ -#define PFC_PMC1C (PFC_BASE + 0x021C) /* Port mode control register */ -#define PFC_PMC1D (PFC_BASE + 0x021D) /* Port mode control register */ -#define PFC_PMC1E (PFC_BASE + 0x021E) /* Port mode control register */ -#define PFC_PMC1F (PFC_BASE + 0x021F) /* Port mode control register */ -#define PFC_PMC20 (PFC_BASE + 0x0220) /* Port mode control register */ -#define PFC_PMC21 (PFC_BASE + 0x0221) /* Port mode control register */ -#define PFC_PMC22 (PFC_BASE + 0x0222) /* Port mode control register */ -#define PFC_PMC23 (PFC_BASE + 0x0223) /* Port mode control register */ -#define PFC_PMC24 (PFC_BASE + 0x0224) /* Port mode control register */ -#define PFC_PMC25 (PFC_BASE + 0x0225) /* Port mode control register */ -#define PFC_PMC26 (PFC_BASE + 0x0226) /* Port mode control register */ -#define PFC_PMC27 (PFC_BASE + 0x0227) /* Port mode control register */ -#define PFC_PMC28 (PFC_BASE + 0x0228) /* Port mode control register */ -#define PFC_PMC29 (PFC_BASE + 0x0229) /* Port mode control register */ -#define PFC_PMC2A (PFC_BASE + 0x022A) /* Port mode control register */ -#define PFC_PMC2B (PFC_BASE + 0x022B) /* Port mode control register */ -#define PFC_PMC2C (PFC_BASE + 0x022C) /* Port mode control register */ -#define PFC_PMC2D (PFC_BASE + 0x022D) /* Port mode control register */ -#define PFC_PMC2E (PFC_BASE + 0x022E) /* Port mode control register */ -#define PFC_PMC2F (PFC_BASE + 0x022F) /* Port mode control register */ -#define PFC_PMC30 (PFC_BASE + 0x0230) /* Port mode control register */ -#define PFC_PMC31 (PFC_BASE + 0x0231) /* Port mode control register */ -#define PFC_PMC32 (PFC_BASE + 0x0232) /* Port mode control register */ -#define PFC_PMC33 (PFC_BASE + 0x0233) /* Port mode control register */ -#define PFC_PMC34 (PFC_BASE + 0x0234) /* Port mode control register */ -#define PFC_PMC35 (PFC_BASE + 0x0235) /* Port mode control register */ -#define PFC_PMC36 (PFC_BASE + 0x0236) /* Port mode control register */ -#define PFC_PMC37 (PFC_BASE + 0x0237) /* Port mode control register */ -#define PFC_PMC38 (PFC_BASE + 0x0238) /* Port mode control register */ -#define PFC_PMC39 (PFC_BASE + 0x0239) /* Port mode control register */ -#define PFC_PMC3A (PFC_BASE + 0x023A) /* Port mode control register */ -#define PFC_PMC3B (PFC_BASE + 0x023B) /* Port mode control register */ -#define PFC_PMC3C (PFC_BASE + 0x023C) /* Port mode control register */ -#define PFC_PMC3D (PFC_BASE + 0x023D) /* Port mode control register */ -#define PFC_PMC3E (PFC_BASE + 0x023E) /* Port mode control register */ -#define PFC_PMC3F (PFC_BASE + 0x023F) /* Port mode control register */ -#define PFC_PMC40 (PFC_BASE + 0x0240) /* Port mode control register */ -#define PFC_PFC04 (PFC_BASE + 0x0410) /* Port function control register */ -#define PFC_PFC05 (PFC_BASE + 0x0414) /* Port function control register */ -#define PFC_PFC10 (PFC_BASE + 0x0440) /* Port function control register */ -#define PFC_PFC11 (PFC_BASE + 0x0444) /* Port function control register */ -#define PFC_PFC12 (PFC_BASE + 0x0448) /* Port function control register */ -#define PFC_PFC13 (PFC_BASE + 0x044C) /* Port function control register */ -#define PFC_PFC14 (PFC_BASE + 0x0450) /* Port function control register */ -#define PFC_PFC15 (PFC_BASE + 0x0454) /* Port function control register */ -#define PFC_PFC16 (PFC_BASE + 0x0458) /* Port function control register */ -#define PFC_PFC17 (PFC_BASE + 0x045C) /* Port function control register */ -#define PFC_PFC18 (PFC_BASE + 0x0460) /* Port function control register */ -#define PFC_PFC19 (PFC_BASE + 0x0464) /* Port function control register */ -#define PFC_PFC1A (PFC_BASE + 0x0468) /* Port function control register */ -#define PFC_PFC1B (PFC_BASE + 0x046C) /* Port function control register */ -#define PFC_PFC1C (PFC_BASE + 0x0470) /* Port function control register */ -#define PFC_PFC1D (PFC_BASE + 0x0474) /* Port function control register */ -#define PFC_PFC1E (PFC_BASE + 0x0478) /* Port function control register */ -#define PFC_PFC1F (PFC_BASE + 0x047C) /* Port function control register */ -#define PFC_PFC20 (PFC_BASE + 0x0480) /* Port function control register */ -#define PFC_PFC21 (PFC_BASE + 0x0484) /* Port function control register */ -#define PFC_PFC22 (PFC_BASE + 0x0488) /* Port function control register */ -#define PFC_PFC23 (PFC_BASE + 0x048C) /* Port function control register */ -#define PFC_PFC24 (PFC_BASE + 0x0490) /* Port function control register */ -#define PFC_PFC25 (PFC_BASE + 0x0494) /* Port function control register */ -#define PFC_PFC26 (PFC_BASE + 0x0498) /* Port function control register */ -#define PFC_PFC27 (PFC_BASE + 0x049C) /* Port function control register */ -#define PFC_PFC28 (PFC_BASE + 0x04A0) /* Port function control register */ -#define PFC_PFC29 (PFC_BASE + 0x04A4) /* Port function control register */ -#define PFC_PFC2A (PFC_BASE + 0x04A8) /* Port function control register */ -#define PFC_PFC2B (PFC_BASE + 0x04AC) /* Port function control register */ -#define PFC_PFC2C (PFC_BASE + 0x04B0) /* Port function control register */ -#define PFC_PFC2D (PFC_BASE + 0x04B4) /* Port function control register */ -#define PFC_PFC2E (PFC_BASE + 0x04B8) /* Port function control register */ -#define PFC_PFC2F (PFC_BASE + 0x04BC) /* Port function control register */ -#define PFC_PFC30 (PFC_BASE + 0x04C0) /* Port function control register */ -#define PFC_PFC31 (PFC_BASE + 0x04C4) /* Port function control register */ -#define PFC_PFC32 (PFC_BASE + 0x04C8) /* Port function control register */ -#define PFC_PFC33 (PFC_BASE + 0x04CC) /* Port function control register */ -#define PFC_PFC34 (PFC_BASE + 0x04D0) /* Port function control register */ -#define PFC_PFC35 (PFC_BASE + 0x04D4) /* Port function control register */ -#define PFC_PFC36 (PFC_BASE + 0x04D8) /* Port function control register */ -#define PFC_PFC37 (PFC_BASE + 0x04DC) /* Port function control register */ -#define PFC_PFC38 (PFC_BASE + 0x04E0) /* Port function control register */ -#define PFC_PFC39 (PFC_BASE + 0x04E4) /* Port function control register */ -#define PFC_PFC3A (PFC_BASE + 0x04E8) /* Port function control register */ -#define PFC_PFC3B (PFC_BASE + 0x04EC) /* Port function control register */ -#define PFC_PFC3C (PFC_BASE + 0x04F0) /* Port function control register */ -#define PFC_PFC3D (PFC_BASE + 0x04F4) /* Port function control register */ -#define PFC_PFC3E (PFC_BASE + 0x04F8) /* Port function control register */ -#define PFC_PFC3F (PFC_BASE + 0x04FC) /* Port function control register */ -#define PFC_PFC40 (PFC_BASE + 0x0500) /* Port function control register */ -#define PFC_IOLH02 (PFC_BASE + 0x1010) /* IOLH switch register */ -#define PFC_IOLH03 (PFC_BASE + 0x1018) /* IOLH switch register */ -#define PFC_IOLH04 (PFC_BASE + 0x1020) /* IOLH switch register */ -#define PFC_IOLH05 (PFC_BASE + 0x1028) /* IOLH switch register */ -#define PFC_IOLH06 (PFC_BASE + 0x1030) /* IOLH switch register */ -#define PFC_IOLH07 (PFC_BASE + 0x1038) /* IOLH switch register */ -#define PFC_IOLH08 (PFC_BASE + 0x1040) /* IOLH switch register */ -#define PFC_IOLH09 (PFC_BASE + 0x1048) /* IOLH switch register */ -#define PFC_IOLH0A (PFC_BASE + 0x1050) /* IOLH switch register */ -#define PFC_IOLH0B (PFC_BASE + 0x1058) /* IOLH switch register */ -#define PFC_IOLH0C (PFC_BASE + 0x1060) /* IOLH switch register */ -#define PFC_IOLH0D (PFC_BASE + 0x1068) /* IOLH switch register */ -#define PFC_IOLH10 (PFC_BASE + 0x1080) /* IOLH switch register */ -#define PFC_IOLH11 (PFC_BASE + 0x1088) /* IOLH switch register */ -#define PFC_IOLH12 (PFC_BASE + 0x1090) /* IOLH switch register */ -#define PFC_IOLH13 (PFC_BASE + 0x1098) /* IOLH switch register */ -#define PFC_IOLH14 (PFC_BASE + 0x10A0) /* IOLH switch register */ -#define PFC_IOLH15 (PFC_BASE + 0x10A8) /* IOLH switch register */ -#define PFC_IOLH16 (PFC_BASE + 0x10B0) /* IOLH switch register */ -#define PFC_IOLH17 (PFC_BASE + 0x10B8) /* IOLH switch register */ -#define PFC_IOLH18 (PFC_BASE + 0x10C0) /* IOLH switch register */ -#define PFC_IOLH19 (PFC_BASE + 0x10C8) /* IOLH switch register */ -#define PFC_IOLH1A (PFC_BASE + 0x10D0) /* IOLH switch register */ -#define PFC_IOLH1B (PFC_BASE + 0x10D8) /* IOLH switch register */ -#define PFC_IOLH1C (PFC_BASE + 0x10E0) /* IOLH switch register */ -#define PFC_IOLH1D (PFC_BASE + 0x10E8) /* IOLH switch register */ -#define PFC_IOLH1E (PFC_BASE + 0x10F0) /* IOLH switch register */ -#define PFC_IOLH1F (PFC_BASE + 0x10F8) /* IOLH switch register */ -#define PFC_IOLH20 (PFC_BASE + 0x1100) /* IOLH switch register */ -#define PFC_IOLH21 (PFC_BASE + 0x1108) /* IOLH switch register */ -#define PFC_IOLH22 (PFC_BASE + 0x1120) /* IOLH switch register */ -#define PFC_IOLH23 (PFC_BASE + 0x1128) /* IOLH switch register */ -#define PFC_IOLH36 (PFC_BASE + 0x11B0) /* IOLH switch register */ -#define PFC_IOLH37 (PFC_BASE + 0x11B8) /* IOLH switch register */ -#define PFC_IOLH38 (PFC_BASE + 0x11C0) /* IOLH switch register */ -#define PFC_IOLH39 (PFC_BASE + 0x11C8) /* IOLH switch register */ -#define PFC_IOLH3A (PFC_BASE + 0x11D0) /* IOLH switch register */ -#define PFC_IOLH3B (PFC_BASE + 0x11D8) /* IOLH switch register */ -#define PFC_IOLH3C (PFC_BASE + 0x11E0) /* IOLH switch register */ -#define PFC_IOLH3D (PFC_BASE + 0x11E8) /* IOLH switch register */ -#define PFC_IOLH3E (PFC_BASE + 0x11F0) /* IOLH switch register */ -#define PFC_IOLH3F (PFC_BASE + 0x11F8) /* IOLH switch register */ -#define PFC_IOLH40 (PFC_BASE + 0x1200) /* IOLH switch register */ -#define PFC_SR04 (PFC_BASE + 0x1420) /* Slew-Rate switch register */ -#define PFC_SR05 (PFC_BASE + 0x1428) /* Slew-Rate switch register */ -#define PFC_SR06 (PFC_BASE + 0x1430) /* Slew-Rate switch register */ -#define PFC_SR07 (PFC_BASE + 0x1438) /* Slew-Rate switch register */ -#define PFC_SR08 (PFC_BASE + 0x1440) /* Slew-Rate switch register */ -#define PFC_SR09 (PFC_BASE + 0x1448) /* Slew-Rate switch register */ -#define PFC_SR0A (PFC_BASE + 0x1450) /* Slew-Rate switch register */ -#define PFC_SR0B (PFC_BASE + 0x1458) /* Slew-Rate switch register */ -#define PFC_SR0C (PFC_BASE + 0x1460) /* Slew-Rate switch register */ -#define PFC_SR10 (PFC_BASE + 0x1480) /* Slew-Rate switch register */ -#define PFC_SR15 (PFC_BASE + 0x14A8) /* Slew-Rate switch register */ -#define PFC_SR16 (PFC_BASE + 0x14B0) /* Slew-Rate switch register */ -#define PFC_SR1A (PFC_BASE + 0x14D0) /* Slew-Rate switch register */ -#define PFC_SR1B (PFC_BASE + 0x14D8) /* Slew-Rate switch register */ -#define PFC_SR1C (PFC_BASE + 0x14E0) /* Slew-Rate switch register */ -#define PFC_SR1D (PFC_BASE + 0x14E8) /* Slew-Rate switch register */ -#define PFC_SR1E (PFC_BASE + 0x14F0) /* Slew-Rate switch register */ -#define PFC_SR1F (PFC_BASE + 0x14F8) /* Slew-Rate switch register */ -#define PFC_SR20 (PFC_BASE + 0x1500) /* Slew-Rate switch register */ -#define PFC_SR21 (PFC_BASE + 0x1508) /* Slew-Rate switch register */ -#define PFC_SR22 (PFC_BASE + 0x1510) /* Slew-Rate switch register */ -#define PFC_SR23 (PFC_BASE + 0x1518) /* Slew-Rate switch register */ -#define PFC_SR36 (PFC_BASE + 0x15B0) /* Slew-Rate switch register */ -#define PFC_SR37 (PFC_BASE + 0x15B8) /* Slew-Rate switch register */ -#define PFC_IEN06 (PFC_BASE + 0x1830) /* IEN switch register */ -#define PFC_IEN07 (PFC_BASE + 0x1838) /* IEN switch register */ -#define PFC_IEN08 (PFC_BASE + 0x1840) /* IEN switch register */ -#define PFC_IEN09 (PFC_BASE + 0x1848) /* IEN switch register */ -#define PFC_PUPD04 (PFC_BASE + 0x1C20) /* PU/PD switch register */ -#define PFC_PUPD05 (PFC_BASE + 0x1C28) /* PU/PD switch register */ -#define PFC_PUPD06 (PFC_BASE + 0x1C30) /* PU/PD switch register */ -#define PFC_PUPD07 (PFC_BASE + 0x1C38) /* PU/PD switch register */ -#define PFC_PUPD08 (PFC_BASE + 0x1C40) /* PU/PD switch register */ -#define PFC_PUPD09 (PFC_BASE + 0x1C48) /* PU/PD switch register */ -#define PFC_PUPD0A (PFC_BASE + 0x1C50) /* PU/PD switch register */ -#define PFC_PUPD0B (PFC_BASE + 0x1C58) /* PU/PD switch register */ -#define PFC_PUPD0C (PFC_BASE + 0x1C60) /* PU/PD switch register */ -#define PFC_PUPD10 (PFC_BASE + 0x1C80) /* PU/PD switch register */ -#define PFC_PUPD15 (PFC_BASE + 0x1CA8) /* PU/PD switch register */ -#define PFC_PUPD16 (PFC_BASE + 0x1CB0) /* PU/PD switch register */ -#define PFC_PUPD1A (PFC_BASE + 0x1CD0) /* PU/PD switch register */ -#define PFC_PUPD1B (PFC_BASE + 0x1CD8) /* PU/PD switch register */ -#define PFC_PUPD1C (PFC_BASE + 0x1CE0) /* PU/PD switch register */ -#define PFC_PUPD1D (PFC_BASE + 0x1CE8) /* PU/PD switch register */ -#define PFC_PUPD1E (PFC_BASE + 0x1CF0) /* PU/PD switch register */ -#define PFC_PUPD1F (PFC_BASE + 0x1CF8) /* PU/PD switch register */ -#define PFC_PUPD20 (PFC_BASE + 0x1D00) /* PU/PD switch register */ -#define PFC_PUPD21 (PFC_BASE + 0x1D08) /* PU/PD switch register */ -#define PFC_PUPD22 (PFC_BASE + 0x1D10) /* PU/PD switch register */ -#define PFC_PUPD23 (PFC_BASE + 0x1D18) /* PU/PD switch register */ -#define PFC_PUPD36 (PFC_BASE + 0x1DB0) /* PU/PD switch register */ -#define PFC_PUPD37 (PFC_BASE + 0x1DB8) /* PU/PD switch register */ -#define PFC_SD_ch0 (PFC_BASE + 0x3000) /* SD ch0 IO voltage control register */ -#define PFC_SD_ch1 (PFC_BASE + 0x3004) /* SD ch1 IO voltage control register */ -#define PFC_QSPI (PFC_BASE + 0x3008) /* QSPI IO voltage control register */ -#define PFC_ETH_ch0 (PFC_BASE + 0x300C) /* ETH ch0 voltage control register */ -#define PFC_ETH_ch1 (PFC_BASE + 0x3010) /* ETH ch1 voltage control register */ -#define PFC_PWPR (PFC_BASE + 0x3014) /* Write protect */ -#define PFC_FILONOFF01 (PFC_BASE + 0x2008) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF10 (PFC_BASE + 0x2080) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF11 (PFC_BASE + 0x2088) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF12 (PFC_BASE + 0x2090) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF13 (PFC_BASE + 0x2098) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF14 (PFC_BASE + 0x20A0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF15 (PFC_BASE + 0x20A8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF16 (PFC_BASE + 0x20B0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF17 (PFC_BASE + 0x20B8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF18 (PFC_BASE + 0x20C0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF19 (PFC_BASE + 0x20C8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1A (PFC_BASE + 0x20D0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1B (PFC_BASE + 0x20D8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1C (PFC_BASE + 0x20E0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1D (PFC_BASE + 0x20E8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1E (PFC_BASE + 0x20F0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF1F (PFC_BASE + 0x20F8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF20 (PFC_BASE + 0x2100) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF21 (PFC_BASE + 0x2108) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF22 (PFC_BASE + 0x2110) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF23 (PFC_BASE + 0x2118) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF24 (PFC_BASE + 0x2120) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF25 (PFC_BASE + 0x2128) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF26 (PFC_BASE + 0x2130) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF27 (PFC_BASE + 0x2138) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF28 (PFC_BASE + 0x2140) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF29 (PFC_BASE + 0x2148) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2A (PFC_BASE + 0x2150) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2B (PFC_BASE + 0x2158) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2C (PFC_BASE + 0x2160) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2D (PFC_BASE + 0x2168) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2E (PFC_BASE + 0x2170) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF2F (PFC_BASE + 0x2178) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF30 (PFC_BASE + 0x2180) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF31 (PFC_BASE + 0x2188) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF32 (PFC_BASE + 0x2190) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF33 (PFC_BASE + 0x2198) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF34 (PFC_BASE + 0x21A0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF35 (PFC_BASE + 0x21A8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF36 (PFC_BASE + 0x21B0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF37 (PFC_BASE + 0x21B8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF38 (PFC_BASE + 0x21C0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF39 (PFC_BASE + 0x21C8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3A (PFC_BASE + 0x21D0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3B (PFC_BASE + 0x21D8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3C (PFC_BASE + 0x21E0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3D (PFC_BASE + 0x21E8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3E (PFC_BASE + 0x21F0) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF3F (PFC_BASE + 0x21F8) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILONOFF40 (PFC_BASE + 0x2200) /* Digital noise filter (FILONOFF) register */ -#define PFC_FILNUM01 (PFC_BASE + 0x2408) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM10 (PFC_BASE + 0x2480) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM11 (PFC_BASE + 0x2488) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM12 (PFC_BASE + 0x2490) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM13 (PFC_BASE + 0x2498) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM14 (PFC_BASE + 0x24A0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM15 (PFC_BASE + 0x24A8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM16 (PFC_BASE + 0x24B0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM17 (PFC_BASE + 0x24B8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM18 (PFC_BASE + 0x24C0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM19 (PFC_BASE + 0x24C8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1A (PFC_BASE + 0x24D0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1B (PFC_BASE + 0x24D8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1C (PFC_BASE + 0x24E0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1D (PFC_BASE + 0x24E8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1E (PFC_BASE + 0x24F0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM1F (PFC_BASE + 0x24F8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM20 (PFC_BASE + 0x2500) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM21 (PFC_BASE + 0x2508) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM22 (PFC_BASE + 0x2510) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM23 (PFC_BASE + 0x2518) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM24 (PFC_BASE + 0x2520) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM25 (PFC_BASE + 0x2528) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM26 (PFC_BASE + 0x2530) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM27 (PFC_BASE + 0x2538) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM28 (PFC_BASE + 0x2540) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM29 (PFC_BASE + 0x2548) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2A (PFC_BASE + 0x2550) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2B (PFC_BASE + 0x2558) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2C (PFC_BASE + 0x2560) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2D (PFC_BASE + 0x2568) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2E (PFC_BASE + 0x2570) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM2F (PFC_BASE + 0x2578) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM30 (PFC_BASE + 0x2580) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM31 (PFC_BASE + 0x2588) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM32 (PFC_BASE + 0x2590) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM33 (PFC_BASE + 0x2598) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM34 (PFC_BASE + 0x25A0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM35 (PFC_BASE + 0x25A8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM36 (PFC_BASE + 0x25B0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM37 (PFC_BASE + 0x25B8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM38 (PFC_BASE + 0x25C0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM39 (PFC_BASE + 0x25C8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3A (PFC_BASE + 0x25D0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3B (PFC_BASE + 0x25D8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3C (PFC_BASE + 0x25E0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3D (PFC_BASE + 0x25E8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3E (PFC_BASE + 0x25F0) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM3F (PFC_BASE + 0x25F8) /* Digital noise filter (FILNUM) register */ -#define PFC_FILNUM40 (PFC_BASE + 0x2600) /* Digital noise filter (FILNUM) register */ -#define PFC_FILCLKSEL01 (PFC_BASE + 0x2808) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL10 (PFC_BASE + 0x2880) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL11 (PFC_BASE + 0x2888) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL12 (PFC_BASE + 0x2890) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL13 (PFC_BASE + 0x2898) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL14 (PFC_BASE + 0x28A0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL15 (PFC_BASE + 0x28A8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL16 (PFC_BASE + 0x28B0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL17 (PFC_BASE + 0x28B8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL18 (PFC_BASE + 0x28C0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL19 (PFC_BASE + 0x28C8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1A (PFC_BASE + 0x28D0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1B (PFC_BASE + 0x28D8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1C (PFC_BASE + 0x28E0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1D (PFC_BASE + 0x28E8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1E (PFC_BASE + 0x28F0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL1F (PFC_BASE + 0x28F8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL20 (PFC_BASE + 0x2900) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL21 (PFC_BASE + 0x2908) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL22 (PFC_BASE + 0x2910) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL23 (PFC_BASE + 0x2918) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL24 (PFC_BASE + 0x2920) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL25 (PFC_BASE + 0x2928) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL26 (PFC_BASE + 0x2930) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL27 (PFC_BASE + 0x2938) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL28 (PFC_BASE + 0x2940) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL29 (PFC_BASE + 0x2948) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2A (PFC_BASE + 0x2950) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2B (PFC_BASE + 0x2958) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2C (PFC_BASE + 0x2960) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2D (PFC_BASE + 0x2968) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2E (PFC_BASE + 0x2970) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL2F (PFC_BASE + 0x2978) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL30 (PFC_BASE + 0x2980) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL31 (PFC_BASE + 0x2988) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL32 (PFC_BASE + 0x2990) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL33 (PFC_BASE + 0x2998) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL34 (PFC_BASE + 0x29A0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL35 (PFC_BASE + 0x29A8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL36 (PFC_BASE + 0x29B0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL37 (PFC_BASE + 0x29B8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL38 (PFC_BASE + 0x29C0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL39 (PFC_BASE + 0x29C8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3A (PFC_BASE + 0x29D0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3B (PFC_BASE + 0x29D8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3C (PFC_BASE + 0x29E0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3D (PFC_BASE + 0x29E8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3E (PFC_BASE + 0x29F0) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL3F (PFC_BASE + 0x29F8) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_FILCLKSEL40 (PFC_BASE + 0x2A00) /* Digital noise filter (FILCLKSEL) register */ -#define PFC_ETH_MII (PFC_BASE + 0x3018) /* Register for setting the mode of ETH MII / RGMII */ - -/* Combined terminal setting */ -/* Definition for port register */ -#define P_P0 (1 << 0) -#define P_P1 (1 << 1) -#define P_P2 (1 << 2) -#define P_P3 (1 << 3) -#define P_P4 (1 << 4) -#define P_P5 (1 << 5) -#define P_P6 (1 << 6) -#define P_P7 (1 << 7) -/* Definition for port mode register */ -#define PM0_HIZ (0 << 0) -#define PM0_IN (1 << 0) -#define PM0_OUT_DIS (2 << 0) -#define PM0_OUT_EN (3 << 0) -#define PM1_HIZ (0 << 2) -#define PM1_IN (1 << 2) -#define PM1_OUT_DIS (2 << 2) -#define PM1_OUT_EN (3 << 2) -#define PM2_HIZ (0 << 4) -#define PM2_IN (1 << 4) -#define PM2_OUT_DIS (2 << 4) -#define PM2_OUT_EN (3 << 4) -#define PM3_HIZ (0 << 6) -#define PM3_IN (1 << 6) -#define PM3_OUT_DIS (2 << 6) -#define PM3_OUT_EN (3 << 6) -#define PM4_HIZ (0 << 8) -#define PM4_IN (1 << 8) -#define PM4_OUT_DIS (2 << 8) -#define PM4_OUT_EN (3 << 8) -/* Definition for port mode control register */ -#define PMC_PMC0 (1 << 0) -#define PMC_PMC1 (1 << 1) -#define PMC_PMC2 (1 << 2) -#define PMC_PMC3 (1 << 3) -#define PMC_PMC4 (1 << 4) -#define PMC_PMC5 (1 << 5) -#define PMC_PMC6 (1 << 6) -#define PMC_PMC7 (1 << 7) -/* Definition for port function control register */ -#define PFC0_MODE0 (0 << 0) -#define PFC0_MODE1 (1 << 0) -#define PFC0_MODE2 (2 << 0) -#define PFC0_MODE3 (3 << 0) -#define PFC0_MODE4 (4 << 0) -#define PFC0_MODE5 (5 << 0) -#define PFC1_MODE0 (0 << 4) -#define PFC1_MODE1 (1 << 4) -#define PFC1_MODE2 (2 << 4) -#define PFC1_MODE3 (3 << 4) -#define PFC1_MODE4 (4 << 4) -#define PFC1_MODE5 (5 << 4) -#define PFC2_MODE0 (0 << 8) -#define PFC2_MODE1 (1 << 8) -#define PFC2_MODE2 (2 << 8) -#define PFC2_MODE3 (3 << 8) -#define PFC2_MODE4 (4 << 8) -#define PFC2_MODE5 (5 << 8) -#define PFC3_MODE0 (0 << 12) -#define PFC3_MODE1 (1 << 12) -#define PFC3_MODE2 (2 << 12) -#define PFC3_MODE3 (3 << 12) -#define PFC3_MODE4 (4 << 12) -#define PFC3_MODE5 (5 << 12) -#define PFC4_MODE0 (0 << 16) -#define PFC4_MODE1 (1 << 16) -#define PFC4_MODE2 (2 << 16) -#define PFC4_MODE3 (3 << 16) -#define PFC4_MODE4 (4 << 16) -#define PFC4_MODE5 (5 << 16) -/* Definition for IOLH switch register */ -#define IOLH0_2MA (0 << 0) -#define IOLH0_4MA (1 << 0) -#define IOLH0_8MA (2 << 0) -#define IOLH0_12MA (3 << 0) -#define IOLH1_2MA (0 << 8) -#define IOLH1_4MA (1 << 8) -#define IOLH1_8MA (2 << 8) -#define IOLH1_12MA (3 << 8) -#define IOLH2_2MA (0 << 16) -#define IOLH2_4MA (1 << 16) -#define IOLH2_8MA (2 << 16) -#define IOLH2_12MA (3 << 16) -#define IOLH3_2MA (0 << 24) -#define IOLH3_4MA (1 << 24) -#define IOLH3_8MA (2 << 24) -#define IOLH3_12MA (3 << 24) -#define IOLH4_2MA (0 << 32) -#define IOLH4_4MA (1 << 32) -#define IOLH4_8MA (2 << 32) -#define IOLH4_12MA (3 << 32) -#define IOLH5_2MA (0 << 40) -#define IOLH5_4MA (1 << 40) -#define IOLH5_8MA (2 << 40) -#define IOLH5_12MA (3 << 40) -#define IOLH6_2MA (0 << 48) -#define IOLH6_4MA (1 << 48) -#define IOLH6_8MA (2 << 48) -#define IOLH6_12MA (3 << 48) -#define IOLH7_2MA (0 << 56) -#define IOLH7_4MA (1 << 56) -#define IOLH7_8MA (2 << 56) -#define IOLH7_12MA (3 << 56) -/* Definition for Slew-Rate switch register */ -#define SR0_FAST (1 << 0) -#define SR1_FAST (1 << 8) -#define SR2_FAST (1 << 16) -#define SR3_FAST (1 << 24) -#define SR4_FAST (1 << 32) -#define SR5_FAST (1 << 40) -#define SR6_FAST (1 << 48) -#define SR7_FAST (1 << 56) -/* Definition for IEN switching register */ -#define IEN0_ENABLE (1 << 0) -#define IEN1_ENABLE (1 << 8) -#define IEN2_ENABLE (1 << 16) -#define IEN3_ENABLE (1 << 24) -#define IEN4_ENABLE (1 << 32) -#define IEN5_ENABLE (1 << 40) -#define IEN6_ENABLE (1 << 48) -#define IEN7_ENABLE (1 << 56) -/* Definition for PUPD switching register */ -#define PUPD0_NO (0 << 0) -#define PUPD0_UP (1 << 0) -#define PUPD0_DOWN (2 << 0) -#define PUPD1_NO (0 << 8) -#define PUPD1_UP (1 << 8) -#define PUPD1_DOWN (2 << 8) -#define PUPD2_NO (0 << 16) -#define PUPD2_UP (1 << 16) -#define PUPD2_DOWN (2 << 16) -#define PUPD3_NO (0 << 24) -#define PUPD3_UP (1 << 24) -#define PUPD3_DOWN (2 << 24) -#define PUPD4_NO (0 << 32) -#define PUPD4_UP (1 << 32) -#define PUPD4_DOWN (2 << 32) -#define PUPD5_NO (0 << 40) -#define PUPD5_UP (1 << 40) -#define PUPD5_DOWN (2 << 40) -#define PUPD6_NO (0 << 48) -#define PUPD6_UP (1 << 48) -#define PUPD6_DOWN (2 << 48) -#define PUPD7_NO (0 << 56) -#define PUPD7_UP (1 << 56) -#define PUPD7_DOWN (2 << 56) -/* SD ch0 IO Definition for voltage control register */ -#define SD0_PVDD (1 << 0) -/* SD ch1 IO Definition for voltage control register */ -#define SD1_PVDD (1 << 0) -/* Definition for QSPI IO voltage control register */ -#define QSPI_PVDD (1 << 0) -/* ETH ch0 voltage control register */ -#define ETH_ch0_3_3 (0 << 0) -#define ETH_ch0_1_8 (1 << 0) -#define ETH_ch0_2_5 (2 << 0) -/* ETH ch1 voltage control register */ -#define ETH_ch1_3_3 (0 << 0) -#define ETH_ch1_1_8 (1 << 0) -#define ETH_ch1_2_5 (2 << 0) -/* Write protection definition */ -#define PWPR_B0Wl (1 << 7) -#define PWPR_PFCWE (1 << 6) -/* Digital noise filter (FILONOFF) register */ -#define FILONOFF_FILON0 (1 << 0) -#define FILONOFF_FILON1 (1 << 8) -#define FILONOFF_FILON2 (1 << 16) -#define FILONOFF_FILON3 (1 << 24) -#define FILONOFF_FILON4 (1 << 32) -#define FILONOFF_FILON5 (1 << 40) -#define FILONOFF_FILON6 (1 << 48) -#define FILONOFF_FILON7 (1 << 56) -/* Digital noise filter (FILNUM) register */ -#define FILNUM_FILNUM0_4 (0 << 0) -#define FILNUM_FILNUM0_8 (1 << 0) -#define FILNUM_FILNUM0_12 (2 << 0) -#define FILNUM_FILNUM0_16 (3 << 0) -#define FILNUM_FILNUM1_4 (0 << 8) -#define FILNUM_FILNUM1_8 (1 << 8) -#define FILNUM_FILNUM1_12 (2 << 8) -#define FILNUM_FILNUM1_16 (3 << 8) -#define FILNUM_FILNUM2_4 (0 << 16) -#define FILNUM_FILNUM2_8 (1 << 16) -#define FILNUM_FILNUM2_12 (2 << 16) -#define FILNUM_FILNUM2_16 (3 << 16) -#define FILNUM_FILNUM3_4 (0 << 24) -#define FILNUM_FILNUM3_8 (1 << 24) -#define FILNUM_FILNUM3_12 (2 << 24) -#define FILNUM_FILNUM3_16 (3 << 24) -#define FILNUM_FILNUM4_4 (0 << 32) -#define FILNUM_FILNUM4_8 (1 << 32) -#define FILNUM_FILNUM4_12 (2 << 32) -#define FILNUM_FILNUM4_16 (3 << 32) -#define FILNUM_FILNUM5_4 (0 << 40) -#define FILNUM_FILNUM5_8 (1 << 40) -#define FILNUM_FILNUM5_12 (2 << 40) -#define FILNUM_FILNUM5_16 (3 << 40) -#define FILNUM_FILNUM6_4 (0 << 48) -#define FILNUM_FILNUM6_8 (1 << 48) -#define FILNUM_FILNUM6_12 (2 << 48) -#define FILNUM_FILNUM6_16 (3 << 48) -#define FILNUM_FILNUM7_4 (0 << 56) -#define FILNUM_FILNUM7_8 (1 << 56) -#define FILNUM_FILNUM7_12 (2 << 56) -#define FILNUM_FILNUM7_16 (3 << 56) -/* Digital noise filter (FILCLKSEL) register */ -#define FILCLKSEL_FILCLK0_0 (0 << 0) -#define FILCLKSEL_FILCLK0_1 (1 << 0) -#define FILCLKSEL_FILCLK0_2 (2 << 0) -#define FILCLKSEL_FILCLK0_3 (3 << 0) -#define FILCLKSEL_FILCLK1_0 (0 << 8) -#define FILCLKSEL_FILCLK1_1 (1 << 8) -#define FILCLKSEL_FILCLK1_2 (2 << 8) -#define FILCLKSEL_FILCLK1_3 (3 << 8) -#define FILCLKSEL_FILCLK2_0 (0 << 16) -#define FILCLKSEL_FILCLK2_1 (1 << 16) -#define FILCLKSEL_FILCLK2_2 (2 << 16) -#define FILCLKSEL_FILCLK2_3 (3 << 16) -#define FILCLKSEL_FILCLK3_0 (0 << 24) -#define FILCLKSEL_FILCLK3_1 (1 << 24) -#define FILCLKSEL_FILCLK3_2 (2 << 24) -#define FILCLKSEL_FILCLK3_3 (3 << 24) -#define FILCLKSEL_FILCLK4_0 (0 << 32) -#define FILCLKSEL_FILCLK4_1 (1 << 32) -#define FILCLKSEL_FILCLK4_2 (2 << 32) -#define FILCLKSEL_FILCLK4_3 (3 << 32) -#define FILCLKSEL_FILCLK5_0 (0 << 40) -#define FILCLKSEL_FILCLK5_1 (1 << 40) -#define FILCLKSEL_FILCLK5_2 (2 << 40) -#define FILCLKSEL_FILCLK5_3 (3 << 40) -#define FILCLKSEL_FILCLK6_0 (0 << 48) -#define FILCLKSEL_FILCLK6_1 (1 << 48) -#define FILCLKSEL_FILCLK6_2 (2 << 48) -#define FILCLKSEL_FILCLK6_3 (3 << 48) -#define FILCLKSEL_FILCLK7_0 (0 << 56) -#define FILCLKSEL_FILCLK7_1 (1 << 56) -#define FILCLKSEL_FILCLK7_2 (2 << 56) -#define FILCLKSEL_FILCLK7_3 (3 << 56) -/* Register for setting the mode of ETH MII / RGMII */ -#define ETH_MII_0_MII (1 << 0) -#define ETH_MII_1_MII (1 << 1) - -#define PFC_SET_TBL_NUM (11) -#define PFC_OFF (0) -#define PFC_ON (1) - -#define PFC_MUX_TBL_NUM (4) -#define PFC_QSPI_TBL_NUM (3) -#define PFC_SD_TBL_NUM (4) - -typedef struct { - int flg; - uintptr_t reg; - uint8_t val; -} PFC_REG_UINT8; - -typedef struct { - int flg; - uintptr_t reg; - uint32_t val; -} PFC_REG_UINT32; - -typedef struct { - int flg; - uintptr_t reg; - uint64_t val; -} PFC_REG_UINT64; - - -typedef struct { - PFC_REG_UINT8 pmc; - PFC_REG_UINT32 pfc; - PFC_REG_UINT64 iolh; - PFC_REG_UINT64 pupd; - PFC_REG_UINT64 sr; - PFC_REG_UINT64 ien; -} PFC_REGS; - - -#endif /* __PFC_REGS_H__ */ diff --git a/plat/renesas/rza/common/include/rz_private.h b/plat/renesas/rza/common/include/rz_private.h index 5866b6bae2..903181bbc8 100644 --- a/plat/renesas/rza/common/include/rz_private.h +++ b/plat/renesas/rza/common/include/rz_private.h @@ -9,18 +9,11 @@ #include -/* plat_gic.c */ -void plat_gic_driver_init(void); -void plat_gic_init(void); -void plat_gic_cpuif_enable(void); -void plat_gic_cpuif_disable(void); -void plat_gic_pcpu_init(void); - /* plat_security.c */ void plat_tzc400_setup(uintptr_t tzc_base); /* plat_storage.c */ -void rz_io_setup(void); +void plat_rza_io_setup(void); /* plat_image_load.c */ #if (APPLOAD == RZ_NOFIP) diff --git a/plat/renesas/rza/common/include/rza_mmu.h b/plat/renesas/rza/common/include/rza_mmu.h deleted file mode 100644 index a7528ab4da..0000000000 --- a/plat/renesas/rza/common/include/rza_mmu.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2022-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _RZA_MMU_H_ -#define _RZA_MMU_H_ - -#include "platform_def.h" - -/*********************************************************************************************************************** - * Includes - **********************************************************************************************************************/ - -/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ - -/*********************************************************************************************************************** - * Macro definitions - **********************************************************************************************************************/ - -/* descripter bits define */ -#define RZA_MMU_DESC_XN (1 << 54) -#define RZA_MMU_DESC_PXN (1 << 53) -#define RZA_MMU_DESC_AF (1 << 10) -#define RZA_MMU_DESC_SH_NS (0 << 8) -#define RZA_MMU_DESC_SH_OS (2 << 8) -#define RZA_MMU_DESC_SH_IS (3 << 8) -#define RZA_MMU_DESC_AP_RW_NONE (0 << 6) -#define RZA_MMU_DESC_AP_RW_RW (1 << 6) -#define RZA_MMU_DESC_AP_RO_NONE (2 << 6) -#define RZA_MMU_DESC_AP_RO_RO (3 << 6) -#define RZA_MMU_DESC_NS (1 << 5) - -/* descripter index for MAIR register */ -#define RZA_MMU_DESC_MAIR_INDEX_0 (0 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_1 (1 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_2 (2 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_3 (3 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_4 (4 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_5 (5 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_6 (6 << 2) -#define RZA_MMU_DESC_MAIR_INDEX_7 (7 << 2) - -/* index number each memory type - * 0: normal memory, cacheable - * 1: device - * 2: normal memory, non-cacheable - */ -#define RZA_MMU_ATTR_NON_CACHEABLE_INDEX (2) -#define RZA_MMU_ATTR_DEVICE_INDEX (1) -#define RZA_MMU_ATTR_IWBWA_OWBWA_NTR_INDEX (0) - -/* Normal Memory, Outer/Inner Non-cacheable */ -#define RZA_MMU_ATTR_NON_CACHEABLE \ - MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) -/* Device */ -#define RZA_MMU_ATTR_DEVICE MAIR_DEV_nGnRE -/* Normal Memory, Outer/Inner Write-Back */ -#define RZA_MMU_ATTR_IWBWA_OWBWA_NTR \ - MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA) - -#define RZA_MMU_ATTR_FIELD_WIDTH (8) -#define RZA_MMU_MAIR_ATTR_SET(attr, index) \ - ((attr) << ((index) * RZA_MMU_ATTR_FIELD_WIDTH)) - -#define RZA_MMU_ATTR_NEXT_TBL (0x03) - -/* descripter entry type */ -#define RZA_MMU_DESC_TABLE_DESC (3 << 0) -#define RZA_MMU_DESC_BLOCK_ENTRY_L12 (1 << 0) -#define RZA_MMU_DESC_BLOCK_ENTRY_L3 (3 << 0) - -/* max address */ -#define RZA_MMU_PHY_ADDR_MAX (PLAT_PHY_ADDR_SPACE_SIZE - 1) -#define RZA_MMU_VIRT_ADDR_MAX (PLAT_VIRT_ADDR_SPACE_SIZE - 1) -#define RZA_MMU_PHY_SIZE_MAX (PLAT_PHY_ADDR_SPACE_SIZE) -#define RZA_MMU_VIRT_SIZE_MAX (PLAT_VIRT_ADDR_SPACE_SIZE) - -/* exception evel */ -#define RZA_MMU_CURRENT_EL0 (0x00) -#define RZA_MMU_CURRENT_EL1 (0x04) -#define RZA_MMU_CURRENT_EL2 (0x08) -#define RZA_MMU_CURRENT_EL3 (0x0C) - -/* Virtual space size per entry each level */ -#define RZA_MMU_L1_ENTRY_SIZE (0x40000000) /* 1GB */ -#define RZA_MMU_L2_ENTRY_SIZE (0x00200000) /* 2MB */ -#define RZA_MMU_L3_ENTRY_SIZE (0x00001000) /* 4KB */ - -/* descripter size (byte) */ -#define RZA_MMU_TABLE_DESC_SIZE (8) - -/* start virtual address each blocks */ -#define RZA_MMU_N1_TABLE_START_VADDR (0x00000000) -#define RZA_MMU_N2_TABLE_START_VADDR (0x40000000) -#define RZA_MMU_N3_TABLE_START_VADDR (0x80000000) -#define RZA_MMU_N4_TABLE_START_VADDR (0xC0000000) - -/* width of virtual space each blocks */ -#define RZA_MMU_TTB_BLOCK_WIDTH (0x40000000) - -#define RZA_MMU_LEVEL2_TABLE_INDEX_MAX (4) -#define RZA_MMU_TABLE_ENTRY (512) - -/* MMU attribute setting (user setting) */ -#define RZA_MMU_ATTRIBUTE_NORMAL_CACHEABLE \ - (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ - RZA_MMU_DESC_MAIR_INDEX_0) -#define RZA_MMU_ATTRIBUTE_NORMAL_UNCACHE \ - (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ - RZA_MMU_DESC_MAIR_INDEX_2) -#define RZA_MMU_ATTRIBUTE_DEVICE \ - (RZA_MMU_DESC_AF | RZA_MMU_DESC_SH_IS | RZA_MMU_DESC_AP_RW_RW | \ - RZA_MMU_DESC_MAIR_INDEX_1) -#define RZA_MMU_ATTRIBUTE_ACCESS_FAULT (0x00000000) -#define RZA_MMU_ATTRIBUTE_CONFIG_END (0xFFFFFFFF) - -/* xSPI device extended configuration structure */ -typedef struct mmu_pagetable_config { - uint64_t vaddress; - uint64_t paddress; - uint64_t size; - uint64_t attribute; -} rza_mmu_pgtbl_cfg_t; - -/* external functions */ -int plat_mmu_init(const rza_mmu_pgtbl_cfg_t *config_table); -void plat_mmu_enable(void); - -#endif /* _RZA_MMU_H_ */ diff --git a/plat/renesas/rza/common/plat_gic.c b/plat/renesas/rza/common/plat_gic.c deleted file mode 100644 index 0f8c743bb5..0000000000 --- a/plat/renesas/rza/common/plat_gic.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include -#include -#include - -uintptr_t plat_rdistif_base_addrs[PLATFORM_CORE_COUNT]; - -static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr) -{ - mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); - return (unsigned int)plat_core_pos_by_mpidr(mpidr); -} - -const gicv3_driver_data_t rza_gic_data = { - .gicd_base = PLAT_GICD_BASE, - .gicr_base = PLAT_GICR_BASE, - .rdistif_num = PLATFORM_CORE_COUNT, - .rdistif_base_addrs = plat_rdistif_base_addrs, - .mpidr_to_core_pos = plat_mpidr_to_core_pos, -}; - -void plat_gic_driver_init(void) -{ - gicv3_driver_init(&rza_gic_data); -} - -void plat_gic_init(void) -{ - gicv3_distif_init(); - gicv3_rdistif_init(plat_my_core_pos()); - gicv3_cpuif_enable(plat_my_core_pos()); -} - -void plat_gic_cpuif_enable(void) -{ - gicv3_cpuif_enable(plat_my_core_pos()); -} - -void plat_gic_cpuif_disable(void) -{ - gicv3_cpuif_disable(plat_my_core_pos()); -} - -void plat_gic_pcpu_init(void) -{ - gicv3_rdistif_init(plat_my_core_pos()); -} diff --git a/plat/renesas/rza/common/plat_image_load.c b/plat/renesas/rza/common/plat_image_load.c index e10416226d..f09fca9f38 100644 --- a/plat/renesas/rza/common/plat_image_load.c +++ b/plat/renesas/rza/common/plat_image_load.c @@ -55,14 +55,14 @@ int rz_check_fsp_header(fsp_app_header_t *header) ERROR("The value of the entry point address does not match its inverted value\n"); } - if (0 == ret) { + if (ret == 0) { if (~(header->dest_addr) != header->dest_addr_inv) { ret = -1; - ERROR("The address to copy application image does not match its inverted value\n"); + ERROR("The destination address does not match its inverted value\n"); } } - if (0 == ret) { + if (ret == 0) { if (~(header->payload_size) != header->payload_size_inv) { ret = -1; ERROR("The size of application image does not match its inverted value\n"); @@ -70,28 +70,25 @@ int rz_check_fsp_header(fsp_app_header_t *header) } if ((FSP_BASE + RZ_APP_PAYLOAD_OFFSET) != header->dest_addr) { - if (0 == ret) { + if (ret == 0) { if ((header->dest_addr < PLAT_SRAM_BASE) || ((header->dest_addr + header->payload_size) > - (PLAT_SRAM_BASE + PLAT_SRAM_SIZE))) { + (PLAT_SRAM_BASE + PLAT_SRAM_SIZE))) { if ((header->dest_addr < PLAT_SPIROM_BASE) || ((header->dest_addr + header->payload_size) > - (PLAT_SPIROM_BASE + PLAT_SPIROM_SIZE))) { - if ((header->dest_addr < - PLAT_DDR1_BASE) || - ((header->dest_addr + - header->payload_size) > - (PLAT_DDR1_BASE + PLAT_DDR1_SIZE + - PLAT_DDR2_SIZE))) { + (PLAT_SPIROM_BASE + PLAT_SPIROM_SIZE))) { + if ((header->dest_addr < PLAT_DDR_BASE) || + ((header->dest_addr + header->payload_size) > + (PLAT_DDR_BASE + PLAT_DDR_SIZE))) { ret = -1; - ERROR("The application image to copy does not fit in memory\n"); + ERROR("The image to copy does not fit in memory\n"); } } } } } - if (0 == ret) { + if (ret == 0) { RZA_PRINTF_VERBOSE("Success!\n"); } @@ -123,7 +120,7 @@ void rza_load_fsp(void) ret = rz_check_fsp_header(header); - if (0 == ret) { + if (ret == 0) { if ((FSP_BASE + RZ_APP_PAYLOAD_OFFSET) != header->dest_addr) { rz_xspi_read((void *)header->dest_addr, RZ_APP_PAYLOAD_OFFSET + FSP_FROM_XSPI_BASE, @@ -153,7 +150,7 @@ void rza_print_descs(void) RZA_PRINTF_VERBOSE("Copy Data Size: %dbyte\n", bl2_params->head->image_info->image_max_size); RZA_PRINTF_VERBOSE("SPSR_EL3 settings:\n"); - if (MODE_RW_64 == GET_RW(bl2_params->head->ep_info->spsr)) { + if (GET_RW(bl2_params->head->ep_info->spsr) == MODE_RW_64) { RZA_PRINTF_VERBOSE("AArch64 execution state\n"); } else { RZA_PRINTF_VERBOSE("AArch32 execution state\n"); @@ -181,7 +178,7 @@ void rza_print_descs(void) RZA_PRINTF_VERBOSE("EL and stack pointer: "); RZA_PRINTF_VERBOSE("EL%d", GET_EL(bl2_params->head->ep_info->spsr)); - if (MODE_SP_EL0 == GET_SP(bl2_params->head->ep_info->spsr)) { + if (GET_SP(bl2_params->head->ep_info->spsr) == MODE_SP_EL0) { RZA_PRINTF_VERBOSE("t\n"); } else { RZA_PRINTF_VERBOSE("h\n"); diff --git a/plat/renesas/rza/common/plat_pm.c b/plat/renesas/rza/common/plat_pm.c deleted file mode 100644 index fe94299b11..0000000000 --- a/plat/renesas/rza/common/plat_pm.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include -#include -#include -#include - -uintptr_t gp_warm_ep; - -static int rza_pwr_domain_on(u_register_t mpidr) -{ - const uint32_t rval[2][2] = { - { SYS_CA55_CFG_RVAL0, SYS_CA55_CFG_RVAH0 }, - { SYS_CA55_CFG_RVAL1, SYS_CA55_CFG_RVAH1 } - }; - const uint32_t pch[2][2] = { { CPG_CORE0_PCHCTL, CPG_CORE0_PCHMON }, - { CPG_CORE1_PCHCTL, CPG_CORE1_PCHMON } }; - uint8_t coreid = MPIDR_AFFLVL1_VAL(mpidr); - - if (coreid > 1) - return PSCI_E_INVALID_PARAMS; - - mmio_write_32(rval[coreid][0], (uint32_t)(gp_warm_ep & 0xFFFFFFFC)); - mmio_write_32(rval[coreid][1], (uint32_t)((gp_warm_ep >> 32) & 0xFF)); - - /* Assert PORESET */ - mmio_write_32(CPG_RST_CA55, (0x00010000 << coreid)); - while ((mmio_read_32(CPG_RSTMON_CA55) & (0x1 << coreid)) == 0x0) - ; - - /* Deassert PORESET */ - mmio_write_32(CPG_RST_CA55, (0x00050005 << coreid)); - while ((mmio_read_32(CPG_RSTMON_CA55) & (0x1 << coreid)) != 0x0) - ; - - mmio_write_32(pch[coreid][0], 0x00080001); - while ((mmio_read_32(pch[coreid][1]) & 0x1) != 0x1) - ; - mmio_write_32(pch[coreid][0], 0x00080000); - while ((mmio_read_32(pch[coreid][1]) & 0x1) != 0x0) - ; - - return PSCI_E_SUCCESS; -} - -static void rza_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ -#if !DEBUG_PLAT_FPGA - plat_gic_pcpu_init(); - plat_gic_cpuif_enable(); -#endif -} - -const plat_psci_ops_t rza_plat_psci_ops = { - .pwr_domain_on = rza_pwr_domain_on, - .pwr_domain_on_finish = rza_pwr_domain_on_finish, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - gp_warm_ep = sec_entrypoint; - *psci_ops = &rza_plat_psci_ops; - - return 0; -} diff --git a/plat/renesas/rza/common/plat_rz_common.c b/plat/renesas/rza/common/plat_rz_common.c index 110655d96f..0adfd1dc49 100644 --- a/plat/renesas/rza/common/plat_rz_common.c +++ b/plat/renesas/rza/common/plat_rz_common.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include unsigned int plat_get_syscnt_freq2(void) { diff --git a/plat/renesas/rza/common/plat_security.c b/plat/renesas/rza/common/plat_security.c index fa138877f7..bfa51c12e0 100644 --- a/plat/renesas/rza/common/plat_security.c +++ b/plat/renesas/rza/common/plat_security.c @@ -6,12 +6,12 @@ #include #include +#include #include #include "plat_tzc_def.h" #include "platform_def.h" #include "rza_printf.h" -#include "sys_regs.h" typedef struct arm_tzc_regions_info { unsigned long long base; diff --git a/plat/renesas/rza/common/plat_storage.c b/plat/renesas/rza/common/plat_storage.c index 2889b8d0e0..c2b0b57b97 100644 --- a/plat/renesas/rza/common/plat_storage.c +++ b/plat/renesas/rza/common/plat_storage.c @@ -13,18 +13,14 @@ #include #include #include -#include +#include #include #include #include -#include #include -#include static uintptr_t memdrv_dev_handle; static uintptr_t fip_dev_handle; -static uintptr_t emmcdrv_dev_handle; - static uintptr_t boot_io_drv_id; static const io_block_spec_t spirom_block_spec = { @@ -32,11 +28,6 @@ static const io_block_spec_t spirom_block_spec = { .length = PLAT_SPIROM_FIP_SIZE, }; -static const io_drv_spec_t emmc_block_spec = { - .offset = PLAT_EMMC_FIP_BASE, - .length = PLAT_EMMC_FIP_SIZE, -}; - static const io_uuid_spec_t bl31_file_spec = { .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, }; @@ -49,33 +40,6 @@ static const io_uuid_spec_t bl33_file_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t soc_fw_key_cert_file_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_content_cert_file_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_file_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_content_cert_file_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_file_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_content_cert_file_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif - -static int32_t open_emmcdrv(const uintptr_t spec); static int32_t open_memmap(const uintptr_t spec); static int32_t open_fipdrv(const uintptr_t spec); @@ -85,8 +49,6 @@ struct plat_io_policy { int32_t (*check)(const uintptr_t spec); }; -static const struct plat_io_policy *policies; - static const struct plat_io_policy spirom_policies[] = { [FIP_IMAGE_ID] = { &memdrv_dev_handle, (uintptr_t)&spirom_block_spec, &open_memmap }, @@ -96,59 +58,6 @@ static const struct plat_io_policy spirom_policies[] = { &open_fipdrv }, [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_file_spec, &open_fipdrv }, -#if TRUSTED_BOARD_BOOT - [SOC_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_file_spec, - &open_fipdrv }, - [SOC_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&soc_fw_content_cert_file_spec, - &open_fipdrv }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_file_spec, - &open_fipdrv }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&tos_fw_content_cert_file_spec, - &open_fipdrv }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_file_spec, - &open_fipdrv }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&nt_fw_content_cert_file_spec, - &open_fipdrv }, -#endif - { 0, 0, 0 } -}; - -static const struct plat_io_policy emmc_policies[] = { - [FIP_IMAGE_ID] = { &emmcdrv_dev_handle, (uintptr_t)&emmc_block_spec, - &open_emmcdrv }, - [BL31_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl31_file_spec, - &open_fipdrv }, - [BL32_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl32_file_spec, - &open_fipdrv }, - [BL33_IMAGE_ID] = { &fip_dev_handle, (uintptr_t)&bl33_file_spec, - &open_fipdrv }, -#if TRUSTED_BOARD_BOOT - [SOC_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_file_spec, - &open_fipdrv }, - [SOC_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&soc_fw_content_cert_file_spec, - &open_fipdrv }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_file_spec, - &open_fipdrv }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&tos_fw_content_cert_file_spec, - &open_fipdrv }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_file_spec, - &open_fipdrv }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&nt_fw_content_cert_file_spec, - &open_fipdrv }, -#endif - { 0, 0, 0 } }; static int32_t open_fipdrv(const uintptr_t spec) @@ -156,8 +65,6 @@ static int32_t open_fipdrv(const uintptr_t spec) int32_t result; result = io_dev_init(fip_dev_handle, boot_io_drv_id); - if (result != 0) - return result; return result; } @@ -178,55 +85,26 @@ static int32_t open_memmap(const uintptr_t spec) return result; } -static int32_t open_emmcdrv(const uintptr_t spec) -{ - return io_dev_init(emmcdrv_dev_handle, 0); -} - -void rz_io_setup(void) +void plat_rza_io_setup(void) { - const io_dev_connector_t *memmap; - const io_dev_connector_t *emmc; - const io_dev_connector_t *rza; - uint16_t boot_dev; + static const io_dev_connector_t *fip_dev_con; + static const io_dev_connector_t *memmap_dev_con; - boot_dev = *((uint16_t *)PLAT_BOOTINFO_BASE) & MASK_BOOTM_DEVICE; + int result __unused; boot_io_drv_id = FIP_IMAGE_ID; - xspi_setup(); - - register_io_dev_fip(&rza); - - io_dev_open(rza, 0, &fip_dev_handle); - - if ((boot_dev == BOOT_MODE_SPI_1_8) || - (boot_dev == BOOT_MODE_SPI_3_3) || - (boot_dev == BOOT_MODE_NAND_SPI_1_8) || - (boot_dev == BOOT_MODE_NAND_SPI_3_3)) { - register_io_dev_memmap(&memmap); - io_dev_open(memmap, 0, &memdrv_dev_handle); - - policies = &spirom_policies[0]; - } else if (USE_EMMC && (boot_dev == BOOT_MODE_EMMC_1_8 || - boot_dev == BOOT_MODE_EMMC_3_3)) { - if (emmc_init() != EMMC_SUCCESS) { - NOTICE("BL2: Failed to eMMC driver initialize.\n"); - panic(); - } - emmc_memcard_power(EMMC_POWER_ON); - if (emmc_mount() != EMMC_SUCCESS) { - NOTICE("BL2: Failed to eMMC mount operation.\n"); - panic(); - } - - register_io_dev_emmcdrv(&emmc); - io_dev_open(emmc, 0, &emmcdrv_dev_handle); - - policies = &emmc_policies[0]; - } else { - panic(); - } + result = register_io_dev_fip(&fip_dev_con); + assert(result == 0); + + result = io_dev_open(fip_dev_con, 0, &fip_dev_handle); + assert(result == 0); + + result = register_io_dev_memmap(&memmap_dev_con); + assert(result == 0); + + result = io_dev_open(memmap_dev_con, 0, &memdrv_dev_handle); + assert(result == 0); } int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, @@ -235,7 +113,7 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, const struct plat_io_policy *policy; int result; - policy = &policies[image_id]; + policy = &spirom_policies[image_id]; result = policy->check(policy->image_spec); if (result != 0) diff --git a/plat/renesas/rza/common/rz_common.mk b/plat/renesas/rza/common/rz_common.mk index 3031ae9829..3327877198 100644 --- a/plat/renesas/rza/common/rz_common.mk +++ b/plat/renesas/rza/common/rz_common.mk @@ -13,22 +13,16 @@ HW_ASSISTED_COHERENCY := 1 USE_COHERENT_MEM := 0 TRUSTED_BOARD_BOOT := 0 PROTECTED_CHIPID := 1 -DEBUG_PLAT_FPGA := 0 EARLY_CONSOLE := 1 $(eval $(call add_define,PROTECTED_CHIPID)) -$(eval $(call add_define,DEBUG_PLAT_FPGA)) WA_PLAT_GIC64BIT := 1 $(eval $(call add_define,WA_PLAT_GIC64BIT)) -ifeq (${DEBUG_PLAT_FPGA}, 0) - USE_SDRAM ?= 1 -else - USE_SDRAM ?= 0 -endif +USE_SDRAM ?= 1 $(eval $(call add_define,USE_SDRAM)) -USE_EMMC ?= 0 +USE_EMMC ?= 0 $(eval $(call add_define,USE_EMMC)) # Enable workarounds for selected Cortex-A55 erratas. @@ -39,20 +33,14 @@ FSP_BASE ?= 0x20020000 $(eval $(call add_define,FSP_BASE)) endif -PLAT_INCLUDES := -Iplat/renesas/rza/common/include \ - -Iplat/renesas/rza/common/drivers/emmc \ - -Iplat/renesas/rza/common/drivers/io \ +PLAT_INCLUDES += -Iplat/renesas/rza/common/include \ -Idrivers/renesas/common/io RZ_TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \ drivers/delay_timer/delay_timer.c ifneq (${USE_SDRAM}, 0) -DDR_SOURCES := plat/renesas/rza/common/drivers/ddr/ddr.c -endif - -ifneq (${ARCH_TYPE}, 0) -MMU_SOURCE := plat/renesas/rza/common/drivers/rza_mmu/ARMv8A/rza_mmu.c +DDR_SOURCES := drivers/renesas/rza/ddr/ddr.c endif BL2_SOURCES += lib/cpus/aarch64/cortex_a55.S \ @@ -63,13 +51,9 @@ BL2_SOURCES += lib/cpus/aarch64/cortex_a55.S \ drivers/io/io_memmap.c \ drivers/io/io_fip.c \ drivers/arm/tzc/tzc400.c \ - plat/renesas/rza/common/drivers/io/io_emmcdrv.c \ - plat/renesas/rza/common/drivers/emmc/emmc_interrupt.c \ - plat/renesas/rza/common/drivers/emmc/emmc_utility.c \ - plat/renesas/rza/common/drivers/emmc/emmc_mount.c \ - plat/renesas/rza/common/drivers/emmc/emmc_init.c \ - plat/renesas/rza/common/drivers/emmc/emmc_read.c \ - plat/renesas/rza/common/drivers/emmc/emmc_cmd.c \ + drivers/renesas/common/syc/syc.c \ + drivers/renesas/rza/pfc/pfc.c \ + drivers/renesas/rza/cpg/cpg.c \ plat/renesas/rza/common/bl2_plat_setup.c \ plat/renesas/rza/common/bl2_plat_mem_params_desc.c \ plat/renesas/rza/common/plat_image_load.c \ @@ -77,21 +61,14 @@ BL2_SOURCES += lib/cpus/aarch64/cortex_a55.S \ plat/renesas/rza/common/plat_storage.c \ plat/renesas/rza/common/plat_security.c \ plat/renesas/rza/common/aarch64/plat_helpers.S \ - plat/renesas/rza/common/drivers/syc.c \ - plat/renesas/rza/common/drivers/pfc.c \ - plat/renesas/rza/common/drivers/cpg.c \ ${DDR_SOURCES} \ ${XSPI_SOURCES} \ ${MMU_SOURCE} -# Include GICv3 driver files -GICV3_IMPL := GIC600 -include drivers/arm/gic/v3/gicv3.mk - include lib/xlat_tables_v2/xlat_tables.mk PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \ - plat/renesas/rza/common/plat_rz_common.c \ - plat/renesas/rza/common/drivers/scifa.S + drivers/renesas/common/scifa/scifa.S \ + plat/renesas/rza/common/plat_rz_common.c ifneq (${TRUSTED_BOARD_BOOT},0) # Include common TBB sources @@ -99,14 +76,14 @@ AUTH_SOURCES := drivers/auth/img_parser_mod.c # Include the selected chain of trust sources. ifeq (${COT},tbbr) -AUTH_SOURCES += plat/renesas/rza/common/drivers/auth/tbbr/tbbr_cot.c +AUTH_SOURCES += drivers/renesas/rza/auth/tbbr/tbbr_cot.c else $(error Unknown chain of trust ${COT}) endif # Include RZ TBB sources -AUTH_SOURCES += plat/renesas/rza/common/drivers/auth/auth_mod.c \ - plat/renesas/rza/common/drivers/auth/sblib/crypto_sblib.c \ - plat/renesas/rza/common/drivers/auth/sblib/sblib_parser.c +AUTH_SOURCES += drivers/renesas/rza/auth/auth_mod.c \ + drivers/renesas/rza/auth/sblib/crypto_sblib.c \ + drivers/renesas/rza/auth/sblib/sblib_parser.c BL2_SOURCES += ${AUTH_SOURCES} endif diff --git a/plat/renesas/rza/common/rz_plat_sip_handler.c b/plat/renesas/rza/common/rz_plat_sip_handler.c index 3df7bd40bf..a866899bcd 100644 --- a/plat/renesas/rza/common/rz_plat_sip_handler.c +++ b/plat/renesas/rza/common/rz_plat_sip_handler.c @@ -21,6 +21,7 @@ static uintptr_t rz_otp_handler_devid(void *handle, u_register_t x1) { uint32_t devid = mmio_read_32(RZ_OTP_BASE_DEVID); + SMC_RET1(handle, devid); } @@ -31,6 +32,7 @@ static uintptr_t rz_otp_handler_chipid(void *handle, u_register_t x1, #if (PROTECTED_CHIPID == 1) uint32_t ns = is_caller_non_secure(flags); + if (ns) { WARN("%s: Unauthorized service call from non-secure\n", __func__); diff --git a/plat/renesas/rza/common/rz_xspi_common.mk b/plat/renesas/rza/common/rz_xspi_common.mk index db1831428d..4b53143712 100644 --- a/plat/renesas/rza/common/rz_xspi_common.mk +++ b/plat/renesas/rza/common/rz_xspi_common.mk @@ -24,7 +24,7 @@ endef define RZ_XSPI_INCLUDE_MAKEFILE $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(call RZ_XSPI_ADD_IFDRIVER,$(RZ_$(1)_IF))) - $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(eval include plat/renesas/rza/common/drivers/xspidevice/$($(1)_DEVICE)/rz_xspidevice.mk)) + $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(eval include drivers/renesas/rza/xspidevice/$($(1)_DEVICE)/rz_xspidevice.mk)) $(if $(filter-out __,_$(strip $($(1)_DEVICE))_),$(eval RZ_USE_XSPI:=1)) endef @@ -63,5 +63,5 @@ $(RZ_XSPI_ENV): $(RZ_BUILD_PLAT_TMP) $(call RZ_ADD_ENV,BOARD) $(RZ_XSPI_DEF): $(RZ_XSPI_ENV) - $(Q)$(SHELL) plat/renesas/rza/common/rz_bl2_xspi_config.sh "$(RZ_XSPI_ENV)" "$(RZ_XSPI_DEF)" + $(Q)$(SHELL) tools/renesas/rza/rz_bl2_xspi_config.sh "$(RZ_XSPI_ENV)" "$(RZ_XSPI_DEF)" endif diff --git a/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c b/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c index 1489876d24..8bed0a23eb 100644 --- a/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c +++ b/plat/renesas/rza/soc/a3m/drivers/ddr/ddr_a3m.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include void ddr_ctrl_reten_en_n(uint8_t val) { diff --git a/plat/renesas/rza/soc/a3m/include/cpg_opt.h b/plat/renesas/rza/soc/a3m/include/cpg_opt.h deleted file mode 100644 index 4d04dd455f..0000000000 --- a/plat/renesas/rza/soc/a3m/include/cpg_opt.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __CPG_OPT_H__ -#define __CPG_OPT_H__ - -#define CPG_RST_DDR_OPT_VALUE (0x00000000) - -#endif // __CPG_OPT_H__ diff --git a/plat/renesas/rza/soc/a3m/include/platform_def.h b/plat/renesas/rza/soc/a3m/include/platform_def.h index 9918dbe90e..491f9e3a84 100644 --- a/plat/renesas/rza/soc/a3m/include/platform_def.h +++ b/plat/renesas/rza/soc/a3m/include/platform_def.h @@ -27,7 +27,7 @@ #define PLATFORM_SYSTEM_COUNT U(1) #define PLATFORM_CLUSTER_COUNT U(1) -#define PLATFORM_CORE_COUNT U(2) +#define PLATFORM_CORE_COUNT U(1) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ @@ -90,8 +90,8 @@ #define MAX_MMAP_REGIONS U(9) #endif -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 34) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 34) /******************************************************************************* * Determining the use of FIP format diff --git a/plat/renesas/rza/soc/a3m/include/rza3m_def.h b/plat/renesas/rza/soc/a3m/include/rza3m_def.h index 1f841a0938..d7cb60028f 100644 --- a/plat/renesas/rza/soc/a3m/include/rza3m_def.h +++ b/plat/renesas/rza/soc/a3m/include/rza3m_def.h @@ -28,9 +28,7 @@ #define PLAT_GIC_BASE (0x11900000) #define PLAT_SD0_BASE (0x11C00000) #define PLAT_SPIROM_BASE (0x20000000) -#define PLAT_DDR1_BASE (0x40000000) -#define PLAT_DDR2_BASE (0x80000000) -#define PLAT_DDR3_BASE (0x100000000) +#define PLAT_DDR_BASE (0x40000000) #define PLAT_GICD_BASE (PLAT_GIC_BASE) #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) @@ -43,8 +41,7 @@ #define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) #define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) #define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) -#define PLAT_DDR1_SIZE (PLAT_DDR2_BASE - PLAT_DDR1_BASE) -#define PLAT_DDR2_SIZE (PLAT_DDR3_BASE - PLAT_DDR2_BASE) +#define PLAT_DDR_SIZE (0x8000000UL) #define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) #define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) diff --git a/plat/renesas/rza/soc/a3m/rz_xspi.mk b/plat/renesas/rza/soc/a3m/rz_xspi.mk index 3b508d6dd7..28a9d40d2f 100644 --- a/plat/renesas/rza/soc/a3m/rz_xspi.mk +++ b/plat/renesas/rza/soc/a3m/rz_xspi.mk @@ -3,10 +3,11 @@ # # SPDX-License-Identifier: BSD-3-Clause # -RZ_XSPI_DRIVER_PATH := plat/renesas/rza/common/drivers/xspi + +RZ_XSPI_DRIVER_PATH := drivers/renesas/rza/xspi RZ_XSPI_CONFIGS := XSPI0 XSPI1 XSPI2 -RZ_XSPI_SOURCES := plat/renesas/rza/soc/a3m/drivers/xspi.c +RZ_XSPI_SOURCES := drivers/renesas/rza/xspi/xspi.c RZ_XSPI_HEADERS := RZ_XSPI0_IF := spim RZ_XSPI0_IF_CONFIG := .channel=0, .base=0x10060000 @@ -27,6 +28,10 @@ ifneq ($(strip $(XSPI0_DEVICE)),) endif endif +PLAT_INCLUDES += -Iinclude/drivers/renesas/rza/spim \ + -Iinclude/drivers/renesas/rza/octal \ + -Iinclude/drivers/renesas/rza/xspi + include plat/renesas/rza/common/rz_xspi_common.mk $(eval $(call add_define,RZ_XSPI_EXCLUSIVE_SELECTOR)) diff --git a/plat/renesas/rza/soc/a3m/soc.mk b/plat/renesas/rza/soc/a3m/soc.mk index b05effe092..11befec5e4 100644 --- a/plat/renesas/rza/soc/a3m/soc.mk +++ b/plat/renesas/rza/soc/a3m/soc.mk @@ -43,9 +43,9 @@ $(RZ_ELF): $(BL2_ELF) $(RZ_BIN): $(BL2_BIN) @echo " IMG $@" ifeq ($(NAND),1) - $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3m/rz_image_nand.pl "$<" "$@" + $(Q)/usr/bin/perl ./tools/renesas/rza/a3m/rz_image_nand.pl "$<" "$@" else - $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3m/rz_image.pl "$<" "$@" + $(Q)/usr/bin/perl ./tools/renesas/rza/a3m/rz_image.pl "$<" "$@" endif $(BL2_MAP): $(BL2_ELF) diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c index 1489876d24..8bed0a23eb 100644 --- a/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c +++ b/plat/renesas/rza/soc/a3ul/drivers/ddr/ddr_a3ul.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include +#include void ddr_ctrl_reten_en_n(uint8_t val) { diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c deleted file mode 100644 index 86cb986f83..0000000000 --- a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-010_D3-02-2.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -const char ddr_an_version[] = "v0.0.0"; - -const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { - { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, - { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, - { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, - { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, - { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, - { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, - { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, - { DENALI_CTL_14, 0x07120200 }, { DENALI_CTL_15, 0x00000000 }, - { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002100 }, - { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E09 }, - { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, - { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A09 }, - { DENALI_CTL_24, 0x09031301 }, { DENALI_CTL_25, 0x01000009 }, - { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, - { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, - { DENALI_CTL_30, 0x000000AE }, { DENALI_CTL_31, 0x00001448 }, - { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, - { DENALI_CTL_34, 0x00B40200 }, { DENALI_CTL_35, 0x000000B4 }, - { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, - { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, - { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, - { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, - { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, - { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, - { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, - { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, - { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, - { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, - { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, - { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, - { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, - { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, - { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, - { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, - { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A50 }, - { DENALI_CTL_70, 0x00000206 }, { DENALI_CTL_71, 0x00000210 }, - { DENALI_CTL_72, 0x00000A50 }, { DENALI_CTL_73, 0x00000206 }, - { DENALI_CTL_74, 0x00000210 }, { DENALI_CTL_75, 0x00000000 }, - { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, - { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, - { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, - { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, - { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, - { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, - { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, - { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, - { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, - { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, - { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, - { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, - { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, - { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, - { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, - { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, - { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, - { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, - { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, - { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, - { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, - { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, - { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, - { DENALI_CTL_122, 0x02010100 }, { DENALI_CTL_123, 0x00010102 }, - { DENALI_CTL_124, 0x07FF0000 }, { DENALI_CTL_125, 0x0000FF00 }, - { DENALI_CTL_126, 0x0FFF0800 }, { DENALI_CTL_127, 0x0100FF00 }, - { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, - { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, - { DENALI_CTL_132, 0x0C030000 }, { DENALI_CTL_133, 0x01000000 }, - { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, - { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, - { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, - { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, - { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, - { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, - { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, - { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, - { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, - { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, - { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, - { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, - { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, - { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, - { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, - { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, - { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, - { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, - { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, - { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, - { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, - { DENALI_CTL_176, 0x02020001 }, { DENALI_CTL_177, 0x01020101 }, - { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, - { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, - { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, - { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, - { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, - { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, - { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, - { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, - { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, - { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, - { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, - { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, - { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, - { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, - { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, - { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, - { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, - { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, - { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, - { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, - { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, - { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, - { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, - { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, - { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, - { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, - { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, - { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, - { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, - { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, - { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, - { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, - { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, - { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, - { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, - { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, - { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, - { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, - { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, - { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, - { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, - { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, - { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, - { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, - { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, - { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, - { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, - { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, - { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, - { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, - { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, - { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, - { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, - { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, - { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, - { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, - { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, - { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, - { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, - { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, - { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, - { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, - { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, - { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, - { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, - { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, - { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, - { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, - { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, - { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, - { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, - { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, - { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, - { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, - { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, - { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, - { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, - { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, - { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, - { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, - { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, - { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, - { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, - { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, - { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, - { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, - { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, - { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, - { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, - { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, - { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, - { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, - { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, - { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, - { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, - { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, - { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, - { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, - { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, - { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, - { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, - { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, - { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, - { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, - { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, - { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, - { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, - { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, - { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, - { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, - { DENALI_CTL_398, 0x01080205 }, { DENALI_CTL_399, 0x00200106 }, - { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000200 }, - { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, - { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, - { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, - { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, - { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, - { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, - { DENALI_CTL_414, 0x4F6C01E8 }, { DENALI_CTL_415, 0x00007822 }, - { DENALI_CTL_416, 0x1E1E3C22 }, { DENALI_CTL_417, 0x00000000 }, - { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, - { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, - { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, - { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, - { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, - { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, - { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, - { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, - { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } -}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c deleted file mode 100644 index 43dac1ea19..0000000000 --- a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-01-2.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const char ddr_an_version[] = "v3.0.0"; - -const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { - { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, - { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, - { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, - { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, - { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, - { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, - { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, - { DENALI_CTL_14, 0x07140200 }, { DENALI_CTL_15, 0x00000000 }, - { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002200 }, - { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E0A }, - { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, - { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A0A }, - { DENALI_CTL_24, 0x0A031401 }, { DENALI_CTL_25, 0x0100000A }, - { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, - { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, - { DENALI_CTL_30, 0x000000EA }, { DENALI_CTL_31, 0x00001448 }, - { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, - { DENALI_CTL_34, 0x00F00200 }, { DENALI_CTL_35, 0x000000F0 }, - { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, - { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, - { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, - { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, - { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, - { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, - { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, - { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, - { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, - { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, - { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, - { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, - { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, - { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, - { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, - { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, - { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A60 }, - { DENALI_CTL_70, 0x00000006 }, { DENALI_CTL_71, 0x00000010 }, - { DENALI_CTL_72, 0x00000A60 }, { DENALI_CTL_73, 0x00000006 }, - { DENALI_CTL_74, 0x00000010 }, { DENALI_CTL_75, 0x00000000 }, - { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, - { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, - { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, - { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, - { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, - { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, - { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, - { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, - { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, - { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, - { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, - { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, - { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, - { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, - { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, - { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, - { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, - { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, - { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, - { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, - { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, - { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, - { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, - { DENALI_CTL_122, 0x01010100 }, { DENALI_CTL_123, 0x00010101 }, - { DENALI_CTL_124, 0x0FFF0000 }, { DENALI_CTL_125, 0x0001FF00 }, - { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, - { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, - { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, - { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, - { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, - { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, - { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, - { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, - { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, - { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, - { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, - { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, - { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, - { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, - { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, - { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, - { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, - { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, - { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, - { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, - { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, - { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, - { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, - { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, - { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, - { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01030101 }, - { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, - { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, - { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, - { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, - { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, - { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, - { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, - { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, - { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, - { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, - { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, - { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, - { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, - { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, - { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, - { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, - { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, - { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, - { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, - { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, - { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, - { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, - { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, - { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, - { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, - { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, - { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, - { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, - { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, - { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, - { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, - { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, - { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, - { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, - { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, - { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, - { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, - { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, - { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, - { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, - { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, - { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, - { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, - { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, - { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, - { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, - { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, - { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, - { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, - { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, - { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, - { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, - { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, - { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, - { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, - { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, - { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, - { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, - { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, - { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, - { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, - { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, - { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, - { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, - { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, - { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, - { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, - { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, - { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, - { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, - { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, - { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, - { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, - { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, - { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, - { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, - { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, - { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, - { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, - { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, - { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, - { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, - { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, - { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, - { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, - { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, - { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, - { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, - { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, - { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, - { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, - { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, - { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, - { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, - { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, - { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, - { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, - { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, - { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, - { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, - { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, - { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, - { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, - { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, - { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, - { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, - { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, - { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, - { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, - { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, - { DENALI_CTL_398, 0x01090205 }, { DENALI_CTL_399, 0x00200106 }, - { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, - { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, - { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, - { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, - { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, - { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, - { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, - { DENALI_CTL_414, 0x4F6306E8 }, { DENALI_CTL_415, 0x00002822 }, - { DENALI_CTL_416, 0x00003C22 }, { DENALI_CTL_417, 0x00000000 }, - { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, - { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, - { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, - { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, - { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, - { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, - { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, - { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, - { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } -}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c b/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c deleted file mode 100644 index 5f6ea0f612..0000000000 --- a/plat/renesas/rza/soc/a3ul/drivers/ddr/param_mc_C-011_D3-02-2.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2020-2025, Renesas Electronics Corporation. All rights reserved. - * SPDX-License-Identifier: BSD-3-Clause - * This code was generated with RZ/A3UL DDR config generation tool v3.0.0 - */ - -#include - -#include - -const char ddr_an_version[] = "v3.0.0"; - -const uint32_t mc_init_tbl[MC_INIT_NUM][2] = { - { DENALI_CTL_00, 0x00000600 }, { DENALI_CTL_01, 0x00000000 }, - { DENALI_CTL_02, 0x00000000 }, { DENALI_CTL_03, 0x00000000 }, - { DENALI_CTL_04, 0x00000000 }, { DENALI_CTL_05, 0x00000000 }, - { DENALI_CTL_06, 0x00000000 }, { DENALI_CTL_07, 0x00000000 }, - { DENALI_CTL_08, 0x00000000 }, { DENALI_CTL_09, 0x00000000 }, - { DENALI_CTL_10, 0x01000007 }, { DENALI_CTL_11, 0x00100100 }, - { DENALI_CTL_12, 0x000208D6 }, { DENALI_CTL_13, 0x00051616 }, - { DENALI_CTL_14, 0x07120200 }, { DENALI_CTL_15, 0x00000000 }, - { DENALI_CTL_16, 0x05000404 }, { DENALI_CTL_17, 0x00002100 }, - { DENALI_CTL_18, 0x0505001E }, { DENALI_CTL_19, 0x05001E09 }, - { DENALI_CTL_20, 0x000C0405 }, { DENALI_CTL_21, 0x0400B6D0 }, - { DENALI_CTL_22, 0x00030305 }, { DENALI_CTL_23, 0x01000A09 }, - { DENALI_CTL_24, 0x09031301 }, { DENALI_CTL_25, 0x01000009 }, - { DENALI_CTL_26, 0x00000101 }, { DENALI_CTL_27, 0x00000000 }, - { DENALI_CTL_28, 0x00000000 }, { DENALI_CTL_29, 0x00040301 }, - { DENALI_CTL_30, 0x000000AE }, { DENALI_CTL_31, 0x00001448 }, - { DENALI_CTL_32, 0x00000005 }, { DENALI_CTL_33, 0x00100004 }, - { DENALI_CTL_34, 0x00B40200 }, { DENALI_CTL_35, 0x000000B4 }, - { DENALI_CTL_36, 0x01000201 }, { DENALI_CTL_37, 0x80104002 }, - { DENALI_CTL_38, 0x00000000 }, { DENALI_CTL_39, 0x00040000 }, - { DENALI_CTL_40, 0x00000000 }, { DENALI_CTL_41, 0x00051200 }, - { DENALI_CTL_42, 0x000007D0 }, { DENALI_CTL_43, 0x00051200 }, - { DENALI_CTL_44, 0x00051200 }, { DENALI_CTL_45, 0x00051200 }, - { DENALI_CTL_46, 0x00000000 }, { DENALI_CTL_47, 0x01000000 }, - { DENALI_CTL_48, 0x00000000 }, { DENALI_CTL_49, 0x00000000 }, - { DENALI_CTL_50, 0x00000000 }, { DENALI_CTL_51, 0x00000000 }, - { DENALI_CTL_52, 0x00000000 }, { DENALI_CTL_53, 0x00000000 }, - { DENALI_CTL_54, 0x00000000 }, { DENALI_CTL_55, 0x00262600 }, - { DENALI_CTL_56, 0x09070000 }, { DENALI_CTL_57, 0x2F0E010A }, - { DENALI_CTL_58, 0x00000300 }, { DENALI_CTL_59, 0x00010004 }, - { DENALI_CTL_60, 0x00000800 }, { DENALI_CTL_61, 0x00000000 }, - { DENALI_CTL_62, 0x00000000 }, { DENALI_CTL_63, 0x00000000 }, - { DENALI_CTL_64, 0x00000100 }, { DENALI_CTL_65, 0x00000200 }, - { DENALI_CTL_66, 0x00001000 }, { DENALI_CTL_67, 0x00000000 }, - { DENALI_CTL_68, 0x00000000 }, { DENALI_CTL_69, 0x00000A50 }, - { DENALI_CTL_70, 0x00000006 }, { DENALI_CTL_71, 0x00000010 }, - { DENALI_CTL_72, 0x00000A50 }, { DENALI_CTL_73, 0x00000006 }, - { DENALI_CTL_74, 0x00000010 }, { DENALI_CTL_75, 0x00000000 }, - { DENALI_CTL_76, 0x00000000 }, { DENALI_CTL_77, 0x00000000 }, - { DENALI_CTL_78, 0x00000000 }, { DENALI_CTL_79, 0x00000000 }, - { DENALI_CTL_80, 0x00000000 }, { DENALI_CTL_81, 0x00000000 }, - { DENALI_CTL_82, 0x00000000 }, { DENALI_CTL_83, 0x00000000 }, - { DENALI_CTL_84, 0x00000000 }, { DENALI_CTL_85, 0x01010000 }, - { DENALI_CTL_86, 0x00000000 }, { DENALI_CTL_87, 0x00000000 }, - { DENALI_CTL_88, 0x00000000 }, { DENALI_CTL_89, 0x00000000 }, - { DENALI_CTL_90, 0x00000000 }, { DENALI_CTL_91, 0x00000000 }, - { DENALI_CTL_92, 0x00000000 }, { DENALI_CTL_93, 0x00000000 }, - { DENALI_CTL_94, 0x00000000 }, { DENALI_CTL_95, 0x01000200 }, - { DENALI_CTL_96, 0x00010801 }, { DENALI_CTL_97, 0x00000000 }, - { DENALI_CTL_98, 0x00000000 }, { DENALI_CTL_99, 0x00000000 }, - { DENALI_CTL_100, 0x00000000 }, { DENALI_CTL_101, 0x00000000 }, - { DENALI_CTL_102, 0x00000000 }, { DENALI_CTL_103, 0x00000000 }, - { DENALI_CTL_104, 0x00000000 }, { DENALI_CTL_105, 0x00000000 }, - { DENALI_CTL_106, 0x00000000 }, { DENALI_CTL_107, 0x00000000 }, - { DENALI_CTL_108, 0x00000000 }, { DENALI_CTL_109, 0x00000000 }, - { DENALI_CTL_110, 0x00000008 }, { DENALI_CTL_111, 0x006403E8 }, - { DENALI_CTL_112, 0x00000000 }, { DENALI_CTL_113, 0x00000000 }, - { DENALI_CTL_114, 0x00000000 }, { DENALI_CTL_115, 0x15110000 }, - { DENALI_CTL_116, 0x00040C18 }, { DENALI_CTL_117, 0x009ECA03 }, - { DENALI_CTL_118, 0x0000A299 }, { DENALI_CTL_119, 0x00000000 }, - { DENALI_CTL_120, 0x01000200 }, { DENALI_CTL_121, 0x00000040 }, - { DENALI_CTL_122, 0x02010100 }, { DENALI_CTL_123, 0x00010102 }, - { DENALI_CTL_124, 0x07FF0000 }, { DENALI_CTL_125, 0x0000FF00 }, - { DENALI_CTL_126, 0xFFFFFFFF }, { DENALI_CTL_127, 0x00FFFF00 }, - { DENALI_CTL_128, 0xFFFF0A00 }, { DENALI_CTL_129, 0x01010001 }, - { DENALI_CTL_130, 0x01010101 }, { DENALI_CTL_131, 0x01030101 }, - { DENALI_CTL_132, 0x0C010000 }, { DENALI_CTL_133, 0x01000000 }, - { DENALI_CTL_134, 0x00000000 }, { DENALI_CTL_135, 0x00010000 }, - { DENALI_CTL_136, 0x00000000 }, { DENALI_CTL_137, 0x00000000 }, - { DENALI_CTL_138, 0x00000000 }, { DENALI_CTL_139, 0x00000000 }, - { DENALI_CTL_140, 0x00000000 }, { DENALI_CTL_141, 0x00000000 }, - { DENALI_CTL_142, 0x00000000 }, { DENALI_CTL_143, 0x00000000 }, - { DENALI_CTL_144, 0x00000000 }, { DENALI_CTL_145, 0x00000000 }, - { DENALI_CTL_146, 0x00000000 }, { DENALI_CTL_147, 0x00000000 }, - { DENALI_CTL_148, 0x00000000 }, { DENALI_CTL_149, 0x00000000 }, - { DENALI_CTL_150, 0x00000000 }, { DENALI_CTL_151, 0x00000000 }, - { DENALI_CTL_152, 0x00000000 }, { DENALI_CTL_153, 0x00000000 }, - { DENALI_CTL_154, 0x00000000 }, { DENALI_CTL_155, 0x00000000 }, - { DENALI_CTL_156, 0x00000000 }, { DENALI_CTL_157, 0x00010000 }, - { DENALI_CTL_158, 0x00000000 }, { DENALI_CTL_159, 0x00000800 }, - { DENALI_CTL_160, 0x00000000 }, { DENALI_CTL_161, 0x00000898 }, - { DENALI_CTL_162, 0x03000000 }, { DENALI_CTL_163, 0x00000408 }, - { DENALI_CTL_164, 0x00000000 }, { DENALI_CTL_165, 0x00000000 }, - { DENALI_CTL_166, 0x00000000 }, { DENALI_CTL_167, 0x00000000 }, - { DENALI_CTL_168, 0x00000000 }, { DENALI_CTL_169, 0x00000000 }, - { DENALI_CTL_170, 0x00000000 }, { DENALI_CTL_171, 0x00000000 }, - { DENALI_CTL_172, 0x00000000 }, { DENALI_CTL_173, 0x00000000 }, - { DENALI_CTL_174, 0x00000000 }, { DENALI_CTL_175, 0x06060600 }, - { DENALI_CTL_176, 0x03020001 }, { DENALI_CTL_177, 0x01020101 }, - { DENALI_CTL_178, 0x03000302 }, { DENALI_CTL_179, 0x00000000 }, - { DENALI_CTL_180, 0x00080801 }, { DENALI_CTL_181, 0x00080801 }, - { DENALI_CTL_182, 0x00070601 }, { DENALI_CTL_183, 0x00000000 }, - { DENALI_CTL_184, 0x000FFFFF }, { DENALI_CTL_185, 0xFFFFFFFF }, - { DENALI_CTL_186, 0x000F000F }, { DENALI_CTL_187, 0x00000000 }, - { DENALI_CTL_188, 0x030FFFFF }, { DENALI_CTL_189, 0xFFFFFFFF }, - { DENALI_CTL_190, 0x000F000F }, { DENALI_CTL_191, 0x00000000 }, - { DENALI_CTL_192, 0x030FFFFF }, { DENALI_CTL_193, 0xFFFFFFFF }, - { DENALI_CTL_194, 0x000F000F }, { DENALI_CTL_195, 0x00000000 }, - { DENALI_CTL_196, 0x030FFFFF }, { DENALI_CTL_197, 0xFFFFFFFF }, - { DENALI_CTL_198, 0x000F000F }, { DENALI_CTL_199, 0x00000000 }, - { DENALI_CTL_200, 0x030FFFFF }, { DENALI_CTL_201, 0xFFFFFFFF }, - { DENALI_CTL_202, 0x000F000F }, { DENALI_CTL_203, 0x00000000 }, - { DENALI_CTL_204, 0x030FFFFF }, { DENALI_CTL_205, 0xFFFFFFFF }, - { DENALI_CTL_206, 0x000F000F }, { DENALI_CTL_207, 0x00000000 }, - { DENALI_CTL_208, 0x030FFFFF }, { DENALI_CTL_209, 0xFFFFFFFF }, - { DENALI_CTL_210, 0x000F000F }, { DENALI_CTL_211, 0x00000000 }, - { DENALI_CTL_212, 0x030FFFFF }, { DENALI_CTL_213, 0xFFFFFFFF }, - { DENALI_CTL_214, 0x000F000F }, { DENALI_CTL_215, 0x00000000 }, - { DENALI_CTL_216, 0x030FFFFF }, { DENALI_CTL_217, 0xFFFFFFFF }, - { DENALI_CTL_218, 0x000F000F }, { DENALI_CTL_219, 0x00000000 }, - { DENALI_CTL_220, 0x030FFFFF }, { DENALI_CTL_221, 0xFFFFFFFF }, - { DENALI_CTL_222, 0x000F000F }, { DENALI_CTL_223, 0x00000000 }, - { DENALI_CTL_224, 0x030FFFFF }, { DENALI_CTL_225, 0xFFFFFFFF }, - { DENALI_CTL_226, 0x000F000F }, { DENALI_CTL_227, 0x00000000 }, - { DENALI_CTL_228, 0x030FFFFF }, { DENALI_CTL_229, 0xFFFFFFFF }, - { DENALI_CTL_230, 0x000F000F }, { DENALI_CTL_231, 0x00000000 }, - { DENALI_CTL_232, 0x030FFFFF }, { DENALI_CTL_233, 0xFFFFFFFF }, - { DENALI_CTL_234, 0x000F000F }, { DENALI_CTL_235, 0x00000000 }, - { DENALI_CTL_236, 0x030FFFFF }, { DENALI_CTL_237, 0xFFFFFFFF }, - { DENALI_CTL_238, 0x000F000F }, { DENALI_CTL_239, 0x00000000 }, - { DENALI_CTL_240, 0x030FFFFF }, { DENALI_CTL_241, 0xFFFFFFFF }, - { DENALI_CTL_242, 0x000F000F }, { DENALI_CTL_243, 0x00000000 }, - { DENALI_CTL_244, 0x030FFFFF }, { DENALI_CTL_245, 0xFFFFFFFF }, - { DENALI_CTL_246, 0x000F000F }, { DENALI_CTL_247, 0x00000000 }, - { DENALI_CTL_248, 0x000FFFFF }, { DENALI_CTL_249, 0xFFFFFFFF }, - { DENALI_CTL_250, 0x000F000F }, { DENALI_CTL_251, 0x00000000 }, - { DENALI_CTL_252, 0x030FFFFF }, { DENALI_CTL_253, 0xFFFFFFFF }, - { DENALI_CTL_254, 0x000F000F }, { DENALI_CTL_255, 0x00000000 }, - { DENALI_CTL_256, 0x030FFFFF }, { DENALI_CTL_257, 0xFFFFFFFF }, - { DENALI_CTL_258, 0x000F000F }, { DENALI_CTL_259, 0x00000000 }, - { DENALI_CTL_260, 0x030FFFFF }, { DENALI_CTL_261, 0xFFFFFFFF }, - { DENALI_CTL_262, 0x000F000F }, { DENALI_CTL_263, 0x00000000 }, - { DENALI_CTL_264, 0x030FFFFF }, { DENALI_CTL_265, 0xFFFFFFFF }, - { DENALI_CTL_266, 0x000F000F }, { DENALI_CTL_267, 0x00000000 }, - { DENALI_CTL_268, 0x030FFFFF }, { DENALI_CTL_269, 0xFFFFFFFF }, - { DENALI_CTL_270, 0x000F000F }, { DENALI_CTL_271, 0x00000000 }, - { DENALI_CTL_272, 0x030FFFFF }, { DENALI_CTL_273, 0xFFFFFFFF }, - { DENALI_CTL_274, 0x000F000F }, { DENALI_CTL_275, 0x00000000 }, - { DENALI_CTL_276, 0x030FFFFF }, { DENALI_CTL_277, 0xFFFFFFFF }, - { DENALI_CTL_278, 0x000F000F }, { DENALI_CTL_279, 0x00000000 }, - { DENALI_CTL_280, 0x030FFFFF }, { DENALI_CTL_281, 0xFFFFFFFF }, - { DENALI_CTL_282, 0x000F000F }, { DENALI_CTL_283, 0x00000000 }, - { DENALI_CTL_284, 0x030FFFFF }, { DENALI_CTL_285, 0xFFFFFFFF }, - { DENALI_CTL_286, 0x000F000F }, { DENALI_CTL_287, 0x00000000 }, - { DENALI_CTL_288, 0x030FFFFF }, { DENALI_CTL_289, 0xFFFFFFFF }, - { DENALI_CTL_290, 0x000F000F }, { DENALI_CTL_291, 0x00000000 }, - { DENALI_CTL_292, 0x030FFFFF }, { DENALI_CTL_293, 0xFFFFFFFF }, - { DENALI_CTL_294, 0x000F000F }, { DENALI_CTL_295, 0x00000000 }, - { DENALI_CTL_296, 0x030FFFFF }, { DENALI_CTL_297, 0xFFFFFFFF }, - { DENALI_CTL_298, 0x000F000F }, { DENALI_CTL_299, 0x00000000 }, - { DENALI_CTL_300, 0x030FFFFF }, { DENALI_CTL_301, 0xFFFFFFFF }, - { DENALI_CTL_302, 0x000F000F }, { DENALI_CTL_303, 0x00000000 }, - { DENALI_CTL_304, 0x030FFFFF }, { DENALI_CTL_305, 0xFFFFFFFF }, - { DENALI_CTL_306, 0x000F000F }, { DENALI_CTL_307, 0x00000000 }, - { DENALI_CTL_308, 0x030FFFFF }, { DENALI_CTL_309, 0xFFFFFFFF }, - { DENALI_CTL_310, 0x000F000F }, { DENALI_CTL_311, 0x00000000 }, - { DENALI_CTL_312, 0x000FFFFF }, { DENALI_CTL_313, 0xFFFFFFFF }, - { DENALI_CTL_314, 0x000F000F }, { DENALI_CTL_315, 0x00000000 }, - { DENALI_CTL_316, 0x030FFFFF }, { DENALI_CTL_317, 0xFFFFFFFF }, - { DENALI_CTL_318, 0x000F000F }, { DENALI_CTL_319, 0x00000000 }, - { DENALI_CTL_320, 0x030FFFFF }, { DENALI_CTL_321, 0xFFFFFFFF }, - { DENALI_CTL_322, 0x000F000F }, { DENALI_CTL_323, 0x00000000 }, - { DENALI_CTL_324, 0x030FFFFF }, { DENALI_CTL_325, 0xFFFFFFFF }, - { DENALI_CTL_326, 0x000F000F }, { DENALI_CTL_327, 0x00000000 }, - { DENALI_CTL_328, 0x030FFFFF }, { DENALI_CTL_329, 0xFFFFFFFF }, - { DENALI_CTL_330, 0x000F000F }, { DENALI_CTL_331, 0x00000000 }, - { DENALI_CTL_332, 0x030FFFFF }, { DENALI_CTL_333, 0xFFFFFFFF }, - { DENALI_CTL_334, 0x000F000F }, { DENALI_CTL_335, 0x00000000 }, - { DENALI_CTL_336, 0x030FFFFF }, { DENALI_CTL_337, 0xFFFFFFFF }, - { DENALI_CTL_338, 0x000F000F }, { DENALI_CTL_339, 0x00000000 }, - { DENALI_CTL_340, 0x030FFFFF }, { DENALI_CTL_341, 0xFFFFFFFF }, - { DENALI_CTL_342, 0x000F000F }, { DENALI_CTL_343, 0x00000000 }, - { DENALI_CTL_344, 0x030FFFFF }, { DENALI_CTL_345, 0xFFFFFFFF }, - { DENALI_CTL_346, 0x000F000F }, { DENALI_CTL_347, 0x00000000 }, - { DENALI_CTL_348, 0x030FFFFF }, { DENALI_CTL_349, 0xFFFFFFFF }, - { DENALI_CTL_350, 0x000F000F }, { DENALI_CTL_351, 0x00000000 }, - { DENALI_CTL_352, 0x030FFFFF }, { DENALI_CTL_353, 0xFFFFFFFF }, - { DENALI_CTL_354, 0x000F000F }, { DENALI_CTL_355, 0x00000000 }, - { DENALI_CTL_356, 0x030FFFFF }, { DENALI_CTL_357, 0xFFFFFFFF }, - { DENALI_CTL_358, 0x000F000F }, { DENALI_CTL_359, 0x00000000 }, - { DENALI_CTL_360, 0x030FFFFF }, { DENALI_CTL_361, 0xFFFFFFFF }, - { DENALI_CTL_362, 0x000F000F }, { DENALI_CTL_363, 0x00000000 }, - { DENALI_CTL_364, 0x030FFFFF }, { DENALI_CTL_365, 0xFFFFFFFF }, - { DENALI_CTL_366, 0x000F000F }, { DENALI_CTL_367, 0x00000000 }, - { DENALI_CTL_368, 0x030FFFFF }, { DENALI_CTL_369, 0xFFFFFFFF }, - { DENALI_CTL_370, 0x000F000F }, { DENALI_CTL_371, 0x00000000 }, - { DENALI_CTL_372, 0x030FFFFF }, { DENALI_CTL_373, 0xFFFFFFFF }, - { DENALI_CTL_374, 0x000F000F }, { DENALI_CTL_375, 0x03000000 }, - { DENALI_CTL_376, 0x03030303 }, { DENALI_CTL_377, 0x03030303 }, - { DENALI_CTL_378, 0x03030303 }, { DENALI_CTL_379, 0x00030303 }, - { DENALI_CTL_380, 0x02020064 }, { DENALI_CTL_381, 0x02020202 }, - { DENALI_CTL_382, 0x02020202 }, { DENALI_CTL_383, 0x02020202 }, - { DENALI_CTL_384, 0x00010202 }, { DENALI_CTL_385, 0x01010064 }, - { DENALI_CTL_386, 0x01010101 }, { DENALI_CTL_387, 0x01010101 }, - { DENALI_CTL_388, 0x01010101 }, { DENALI_CTL_389, 0x00020101 }, - { DENALI_CTL_390, 0x00000064 }, { DENALI_CTL_391, 0x00000006 }, - { DENALI_CTL_392, 0x000007D0 }, { DENALI_CTL_393, 0x00000032 }, - { DENALI_CTL_394, 0x00000200 }, { DENALI_CTL_395, 0x00000200 }, - { DENALI_CTL_396, 0x00000000 }, { DENALI_CTL_397, 0x00000000 }, - { DENALI_CTL_398, 0x01080205 }, { DENALI_CTL_399, 0x00200106 }, - { DENALI_CTL_400, 0x00000000 }, { DENALI_CTL_401, 0x0A000202 }, - { DENALI_CTL_402, 0x000C000A }, { DENALI_CTL_403, 0x00000000 }, - { DENALI_CTL_404, 0x00000000 }, { DENALI_CTL_405, 0x00000000 }, - { DENALI_CTL_406, 0x00000000 }, { DENALI_CTL_407, 0x00000000 }, - { DENALI_CTL_408, 0x00000000 }, { DENALI_CTL_409, 0x00000000 }, - { DENALI_CTL_410, 0x00000000 }, { DENALI_CTL_411, 0x00000000 }, - { DENALI_CTL_412, 0x0000000F }, { DENALI_CTL_413, 0x017105DD }, - { DENALI_CTL_414, 0x4F6306E8 }, { DENALI_CTL_415, 0x00002822 }, - { DENALI_CTL_416, 0x00003C22 }, { DENALI_CTL_417, 0x00000000 }, - { DENALI_CTL_418, 0x00000000 }, { DENALI_CTL_419, 0x00000000 }, - { DENALI_CTL_420, 0x00000000 }, { DENALI_CTL_421, 0x00000000 }, - { DENALI_CTL_422, 0x00000000 }, { DENALI_CTL_423, 0x00000000 }, - { DENALI_CTL_424, 0x00000000 }, { DENALI_CTL_425, 0x00000000 }, - { DENALI_CTL_426, 0x00000000 }, { DENALI_CTL_427, 0x00000000 }, - { DENALI_CTL_428, 0x00000000 }, { DENALI_CTL_429, 0x00000000 }, - { DENALI_CTL_430, 0x00000000 }, { DENALI_CTL_431, 0x00000000 }, - { DENALI_CTL_432, 0x00000000 }, { DENALI_CTL_433, 0x00000000 }, - { DENALI_CTL_434, 0x00000000 }, { DENALI_CTL_435, 0x00000000 } -}; diff --git a/plat/renesas/rza/soc/a3ul/drivers/xspi.c b/plat/renesas/rza/soc/a3ul/drivers/xspi.c deleted file mode 100644 index 2ee8da56be..0000000000 --- a/plat/renesas/rza/soc/a3ul/drivers/xspi.c +++ /dev/null @@ -1,71 +0,0 @@ -#include - -#include -#include -#include -#include - -static int sub_init_xip(const xspidevice_instance_t *inst) -{ - int result; - result = inst->api->open(inst->ctrl, inst->cfg); - if (!result) { - result = inst->api->enter_xip(inst->ctrl); - inst->api->close(inst->ctrl); - } - return result; -} - -static int sub_post_init_xip(const xspi_instance_t *xspi) -{ - int result; - result = xspi->api->open(xspi->ctrl, xspi->cfg); - if (!result) { - xspi->api->enable_auto_calibration(xspi->ctrl); - result = xspi->api->post_init(xspi->ctrl); - xspi->api->close(xspi->ctrl); - } - return result; -} - -void xspi_setup(void) -{ - int i; - int result = 0; - -#ifdef XSPI_DEVICE_TYPE - RZA_PRINTF("Configure %s Flash Memory\n", XSPI_DEVICE_TYPE); -#endif - for (i = 0; result >= 0 && i < xspidevices_count; i++) { - result = sub_init_xip(xspidevices[i]); - if (result < 0) { - ERROR("xspi.c: abort on sub_init_xip (#%d)\n", i); - panic(); - } - } - for (i = 0; result >= 0 && i < xspidevices_count; i++) { - result = sub_post_init_xip(xspidevices[i]->cfg->xspi); - if (result < 0) { - ERROR("xspi.c: abort on sub_post_init_xip (#%d)\n", i); - panic(); - } - } -} - -/** - * memcpy for xspi - */ -int rz_xspi_read(void *to, uint64_t offset, size_t length) -{ - int result; - const xspidevice_instance_t *inst = xspidevices[0]; - if (!inst) - return -1; - - result = inst->api->open(inst->ctrl, inst->cfg); - if (!result) { - inst->api->read(inst->ctrl, to, (size_t)offset, length); - inst->api->close(inst->ctrl); - } - return result; -} diff --git a/plat/renesas/rza/soc/a3ul/include/cpg_opt.h b/plat/renesas/rza/soc/a3ul/include/cpg_opt.h deleted file mode 100644 index 4d04dd455f..0000000000 --- a/plat/renesas/rza/soc/a3ul/include/cpg_opt.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __CPG_OPT_H__ -#define __CPG_OPT_H__ - -#define CPG_RST_DDR_OPT_VALUE (0x00000000) - -#endif // __CPG_OPT_H__ diff --git a/plat/renesas/rza/soc/a3ul/include/platform_def.h b/plat/renesas/rza/soc/a3ul/include/platform_def.h index 4f9e0d3d16..47fda29745 100644 --- a/plat/renesas/rza/soc/a3ul/include/platform_def.h +++ b/plat/renesas/rza/soc/a3ul/include/platform_def.h @@ -27,7 +27,7 @@ #define PLATFORM_SYSTEM_COUNT U(1) #define PLATFORM_CLUSTER_COUNT U(1) -#define PLATFORM_CORE_COUNT U(2) +#define PLATFORM_CORE_COUNT U(1) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ @@ -90,8 +90,8 @@ #define MAX_MMAP_REGIONS U(9) #endif -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) -#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 34) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 34) /******************************************************************************* * Determining the use of FIP format diff --git a/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h b/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h index 06b7752f88..6ba4eebdb6 100644 --- a/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h +++ b/plat/renesas/rza/soc/a3ul/include/rza3ul_def.h @@ -7,62 +7,59 @@ #ifndef __RZA3UL_DEF_H__ #define __RZA3UL_DEF_H__ -#define PLAT_BOOT_ROM_BASE (0x00000000) -#define PLAT_MSRAM_BASE (0x00010000) -#define PLAT_ASRAM_BASE (0x00020000) -#define PLAT_DEVICE_BASE (0x10000000) -#define PLAT_SCIF0_BASE (0x1004B800) -#define PLAT_SPIMULT_BASE (0x10060000) -#define PLAT_SPIMULT_WBUF_BASE (0x10070000) -#define PLAT_SYC_BASE (0x11000000) -#define PLAT_CPG_BASE (0x11010000) -#define PLAT_SYSC_BASE (0x11020000) -#define PLAT_GPIO_BASE (0x11030000) -#define PLAT_TZC_ASRAM_BASE (0x11040000) -#define PLAT_TZC_MSRAM_BASE (0x11050000) -#define PLAT_TZC_SPI_BASE (0x11060000) -#define PLAT_TZC_DDR_BASE (0x11070000) -#define PLAT_DDR_PHY_BASE (0x11400000) -#define PLAT_DDR_MEMC_BASE (0x11410000) -#define PLAT_OTP_BASE (0x11860000) -#define PLAT_GIC_BASE (0x11900000) -#define PLAT_SD0_BASE (0x11C00000) -#define PLAT_SPIROM_BASE (0x20000000) -#define PLAT_DDR1_BASE (0x40000000) -#define PLAT_DDR2_BASE (0x80000000) -#define PLAT_DDR3_BASE (0x100000000) +#define PLAT_BOOT_ROM_BASE (0x00000000) +#define PLAT_MSRAM_BASE (0x00010000) +#define PLAT_ASRAM_BASE (0x00020000) +#define PLAT_DEVICE_BASE (0x10000000) +#define PLAT_SCIF0_BASE (0x1004B800) +#define PLAT_SPIMULT_BASE (0x10060000) +#define PLAT_SPIMULT_WBUF_BASE (0x10070000) +#define PLAT_SYC_BASE (0x11000000) +#define PLAT_CPG_BASE (0x11010000) +#define PLAT_SYSC_BASE (0x11020000) +#define PLAT_GPIO_BASE (0x11030000) +#define PLAT_TZC_ASRAM_BASE (0x11040000) +#define PLAT_TZC_MSRAM_BASE (0x11050000) +#define PLAT_TZC_SPI_BASE (0x11060000) +#define PLAT_TZC_DDR_BASE (0x11070000) +#define PLAT_DDR_PHY_BASE (0x11400000) +#define PLAT_DDR_MEMC_BASE (0x11410000) +#define PLAT_OTP_BASE (0x11860000) +#define PLAT_GIC_BASE (0x11900000) +#define PLAT_SD0_BASE (0x11C00000) +#define PLAT_SPIROM_BASE (0x20000000) +#define PLAT_DDR_BASE (0x40000000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE) -#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE) +#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x00040000) -#define PLAT_SRAM_BASE (PLAT_MSRAM_BASE) +#define PLAT_SRAM_BASE (PLAT_MSRAM_BASE) -#define PLAT_BOOT_ROM_SIZE (0x00010000 - PLAT_BOOT_ROM_BASE) -#define PLAT_MSRAM_SIZE (0x00020000 - PLAT_MSRAM_BASE) -#define PLAT_ASRAM_SIZE (0x00030000 - PLAT_ASRAM_BASE) -#define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) -#define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) -#define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) -#define PLAT_DDR1_SIZE (PLAT_DDR2_BASE - PLAT_DDR1_BASE) -#define PLAT_DDR2_SIZE (PLAT_DDR3_BASE - PLAT_DDR2_BASE) +#define PLAT_BOOT_ROM_SIZE (0x00010000 - PLAT_BOOT_ROM_BASE) +#define PLAT_MSRAM_SIZE (0x00020000 - PLAT_MSRAM_BASE) +#define PLAT_ASRAM_SIZE (0x00030000 - PLAT_ASRAM_BASE) +#define PLAT_SRAM_SIZE (PLAT_MSRAM_SIZE + PLAT_ASRAM_SIZE) +#define PLAT_DEVICE_SIZE (0x15000000 - PLAT_DEVICE_BASE) +#define PLAT_SPIROM_SIZE (0x30000000 - PLAT_SPIROM_BASE) +#define PLAT_DDR_SIZE (0x40000000UL) -#define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) -#define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) +#define PLAT_SPIROM_FIP_BASE (PLAT_SPIROM_BASE + 0x0001D200) +#define PLAT_SPIROM_FIP_SIZE (0x30000000 - PLAT_SPIROM_FIP_BASE) -#define PLAT_OTP_DEVICE_INFO (PLAT_OTP_BASE + 0x1178) +#define PLAT_OTP_DEVICE_INFO (PLAT_OTP_BASE + 0x1178) -#define PLAT_EMMC_FIP_BASE (0x00020000) -#define PLAT_EMMC_FIP_SIZE (0x001DFFFF) +#define PLAT_EMMC_FIP_BASE (0x00020000) +#define PLAT_EMMC_FIP_SIZE (0x001DFFFF) -#define PLAT_SYC_INCK_HZ (24000000) -#define PLAT_UART_INCK_HZ (100000000) -#define PLAT_UART_BARDRATE (115200) +#define PLAT_SYC_INCK_HZ (24000000) +#define PLAT_UART_INCK_HZ (100000000) +#define PLAT_UART_BARDRATE (115200) /* Boot Info base address */ -#define PLAT_BOOTINFO_BASE (PLAT_SRAM_BASE) +#define PLAT_BOOTINFO_BASE (PLAT_SRAM_BASE) /* Base address where parameters to BL31 are stored */ -#define PARAMS_BASE (PLAT_SRAM_BASE + 0x0001F000) -#define PARAMS_SIZE (0x1000) +#define PARAMS_BASE (PLAT_SRAM_BASE + 0x0001F000) +#define PARAMS_SIZE (0x1000) #endif /* __RZA3UL_DEF_H__ */ diff --git a/plat/renesas/rza/soc/a3ul/rz_image.pl b/plat/renesas/rza/soc/a3ul/rz_image.pl deleted file mode 100644 index 8299b9c416..0000000000 --- a/plat/renesas/rza/soc/a3ul/rz_image.pl +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/bin/perl -w -# Copyright (c) 2021-2025, Renesas Electronics Corporation. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause - -use strict; -use bigint; -my $size_limit = 0x1D000; - -die("Not enough parameter\n") if ($#ARGV < 0); - -# Open input file -my $name = shift(@ARGV); -my $outname; -if ($#ARGV < 0) { - $outname = "rz_" . $name; -} -else { - $outname = shift(@ARGV); -} -open(my $origin, '<', $name) or die("Can not open input file"); -binmode $origin; - -# Obtaining size ($st[7]) -my @st = stat($origin); - -# Check appended size -my $size = ($st[7] + 3) & "0xfffffffffffffffc"; -my $msg; -if ($size != $st[7]) {$msg = "Appended size";} else {$msg="Size";} -die("$msg too big ($size > $size_limit)") if ($size > $size_limit); - -# Create temporary file -open(my $out, '>', $outname) or die("Can not open output file"); -binmode $out; - -# Write header -$out->print(pack('L', $size)); -for(my $i = 1; $i < 112; $i++) { - $out->print(pack('L', 0xffffffff)); -} -$out->print(pack('L', 0xffff0000)); -$out->print(pack('L', 0x000800ff)); -$out->print(pack('L', 0x00fff700)); -$out->print(pack('L', 0xf700f708)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xffffffff)); -$out->print(pack('L', 0xaa55ffff)); - -# Append original data to temporary file -my $buf; -read($origin, $buf, $st[7]); -$out->print($buf); -if($st[7] < $size) { - warn "Not aligned. Append " . ($size-$st[7]) . " zero(s)"; - # Append zero - for(;$st[7] < $size; $size--) { - $out->print(pack('C', 0)); - } -} -$out->flush; - -# close -close $out; -close $origin; diff --git a/plat/renesas/rza/soc/a3ul/rz_xspi.mk b/plat/renesas/rza/soc/a3ul/rz_xspi.mk index 3e8a7d2ae1..28a9d40d2f 100644 --- a/plat/renesas/rza/soc/a3ul/rz_xspi.mk +++ b/plat/renesas/rza/soc/a3ul/rz_xspi.mk @@ -3,10 +3,11 @@ # # SPDX-License-Identifier: BSD-3-Clause # -RZ_XSPI_DRIVER_PATH := plat/renesas/rza/common/drivers/xspi + +RZ_XSPI_DRIVER_PATH := drivers/renesas/rza/xspi RZ_XSPI_CONFIGS := XSPI0 XSPI1 XSPI2 -RZ_XSPI_SOURCES := plat/renesas/rza/soc/a3ul/drivers/xspi.c +RZ_XSPI_SOURCES := drivers/renesas/rza/xspi/xspi.c RZ_XSPI_HEADERS := RZ_XSPI0_IF := spim RZ_XSPI0_IF_CONFIG := .channel=0, .base=0x10060000 @@ -27,6 +28,10 @@ ifneq ($(strip $(XSPI0_DEVICE)),) endif endif +PLAT_INCLUDES += -Iinclude/drivers/renesas/rza/spim \ + -Iinclude/drivers/renesas/rza/octal \ + -Iinclude/drivers/renesas/rza/xspi + include plat/renesas/rza/common/rz_xspi_common.mk $(eval $(call add_define,RZ_XSPI_EXCLUSIVE_SELECTOR)) diff --git a/plat/renesas/rza/soc/a3ul/soc.mk b/plat/renesas/rza/soc/a3ul/soc.mk index 0df067df14..ce67a78e7b 100644 --- a/plat/renesas/rza/soc/a3ul/soc.mk +++ b/plat/renesas/rza/soc/a3ul/soc.mk @@ -42,7 +42,7 @@ $(RZ_ELF): $(BL2_ELF) $(RZ_BIN): $(BL2_BIN) @echo " IMG $@" - $(Q)/usr/bin/perl ./plat/renesas/rza/soc/a3ul/rz_image.pl "$<" "$@" + $(Q)/usr/bin/perl ./tools/renesas/rza/a3ul/rz_image.pl "$<" "$@" $(BL2_MAP): $(BL2_ELF) $(RZ_MAP): $(BL2_MAP) diff --git a/plat/renesas/rza/soc/a3m/rz_image.pl b/tools/renesas/rza/a3m/rz_image.pl similarity index 100% rename from plat/renesas/rza/soc/a3m/rz_image.pl rename to tools/renesas/rza/a3m/rz_image.pl diff --git a/plat/renesas/rza/soc/a3m/rz_image_nand.pl b/tools/renesas/rza/a3m/rz_image_nand.pl similarity index 73% rename from plat/renesas/rza/soc/a3m/rz_image_nand.pl rename to tools/renesas/rza/a3m/rz_image_nand.pl index deb4262566..cd67f95da9 100644 --- a/plat/renesas/rza/soc/a3m/rz_image_nand.pl +++ b/tools/renesas/rza/a3m/rz_image_nand.pl @@ -8,26 +8,26 @@ use Digest::SHA; sub padding256 { - my ($f, $size, $fourth) = @_; - - for(my $i=1;$i<4;$i++) { - $f->print(pack('C', 0)); - } - $f->print(pack('C', $fourth)); - for(my $i=5;$i<57;$i++) { - $f->print(pack('C', 0)); - } - $f->print(pack('C',($size & (0b111 << 29)) >> 29)); - for(my $i=58;$i<61;$i++) { - $f->print(pack('C', 0)); - } - $f->print(pack('C',($size & (0x1F << 0)) << 3)); - $f->print(pack('C',($size & (0xFF << 5)) >> 5)); - $f->print(pack('C',($size & (0xFF << 13)) >> 13)); - $f->print(pack('C',($size & (0xFF << 21)) >> 21)); - for(my $i=65;$i<257;$i++) { - $f->print(pack('C', 0)); - } + my ($f, $size, $fourth) = @_; + + for(my $i=1; $i<4; $i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C', $fourth)); + for(my $i=5; $i<57; $i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0b111 << 29)) >> 29)); + for(my $i=58; $i<61; $i++) { + $f->print(pack('C', 0)); + } + $f->print(pack('C',($size & (0x1F << 0)) << 3)); + $f->print(pack('C',($size & (0xFF << 5)) >> 5)); + $f->print(pack('C',($size & (0xFF << 13)) >> 13)); + $f->print(pack('C',($size & (0xFF << 21)) >> 21)); + for(my $i=65; $i<257; $i++) { + $f->print(pack('C', 0)); + } } my $size_limit = 0x1D000; @@ -66,13 +66,13 @@ sub padding256 { $tmp->print($buf); #print "size:$size st:$st[7]\n"; if ($size != $st[7]) { - $tmp->print(pack('C', 0x80)); - for(my $i=($st[7] + 1);$i<$size;$i++) { + $tmp->print(pack('C', 0x80)); + for(my $i=($st[7] + 1);$i<$size;$i++) { $tmp->print(pack('C', 0)); - } - padding256($tmp, $st[7], 0); + } + padding256($tmp, $st[7], 0); } else { - padding256($tmp, $st[7], 0x80); + padding256($tmp, $st[7], 0x80); } close($tmp); open($tmp, '<', $tmpname) or die("Can not open temporary file"); @@ -93,7 +93,7 @@ sub padding256 { # Write header $header->print(pack('L', $size)); for(my $i = 1; $i < 4; $i++) { - $header->print(pack('L', 0xffffffff)); + $header->print(pack('L', 0xffffffff)); } $header->print($digest); for(my $i = 12; $i < 112; $i++) { @@ -123,12 +123,12 @@ sub padding256 { my @head = unpack('C512', $hbuf); for(my $h = 0;$h<2;$h++) { - for my $i (0..$#head){ - $out->print(pack('C', $head[$i])); - } - for my $i (0..$#head){ - $out->print(pack('C', 255 - $head[$i])); - } + for my $i (0..$#head){ + $out->print(pack('C', $head[$i])); + } + for my $i (0..$#head){ + $out->print(pack('C', 255 - $head[$i])); + } } # Append original data to temporary file diff --git a/plat/renesas/rza/common/rz_image.pl b/tools/renesas/rza/a3ul/rz_image.pl similarity index 100% rename from plat/renesas/rza/common/rz_image.pl rename to tools/renesas/rza/a3ul/rz_image.pl diff --git a/plat/renesas/rza/common/rz_bl2_xspi_config.sh b/tools/renesas/rza/rz_bl2_xspi_config.sh similarity index 100% rename from plat/renesas/rza/common/rz_bl2_xspi_config.sh rename to tools/renesas/rza/rz_bl2_xspi_config.sh