|
67 | 67 | * or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ
|
68 | 68 | * between non-secure (0x40000000) and secure modes (0x50000000).
|
69 | 69 | */
|
70 |
| - iomuxc: iomuxc@2A10000 { |
| 70 | + iomuxc: pinctrl@2A10000 { |
71 | 71 | compatible = "nxp,imx-iomuxc";
|
72 | 72 | reg = <0x2A10000 0x4000>;
|
73 | 73 | pinctrl: pinctrl {
|
|
76 | 76 | };
|
77 | 77 | };
|
78 | 78 |
|
79 |
| - iomuxc_aon: iomuxc@43C0000 { |
| 79 | + iomuxc_aon: pinctrl@43C0000 { |
80 | 80 | compatible = "nxp,mcux-rt-pinctrl";
|
81 | 81 | reg = <0x43C0000 0x4000>;
|
82 | 82 | status = "okay";
|
83 | 83 | };
|
84 | 84 |
|
85 |
| - ccm: ccm@4450000 { |
| 85 | + ccm: clock-controller@4450000 { |
86 | 86 | compatible = "nxp,imx-ccm-rev2";
|
87 | 87 | reg = <0x4450000 0x4000>;
|
88 | 88 | #clock-cells = <3>;
|
|
94 | 94 | };
|
95 | 95 | };
|
96 | 96 |
|
97 |
| - lpuart1: uart@4380000 { |
| 97 | + lpuart1: serial@4380000 { |
98 | 98 | compatible = "nxp,lpuart";
|
99 | 99 | reg = <0x4380000 0x4000>;
|
100 | 100 | interrupts = <19 0>;
|
|
104 | 104 | status = "disabled";
|
105 | 105 | };
|
106 | 106 |
|
107 |
| - lpuart2: uart@4390000 { |
| 107 | + lpuart2: serial@4390000 { |
108 | 108 | compatible = "nxp,lpuart";
|
109 | 109 | reg = <0x4390000 0x4000>;
|
110 | 110 | interrupts = <20 0>;
|
|
114 | 114 | status = "disabled";
|
115 | 115 | };
|
116 | 116 |
|
117 |
| - lpuart3: uart@2570000 { |
| 117 | + lpuart3: serial@2570000 { |
118 | 118 | compatible = "nxp,lpuart";
|
119 | 119 | reg = <0x2570000 0x4000>;
|
120 | 120 | interrupts = <68 0>;
|
|
124 | 124 | status = "disabled";
|
125 | 125 | };
|
126 | 126 |
|
127 |
| - lpuart4: uart@2580000 { |
| 127 | + lpuart4: serial@2580000 { |
128 | 128 | compatible = "nxp,lpuart";
|
129 | 129 | reg = <0x2580000 0x4000>;
|
130 | 130 | interrupts = <69 0>;
|
|
144 | 144 | status = "disabled";
|
145 | 145 | };
|
146 | 146 |
|
147 |
| - lpuart6: uart@25A0000 { |
| 147 | + lpuart6: serial@25A0000 { |
148 | 148 | compatible = "nxp,lpuart";
|
149 | 149 | reg = <0x25A0000 0x4000>;
|
150 | 150 | interrupts = <71 0>;
|
|
154 | 154 | status = "disabled";
|
155 | 155 | };
|
156 | 156 |
|
157 |
| - lpuart7: uart@4570000 { |
| 157 | + lpuart7: serial@4570000 { |
158 | 158 | compatible = "nxp,lpuart";
|
159 | 159 | reg = <0x4570000 0x4000>;
|
160 | 160 | interrupts = <196 0>;
|
|
164 | 164 | status = "disabled";
|
165 | 165 | };
|
166 | 166 |
|
167 |
| - lpuart8: uart@2DA0000 { |
| 167 | + lpuart8: serial@2DA0000 { |
168 | 168 | compatible = "nxp,lpuart";
|
169 | 169 | reg = <0x2DA0000 0x4000>;
|
170 | 170 | interrupts = <197 0>;
|
|
174 | 174 | status = "disabled";
|
175 | 175 | };
|
176 | 176 |
|
177 |
| - lpuart9: uart@2D70000 { |
| 177 | + lpuart9: serial@2D70000 { |
178 | 178 | compatible = "nxp,lpuart";
|
179 | 179 | reg = <0x2D70000 0x4000>;
|
180 | 180 | interrupts = <156 0>;
|
|
184 | 184 | status = "disabled";
|
185 | 185 | };
|
186 | 186 |
|
187 |
| - lpuart10: uart@2D80000 { |
| 187 | + lpuart10: serial@2D80000 { |
188 | 188 | compatible = "nxp,lpuart";
|
189 | 189 | reg = <0x2D80000 0x4000>;
|
190 | 190 | interrupts = <157 0>;
|
|
194 | 194 | status = "disabled";
|
195 | 195 | };
|
196 | 196 |
|
197 |
| - lpuart11: uart@2D90000 { |
| 197 | + lpuart11: serial@2D90000 { |
198 | 198 | compatible = "nxp,lpuart";
|
199 | 199 | reg = <0x2D90000 0x4000>;
|
200 | 200 | interrupts = <158 0>;
|
|
204 | 204 | status = "disabled";
|
205 | 205 | };
|
206 | 206 |
|
207 |
| - lpuart12: uart@4580000 { |
| 207 | + lpuart12: serial@4580000 { |
208 | 208 | compatible = "nxp,lpuart";
|
209 | 209 | reg = <0x4580000 0x4000>;
|
210 | 210 | interrupts = <159 0>;
|
|
328 | 328 | status = "disabled";
|
329 | 329 | };
|
330 | 330 |
|
331 |
| - gpt1: gpt@46c0000 { |
| 331 | + gpt1: timer@46c0000 { |
332 | 332 | compatible = "nxp,imx-gpt";
|
333 | 333 | reg = <0x46c0000 0x4000>;
|
334 | 334 | interrupts = <209 0>;
|
|
337 | 337 | status = "disabled";
|
338 | 338 | };
|
339 | 339 |
|
340 |
| - gpt2: gpt@2ec0000 { |
| 340 | + gpt2: timer@2ec0000 { |
341 | 341 | compatible = "nxp,imx-gpt";
|
342 | 342 | reg = <0x2ec0000 0x4000>;
|
343 | 343 | interrupts = <210 0>;
|
344 | 344 | gptfreq = <240000000>;
|
345 | 345 | clocks = <&ccm IMX_CCM_GPT2_CLK 0x41 0>;
|
346 | 346 | };
|
347 | 347 |
|
348 |
| - acmp1: cmp@2dc0000 { |
| 348 | + acmp1: comparator@2dc0000 { |
349 | 349 | compatible = "nxp,kinetis-acmp";
|
350 | 350 | reg = <0x2dc0000 0x4000>;
|
351 | 351 | interrupts = <200 0>;
|
352 | 352 | status = "disabled";
|
353 | 353 | };
|
354 | 354 |
|
355 |
| - acmp2: cmp@2dd0000 { |
| 355 | + acmp2: comparator@2dd0000 { |
356 | 356 | compatible = "nxp,kinetis-acmp";
|
357 | 357 | reg = <0x2dd0000 0x4000>;
|
358 | 358 | interrupts = <201 0>;
|
359 | 359 | status = "disabled";
|
360 | 360 | };
|
361 | 361 |
|
362 |
| - acmp3: cmp@2de0000 { |
| 362 | + acmp3: comparator@2de0000 { |
363 | 363 | compatible = "nxp,kinetis-acmp";
|
364 | 364 | reg = <0x2de0000 0x4000>;
|
365 | 365 | interrupts = <202 0>;
|
366 | 366 | status = "disabled";
|
367 | 367 | };
|
368 | 368 |
|
369 |
| - acmp4: cmp@2df0000 { |
| 369 | + acmp4: comparator@2df0000 { |
370 | 370 | compatible = "nxp,kinetis-acmp";
|
371 | 371 | reg = <0x2df0000 0x4000>;
|
372 | 372 | interrupts = <203 0>;
|
|
412 | 412 | #io-channel-cells = <1>;
|
413 | 413 | };
|
414 | 414 |
|
415 |
| - qtmr1: qtmr@2690000 { |
| 415 | + qtmr1: timer@2690000 { |
416 | 416 | compatible = "nxp,imx-qtmr";
|
417 | 417 | reg = <0x2690000 0x4000>;
|
418 | 418 | interrupts = <0 0>;
|
|
439 | 439 | };
|
440 | 440 | };
|
441 | 441 |
|
442 |
| - qtmr2: qtmr@26a0000 { |
| 442 | + qtmr2: timer@26a0000 { |
443 | 443 | compatible = "nxp,imx-qtmr";
|
444 | 444 | reg = <0x26a0000 0x4000>;
|
445 | 445 | interrupts = <233 0>;
|
|
466 | 466 | };
|
467 | 467 | };
|
468 | 468 |
|
469 |
| - qtmr3: qtmr@26b0000 { |
| 469 | + qtmr3: timer@26b0000 { |
470 | 470 | compatible = "nxp,imx-qtmr";
|
471 | 471 | reg = <0x26b0000 0x4000>;
|
472 | 472 | interrupts = <164 0>;
|
|
493 | 493 | };
|
494 | 494 | };
|
495 | 495 |
|
496 |
| - qtmr4: qtmr@26c0000 { |
| 496 | + qtmr4: timer@26c0000 { |
497 | 497 | compatible = "nxp,imx-qtmr";
|
498 | 498 | reg = <0x26c0000 0x4000>;
|
499 | 499 | interrupts = <151 0>;
|
|
520 | 520 | };
|
521 | 521 | };
|
522 | 522 |
|
523 |
| - qtmr5: qtmr@26d0000 { |
| 523 | + qtmr5: timer@26d0000 { |
524 | 524 | compatible = "nxp,imx-qtmr";
|
525 | 525 | reg = <0x26d0000 0x4000>;
|
526 | 526 | interrupts = <4 0>;
|
|
547 | 547 | };
|
548 | 548 | };
|
549 | 549 |
|
550 |
| - qtmr6: qtmr@26e0000 { |
| 550 | + qtmr6: timer@26e0000 { |
551 | 551 | compatible = "nxp,imx-qtmr";
|
552 | 552 | reg = <0x26e0000 0x4000>;
|
553 | 553 | interrupts = <5 0>;
|
|
574 | 574 | };
|
575 | 575 | };
|
576 | 576 |
|
577 |
| - qtmr7: qtmr@26f0000 { |
| 577 | + qtmr7: timer@26f0000 { |
578 | 578 | compatible = "nxp,imx-qtmr";
|
579 | 579 | reg = <0x26f0000 0x4000>;
|
580 | 580 | interrupts = <6 0>;
|
|
601 | 601 | };
|
602 | 602 | };
|
603 | 603 |
|
604 |
| - qtmr8: qtmr@2700000 { |
| 604 | + qtmr8: timer@2700000 { |
605 | 605 | compatible = "nxp,imx-qtmr";
|
606 | 606 | reg = <0x2700000 0x4000>;
|
607 | 607 | interrupts = <7 0>;
|
|
844 | 844 | };
|
845 | 845 |
|
846 | 846 |
|
847 |
| - lptmr1: lptmr@4300000 { |
| 847 | + lptmr1: timer@4300000 { |
848 | 848 | compatible = "nxp,lptmr";
|
849 | 849 | reg = <0x4300000 0x1000>;
|
850 | 850 | interrupts = <18 0>;
|
|
855 | 855 | status = "disabled";
|
856 | 856 | };
|
857 | 857 |
|
858 |
| - lptmr2: lptmr@24d0000 { |
| 858 | + lptmr2: timer@24d0000 { |
859 | 859 | compatible = "nxp,lptmr";
|
860 | 860 | reg = <0x24d0000 0x1000>;
|
861 | 861 | interrupts = <67 0>;
|
|
866 | 866 | status = "disabled";
|
867 | 867 | };
|
868 | 868 |
|
869 |
| - lptmr3: lptmr@2cd0000 { |
| 869 | + lptmr3: timer@2cd0000 { |
870 | 870 | compatible = "nxp,lptmr";
|
871 | 871 | reg = <0x2cd0000 0x1000>;
|
872 | 872 | interrupts = <150 0>;
|
|
893 | 893 | status = "disabled";
|
894 | 894 | };
|
895 | 895 |
|
896 |
| - flexpwm1: flexpwm@2650000 { |
| 896 | + flexpwm1: pwm@2650000 { |
897 | 897 | compatible = "nxp,flexpwm";
|
898 | 898 | reg = <0x2650000 0x4000>;
|
899 | 899 | interrupts = <23 0>;
|
|
939 | 939 | };
|
940 | 940 | };
|
941 | 941 |
|
942 |
| - flexpwm2: flexpwm@2660000 { |
| 942 | + flexpwm2: pwm@2660000 { |
943 | 943 | compatible = "nxp,flexpwm";
|
944 | 944 | reg = <0x2660000 0x4000>;
|
945 | 945 | interrupts = <170 0>;
|
|
985 | 985 | };
|
986 | 986 | };
|
987 | 987 |
|
988 |
| - flexpwm3: flexpwm@2670000 { |
| 988 | + flexpwm3: pwm@2670000 { |
989 | 989 | compatible = "nxp,flexpwm";
|
990 | 990 | reg = <0x2670000 0x4000>;
|
991 | 991 | interrupts = <175 0>;
|
|
1031 | 1031 | };
|
1032 | 1032 | };
|
1033 | 1033 |
|
1034 |
| - flexpwm4: flexpwm@2680000 { |
| 1034 | + flexpwm4: pwm@2680000 { |
1035 | 1035 | compatible = "nxp,flexpwm";
|
1036 | 1036 | reg = <0x2680000 0x4000>;
|
1037 | 1037 | interrupts = <180 0>;
|
|
1163 | 1163 | #size-cells = <0>;
|
1164 | 1164 | };
|
1165 | 1165 |
|
1166 |
| - usdhc1: usdhc@2850000 { |
| 1166 | + usdhc1: memory-controller@2850000 { |
1167 | 1167 | compatible = "nxp,imx-usdhc";
|
1168 | 1168 | reg = <0x2850000 0x4000>;
|
1169 | 1169 | status = "disabled";
|
|
1175 | 1175 | min-bus-freq = <400000>;
|
1176 | 1176 | };
|
1177 | 1177 |
|
1178 |
| - usdhc2: usdhc@2860000 { |
| 1178 | + usdhc2: memory-controller@2860000 { |
1179 | 1179 | compatible = "nxp,imx-usdhc";
|
1180 | 1180 | reg = <0x2860000 0x4000>;
|
1181 | 1181 | status = "disabled";
|
|
1333 | 1333 | clk-divider = <1>;
|
1334 | 1334 | };
|
1335 | 1335 |
|
1336 |
| - rtwdog1: wdog@42e0000 { |
| 1336 | + rtwdog1: watchdog@42e0000 { |
1337 | 1337 | compatible = "nxp,rtwdog";
|
1338 | 1338 | reg = <0x42e0000 0x10>;
|
1339 | 1339 | status = "disabled";
|
|
1343 | 1343 | clk-divider = <1>;
|
1344 | 1344 | };
|
1345 | 1345 |
|
1346 |
| - rtwdog2: wdog@2490000 { |
| 1346 | + rtwdog2: watchdog@2490000 { |
1347 | 1347 | compatible = "nxp,rtwdog";
|
1348 | 1348 | reg = <0x2490000 0x10>;
|
1349 | 1349 | status = "disabled";
|
|
1363 | 1363 | clk-divider = <1>;
|
1364 | 1364 | };
|
1365 | 1365 |
|
1366 |
| - rtwdog4: wdog@24b0000 { |
| 1366 | + rtwdog4: watchdog@24b0000 { |
1367 | 1367 | compatible = "nxp,rtwdog";
|
1368 | 1368 | reg = <0x24b0000 0x10>;
|
1369 | 1369 | status = "disabled";
|
|
1383 | 1383 | status = "disabled";
|
1384 | 1384 | };
|
1385 | 1385 |
|
1386 |
| - usb2: usbd@2c90000 { |
| 1386 | + usb2: usb@2c90000 { |
1387 | 1387 | compatible = "nxp,ehci";
|
1388 | 1388 | reg = <0x2c90000 0x1000>;
|
1389 | 1389 | interrupts = <214 0>;
|
|
1393 | 1393 | status = "disabled";
|
1394 | 1394 | };
|
1395 | 1395 |
|
1396 |
| - usbphy1: usbphy@2ca0000 { |
| 1396 | + usbphy1: usb-phy@2ca0000 { |
1397 | 1397 | compatible = "nxp,usbphy";
|
1398 | 1398 | reg = <0x2ca0000 0x1000>;
|
1399 | 1399 | status = "disabled";
|
1400 | 1400 | };
|
1401 | 1401 |
|
1402 |
| - usbphy2: usbphy@2cb0000 { |
| 1402 | + usbphy2: usb-phy@2cb0000 { |
1403 | 1403 | compatible = "nxp,usbphy";
|
1404 | 1404 | reg = <0x2cb0000 0x1000>;
|
1405 | 1405 | status = "disabled";
|
|
1427 | 1427 | &memory {
|
1428 | 1428 | #address-cells = <1>;
|
1429 | 1429 | #size-cells = <1>;
|
1430 |
| - ocram1: ocram@0 { |
| 1430 | + ocram1: memory@0 { |
1431 | 1431 | compatible = "zephyr,memory-region", "mmio-sram";
|
1432 | 1432 | zephyr,memory-region = "OCRAM1";
|
1433 | 1433 | /* OCRAM1 first 16K access is blocked by TRDC */
|
1434 | 1434 | reg = <0x0 DT_SIZE_K(496)>;
|
1435 | 1435 | };
|
1436 | 1436 |
|
1437 |
| - ocram2: ocram@7c000 { |
| 1437 | + ocram2: memory@7c000 { |
1438 | 1438 | compatible = "zephyr,memory-region", "mmio-sram";
|
1439 | 1439 | zephyr,memory-region = "OCRAM2";
|
1440 | 1440 | reg = <0x7c000 DT_SIZE_K(256)>;
|
|
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