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drivers: pwm: Add PWM driver for SOPHGO CVI series
This commit adds PWM driver for CVI series SoCs. Signed-off-by: Chen Xingyu <[email protected]>
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‎drivers/pwm/CMakeLists.txt‎

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@@ -54,6 +54,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_FAKE pwm_fake.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RZ_GPT pwm_renesas_rz_gpt.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NEORV32 pwm_neorv32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_WCH_GPTM pwm_wch_gptm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SOPHGO_CVI pwm_sophgo_cvi.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c)

‎drivers/pwm/Kconfig‎

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@@ -130,4 +130,6 @@ source "drivers/pwm/Kconfig.neorv32"
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source "drivers/pwm/Kconfig.wch"
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source "drivers/pwm/Kconfig.sophgo"
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endif # PWM

‎drivers/pwm/Kconfig.sophgo‎

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config PWM_SOPHGO_CVI
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bool "SOPHGO CVI series PWM driver"
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default y
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depends on DT_HAS_SOPHGO_CVI_PWM_ENABLED
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help
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Enables support for the SOPHGO CVI series PWM.

‎drivers/pwm/pwm_sophgo_cvi.c‎

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/*
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* Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sophgo_cvi_pwm
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/pwm.h>
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#if defined(CONFIG_PINCTRL)
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#include <zephyr/drivers/pinctrl.h>
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#endif /* CONFIG_PINCTRL */
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#define HLPERIOD(base, n) (base + 0x000 + (n) * 8)
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#define PERIOD(base, n) (base + 0x004 + (n) * 8)
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#define PWMCONFIG(base) (base + 0x040)
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#define PWMSTART(base) (base + 0x044)
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#define PWMDONE(base) (base + 0x048)
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#define PWMUPDATE(base) (base + 0x04c)
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#define PCOUNT(base, n) (base + 0x050 + (n) * 4)
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#define PULSECOUNT(base, n) (base + 0x060 + (n) * 4)
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#define SHIFTCOUNT(base, n) (base + 0x080 + (n) * 4)
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#define SHIFTSTART(base) (base + 0x090)
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#define PWM_OE(base) (base + 0x0d0)
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/* PWMCONFIG */
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#define CFG_POLARITY(n) BIT(n + 0)
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#define CFG_PWMMODE(n) BIT(n + 8)
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#define CFG_SHIFTMODE BIT(16)
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#define PWM_CH_MAX 4
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struct pwm_cvi_config {
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mm_reg_t base;
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uint32_t clk_pwm;
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#if defined(CONFIG_PINCTRL)
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const struct pinctrl_dev_config *pcfg;
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#endif /* CONFIG_PINCTRL */
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};
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static int pwm_cvi_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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const struct pwm_cvi_config *cfg = dev->config;
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uint32_t regval;
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if (channel > PWM_CH_MAX) {
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return -EINVAL;
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}
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if (period_cycles > cfg->clk_pwm) {
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return -EINVAL;
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}
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if (pulse_cycles >= period_cycles) {
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pulse_cycles = period_cycles - 1;
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}
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/* Configure output */
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regval = sys_read32(PWM_OE(cfg->base));
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regval |= BIT(channel);
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sys_write32(regval, PWM_OE(cfg->base));
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/* Set polarity and mode */
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regval = sys_read32(PWMCONFIG(cfg->base));
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if (flags & PWM_POLARITY_INVERTED) {
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regval &= ~CFG_POLARITY(channel); /* active low */
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} else {
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regval |= CFG_POLARITY(channel); /* active high */
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}
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regval &= ~CFG_PWMMODE(channel); /* continuous mode */
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sys_write32(regval, PWMCONFIG(cfg->base));
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/* Set period and pulse */
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sys_write32(period_cycles, PERIOD(cfg->base, channel));
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sys_write32(pulse_cycles, HLPERIOD(cfg->base, channel));
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if (sys_read32(PWMSTART(cfg->base)) & BIT(channel)) {
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/* Update channel */
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regval = sys_read32(PWMUPDATE(cfg->base));
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regval |= BIT(channel);
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sys_write32(regval, PWMUPDATE(cfg->base));
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regval &= ~BIT(channel);
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sys_write32(regval, PWMUPDATE(cfg->base));
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} else {
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/* Start channel */
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regval = sys_read32(PWMSTART(cfg->base));
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regval &= ~BIT(channel);
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sys_write32(regval, PWMSTART(cfg->base));
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regval |= BIT(channel);
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sys_write32(regval, PWMSTART(cfg->base));
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}
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return 0;
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}
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static int pwm_cvi_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_cvi_config *cfg = dev->config;
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if (channel > PWM_CH_MAX) {
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return -EINVAL;
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}
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*cycles = cfg->clk_pwm;
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return 0;
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}
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static int pwm_cvi_init(const struct device *dev)
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{
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#if defined(CONFIG_PINCTRL)
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const struct pwm_cvi_config *cfg = dev->config;
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int ret;
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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#endif /* CONFIG_PINCTRL */
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return 0;
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}
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static DEVICE_API(pwm, pwm_cvi_api) = {
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.set_cycles = pwm_cvi_set_cycles,
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.get_cycles_per_sec = pwm_cvi_get_cycles_per_sec,
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};
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#define PWM_CVI_INST(n) \
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IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n);)) \
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\
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static const struct pwm_cvi_config pwm_cvi_cfg_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.clk_pwm = DT_INST_PROP(n, clock_frequency), \
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IF_ENABLED(CONFIG_PINCTRL, (.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),)) \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &pwm_cvi_init, NULL, NULL, &pwm_cvi_cfg_##n, PRE_KERNEL_1, \
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CONFIG_PWM_INIT_PRIORITY, &pwm_cvi_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_CVI_INST)

‎dts/bindings/pwm/sophgo,cvi-pwm.yaml‎

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# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: SOPHGO CVI series PWM
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compatible: "sophgo,cvi-pwm"
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include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
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properties:
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clock-frequency:
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type: int
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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"#pwm-cells":
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const: 3
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pwm-cells:
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- channel
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- period
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- flags

‎dts/riscv/sophgo/cv180x.dtsi‎

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status = "disabled";
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};
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pwm0: pwm@3060000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3060000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm1: pwm@3061000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3061000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm2: pwm@3062000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3062000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm3: pwm@3063000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3063000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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uart0: uart@4140000 {
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compatible = "ns16550";
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reg = <0x4140000 DT_SIZE_K(64)>;

‎dts/riscv/sophgo/cv181x.dtsi‎

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status = "disabled";
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};
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pwm0: pwm@3060000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3060000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm1: pwm@3061000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3061000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm2: pwm@3062000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3062000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm3: pwm@3063000 {
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compatible = "sophgo,cvi-pwm";
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reg = <0x3063000 DT_SIZE_K(4)>;
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clock-frequency = <DT_FREQ_M(100)>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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uart0: uart@4140000 {
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compatible = "ns16550";
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reg = <0x4140000 DT_SIZE_K(64)>;

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