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drivers: dma: add ti mspm0 dma driver support
Add DMA driver support for Texas Instruments MSPM0 Family Series. Signed-off-by: Karthikeyan Krishnasamy <[email protected]>
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‎drivers/dma/CMakeLists.txt‎

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@@ -53,3 +53,4 @@ zephyr_library_sources_ifdef(CONFIG_DMA_XILINX_AXI_DMA dma_xilinx_axi_dma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_NXP_SDMA dma_nxp_sdma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_WCH dma_wch.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_TI_CC23X0 dma_ti_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_TI_MSPM0 dma_ti_mspm0.c)

‎drivers/dma/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -96,5 +96,6 @@ source "drivers/dma/Kconfig.nxp_sdma"
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source "drivers/dma/Kconfig.wch"
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source "drivers/dma/Kconfig.ti_cc23x0"
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source "drivers/dma/Kconfig.ti_mspm0"
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endif # DMA

‎drivers/dma/Kconfig.ti_mspm0‎

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@@ -0,0 +1,11 @@
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# Copyright (c) 2025 Linumiz GmbH
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#
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# SPDX-License-Identifier: Apache-2.0
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config DMA_TI_MSPM0
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bool "Texas Instruments MSPM0 DMA Controller Driver"
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default y
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depends on DT_HAS_TI_MSPM0_DMA_ENABLED
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select USE_MSPM0_DL_DMA
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help
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Enable Texas Instruments MSPM0 Family DMA driver.

‎drivers/dma/dma_ti_mspm0.c‎

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/*
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* Copyright (c) 2025 Linumiz GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_mspm0_dma
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#include <stdio.h>
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#include <string.h>
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#include <soc.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <driverlib/dl_dma.h>
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LOG_MODULE_REGISTER(ti_mspm0_dma, CONFIG_DMA_LOG_LEVEL);
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#define DMA_TI_MSPM0_BASE_CHANNEL_NUM 1
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/* Data Transfer Width */
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#define DMA_TI_MSPM0_DATAWIDTH_BYTE 1
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#define DMA_TI_MSPM0_DATAWIDTH_HALF 2
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#define DMA_TI_MSPM0_DATAIWDTH_WORD 3
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#define DMA_TI_MSPM0_DATAWIDTH_LONG 4
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#define DMA_TI_MSPM0_MAX_CHANNEL DT_INST_PROP(0, dma_channels)
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BUILD_ASSERT((DMA_TI_MSPM0_MAX_CHANNEL != 0), "dma-channels property required");
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struct dma_ti_mspm0_config {
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DMA_Regs *regs;
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void (*irq_config_func)(void);
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};
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struct dma_ti_mspm0_channel_data {
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dma_callback_t dma_callback;
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void *user_data;
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uint8_t direction;
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bool busy;
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};
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struct dma_ti_mspm0_data {
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struct dma_context dma_ctx;
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struct dma_ti_mspm0_channel_data ch_data[DMA_TI_MSPM0_MAX_CHANNEL];
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};
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static inline int dma_ti_mspm0_get_memory_increment(uint8_t adj,
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uint32_t *increment)
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{
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if (increment == NULL) {
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return -EINVAL;
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}
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switch (adj) {
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case DMA_ADDR_ADJ_INCREMENT:
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*increment = DL_DMA_ADDR_INCREMENT;
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break;
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case DMA_ADDR_ADJ_NO_CHANGE:
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*increment = DL_DMA_ADDR_UNCHANGED;
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break;
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case DMA_ADDR_ADJ_DECREMENT:
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*increment = DL_DMA_ADDR_DECREMENT;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static inline int dma_ti_mspm0_get_dstdatawidth(uint8_t wd, uint32_t *dwidth)
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{
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if (dwidth == NULL) {
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return -EINVAL;
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}
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switch (wd) {
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case DMA_TI_MSPM0_DATAWIDTH_BYTE:
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*dwidth = DL_DMA_WIDTH_BYTE;
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break;
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case DMA_TI_MSPM0_DATAWIDTH_HALF:
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*dwidth = DMA_DMACTL_DMADSTWDTH_HALF;
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break;
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case DMA_TI_MSPM0_DATAIWDTH_WORD:
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*dwidth = DMA_DMACTL_DMADSTWDTH_WORD;
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break;
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case DMA_TI_MSPM0_DATAWIDTH_LONG:
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*dwidth = DMA_DMACTL_DMADSTWDTH_LONG;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static inline int dma_ti_mspm0_get_srcdatawidth(uint8_t wd, uint32_t *dwidth)
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{
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if (dwidth == NULL) {
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return -EINVAL;
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}
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switch (wd) {
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case DMA_TI_MSPM0_DATAWIDTH_BYTE:
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*dwidth = DL_DMA_WIDTH_BYTE;
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break;
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case DMA_TI_MSPM0_DATAWIDTH_HALF:
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*dwidth = DMA_DMACTL_DMASRCWDTH_HALF;
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break;
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case DMA_TI_MSPM0_DATAIWDTH_WORD:
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*dwidth = DMA_DMACTL_DMASRCWDTH_WORD;
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break;
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case DMA_TI_MSPM0_DATAWIDTH_LONG:
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*dwidth = DMA_DMACTL_DMASRCWDTH_LONG;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int dma_ti_mspm0_configure(const struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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uint32_t temp;
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const struct dma_ti_mspm0_config *cfg = dev->config;
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struct dma_ti_mspm0_data *dma_data = dev->data;
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struct dma_ti_mspm0_channel_data *data = NULL;
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struct dma_block_config *b_cfg = config->head_block;
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DL_DMA_Config dma_cfg = {0};
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if ((config == NULL) || (channel > DMA_TI_MSPM0_MAX_CHANNEL)) {
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return -EINVAL;
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}
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data = &dma_data->ch_data[channel];
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if (data->busy != false) {
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return -EBUSY;
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}
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if (config->dest_data_size != config->source_data_size) {
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LOG_ERR("Source and Destination data width is not same");
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return -EINVAL;
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}
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if (dma_ti_mspm0_get_memory_increment(b_cfg->source_addr_adj, &temp)) {
152+
LOG_ERR("Invalid Source address increment");
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return -EINVAL;
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}
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dma_cfg.srcIncrement = temp;
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if (dma_ti_mspm0_get_memory_increment(b_cfg->dest_addr_adj, &temp)) {
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LOG_ERR("Invalid Destination address increment");
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return -EINVAL;
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}
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dma_cfg.destIncrement = temp;
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if (dma_ti_mspm0_get_dstdatawidth(config->dest_data_size, &temp)) {
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LOG_ERR("Invalid Destination data width");
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return -EINVAL;
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}
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dma_cfg.destWidth = temp;
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if (dma_ti_mspm0_get_srcdatawidth(config->source_data_size, &temp)) {
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LOG_ERR("Invalid Source data width");
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return -EINVAL;
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}
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dma_cfg.srcWidth = temp;
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data->direction = config->channel_direction;
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data->dma_callback = config->dma_callback;
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data->user_data = config->user_data;
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dma_cfg.transferMode = DL_DMA_SINGLE_TRANSFER_MODE,
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dma_cfg.extendedMode = DL_DMA_NORMAL_MODE,
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dma_cfg.triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL;
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dma_cfg.trigger = config->dma_slot;
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DL_DMA_clearInterruptStatus(DMA, channel + DMA_TI_MSPM0_BASE_CHANNEL_NUM);
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DL_DMA_setTransferSize(cfg->regs, channel, b_cfg->block_size);
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DL_DMA_initChannel(cfg->regs, channel, &dma_cfg);
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DL_DMA_setSrcAddr(cfg->regs, channel, b_cfg->source_address);
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DL_DMA_setDestAddr(cfg->regs, channel, b_cfg->dest_address);
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DL_DMA_enableInterrupt(DMA, channel + DMA_TI_MSPM0_BASE_CHANNEL_NUM);
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data->busy = true;
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LOG_DBG("DMA Channel %u configured", channel);
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return 0;
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}
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static int dma_ti_mspm0_start(const struct device *dev, const uint32_t channel)
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{
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const struct dma_ti_mspm0_config *cfg = dev->config;
202+
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if (channel > DMA_TI_MSPM0_MAX_CHANNEL) {
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return -EINVAL;
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}
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DL_DMA_enableChannel(cfg->regs, channel);
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return 0;
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}
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static int dma_ti_mspm0_stop(const struct device *dev, const uint32_t channel)
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{
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const struct dma_ti_mspm0_config *cfg = dev->config;
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struct dma_ti_mspm0_data *data = dev->data;
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if (channel > DMA_TI_MSPM0_MAX_CHANNEL) {
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return -EINVAL;
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}
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DL_DMA_disableChannel(cfg->regs, channel);
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data->ch_data[channel].busy = false;
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return 0;
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}
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static int dma_ti_mspm0_reload(const struct device *dev, uint32_t channel,
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uint32_t src_addr, uint32_t dest_addr, size_t size)
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{
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const struct dma_ti_mspm0_config *cfg = dev->config;
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struct dma_ti_mspm0_channel_data *data = NULL;
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struct dma_ti_mspm0_data *dma_data = dev->data;
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if (channel > DMA_TI_MSPM0_MAX_CHANNEL) {
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return -EINVAL;
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}
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data = &dma_data->ch_data[channel];
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switch (data->direction) {
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case PERIPHERAL_TO_MEMORY:
241+
DL_DMA_setDestAddr(cfg->regs, channel, dest_addr);
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break;
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case MEMORY_TO_PERIPHERAL:
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DL_DMA_setSrcAddr(cfg->regs, channel, src_addr);
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break;
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default:
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LOG_ERR("Unsupported data direction");
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return -ENOTSUP;
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}
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DL_DMA_setTransferSize(cfg->regs, channel, size);
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data->busy = true;
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return 0;
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}
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static int dma_ti_mspm0_get_status(const struct device *dev, uint32_t channel,
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struct dma_status *stat)
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{
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const struct dma_ti_mspm0_config *cfg = dev->config;
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struct dma_ti_mspm0_data *dma_data = dev->data;
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struct dma_ti_mspm0_channel_data *data;
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if (channel > DMA_TI_MSPM0_MAX_CHANNEL) {
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return -EINVAL;
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}
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data = &dma_data->ch_data[channel];
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stat->pending_length = DL_DMA_getTransferSize(cfg->regs, channel);
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stat->dir = data->direction;
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stat->busy = data->busy;
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return 0;
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}
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static inline void dma_ti_mspm0_isr(const struct device *dev)
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{
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int channel;
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const struct dma_ti_mspm0_config *cfg = dev->config;
280+
struct dma_ti_mspm0_data *dma_data = dev->data;
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struct dma_ti_mspm0_channel_data *data;
282+
uint32_t key = irq_lock();
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channel = DL_DMA_getPendingInterrupt(cfg->regs);
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channel -= DMA_TI_MSPM0_BASE_CHANNEL_NUM;
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if ((channel < 0) || (channel > DMA_TI_MSPM0_MAX_CHANNEL)) {
288+
goto out;
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}
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data = &dma_data->ch_data[channel];
292+
DL_DMA_disableChannel(cfg->regs, channel);
293+
294+
if (data->dma_callback != NULL) {
295+
data->busy = false;
296+
data->dma_callback(dev, data->user_data, channel, 0);
297+
}
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out:
300+
irq_unlock(key);
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}
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static int dma_ti_mspm0_init(const struct device *dev)
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{
305+
const struct dma_ti_mspm0_config *cfg = dev->config;
306+
307+
if (cfg->irq_config_func != NULL) {
308+
cfg->irq_config_func();
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}
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return 0;
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};
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static DEVICE_API(dma, dma_ti_mspm0_api) = {
315+
.config = dma_ti_mspm0_configure,
316+
.start = dma_ti_mspm0_start,
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.stop = dma_ti_mspm0_stop,
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.reload = dma_ti_mspm0_reload,
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.get_status = dma_ti_mspm0_get_status,
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};
321+
322+
#define MSPM0_DMA_INIT(inst) \
323+
static inline void dma_ti_mspm0_irq_cfg_##inst(void) \
324+
{ \
325+
irq_disable(DT_INST_IRQN(inst)); \
326+
IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), \
327+
dma_ti_mspm0_isr, DEVICE_DT_INST_GET(inst), 0); \
328+
\
329+
irq_enable(DT_INST_IRQN(inst)); \
330+
} \
331+
\
332+
static const struct dma_ti_mspm0_config dma_cfg_##inst = { \
333+
.regs = (DMA_Regs *)DT_INST_REG_ADDR(inst), \
334+
.irq_config_func = dma_ti_mspm0_irq_cfg_##inst, \
335+
}; \
336+
\
337+
struct dma_ti_mspm0_data dma_data_##inst; \
338+
\
339+
DEVICE_DT_INST_DEFINE(inst, &dma_ti_mspm0_init, NULL, \
340+
&dma_data_##inst, &dma_cfg_##inst, \
341+
PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, \
342+
&dma_ti_mspm0_api);
343+
344+
DT_INST_FOREACH_STATUS_OKAY(MSPM0_DMA_INIT);

‎modules/Kconfig.mspm0‎

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Original file line numberDiff line numberDiff line change
@@ -14,3 +14,6 @@ config USE_MSPM0_DL_UART
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config USE_MSPM0_DL_TIMER
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bool
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config USE_MSPM0_DL_DMA
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bool

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