devicetree: format SoC-level files in dts/riscv

Author: kylebonnici

dts/riscv/neorv32.dtsi

@@ -34,23 +34,23 @@
 					#address-cells = <1>;
 					interrupt-map-mask = <0x0 0xffffffff>;
 					interrupt-map = <
-						0  0 &intc 0 16
-						0  1 &intc 0 17
-						0  2 &intc 0 18
-						0  3 &intc 0 19
-						0  4 &intc 0 20
-						0  5 &intc 0 21
-						0  6 &intc 0 22
-						0  7 &intc 0 23
-						0  8 &intc 0 24
-						0  9 &intc 0 25
-						0 10 &intc 0 26
-						0 11 &intc 0 27
-						0 12 &intc 0 28
-						0 13 &intc 0 29
-						0 14 &intc 0 30
-						0 15 &intc 0 31
-					>;
+							 0 0 &intc 0 16
+							 0 1 &intc 0 17
+							 0 2 &intc 0 18
+							 0 3 &intc 0 19
+							 0 4 &intc 0 20
+							 0 5 &intc 0 21
+							 0 6 &intc 0 22
+							 0 7 &intc 0 23
+							 0 8 &intc 0 24
+							 0 9 &intc 0 25
+							 0 10 &intc 0 26
+							 0 11 &intc 0 27
+							 0 12 &intc 0 28
+							 0 13 &intc 0 29
+							 0 14 &intc 0 30
+							 0 15 &intc 0 31
+							>;
 					#interrupt-cells = <1>;
 				};
 			};

dts/riscv/renode_riscv32_virt.dtsi

@@ -80,24 +80,24 @@
 		};
 
 		uart0: uart@10000000 {
-			interrupts = < 0x0a 1 >;
-			interrupt-parent = < &plic0 >;
+			interrupts = <0x0a 1>;
+			interrupt-parent = <&plic0>;
 			clock-frequency = <150000000>;
 			current-speed = <115200>;
-			reg = < 0x10000000 0x100 >;
+			reg = <0x10000000 0x100>;
 			compatible = "ns16550";
-			reg-shift = < 0 >;
+			reg-shift = <0>;
 			status = "disabled";
 		};
 
 		uart1: uart@10000100 {
-			interrupts = < 0x0a 1 >;
-			interrupt-parent = < &plic1 >;
+			interrupts = <0x0a 1>;
+			interrupt-parent = <&plic1>;
 			clock-frequency = <150000000>;
 			current-speed = <115200>;
-			reg = < 0x10000100 0x100 >;
+			reg = <0x10000100 0x100>;
 			compatible = "ns16550";
-			reg-shift = < 0 >;
+			reg-shift = <0>;
 			status = "disabled";
 		};
 	};